Lines Matching defs:temp
179 double temp;
182 temp = delay_inside_mat + bank.mat.delay_wl_reset + bank.mat.delay_bl_restore;//TODO: Sheng: revisit
184 temp += bank.mat.delay_writeback; // temp stores random cycle time
188 temp = MAX(temp, bank.mat.r_predec->delay);
189 temp = MAX(temp, bank.mat.b_mux_predec->delay);
190 temp = MAX(temp, bank.mat.sa_mux_lev_1_predec->delay);
191 temp = MAX(temp, bank.mat.sa_mux_lev_2_predec->delay);
194 temp = ram_delay_inside_mat + bank.mat.delay_cam_sl_restore + bank.mat.delay_cam_ml_reset + bank.mat.delay_bl_restore
197 temp = MAX(temp, bank.mat.b_mux_predec->delay);//TODO: Sheng revisit whether distinguish cam and ram bitline etc.
198 temp = MAX(temp, bank.mat.sa_mux_lev_1_predec->delay);
199 temp = MAX(temp, bank.mat.sa_mux_lev_2_predec->delay);
204 temp = MAX(temp, bank.htree_in_add->max_unpipelined_link_delay);
206 cycle_time = temp;