Lines Matching refs:width_nand2_path_p
995 width_nand2_path_p[i] = 0;
1091 width_nand2_path_p[0] = p_to_n_sz_ratio * width_nand2_path_n[0];
1092 F = c_load_nand2_path_out / gate_C(width_nand2_path_n[0] + width_nand2_path_p[0], 0, is_dram_);
1098 width_nand2_path_p,
1138 compute_gate_area(INV, 1, width_nand2_path_p[i],
1141 cmos_Isub_leakage(width_nand2_path_n[i], width_nand2_path_p[i],
1144 cmos_Ig_leakage(width_nand2_path_n[i], width_nand2_path_p[i],
1195 c_gate_load = gate_C(width_nand2_path_p[i+1] + width_nand2_path_n[i+1], 0.0, is_dram_);
1196 c_intrinsic = drain_C_(width_nand2_path_p[i], PCH, 1, 1, g_tp.cell_h_def, is_dram_) +
1209 c_intrinsic = drain_C_(width_nand2_path_p[i], PCH, 1, 1, g_tp.cell_h_def, is_dram_) +
1297 leak_nand2_path += cmos_Isub_leakage(width_nand2_path_n[i], width_nand2_path_p[i], 1, inv,is_dram_);
1298 gate_leak_nand2_path += cmos_Ig_leakage(width_nand2_path_n[i], width_nand2_path_p[i], 1, inv,is_dram_);