Lines Matching defs:ram
130 ElectricalModel* ram = ModelGen::createRAM(buffer_model, ram_name, getTechModel());
131 ram->setParameter("NumberEntries", total_number_bufs);
132 ram->setParameter("NumberBits", number_bits_per_flit);
133 ram->construct();
155 portConnect(ram, "In", "FlitIn");
158 portConnect(ram, "WRAddr" + (String)i, "FlitIn", makeNetIndex(i));
159 portConnect(ram, "RDAddr" + (String)i, "RDAddr_DFF_Out" + (String)i);
161 portConnect(ram, "WE", "FlitIn", makeNetIndex(number_bits_per_flit-1));
162 portConnect(ram, "CK", "CK");
163 portConnect(ram, "Out", "FlitOut");
171 addSubInstances(ram, 1.0);
172 addElectricalSubResults(ram, 1.0);
174 getEventResult("WriteBuffer")->addSubResult(ram->getEventResult("Write"), ram_name, 1.0);
182 getEventResult("ReadBuffer")->addSubResult(ram->getEventResult("Read"), ram_name, 1.0);
201 ElectricalModel* ram = (ElectricalModel*)getSubInstance("RAM");
207 propagatePortTransitionInfo(ram, "In", "FlitIn");
208 propagatePortTransitionInfo(ram, "CK", "CK");
209 assignPortTransitionInfo(ram, "WE", TransitionInfo(0.0, 0.0, 1.0));
212 assignPortTransitionInfo(ram, "WRAddr" + (String)i, TransitionInfo(0.25, 0.25, 0.25));
213 assignPortTransitionInfo(ram, "RDAddr" + (String)i, TransitionInfo(0.25, 0.25, 0.25));
216 ram->use();
218 propagatePortTransitionInfo("FlitOut", ram, "Out");