Lines Matching defs:clock_tree
215 Model* clock_tree = getSubInstance("ClockTree");
216 clock_tree->setProperty("SitePitch", sqrt(router_area));
217 clock_tree->setProperty("TotalLoadCapPerBit", total_clock_tree_cap);
218 clock_tree->update();
298 ElectricalModel* clock_tree = (ElectricalModel*)getSubInstance("ClockTree");
299 propagatePortTransitionInfo(clock_tree, "In", "CK");
300 clock_tree->use();
542 ElectricalModel* clock_tree = (ElectricalModel*)ModelGen::createModel(clock_tree_model, clock_tree_name, getTechModel());
543 clock_tree->setParameter("NumberLevels", clock_tree_number_levels);
544 clock_tree->setParameter("NumberBits", 1);
545 clock_tree->setParameter("WireLayer", clock_tree_wire_layer);
546 clock_tree->setParameter("WireWidthMultiplier", clock_tree_wire_width_multiplier);
547 clock_tree->setParameter("WireSpacingMultiplier", clock_tree_wire_spacing_multiplier);
548 clock_tree->construct();
551 addSubInstances(clock_tree, 1.0);
552 addElectricalSubResults(clock_tree, 1.0);