drampower/src/MemoryPowerModel.cc

68   const MemArchitectureSpec& memArchSpec = memSpec.memArchSpec;
70   const int64_t nbrofBanks               = memSpec.memArchSpec.nbrOfBanks;
134   int64_t burstCc = memArchSpec.burstLength / memArchSpec.dataRate;
140     // memArchSpec.width represents the number of data (dq) pins.
142     int64_t dqPlusDqsBits = memArchSpec.width + memArchSpec.width / 8;
144     int64_t dqPlusDqsPlusMaskBits = memArchSpec.width + memArchSpec.width / 8 + memArchSpec.width / 8;
146     double ddrPeriod = t.clkPeriod / static_cast<double>(memArchSpec.dataRate);
149     energy.read_io_energy = calcIoTermEnergy(sum(c.numberofreadsBanks) * memArchSpec.burstLength,
155     energy.write_term_energy = calcIoTermEnergy(sum(c.numberofwritesBanks) * memArchSpec.burstLength,
160     if (memArchSpec.nbrOfRanks > 1) {
163       energy.read_oterm_energy = calcIoTermEnergy(sum(c.numberofreadsBanks) * memArchSpec.burstLength,
170       energy.write_oterm_energy = calcIoTermEnergy(sum(c.numberofwritesBanks) * memArchSpec.burstLength,
289   if (memArchSpec.twoVoltageDomains) {
349                                             + static_cast<double>(memArchSpec.nbrOfRanks) * energy.act_stdby_energy_banks[i]
359                           + static_cast<double>(memArchSpec.nbrOfRanks) * (energy.act_stdby_energy
378   const MemArchitectureSpec& memArchSpec = memSpec.memArchSpec;
379   const uint64_t nRanks = static_cast<uint64_t>(memArchSpec.nbrOfRanks);
381   const int64_t nbrofBanks = memSpec.memArchSpec.nbrOfBanks;
479     if (memSpec.memArchSpec.termination) {
483     if (nRanks > 1 && memSpec.memArchSpec.termination) {
582   const MemArchitectureSpec& memArchSpec = memSpec.memArchSpec;
588   if (memArchSpec.nbrOfRanks > 1) {