drampower/src/CmdScheduler.cc

85   const MemTimingSpec& memTimingSpec = memSpec.memTimingSpec;
108       cmd.time = 1 - memSpec.memTimingSpec.TAW;
110       cmd.time = 1 - memSpec.memTimingSpec.FAW;
124   tREF             = memTimingSpec.REFI;
217   const MemTimingSpec& memTimingSpec = memSpec.memTimingSpec;
241                                     static_cast<int>(memTimingSpec.RP));
255                                memTimingSpec.REFI : 0); i++) {
258         cmd.time = max(max(max(transFinish.time, PRE[static_cast<size_t>(transFinish.bank)].time + memTimingSpec.RP), tREF), startTime);
261           startTime = cmd.time + memTimingSpec.RFC;
263         tREF = tREF + memTimingSpec.REFI;
308                                                 PRE[cmd.bank].time + static_cast<int>(memTimingSpec.RP)),
310                                             static_cast<int>(memTimingSpec.FAW));
314                                  PRE[cmd.bank].time + static_cast<int>(memTimingSpec.RP)),
316                              static_cast<int>(memTimingSpec.TAW));
367                              + static_cast<int>(memTimingSpec.RCD));
401                                          static_cast<int>(memTimingSpec.RAS),
454   const MemTimingSpec& memTimingSpec = memSpec.memTimingSpec;
459   if ((timer > (endTime + memTimingSpec.CKE)) && (power_down == POWER_DOWN)) {
466     if (pdTime > memTimingSpec.REFI)
467       cmd.time = cmd.time + memTimingSpec.REFI;
472       startTime = cmd.time + memTimingSpec.XP;
474       startTime = cmd.time + memTimingSpec.XPDLL - memTimingSpec.RCD;
477   } else if ((timer > (endTime + memTimingSpec.CKESR)) && (power_down == SELF_REFRESH))    {
487       startTime = cmd.time + memTimingSpec.XS;
489       startTime = cmd.time + memTimingSpec.XSDLL - memTimingSpec.RCD;
500   const MemTimingSpec& memTimingSpec     = memSpec.memTimingSpec;
513                    max(int64_t(0), memTimingSpec.RTP - 2);
517       tRWTP_init = memTimingSpec.AL + memArchSpec.burstLength /
519                    max(memTimingSpec.RTP, int64_t(2)) - 2;
524       tRWTP_init = memTimingSpec.RTP;
531       tRWTP_init = memTimingSpec.WL + memArchSpec.burstLength /
532                    memArchSpec.dataRate - 1 + memTimingSpec.WR;
534       tRWTP_init = memTimingSpec.WL + memArchSpec.burstLength /
535                    memArchSpec.dataRate + memTimingSpec.WR;
553   const MemTimingSpec& memTimingSpec     = memSpec.memTimingSpec;
557     tRRD_init = memTimingSpec.RRD;
559       tSwitch_init = memTimingSpec.CCD;
565         tSwitch_init = memTimingSpec.WL + memArchSpec.burstLength /
566                        memArchSpec.dataRate - 1 + memTimingSpec.WTR;
568         tSwitch_init = memTimingSpec.WL + memArchSpec.burstLength /
569                        memArchSpec.dataRate + memTimingSpec.WTR;
581       tCCD_init = memTimingSpec.CCD_S;
582       tRRD_init = memTimingSpec.RRD_S;
583       tWTR_init = memTimingSpec.WTR_S;
585       tCCD_init = memTimingSpec.CCD_L;
586       tRRD_init = memTimingSpec.RRD_L;
587       tWTR_init = memTimingSpec.WTR_L;
594       tSwitch_init = memTimingSpec.WL + memArchSpec.burstLength /
600     tSwitch_init = memTimingSpec.RL + memArchSpec.burstLength /
601                    memArchSpec.dataRate + 2 - memTimingSpec.WL;