Lines Matching defs:system
30 """ This file creates a barebones system and executes 'hello', a simple Hello
44 # create the system we are going to simulate
45 system = System()
47 # Set the clock fequency of the system (and all of its children)
48 system.clk_domain = SrcClockDomain()
49 system.clk_domain.clock = '1GHz'
50 system.clk_domain.voltage_domain = VoltageDomain()
52 # Set up the system
53 system.mem_mode = 'timing' # Use timing accesses
54 system.mem_ranges = [AddrRange('512MB')] # Create an address range
57 system.cpu = TimingSimpleCPU()
60 system.membus = SystemXBar()
63 system.cache = SimpleCache(size='1kB')
68 system.cpu.icache_port = system.cache.cpu_side
69 system.cpu.dcache_port = system.cache.cpu_side
72 system.cache.mem_side = system.membus.slave
75 system.cpu.createInterruptController()
76 system.cpu.interrupts[0].pio = system.membus.master
77 system.cpu.interrupts[0].int_master = system.membus.slave
78 system.cpu.interrupts[0].int_slave = system.membus.master
81 system.mem_ctrl = DDR3_1600_8x8()
82 system.mem_ctrl.range = system.mem_ranges[0]
83 system.mem_ctrl.port = system.membus.master
85 # Connect the system up to the membus
86 system.system_port = system.membus.slave
98 system.cpu.workload = process
99 system.cpu.createThreads()
102 root = Root(full_system = False, system = system)