configs/example/fs.py

85         test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby,
88         test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline)
90         test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline)
92         test_sys = makeLinuxX86System(test_mem_mode, np, bm[0], options.ruby,
95         test_sys = makeArmSystem(test_mem_mode, options.machine_type, np,
104             test_sys.enable_context_switch_stats_dump = True
109     test_sys.cache_line_size = options.cacheline_size
112     test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
115     test_sys.clk_domain = SrcClockDomain(clock =  options.sys_clock,
116             voltage_domain = test_sys.voltage_domain)
119     test_sys.cpu_voltage_domain = VoltageDomain()
122     test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
124                                              test_sys.cpu_voltage_domain)
127         test_sys.kernel = binary(options.kernel)
133         test_sys.readfile = options.script
136         test_sys.have_lpae = True
139         test_sys.have_virtualization = True
141     test_sys.init_param = options.init_param
144     test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i)
148         test_sys.kvm_vm = KvmVM()
151         bootmem = getattr(test_sys, 'bootmem', None)
152         Ruby.create_system(options, True, test_sys, test_sys.iobus,
153                            test_sys._dma_ports, bootmem)
156         test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
157                                         voltage_domain = test_sys.voltage_domain)
161         test_sys.iobus.master = test_sys.ruby._io_port.slave
163         for (i, cpu) in enumerate(test_sys.cpu):
167             cpu.clk_domain = test_sys.cpu_clk_domain
171             cpu.icache_port = test_sys.ruby._cpu_ports[i].slave
172             cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave
175                 cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave
176                 cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave
179                 cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master
180                 cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[i].slave
181                 cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[i].master
186             test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges)
187             test_sys.iocache.cpu_side = test_sys.iobus.master
188             test_sys.iocache.mem_side = test_sys.membus.slave
190             test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
191             test_sys.iobridge.slave = test_sys.iobus.master
192             test_sys.iobridge.master = test_sys.membus.slave
203                 test_sys.cpu[i].addSimPointProbe(options.simpoint_interval)
205                 test_sys.cpu[i].addCheckerCpu()
208                 test_sys.cpu[i].branchPred = bpClass()
212                 test_sys.cpu[i].branchPred.indirectBranchPred = \
214             test_sys.cpu[i].createThreads()
225             CpuConfig.config_etrace(TestCPUClass, test_sys.cpu, options)
227         CacheConfig.config_cache(options, test_sys)
229         MemConfig.config_mem(options, test_sys)
231     return test_sys
340 test_sys = build_test_system(np)
343     root = makeDualRoot(True, test_sys, drive_sys, options.etherdump)
346     root = makeDistRoot(test_sys,
357     root = Root(full_system=True, system=test_sys)
381 Simulation.setWorkCountOptions(test_sys, options)
382 Simulation.run(options, root, test_sys, FutureClass)