Lines Matching defs:system
101 # start by creating the system itself, using a multi-layer 2.0 GHz
104 system = System(membus = SystemXBar(width = 32))
105 system.clk_domain = SrcClockDomain(clock = '2.0GHz',
110 system.mem_ranges = [mem_range]
113 system.mmap_using_noreserve = True
122 MemConfig.config_mem(options, system)
125 for ctrl in system.mem_ctrls:
142 system.cache_line_size = burst_size
167 # do not pile up in the system, adjust if needed
253 system.tgen = TrafficGen(config_file = cfg_file_name,
257 system.monitor = CommMonitor()
258 system.monitor.footprint = MemFootprintProbe()
260 # connect the traffic generator to the system
261 system.tgen.port = system.monitor.slave
280 system.l1cache = L1_DCache(size = '64kB')
281 system.monitor.master = system.l1cache.cpu_side
283 system.l2cache = L2Cache(size = '512kB', writeback_clean = True)
284 system.l2cache.xbar = L2XBar()
285 system.l1cache.mem_side = system.l2cache.xbar.slave
286 system.l2cache.cpu_side = system.l2cache.xbar.master
290 system.l3cache = L3Cache(size = '4MB', clusivity = 'mostly_excl')
291 system.l3cache.xbar = L2XBar()
292 system.l2cache.mem_side = system.l3cache.xbar.slave
293 system.l3cache.cpu_side = system.l3cache.xbar.master
294 system.l3cache.mem_side = system.membus.slave
296 # connect the system port even if it is not used in this example
297 system.system_port = system.membus.slave
303 root = Root(full_system = False, system = system)
304 root.system.mem_mode = 'timing'