Lines Matching refs:level
44 def TLB_constructor(level):
46 constructor_call = "X86GPUTLB(size = options.L%(level)dTLBentries, \
47 assoc = options.L%(level)dTLBassoc, \
48 hitLatency = options.L%(level)dAccessLatency,\
49 missLatency2 = options.L%(level)dMissLatency,\
50 maxOutstandingReqs = options.L%(level)dMaxOutstandingReqs,\
51 accessDistance = options.L%(level)dAccessDistanceStat,\
58 def Coalescer_constructor(level):
61 options.L%(level)dProbesPerCycle, \
62 coalescingWindow = options.L%(level)dCoalescingWindow,\
63 disableCoalescing = options.L%(level)dDisableCoalescing,\
71 # arguments: options, TLB level, number of private structures for this Level,
99 # width is the number of TLBs of the given type (i.e., D-TLB, I-TLB etc) for this level
115 level = i+1
127 create_TLB_Coalescer(options, level, TLB_index,\
141 # All TLBs but the last level TLB need to have a memSidePort (master)
145 # There is a one-to-one mapping of TLBs to Coalescers at a given level
149 level = i+1
157 # Connect the cpuSidePort (slave) of all the coalescers in level 1
190 # cpuSidePorts (slaves) of the Coalescers of the next level