History log of /gem5/src/mem/slicc/ast/
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14097:1f8f4c773c49 27-Feb-2019 Pouya Fotouhi <pfotouhi@ucdavis.edu>

mem-ruby: Adding a new slicc statement - to not evict locked cachelines

Ruby caches block incoming ports with messages on a locked
address to make sure the line would not be replaced by others.
But they do not check the lock upon capacity/conflict misses.

This change adds a new slicc statement "check_on_cache_probe" which takes
two arguments (mandatoryQueue for the controller, and the line subject
to eviction - i.e. address returned by cacheProbe).
If the line is locked, incoming message is delayed for 1 cycle and the
controller skips this request (i.e. does not trigger an event).

Coherence protocols should be updated accordingly. One use case for MESI
Two Level will be added in a separate change.

Signed-off-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>
Change-Id: I79ca2d45518de7a4e382b520a11f8e221b0cb803
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16808
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Srikant Bharadwaj <srikant.bharadwaj@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

13675:afeab32b3655 24-Jan-2019 Andreas Sandberg <andreas.sandberg@arm.com>

python: Replace dict.has_key with 'key in dict'

Python 3 has removed dict.has_key in favour of 'key in dict'.

Change-Id: I9852a5f57d672bea815308eb647a0ce45624fad5
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15987
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

12662:bcda9eb2aef5 16-Apr-2018 John Alsop <johnathan.alsop@amd.com>

mem-ruby: enable DPRINTFN calls in slicc for temporary debug printing

Change-Id: Ib92f8bb4ab7b61ebc96b935cb8abc42cf5ec6ac8
Reviewed-on: https://gem5-review.googlesource.com/9921
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

11320:42ecb523c64a 06-Feb-2016 Steve Reinhardt <steve.reinhardt@amd.com>

style: remove trailing whitespace

Result of running 'hg m5style --skip-all --fix-white -a'.


/gem5/configs/common/CacheConfig.py
/gem5/configs/common/Simulation.py
/gem5/configs/example/ruby_mem_test.py
/gem5/src/arch/alpha/isa/decoder.isa
/gem5/src/arch/alpha/linux/linux.hh
/gem5/src/arch/alpha/process.cc
/gem5/src/arch/alpha/tlb.cc
/gem5/src/arch/arm/SConscript
/gem5/src/arch/arm/interrupts.cc
/gem5/src/arch/arm/isa/bitfields.isa
/gem5/src/arch/arm/isa/formats/pred.isa
/gem5/src/arch/arm/linux/linux.hh
/gem5/src/arch/arm/stacktrace.cc
/gem5/src/arch/mips/isa/decoder.isa
/gem5/src/arch/mips/linux/linux.hh
/gem5/src/arch/mips/linux/process.cc
/gem5/src/arch/mips/pagetable.hh
/gem5/src/arch/power/SConscript
/gem5/src/arch/sparc/interrupts.cc
/gem5/src/arch/sparc/linux/linux.hh
/gem5/src/arch/sparc/pagetable.hh
/gem5/src/arch/x86/cpuid.cc
/gem5/src/arch/x86/faults.cc
/gem5/src/arch/x86/insts/micromediaop.hh
/gem5/src/arch/x86/isa/insts/general_purpose/system_calls.py
/gem5/src/arch/x86/isa/insts/romutil.py
/gem5/src/arch/x86/isa/insts/simd64/integer/data_transfer/move.py
/gem5/src/arch/x86/isa/microops/base.isa
/gem5/src/arch/x86/isa/microops/mediaop.isa
/gem5/src/arch/x86/isa/microops/regop.isa
/gem5/src/arch/x86/process.cc
/gem5/src/arch/x86/process.hh
/gem5/src/base/cp_annotate.cc
/gem5/src/base/cp_annotate.hh
/gem5/src/base/cprintf.hh
/gem5/src/base/flags.hh
/gem5/src/base/inet.cc
/gem5/src/base/inet.hh
/gem5/src/base/loader/ecoff_object.cc
/gem5/src/base/loader/elf_object.cc
/gem5/src/base/statistics.cc
/gem5/src/cpu/o3/decode_impl.hh
/gem5/src/cpu/simple/timing.cc
/gem5/src/cpu/testers/directedtest/DirectedGenerator.cc
/gem5/src/cpu/testers/directedtest/DirectedGenerator.hh
/gem5/src/cpu/testers/directedtest/InvalidateGenerator.cc
/gem5/src/cpu/testers/directedtest/InvalidateGenerator.hh
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.cc
/gem5/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
/gem5/src/cpu/testers/directedtest/SeriesRequestGenerator.hh
/gem5/src/cpu/testers/networktest/networktest.cc
/gem5/src/cpu/timebuf.hh
/gem5/src/dev/mc146818.cc
/gem5/src/dev/net/i8254xGBe.cc
/gem5/src/dev/net/i8254xGBe.hh
/gem5/src/dev/net/i8254xGBe_defs.hh
/gem5/src/dev/x86/i8042.cc
/gem5/src/dev/x86/i8254.hh
/gem5/src/dev/x86/intdev.hh
/gem5/src/mem/mport.hh
/gem5/src/mem/ruby/network/Topology.cc
/gem5/src/mem/ruby/network/Topology.hh
/gem5/src/mem/ruby/network/fault_model/FaultModel.cc
/gem5/src/mem/ruby/network/fault_model/FaultModel.hh
/gem5/src/mem/ruby/network/fault_model/FaultModel.py
/gem5/src/mem/ruby/network/fault_model/SConscript
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.py
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/Router.hh
/gem5/src/mem/ruby/network/simple/SimpleLink.cc
StallAndWaitStatementAST.py
TypeFieldEnumAST.py
TypeFieldStateAST.py
/gem5/src/python/m5/util/__init__.py
/gem5/src/python/swig/event.i
/gem5/src/sim/Root.py
/gem5/src/sim/eventq.cc
/gem5/src/sim/eventq.hh
/gem5/src/sim/insttracer.hh
/gem5/src/sim/pseudo_inst.cc
/gem5/src/unittest/cprintftest.cc
/gem5/system/alpha/console/console.c
/gem5/tests/configs/memtest-ruby.py
/gem5/util/checkpoint-tester.py
/gem5/util/compile
/gem5/util/m5/m5.c
/gem5/util/qdo
/gem5/util/statetrace/SConstruct
11283:4cc8b312f026 20-Jul-2015 Tony Gutierrez <anthony.gutierrez@amd.com>

ruby: slicc: have a static MachineType

This patch is imported from reviewboard patch 2551 by Nilay.
This patch moves from a dynamically defined MachineType to a statically
defined one. The need for this patch was felt since a dynamically defined
type prevents us from having types for which no machine definition may
exist.

The following changes have been made:
i. each machine definition now uses a type from the MachineType enumeration
instead of any random identifier. This required changing the grammar and the
*.sm files.
ii. MachineType enumeration defined statically in RubySlicc_Exports.sm.
* * *
normal protocol fixes for nilay's parser machine type fix

11282:afdcebd314be 20-Jul-2015 Tony Gutierrez <anthony.gutierrez@amd.com>

ruby: slicc: remove support for single machine, multiple types

This patch is imported from reviewboard patch 2550 by Nilay.
It was possible to specify multiple machine types with a single state machine.
This seems unnecessary and is being removed.

11111:6da33e720481 16-Sep-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: message buffer, timer table: significant changes

This patch changes MessageBuffer and TimerTable, two structures used for
buffering messages by components in ruby. These structures would no longer
maintain pointers to clock objects. Functions in these structures have been
changed to take as input current time in Tick. Similarly, these structures
will not operate on Cycle valued latencies for different operations. The
corresponding functions would need to be provided with these latencies by
components invoking the relevant functions. These latencies should also be
in Ticks.

I felt the need for these changes while trying to speed up ruby. The ultimate
aim is to eliminate Consumer class and replace it with an EventManager object in
the MessageBuffer and TimerTable classes. This object would be used for
scheduling events. The event itself would contain information on the object and
function to be invoked.

In hindsight, it seems I should have done this while I was moving away from use
of a single global clock in the memory system. That change led to introduction
of clock objects that replaced the global clock object. It never crossed my
mind that having clock object pointers is not a good design. And now I really
don't like the fact that we have separate consumer, receiver and sender
pointers in message buffers.


/gem5/src/mem/protocol/MESI_Three_Level-L0cache.sm
/gem5/src/mem/protocol/MESI_Three_Level-L1cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-L1cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-L2cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-dir.sm
/gem5/src/mem/protocol/MESI_Two_Level-dma.sm
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MI_example-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dma.sm
/gem5/src/mem/protocol/MOESI_hammer-cache.sm
/gem5/src/mem/protocol/MOESI_hammer-dir.sm
/gem5/src/mem/protocol/MOESI_hammer-dma.sm
/gem5/src/mem/protocol/Network_test-cache.sm
/gem5/src/mem/protocol/Network_test-dir.sm
/gem5/src/mem/protocol/RubySlicc_Defines.sm
/gem5/src/mem/protocol/RubySlicc_Exports.sm
/gem5/src/mem/protocol/RubySlicc_Types.sm
/gem5/src/mem/ruby/network/MessageBuffer.cc
/gem5/src/mem/ruby/network/MessageBuffer.hh
/gem5/src/mem/ruby/network/MessageBuffer.py
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
/gem5/src/mem/ruby/network/simple/PerfectSwitch.cc
/gem5/src/mem/ruby/network/simple/SimpleNetwork.py
/gem5/src/mem/ruby/network/simple/Switch.cc
/gem5/src/mem/ruby/network/simple/Throttle.cc
/gem5/src/mem/ruby/slicc_interface/AbstractController.cc
/gem5/src/mem/ruby/structures/TBETable.hh
/gem5/src/mem/ruby/structures/TimerTable.cc
/gem5/src/mem/ruby/structures/TimerTable.hh
/gem5/src/mem/ruby/system/DMASequencer.cc
/gem5/src/mem/ruby/system/RubyPort.cc
/gem5/src/mem/ruby/system/Sequencer.cc
EnqueueStatementAST.py
ObjDeclAST.py
PeekStatementAST.py
StallAndWaitStatementAST.py
/gem5/src/mem/slicc/symbols/StateMachine.py
11095:12c36d719139 14-Sep-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: slicc: remove member buffer_expr from Var class
This was added by changeset 51f40b101a56. Instead, buffer_expr would now be
associated with the InPort class.

11062:262d8494b253 30-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: slicc: avoid duplicate code for function argument check
Both FuncCallExprAST and MethodCallExprAST had code for checking the arguments
with which a function is being called. The patch does away with this
duplication. Now the code for checking function call arguments resides in the
Func class.

11049:dfb0aa3f0649 19-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: reverts to changeset: bf82f1f7b040


/gem5/configs/ruby/Ruby.py
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.hh
/gem5/src/cpu/testers/rubytest/RubyTester.hh
/gem5/src/mem/protocol/MESI_Three_Level-L0cache.sm
/gem5/src/mem/protocol/MESI_Three_Level-L1cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-L1cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-L2cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-dir.sm
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_hammer-cache.sm
/gem5/src/mem/protocol/MOESI_hammer-dir.sm
/gem5/src/mem/protocol/RubySlicc_Types.sm
/gem5/src/mem/ruby/common/DataBlock.hh
/gem5/src/mem/ruby/common/Histogram.cc
/gem5/src/mem/ruby/common/Histogram.hh
/gem5/src/mem/ruby/common/SubBlock.cc
/gem5/src/mem/ruby/common/SubBlock.hh
/gem5/src/mem/ruby/common/TypeDefines.hh
/gem5/src/mem/ruby/filters/H3BloomFilter.cc
/gem5/src/mem/ruby/filters/H3BloomFilter.hh
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.hh
/gem5/src/mem/ruby/network/MessageBuffer.cc
/gem5/src/mem/ruby/network/MessageBuffer.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/flit.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/flit.hh
/gem5/src/mem/ruby/network/simple/PerfectSwitch.cc
/gem5/src/mem/ruby/network/simple/PerfectSwitch.hh
/gem5/src/mem/ruby/network/simple/SimpleNetwork.cc
/gem5/src/mem/ruby/network/simple/SimpleNetwork.hh
/gem5/src/mem/ruby/network/simple/Switch.cc
/gem5/src/mem/ruby/network/simple/Throttle.cc
/gem5/src/mem/ruby/network/simple/Throttle.hh
/gem5/src/mem/ruby/profiler/AccessTraceForAddress.hh
/gem5/src/mem/ruby/profiler/AddressProfiler.cc
/gem5/src/mem/ruby/profiler/AddressProfiler.hh
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/profiler/StoreTrace.cc
/gem5/src/mem/ruby/profiler/StoreTrace.hh
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/structures/AbstractReplacementPolicy.cc
/gem5/src/mem/ruby/structures/AbstractReplacementPolicy.hh
/gem5/src/mem/ruby/structures/BankedArray.cc
/gem5/src/mem/ruby/structures/BankedArray.hh
/gem5/src/mem/ruby/structures/CacheMemory.cc
/gem5/src/mem/ruby/structures/CacheMemory.hh
/gem5/src/mem/ruby/structures/DirectoryMemory.cc
/gem5/src/mem/ruby/structures/DirectoryMemory.hh
/gem5/src/mem/ruby/structures/LRUPolicy.cc
/gem5/src/mem/ruby/structures/LRUPolicy.hh
/gem5/src/mem/ruby/structures/PseudoLRUPolicy.cc
/gem5/src/mem/ruby/structures/PseudoLRUPolicy.hh
/gem5/src/mem/ruby/structures/RubyMemoryControl.cc
/gem5/src/mem/ruby/structures/RubyMemoryControl.hh
/gem5/src/mem/ruby/system/CacheRecorder.cc
/gem5/src/mem/ruby/system/CacheRecorder.hh
/gem5/src/mem/ruby/system/RubySystem.py
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/ruby/system/System.hh
EnumDeclAST.py
FormalParamAST.py
FuncCallExprAST.py
FuncDeclAST.py
InPortDeclAST.py
MethodCallExprAST.py
StateDeclAST.py
/gem5/src/mem/slicc/parser.py
/gem5/src/mem/slicc/symbols/Func.py
/gem5/src/mem/slicc/symbols/StateMachine.py
11030:17240f381d6a 14-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: slicc: use default argument value
Before this patch, while one could declare / define a function with default
argument values, but the actual function call would require one to specify
all the arguments. This patch changes the check for function arguments.
Now a function call needs to specify arguments that are at least as much as
those with default values and at most the total number of arguments taken
as input by the function.

11029:32604f9e190b 14-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: slicc: avoid duplicate code for function argument check
Both FuncCallExprAST and MethodCallExprAST had code for checking the arguments
with which a function is being called. The patch does away with this
duplication. Now the code for checking function call arguments resides in the
Func class.

11025:4872dbdea907 14-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: replace Address by Addr
This patch eliminates the type Address defined by the ruby memory system.
This memory system would now use the type Addr that is in use by the
rest of the system.


/gem5/src/cpu/testers/rubytest/Check.cc
/gem5/src/cpu/testers/rubytest/Check.hh
/gem5/src/cpu/testers/rubytest/CheckTable.cc
/gem5/src/cpu/testers/rubytest/CheckTable.hh
/gem5/src/cpu/testers/rubytest/RubyTester.hh
/gem5/src/mem/protocol/MESI_Three_Level-L0cache.sm
/gem5/src/mem/protocol/MESI_Three_Level-L1cache.sm
/gem5/src/mem/protocol/MESI_Three_Level-msg.sm
/gem5/src/mem/protocol/MESI_Two_Level-L1cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-L2cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-dir.sm
/gem5/src/mem/protocol/MESI_Two_Level-dma.sm
/gem5/src/mem/protocol/MESI_Two_Level-msg.sm
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MI_example-dma.sm
/gem5/src/mem/protocol/MI_example-msg.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-msg.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_token-msg.sm
/gem5/src/mem/protocol/MOESI_hammer-cache.sm
/gem5/src/mem/protocol/MOESI_hammer-dir.sm
/gem5/src/mem/protocol/MOESI_hammer-dma.sm
/gem5/src/mem/protocol/MOESI_hammer-msg.sm
/gem5/src/mem/protocol/Network_test-cache.sm
/gem5/src/mem/protocol/Network_test-dir.sm
/gem5/src/mem/protocol/Network_test-msg.sm
/gem5/src/mem/protocol/RubySlicc_ComponentMapping.sm
/gem5/src/mem/protocol/RubySlicc_Defines.sm
/gem5/src/mem/protocol/RubySlicc_Exports.sm
/gem5/src/mem/protocol/RubySlicc_MemControl.sm
/gem5/src/mem/protocol/RubySlicc_Types.sm
/gem5/src/mem/protocol/RubySlicc_Util.sm
/gem5/src/mem/ruby/common/Address.cc
/gem5/src/mem/ruby/common/Address.hh
/gem5/src/mem/ruby/common/SubBlock.cc
/gem5/src/mem/ruby/common/SubBlock.hh
/gem5/src/mem/ruby/common/TypeDefines.hh
/gem5/src/mem/ruby/filters/AbstractBloomFilter.hh
/gem5/src/mem/ruby/filters/BlockBloomFilter.cc
/gem5/src/mem/ruby/filters/BlockBloomFilter.hh
/gem5/src/mem/ruby/filters/BulkBloomFilter.cc
/gem5/src/mem/ruby/filters/BulkBloomFilter.hh
/gem5/src/mem/ruby/filters/GenericBloomFilter.cc
/gem5/src/mem/ruby/filters/GenericBloomFilter.hh
/gem5/src/mem/ruby/filters/H3BloomFilter.cc
/gem5/src/mem/ruby/filters/H3BloomFilter.hh
/gem5/src/mem/ruby/filters/LSB_CountingBloomFilter.cc
/gem5/src/mem/ruby/filters/LSB_CountingBloomFilter.hh
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.hh
/gem5/src/mem/ruby/filters/MultiGrainBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiGrainBloomFilter.hh
/gem5/src/mem/ruby/filters/NonCountingBloomFilter.cc
/gem5/src/mem/ruby/filters/NonCountingBloomFilter.hh
/gem5/src/mem/ruby/network/MessageBuffer.cc
/gem5/src/mem/ruby/network/MessageBuffer.hh
/gem5/src/mem/ruby/profiler/AccessTraceForAddress.hh
/gem5/src/mem/ruby/profiler/AddressProfiler.cc
/gem5/src/mem/ruby/profiler/AddressProfiler.hh
/gem5/src/mem/ruby/profiler/StoreTrace.cc
/gem5/src/mem/ruby/profiler/StoreTrace.hh
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
/gem5/src/mem/ruby/slicc_interface/AbstractController.cc
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/slicc_interface/RubyRequest.cc
/gem5/src/mem/ruby/slicc_interface/RubyRequest.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
/gem5/src/mem/ruby/structures/CacheMemory.cc
/gem5/src/mem/ruby/structures/CacheMemory.hh
/gem5/src/mem/ruby/structures/DirectoryMemory.cc
/gem5/src/mem/ruby/structures/DirectoryMemory.hh
/gem5/src/mem/ruby/structures/MemoryNode.hh
/gem5/src/mem/ruby/structures/PerfectCacheMemory.hh
/gem5/src/mem/ruby/structures/PersistentTable.cc
/gem5/src/mem/ruby/structures/PersistentTable.hh
/gem5/src/mem/ruby/structures/Prefetcher.cc
/gem5/src/mem/ruby/structures/Prefetcher.hh
/gem5/src/mem/ruby/structures/RubyMemoryControl.cc
/gem5/src/mem/ruby/structures/RubyMemoryControl.hh
/gem5/src/mem/ruby/structures/TBETable.hh
/gem5/src/mem/ruby/structures/TimerTable.cc
/gem5/src/mem/ruby/structures/TimerTable.hh
/gem5/src/mem/ruby/system/CacheRecorder.cc
/gem5/src/mem/ruby/system/CacheRecorder.hh
/gem5/src/mem/ruby/system/DMASequencer.cc
/gem5/src/mem/ruby/system/DMASequencer.hh
/gem5/src/mem/ruby/system/RubyPort.cc
/gem5/src/mem/ruby/system/RubyPort.hh
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/Sequencer.hh
/gem5/src/mem/ruby/system/System.cc
ActionDeclAST.py
InPortDeclAST.py
StallAndWaitStatementAST.py
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/mem/slicc/symbols/Type.py
11021:e8a6637afa4c 14-Aug-2015 Joel Hestness <jthestness@gmail.com>

ruby: Expose MessageBuffers as SimObjects

Expose MessageBuffers from SLICC controllers as SimObjects that can be
manipulated in Python. This patch has numerous benefits:
1) First and foremost, it exposes MessageBuffers as SimObjects that can be
manipulated in Python code. This allows parameters to be set and checked in
Python code to avoid obfuscating parameters within protocol files. Further, now
as SimObjects, MessageBuffer parameters are printed to config output files as a
way to track parameters across simulations (e.g. buffer sizes)

2) Cleans up special-case code for responseFromMemory buffers, and aligns their
instantiation and use with mandatoryQueue buffers. These two special buffers
are the only MessageBuffers that are exposed to components outside of SLICC
controllers, and they're both slave ends of these buffers. They should be
exposed outside of SLICC in the same way, and this patch does it.

3) Distinguishes buffer-specific parameters from buffer-to-network parameters.
Specifically, buffer size, randomization, ordering, recycle latency, and ports
are all specific to a MessageBuffer, while the virtual network ID and type are
intrinsics of how the buffer is connected to network ports. The former are
specified in the Python object, while the latter are specified in the
controller *.sm files. Unlike buffer-specific parameters, which may need to
change depending on the simulated system structure, buffer-to-network
parameters can be specified statically for most or all different simulated
systems.

11020:882ce080c9f7 14-Aug-2015 Joel Hestness <jthestness@gmail.com>

ruby: Change PerfectCacheMemory::lookup to return pointer

CacheMemory and DirectoryMemory lookup functions return pointers to entries
stored in the memory. Bring PerfectCacheMemory in line with this convention,
and clean up SLICC code generation that was in place solely to handle
references like that which was returned by PerfectCacheMemory::lookup.

11016:bc759340631f 11-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: slicc: allow mathematical operations on Ticks

10984:a86f453a7caa 20-Jul-2015 Brad Beckmann <Brad.Beckmann@amd.com>

slicc: enable overloading in functions not in classes

For many years the slicc symbol table has supported overloaded functions in
external classes. This patch extends that support to functions that are not
part of classes (a.k.a. no parent). For example, this support allows slicc
to understand that mapAddressToRange is overloaded and the NodeID is an
optional parameter.

10981:b300dcda5896 20-Jul-2015 Brad Beckmann <Brad.Beckmann@amd.com>

slicc: improved stalling support in protocols

Adds features to allow protocols to reschedule controllers when conditionally
stalling within inport logic or actions. Also insures that resource and
protocol stalls are re-evaluated the next cycle.

10972:53d63eeee46f 20-Jul-2015 David Hashe <david.hashe@amd.com>

slicc: support for arbitrary DPRINTF flags (not just RubySlicc)

This patch allows DPRINTFs to be used in SLICC state machines similar to how
they are used by the rest of gem5. Previously all DPRINTFs in the .sm files
had to use the RubySlicc flag.

10971:3ed88c8334f1 20-Jul-2015 David Hashe <david.hashe@amd.com>

slicc: support for local variable declarations in action blocks

10967:b36204de88c0 20-Jul-2015 David Hashe <david.hashe@amd.com>

slicc: Fix bug in enqueue and peek statements.

These were not generating the correct c names for types declared within a
machine scope.

10966:198726a3c723 20-Jul-2015 David Hashe <david.hashe@amd.com>

slicc: fix missing inline function in LocalVariableAST

10965:6f433e7f9767 20-Jul-2015 David Hashe <david.hashe@amd.com>

slicc: improve support for prefix operations

This patch fixes the type handling when prefix operations are used. Previously
prefix operators would assume a void return type, which made it impossible to
combine prefix operations with other expressions. This patch allows SLICC
programmers to use prefix operations more naturally.

10963:51f40b101a56 20-Jul-2015 David Hashe <david.hashe@amd.com>

slicc: support for multiple message types on the same buffer

This patch allows SLICC protocols to use more than one message type with a
message buffer. For example, you can declare two in ports as such:

in_port(ResponseQueue_in, ResponseMsg, responseFromDir, rank=3) { ... }
in_port(tgtResponseQueue_in, TgtResponseMsg, responseFromDir, rank=2) { ... }

10895:287285860dd6 04-Jul-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: drop NetworkMessage class

This patch drops the NetworkMessage class. The relevant data members and functions
have been moved to the Message class, which was the parent of NetworkMessage.

10521:ca248520649f 06-Nov-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: slicc: allow adding a bool to an int, like C++.

10472:399f35ed5cca 16-Oct-2014 Andreas Hansson <andreas.hansson@arm.com>

mem: Use shared_ptr for Ruby Message classes

This patch transitions the Ruby Message and its derived classes from
the ad-hoc RefCountingPtr to the c++11 shared_ptr. There are no
changes in behaviour, and the code modifications are mainly replacing
"new" with "make_shared".

The cloning of derived messages is slightly changed as they previously
relied on overriding the base-class through covariant return types.

10308:8c0870dbae5c 01-Sep-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: slicc: change the way configurable members are specified
There are two changes this patch makes to the way configurable members of a
state machine are specified in SLICC. The first change is that the data
member declarations will need to be separated by a semi-colon instead of a
comma. Secondly, the default value to be assigned would now use SLICC's
assignment operator i.e. ':='.

10307:6df951dcd7d9 01-Sep-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: slicc: improve the grammar
This patch changes the grammar for SLICC so as to remove some of the
redundant / duplicate rules. In particular rules for object/variable
declaration and class member declaration have been unified. Similarly, the
rules for a general function and a class method have been unified.

One more change is in the priority of two rules. The first rule is on
declaring a function with all the params typed and named. The second rule is
on declaring a function with all the params only typed. Earlier the second
rule had a higher priority. Now the first rule has a higher priority.

10305:76745b567dc3 01-Sep-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: slicc: donot prefix machine name to variables
This changeset does away with prefixing of member variables of state machines
with the identity of the machine itself.

10231:cb2e6950956d 31-May-2014 Steve Reinhardt <steve.reinhardt@amd.com>

style: eliminate equality tests with true and false

Using '== true' in a boolean expression is totally redundant,
and using '== false' is pretty verbose (and arguably less
readable in most cases) compared to '!'.

It's somewhat of a pet peeve, perhaps, but I had some time
waiting for some tests to run and decided to clean these up.

Unfortunately, SLICC appears not to have the '!' operator,
so I had to leave the '== false' tests in the SLICC code.

10226:056363356d15 23-May-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: message buffer: drop dequeue_getDelayCycles()
The functionality of updating and returning the delay cycles would now be
performed by the dequeue() function itself.

10165:7e9edf4297a9 19-Apr-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: slicc: slight change to rule for transitions
It had an unnecessary pairs token which is being removed.

10155:3b0bcc8c34ca 08-Apr-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: slicc: change enqueue statement
As of now, the enqueue statement can take in any number of 'pairs' as
argument. But we only use the pair in which latency is the key. This
latency is allowed to be either a fixed integer or a member variable of
controller in which the expression appears. This patch drops the use of pairs
in an enqueue statement. Instead, an expression is allowed which will be
interpreted to be the latency of the enqueue. This expression can anything
allowed by slicc including a constant integer or a member variable.

10085:b9891fbae4c8 23-Feb-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: slicc: remove unused COPY_HEAD functionality

10075:7322d2b2ec76 20-Feb-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: slicc: slight code refactoring

10009:8523754f8885 08-Jan-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: slicc: remove variable 'addr' used in calls to doTransition
This variable causes trouble if a variable of same name is declared in a
protocol file. Hence it is being eliminated.

10005:8c2b0dc16ccd 04-Jan-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: add support for clusters

A cluster over here means a set of controllers that can be accessed only by a
certain set of cores. For example, consider a two level hierarchy. Assume
there are 4 L1 controllers (private) and 2 L2 controllers. We can have two
different hierarchies here:

a. the address space is partitioned between the two L2 controllers. Each L1
controller accesses both the L2 controllers. In this case, each L1 controller
is a cluster initself.

b. both the L2 controllers can cache any address. An L1 controller has access
to only one of the L2 controllers. In this case, each L2 controller
along with the L1 controllers that access it, form a cluster.

This patch allows for each controller to have a cluster ID, which is 0 by
default. By setting the cluster ID properly, one can instantiate hierarchies
with clusters. Note that the coherence protocol might have to be changed as
well.

9996:150338b8ba12 20-Dec-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: slicc: replace max_in_port_rank with number of inports

This patch replaces max_in_port_rank with the number of inports. The use of
max_in_port_rank was causing spurious re-builds and incorrect initialization
of variables in ruby related regression tests. This was due to the variable
value being used across threads while compiling when it was not meant to be.

Since the number of inports is state machine specific value, this problem
should get solved.

9820:2f9aecba2362 07-Aug-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: slicc: remove double trigger, continueProcessing
These constructs are not in use and are not being maintained by any one.
In addition, it is not known if doubleTrigger works correctly with Ruby now.

9804:6a043adb1e8d 11-Jul-2013 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: removed the very old double trigger hack

Committed by: Nilay Vaish <nilay@cs.wisc.edu>

9773:915be89faf30 25-Jun-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: profiler: lots of inter-related changes
The patch started of with removing the global variables from the profiler for
profiling the miss latency of requests made to the cache. The corrresponding
histograms have been moved to the Sequencer. These are combined together when
the histograms are printed. Separate histograms are now maintained for
tracking latency of all requests together, of hits only and of misses only.

A particular set of histograms used to use the type GenericMachineType defined
in one of the protocol files. This patch removes this type. Now, everything
that relied on this type would use MachineType instead. To do this, SLICC has
been changed so that multiple machine types can be declared by a controller
in its preamble.

9745:884ad4638236 09-Jun-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: stats: use gem5's stats for cache and memory controllers
This moves event and transition count statistics for cache controllers to
gem5's statistics. It does the same for the statistics associated with the
memory controller in ruby.

All the cache/directory/dma controllers individually collect the event and
transition counts. A callback function, collateStats(), has been added that
is invoked on the controller version 0 of each controller class. This
function adds all the individual controller statistics to a vector
variables. All the code for registering the statistical variables and
collating them is generated by SLICC. The patch removes the files
*_Profiler.{cc,hh} and *_ProfileDumper.{cc,hh} which were earlier used for
collecting and dumping statistics respectively.

9703:782b7284de21 21-May-2013 Malek Musleh <malek.musleh@gmail.com>

ruby: slicc: fix error msg in TypeFieldMemberAST.py

9692:67d9da312ef0 21-May-2013 Nilay Vaish <nilay@cs.wisc.edu>, Malek Musleh <malek.musleh@gmail.com>

ruby: add stats to .sm files, remove cache profiler
This patch changes the way cache statistics are collected in ruby.

As of now, there is separate entity called CacheProfiler which holds
statistical variables for caches. The CacheMemory class defines different
functions for accessing the CacheProfiler. These functions are then invoked
in the .sm files. I find this approach opaque and prone to error. Secondly,
we probably should not be paying the cost of a function call for recording
statistics.

Instead, this patch allows for accessing statistical variables in the
.sm files. The collection would become transparent. Secondly, it would happen
in place, so no function calls. The patch also removes the CacheProfiler class.

9628:195d92059654 09-Apr-2013 Jason Power <powerjg@cs.wisc.edu>

Ruby: Fix typo in Slicc if-statement AST error

The error in the SLICC code was hidden by the python error in SLICC parser
before this patch

9595:470016acf37d 22-Mar-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: connect two controllers using only message buffers
This patch modifies ruby so that two controllers can be connected to each
other with only message buffers in between. Before this patch, all the
controllers had to be connected to the network for them to communicate
with each other. With this patch, one can have protocols where a controller
is not connected to the network, but communicates with another controller
through a message buffer.

9508:dde110931867 10-Feb-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: enable multiple clock domains
This patch allows ruby to have multiple clock domains. As I understand
with this patch, controllers can have different frequencies. The entire
network needs to run at a single frequency.

The idea is that with in an object, time is treated in terms of cycles.
But the messages that are passed from one entity to another should contain
the time in Ticks. As of now, this is only true for the message buffers,
but not for the links in the network. As I understand the code, all the
entities in different networks (simple, garnet-fixed, garnet-flexible) should
be clocked at the same frequency.

Another problem is that the directory controller has to operate at the same
frequency as the ruby system. This is because the memory controller does
not make use of the Message Buffer, and instead implements a buffer of its
own. So, it has no idea of the frequency at which the directory controller
is operating and uses ruby system's frequency for scheduling events.

9507:d2ab6d889fc7 10-Feb-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: replace Time with Cycles (final patch in the series)
This patch is as of now the final patch in the series of patches that replace
Time with Cycles.This patch further replaces Time with Cycles in Sequencer,
Profiler, different protocols and related entities.

Though Time has not been completely removed, the places where it is in use
seem benign as of now.

9499:b03b556a8fbb 10-Feb-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: replaces Time with Cycles in many places
The patch started of with replacing Time with Cycles in the Consumer class.
But to get ruby to compile, the rest of the changes had to be carried out.
Subsequent patches will further this process, till we completely replace
Time with Cycles.


/gem5/src/mem/protocol/MESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MESI_CMP_directory-dma.sm
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MI_example-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dma.sm
/gem5/src/mem/protocol/MOESI_hammer-cache.sm
/gem5/src/mem/protocol/MOESI_hammer-dir.sm
/gem5/src/mem/protocol/MOESI_hammer-dma.sm
/gem5/src/mem/protocol/Network_test-cache.sm
/gem5/src/mem/protocol/RubySlicc_Exports.sm
/gem5/src/mem/protocol/RubySlicc_Types.sm
/gem5/src/mem/protocol/RubySlicc_Util.sm
/gem5/src/mem/ruby/buffers/MessageBuffer.cc
/gem5/src/mem/ruby/buffers/MessageBuffer.hh
/gem5/src/mem/ruby/buffers/MessageBufferNode.hh
/gem5/src/mem/ruby/common/Consumer.cc
/gem5/src/mem/ruby/common/Consumer.hh
/gem5/src/mem/ruby/network/BasicLink.hh
/gem5/src/mem/ruby/network/BasicLink.py
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/SWallocator_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/VCallocator_d.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.py
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/Router.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/Router.hh
/gem5/src/mem/ruby/network/simple/PerfectSwitch.cc
/gem5/src/mem/ruby/network/simple/Switch.cc
/gem5/src/mem/ruby/network/simple/Switch.hh
/gem5/src/mem/ruby/network/simple/Throttle.cc
/gem5/src/mem/ruby/network/simple/Throttle.hh
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/slicc_interface/Controller.py
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
/gem5/src/mem/ruby/system/Cache.py
/gem5/src/mem/ruby/system/CacheMemory.hh
/gem5/src/mem/ruby/system/RubyMemoryControl.cc
/gem5/src/mem/ruby/system/RubyMemoryControl.hh
/gem5/src/mem/ruby/system/RubyMemoryControl.py
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/TimerTable.cc
/gem5/src/mem/ruby/system/TimerTable.hh
/gem5/src/mem/ruby/system/WireBuffer.cc
/gem5/src/mem/ruby/system/WireBuffer.hh
EnqueueStatementAST.py
FuncCallExprAST.py
InfixOperatorExprAST.py
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/mem/slicc/symbols/Type.py
9483:c2d205f278fc 28-Jan-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: remove call to curCycle in panic()
The panic() function already prints the current tick value. This call to
curCycle() is as such redundant. Since we are trying to move towards multiple
clock domains, this call will print misleading time.

9466:23e13ad7091f 14-Jan-2013 Nilay Vaish <nilay@cs.wisc.edu>

Ruby: remove reference to g_system_ptr from class Message
This patch was initiated so as to remove reference to g_system_ptr,
the pointer to Ruby System that is used for getting the current time.
That simple change actual requires changing a lot many things in slicc and
garnet. All these changes are related to how time is handled.

In most of the places, g_system_ptr has been replaced by another clock
object. The changes have been done under the assumption that all the
components in the memory system are on the same clock frequency, but the
actual clocks might be distributed.


/gem5/src/mem/ruby/common/Global.hh
/gem5/src/mem/ruby/network/garnet/BaseGarnetNetwork.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/RoutingUnit_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/SWallocator_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/VCallocator_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/VirtualChannel_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/VirtualChannel_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/flitBuffer_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/flitBuffer_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/flit_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/flit_d.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/Router.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/flit.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/flit.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/flitBuffer.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/flitBuffer.hh
/gem5/src/mem/ruby/network/orion/NetworkPower.cc
/gem5/src/mem/ruby/slicc_interface/Message.hh
/gem5/src/mem/ruby/slicc_interface/NetworkMessage.hh
/gem5/src/mem/ruby/slicc_interface/RubyRequest.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
/gem5/src/mem/ruby/structures/Prefetcher.hh
/gem5/src/mem/ruby/system/DMASequencer.cc
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/WireBuffer.cc
EnqueueStatementAST.py
/gem5/src/mem/slicc/symbols/Type.py
9465:4ae4f3f4b870 14-Jan-2013 Nilay Vaish <nilay@cs.wisc.edu>

Ruby: use ClockedObject in Consumer class
Many Ruby structures inherit from the Consumer, which is used for scheduling
events. The Consumer used to relay on an Event Manager for scheduling events
and on g_system_ptr for time. With this patch, the Consumer will now use a
ClockedObject to schedule events and to query for current time. This resulted
in several structures being converted from SimObjects to ClockedObjects. Also,
the MessageBuffer class now requires a pointer to a ClockedObject so as to
query for time.


/gem5/src/mem/protocol/RubySlicc_Profiler.sm
/gem5/src/mem/protocol/RubySlicc_Types.sm
/gem5/src/mem/ruby/buffers/MessageBuffer.cc
/gem5/src/mem/ruby/buffers/MessageBuffer.hh
/gem5/src/mem/ruby/common/Consumer.cc
/gem5/src/mem/ruby/common/Consumer.hh
/gem5/src/mem/ruby/network/BasicRouter.cc
/gem5/src/mem/ruby/network/BasicRouter.hh
/gem5/src/mem/ruby/network/BasicRouter.py
/gem5/src/mem/ruby/network/Network.cc
/gem5/src/mem/ruby/network/Network.hh
/gem5/src/mem/ruby/network/Network.py
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/FlexibleConsumer.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.py
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.hh
/gem5/src/mem/ruby/network/simple/PerfectSwitch.cc
/gem5/src/mem/ruby/network/simple/PerfectSwitch.hh
/gem5/src/mem/ruby/network/simple/Switch.cc
/gem5/src/mem/ruby/network/simple/Throttle.cc
/gem5/src/mem/ruby/network/simple/Throttle.hh
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/slicc_interface/AbstractController.cc
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/slicc_interface/Controller.py
/gem5/src/mem/ruby/slicc_interface/Message.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.cc
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.hh
/gem5/src/mem/ruby/system/MemoryControl.hh
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/TimerTable.cc
/gem5/src/mem/ruby/system/TimerTable.hh
AST.py
/gem5/src/mem/slicc/symbols/StateMachine.py
9366:bf8eb26c7b7e 11-Dec-2012 Nilay Vaish <nilay@cs.wisc.edu>

ruby: add support for prefetching to MESI protocol

9302:c2e70a9bc340 15-Oct-2012 Nilay Vaish <nilay@cs.wisc.edu>

ruby: improved support for functional accesses
This patch adds support to different entities in the ruby memory system
for more reliable functional read/write accesses. Only the simple network
has been augmented as of now. Later on Garnet will also support functional
accesses.
The patch adds functional access code to all the different types of messages
that protocols can send around. These messages are functionally accessed
by going through the buffers maintained by the network entities.
The patch also rectifies some of the bugs found in coherence protocols while
testing the patch.

With this patch applied, functional writes always succeed. But functional
reads can still fail.


/gem5/configs/example/ruby_mem_test.py
/gem5/src/mem/protocol/MESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MESI_CMP_directory-msg.sm
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MI_example-msg.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-msg.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_token-msg.sm
/gem5/src/mem/protocol/MOESI_hammer-cache.sm
/gem5/src/mem/protocol/MOESI_hammer-dir.sm
/gem5/src/mem/protocol/MOESI_hammer-msg.sm
/gem5/src/mem/protocol/Network_test-msg.sm
/gem5/src/mem/protocol/RubySlicc_Exports.sm
/gem5/src/mem/protocol/RubySlicc_MemControl.sm
/gem5/src/mem/ruby/buffers/MessageBuffer.cc
/gem5/src/mem/ruby/buffers/MessageBuffer.hh
/gem5/src/mem/ruby/buffers/MessageBufferNode.hh
/gem5/src/mem/ruby/network/Network.hh
/gem5/src/mem/ruby/network/simple/PerfectSwitch.cc
/gem5/src/mem/ruby/network/simple/SimpleNetwork.cc
/gem5/src/mem/ruby/network/simple/SimpleNetwork.hh
/gem5/src/mem/ruby/network/simple/Switch.cc
/gem5/src/mem/ruby/network/simple/Switch.hh
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/slicc_interface/Message.hh
/gem5/src/mem/ruby/slicc_interface/NetworkMessage.hh
/gem5/src/mem/ruby/slicc_interface/RubyRequest.cc
/gem5/src/mem/ruby/slicc_interface/RubyRequest.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
/gem5/src/mem/ruby/system/MemoryControl.cc
/gem5/src/mem/ruby/system/MemoryControl.hh
/gem5/src/mem/ruby/system/RubyMemoryControl.cc
/gem5/src/mem/ruby/system/RubyMemoryControl.hh
/gem5/src/mem/ruby/system/System.cc
TypeDeclAST.py
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/mem/slicc/symbols/SymbolTable.py
/gem5/src/mem/slicc/symbols/Type.py
9298:9a087e046c58 15-Oct-2012 Nilay Vaish <nilay@cs.wisc.edu>

ruby: allow function definition in slicc structs
This patch adds support for function definitions to appear in slicc structs.
This is required for supporting functional accesses for different types of
messages. Subsequent patches will use this to development.

9271:3859f5d4f2c6 02-Oct-2012 Nilay Vaish <nilay@cs.wisc.edu>

ruby: remove some unused things in slicc
This patch removes the parts of slicc that were required for multi-chip
protocols. Going ahead, it seems multi-chip protocols would be implemented
by playing with the network itself.

9230:33eb3c8a98b9 18-Sep-2012 Nilay Vaish <nilay@cs.wisc.edu>

ruby: avoid using g_system_ptr for event scheduling
This patch removes the use of g_system_ptr for event scheduling. Each consumer
object now needs to specify upfront an EventManager object it would use for
scheduling events. This makes the ruby memory system more amenable for a
multi-threaded simulation.

9205:cc41d310241f 10-Sep-2012 Nilay Vaish <nilay@cs.wisc.edu>

Ruby Slicc: remove the call to cin.get() function
If I understand correctly, this was put in place so that a debugger can be
attached when the protocol aborts. While this sounds useful, it is a problem
when the simulation is not being actively monitored. I think it is better to
remove this.

9171:ae88ecf37145 27-Aug-2012 Nilay Vaish <nilay@cs.wisc.edu>

Ruby: Remove RubyEventQueue
This patch removes RubyEventQueue. Consumer objects now rely on RubySystem
or themselves for scheduling events.


/gem5/src/cpu/testers/directedtest/RubyDirectedTester.cc
/gem5/src/cpu/testers/rubytest/Check.cc
/gem5/src/cpu/testers/rubytest/RubyTester.cc
/gem5/src/mem/ruby/buffers/MessageBuffer.cc
/gem5/src/mem/ruby/buffers/MessageBuffer.hh
/gem5/src/mem/ruby/common/Consumer.cc
/gem5/src/mem/ruby/common/Consumer.hh
/gem5/src/mem/ruby/common/Global.cc
/gem5/src/mem/ruby/common/Global.hh
/gem5/src/mem/ruby/common/SConscript
/gem5/src/mem/ruby/common/TypeDefines.hh
/gem5/src/mem/ruby/eventqueue/RubyEventQueue.cc
/gem5/src/mem/ruby/eventqueue/RubyEventQueue.hh
/gem5/src/mem/ruby/eventqueue/RubyEventQueueNode.cc
/gem5/src/mem/ruby/eventqueue/RubyEventQueueNode.hh
/gem5/src/mem/ruby/eventqueue/SConscript
/gem5/src/mem/ruby/network/garnet/BaseGarnetNetwork.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/OutVcState_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/SWallocator_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/VCallocator_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/VirtualChannel_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/VirtualChannel_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/flitBuffer_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/flit_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/flit_d.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/Router.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/flit.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/flitBuffer.cc
/gem5/src/mem/ruby/network/orion/NetworkPower.cc
/gem5/src/mem/ruby/network/simple/PerfectSwitch.cc
/gem5/src/mem/ruby/network/simple/Throttle.cc
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/profiler/StoreTrace.cc
/gem5/src/mem/ruby/profiler/StoreTrace.hh
/gem5/src/mem/ruby/slicc_interface/Message.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
/gem5/src/mem/ruby/system/CacheMemory.cc
/gem5/src/mem/ruby/system/CacheMemory.hh
/gem5/src/mem/ruby/system/RubyMemoryControl.cc
/gem5/src/mem/ruby/system/RubyPort.cc
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/Sequencer.hh
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/ruby/system/System.hh
/gem5/src/mem/ruby/system/TimerTable.cc
/gem5/src/mem/ruby/system/TimerTable.hh
/gem5/src/mem/ruby/system/WireBuffer.cc
/gem5/src/mem/ruby/system/WireBuffer.hh
AST.py
FuncCallExprAST.py
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/mem/slicc/symbols/Type.py
9106:aa9b75db7ea0 11-Jul-2012 Brad Beckmann <Brad.Beckmann@amd.com>

imported patch jason/slicc-external-structure-fix

9104:27d56b644e78 11-Jul-2012 Joel Hestness <hestness@cs.utexas.edu>

ruby: tag and data cache access support

Updates to Ruby to support statistics counting of cache accesses. This feature
serves multiple purposes beyond simple stats collection. It provides the
foundation for ruby to model the cache tag and data arrays as physical
resources, as well as provide the necessary input data for McPAT power
modeling.

8936:c04af06738e0 06-Apr-2012 Brad Beckmann <Brad.Beckmann@amd.com>

slicc: fixed error message when the type has no inheritance

8644:acf68e5a8cd7 31-Dec-2011 Nilay Vaish<nilay@cs.wisc.edu>

SLICC: Use pointers for directory entries
SLICC uses pointers for cache and TBE entries but not for directory entries.
This patch changes the protocols, SLICC and Ruby memory system so that even
directory entries are referenced using pointers.

8641:4d3ecac1abec 13-Dec-2011 Nathan Binkert <nate@binkert.org>

gcc: fix unused variable warnings from GCC 4.6.1

8531:bfc59fbde824 29-Aug-2011 Nilay Vaish<nilay@cs.wisc.edu>

SLICC: Pass arguments by reference
Arguments to functions were being passed by value. This patch
changes SLICC so that arguments are passed by reference.

8478:435179113834 27-Jul-2011 Nilay Vaish<nilay@cs.wisc.edu>

SLICC: Put functions of a controller in its .cc file
Currently, functions associated with a controller go into separate files.
This patch puts all the functions in the controller's .cc file. This should
hopefully take away some time from compilation.

8453:82fc1267d3bb 05-Jul-2011 Nathan Binkert <nate@binkert.org>

slicc: cleanup slicc code and make it less verbose

8452:3f2c329e9046 05-Jul-2011 Nathan Binkert <nate@binkert.org>

grammar: better encapsulation of a grammar and parsing
This makes it possible to use the grammar multiple times and use the multiple
instances concurrently. This makes implementing an include statement as part
of a grammar possible.

8436:5648986156db 30-Jun-2011 Brad Beckmann <Brad.Beckmann@amd.com>, Nilay Vaish <nilay@cs.wisc.edu>

Ruby: Add support for functional accesses
This patch rpovides functional access support in Ruby. Currently only
the M5Port of RubyPort supports functional accesses. The support for
functional through the PioPort will be added as a separate patch.


/gem5/configs/example/ruby_direct_test.py
/gem5/configs/example/ruby_fs.py
/gem5/configs/example/ruby_mem_test.py
/gem5/configs/example/ruby_network_test.py
/gem5/configs/example/ruby_random_test.py
/gem5/configs/example/se.py
/gem5/configs/ruby/MESI_CMP_directory.py
/gem5/configs/ruby/MI_example.py
/gem5/configs/ruby/MOESI_CMP_directory.py
/gem5/configs/ruby/MOESI_CMP_token.py
/gem5/configs/ruby/MOESI_hammer.py
/gem5/configs/ruby/Ruby.py
/gem5/src/cpu/testers/memtest/MemTest.py
/gem5/src/cpu/testers/memtest/memtest.cc
/gem5/src/cpu/testers/memtest/memtest.hh
/gem5/src/mem/packet.cc
/gem5/src/mem/packet.hh
/gem5/src/mem/protocol/MESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MESI_CMP_directory-dma.sm
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MI_example-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dma.sm
/gem5/src/mem/protocol/MOESI_hammer-cache.sm
/gem5/src/mem/protocol/MOESI_hammer-dir.sm
/gem5/src/mem/protocol/MOESI_hammer-dma.sm
/gem5/src/mem/protocol/RubySlicc_Exports.sm
/gem5/src/mem/ruby/network/Network.cc
/gem5/src/mem/ruby/network/Network.py
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.py
/gem5/src/mem/ruby/recorder/Tracer.cc
/gem5/src/mem/ruby/recorder/Tracer.py
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/slicc_interface/Controller.py
/gem5/src/mem/ruby/slicc_interface/SConscript
/gem5/src/mem/ruby/system/Cache.py
/gem5/src/mem/ruby/system/DirectoryMemory.cc
/gem5/src/mem/ruby/system/DirectoryMemory.py
/gem5/src/mem/ruby/system/RubyPort.cc
/gem5/src/mem/ruby/system/RubyPort.hh
/gem5/src/mem/ruby/system/RubySystem.py
/gem5/src/mem/ruby/system/SConscript
/gem5/src/mem/ruby/system/Sequencer.py
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/ruby/system/System.hh
MemberExprAST.py
/gem5/tests/configs/memtest-ruby.py
/gem5/tests/configs/rubytest-ruby.py
/gem5/tests/configs/simple-timing-mp-ruby.py
/gem5/tests/configs/simple-timing-ruby.py
8341:30daf1dd5c91 08-Jun-2011 Nilay Vaish<nilay@cs.wisc.edu>

Ruby: Correctly set access permissions for directory entries
The access permissions for the directory entries are not being set correctly.
This is because pointers are not used for handling directory entries.
function. get and set functions for access permissions have been added to the
Controller state machine. The changePermission() function provided by the
AbstractEntry and AbstractCacheEntry classes has been exposed to SLICC
code once again. The set_permission() functionality has been removed.

NOTE: Each protocol will have to define these get and set functions in order
to compile successfully.

8192:be38f7b6ad9e 31-Mar-2011 Lisa Hsu <Lisa.Hsu@amd.com>

Ruby: Simplify SLICC and Entry/TBE handling.
Before this changeset, all local variables of type Entry and TBE were considered
to be pointers, but an immediate use of said variables would not be automatically
deferenced in SLICC-generated code. Instead, deferences occurred when such
variables were passed to functions, and were automatically dereferenced in
the bodies of the functions (e.g. the implicitly passed cache_entry).

This is a more general way to do it, which leaves in place the
assumption that parameters to functions and local variables of type AbstractCacheEntry
and TBE are always pointers, but instead of dereferencing to access member variables
on a contextual basis, the dereferencing automatically occurs on a type basis at the
moment a member is being accessed. So, now, things you can do that you couldn't before
include:

Entry foo := getCacheEntry(address);
cache_entry.DataBlk := foo.DataBlk;

or

cache_entry.DataBlk := getCacheEntry(address).DataBlk;

or even

cache_entry.DataBlk := static_cast(Entry, pointer, cache.lookup(address)).DataBlk;

8170:c1c6f36e118e 20-Mar-2011 Nilay Vaish<nilay@cs.wisc.edu>

SLICC: Remove WakeUp* import calls from ast/__init__.py
I had recently committed a patch that removed the WakeUp*.py files from the
slicc/ast directory. I had forgotten to remove the import calls for these
files from slicc/ast/__init__.py. This resulted in error while running
regressions on zizzer. This patch does the needful.

8155:099771c7725d 18-Mar-2011 Nilay Vaish<nilay@cs.wisc.edu>

SLICC: Remove the keyword wake_up_dependents
In order to add stall and wait facility for protocols, a keyword
wake_up_dependents was introduced. This patch removes the keyword,
instead this functionality is now implemented as function call.

8154:f3d1493787d4 18-Mar-2011 Nilay Vaish<nilay@cs.wisc.edu>

SLICC: Remove the keyword wake_up_all_dependents
In order to add stall and wait facility for protocols, a keyword
wake_up_all_dependents was introduced. This patch removes the keyword,
instead this functionality is now implemented as function call.

8086:bf0335d98250 23-Feb-2011 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: automate permission setting

This patch integrates permissions with cache and memory states, and then
automates the setting of permissions within the generated code. No longer
does one need to manually set the permissions within the setState funciton.
This patch will faciliate easier functional access support by always correctly
setting permissions for both cache and memory states.

8085:d1eb504fd302 23-Feb-2011 Brad Beckmann <Brad.Beckmann@amd.com>

MOESI_hammer: cache probe address clean up

7922:7532067f818e 07-Feb-2011 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: support to stallAndWait the mandatory queue

By stalling and waiting the mandatory queue instead of recycling it, one can
ensure that no incoming messages are starved when the mandatory queue puts
signficant of pressure on the L1 cache controller (i.e. the ruby memtester).

7839:9e556fb25900 17-Jan-2011 Nilay Vaish<nilay@cs.wisc.edu>

Change interface between coherence protocols and CacheMemory
The purpose of this patch is to change the way CacheMemory interfaces with
coherence protocols. Currently, whenever a cache controller (defined in the
protocol under consideration) needs to carry out any operation on a cache
block, it looks up the tag hash map and figures out whether or not the block
exists in the cache. In case it does exist, the operation is carried out
(which requires another lookup). As observed through profiling of different
protocols, multiple such lookups take place for a given cache block. It was
noted that the tag lookup takes anything from 10% to 20% of the simulation
time. In order to reduce this time, this patch is being posted.

I have to acknowledge that the many of the thoughts that went in to this
patch belong to Brad.

Changes to CacheMemory, TBETable and AbstractCacheEntry classes:
1. The lookup function belonging to CacheMemory class now returns a pointer
to a cache block entry, instead of a reference. The pointer is NULL in case
the block being looked up is not present in the cache. Similar change has
been carried out in the lookup function of the TBETable class.
2. Function for setting and getting access permission of a cache block have
been moved from CacheMemory class to AbstractCacheEntry class.
3. The allocate function in CacheMemory class now returns pointer to the
allocated cache entry.

Changes to SLICC:
1. Each action now has implicit variables - cache_entry and tbe. cache_entry,
if != NULL, must point to the cache entry for the address on which the action
is being carried out. Similarly, tbe should also point to the transaction
buffer entry of the address on which the action is being carried out.
2. If a cache entry or a transaction buffer entry is passed on as an
argument to a function, it is presumed that a pointer is being passed on.
3. The cache entry and the tbe pointers received __implicitly__ by the
actions, are passed __explicitly__ to the trigger function.
4. While performing an action, set/unset_cache_entry, set/unset_tbe are to
be used for setting / unsetting cache entry and tbe pointers respectively.
5. is_valid() and is_invalid() has been made available for testing whether
a given pointer 'is not NULL' and 'is NULL' respectively.
6. Local variables are now available, but they are assumed to be pointers
always.
7. It is now possible for an object of the derieved class to make calls to
a function defined in the interface.
8. An OOD token has been introduced in SLICC. It is same as the NULL token
used in C/C++. If you are wondering, OOD stands for Out Of Domain.
9. static_cast can now taken an optional parameter that asks for casting the
given variable to a pointer of the given type.
10. Functions can be annotated with 'return_by_pointer=yes' to return a
pointer.
11. StateMachine has two new variables, EntryType and TBEType. EntryType is
set to the type which inherits from 'AbstractCacheEntry'. There can only be
one such type in the machine. TBEType is set to the type for which 'TBE' is
used as the name.

All the protocols have been modified to conform with the new interface.

7793:f6cbeb8712d3 08-Dec-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: remove Ruby asserts for m5.fast

This diff is for changing the way ASSERT is handled in Ruby. m5.fast
compiles out the assert statements by using the macro NDEBUG. Ruby uses the
macro RUBY_NO_ASSERT to do so. This macro has been removed and NDEBUG has
been put in its place.

7780:42da07116e12 01-Dec-2010 Nilay Vaish <nilay@cs.wisc.edu>

ruby: Converted old ruby debug calls to M5 debug calls

This patch developed by Nilay Vaish converts all the old GEMS-style ruby
debug calls to the appropriate M5 debug calls.


/gem5/src/cpu/testers/rubytest/CheckTable.cc
/gem5/src/mem/SConscript
/gem5/src/mem/protocol/MESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-perfectDir.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_hammer-cache.sm
/gem5/src/mem/protocol/MOESI_hammer-dir.sm
/gem5/src/mem/ruby/SConsopts
/gem5/src/mem/ruby/buffers/MessageBuffer.cc
/gem5/src/mem/ruby/common/Debug.cc
/gem5/src/mem/ruby/common/Debug.hh
/gem5/src/mem/ruby/common/NetDest.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/Router.cc
/gem5/src/mem/ruby/network/simple/PerfectSwitch.cc
/gem5/src/mem/ruby/network/simple/Throttle.cc
/gem5/src/mem/ruby/network/simple/Topology.cc
/gem5/src/mem/ruby/storebuffer/storebuffer.cc
/gem5/src/mem/ruby/system/CacheMemory.cc
/gem5/src/mem/ruby/system/DirectoryMemory.cc
/gem5/src/mem/ruby/system/SConscript
/gem5/src/mem/ruby/system/SparseMemory.cc
/gem5/src/mem/ruby/tester/RaceyPseudoThread.cc
FuncCallExprAST.py
/gem5/src/mem/slicc/symbols/StateMachine.py
7567:238f99c9f441 20-Aug-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Stall and wait input messages instead of recycling

This patch allows messages to be stalled in their input buffers and wait
until a corresponding address changes state. In order to make this work,
all in_ports must be ranked in order of dependence and those in_ports that
may unblock an address, must wake up the stalled messages. Alot of this
complexity is handled in slicc and the specification files simply
annotate the in_ports.

7542:49327b849c7f 20-Aug-2010 Brad Beckmann <Brad.Beckmann@amd.com>

slicc: Consolidated the protocol stats printing

Created a separate ProfileDumper that consolidates the generated stats for
each controller of a certain type.

7453:1a5db3dd0f62 11-Jun-2010 Nathan Binkert <nate@binkert.org>

ruby: get rid of RefCnt and Allocator stuff use base/refcnt.hh

This was somewhat tricky because the RefCnt API was somewhat odd. The
biggest confusion was that the the RefCnt object's constructor that
took a TYPE& cloned the object. I created an explicit virtual clone()
function for things that took advantage of this version of the
constructor. I was conservative and used clone() when I was in doubt
of whether or not it was necessary. I still think that there are
probably too many instances of clone(), but hopefully not too many.

I converted several instances of const MsgPtr & to a simple MsgPtr.
If the function wants to avoid the overhead of creating another
reference, then it should just use a regular pointer instead of a ref
counting ptr.

There were a couple of instances where refcounted objects were created
on the stack. This seems pretty dangerous since if you ever
accidentally make a reference to that object with a ref counting
pointer, bad things are bound to happen.

7055:4e24742201d7 02-Apr-2010 Nathan Binkert <nate@binkert.org>

ruby: get "using namespace" out of headers
In addition to obvious changes, this required a slight change to the slicc
grammar to allow types with :: in them. Otherwise slicc barfs on std::string
which we need for the headers that slicc generates.


/gem5/src/cpu/rubytest/Check.cc
/gem5/src/cpu/rubytest/Check.hh
/gem5/src/cpu/rubytest/CheckTable.cc
/gem5/src/cpu/rubytest/RubyTester.cc
/gem5/src/cpu/rubytest/RubyTester.hh
/gem5/src/mem/gems_common/Vector.hh
/gem5/src/mem/protocol/MESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MESI_SCMP_bankdirectory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L2cache.sm
/gem5/src/mem/protocol/MSI_MOSI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MSI_MOSI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MSI_MOSI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MSI_MOSI_CMP_directory-msg.sm
/gem5/src/mem/protocol/RubySlicc_Exports.sm
/gem5/src/mem/protocol/RubySlicc_Profiler.sm
/gem5/src/mem/protocol/RubySlicc_Util.sm
/gem5/src/mem/ruby/buffers/MessageBuffer.cc
/gem5/src/mem/ruby/common/Address.cc
/gem5/src/mem/ruby/common/Address.hh
/gem5/src/mem/ruby/common/Driver.hh
/gem5/src/mem/ruby/common/NetDest.cc
/gem5/src/mem/ruby/common/NetDest.hh
/gem5/src/mem/ruby/common/Set.cc
/gem5/src/mem/ruby/common/Set.hh
/gem5/src/mem/ruby/common/SubBlock.cc
/gem5/src/mem/ruby/common/SubBlock.hh
/gem5/src/mem/ruby/eventqueue/RubyEventQueue.cc
/gem5/src/mem/ruby/filters/AbstractBloomFilter.hh
/gem5/src/mem/ruby/filters/BlockBloomFilter.cc
/gem5/src/mem/ruby/filters/BlockBloomFilter.hh
/gem5/src/mem/ruby/filters/BulkBloomFilter.cc
/gem5/src/mem/ruby/filters/BulkBloomFilter.hh
/gem5/src/mem/ruby/filters/GenericBloomFilter.cc
/gem5/src/mem/ruby/filters/GenericBloomFilter.hh
/gem5/src/mem/ruby/filters/H3BloomFilter.cc
/gem5/src/mem/ruby/filters/H3BloomFilter.hh
/gem5/src/mem/ruby/filters/LSB_CountingBloomFilter.cc
/gem5/src/mem/ruby/filters/LSB_CountingBloomFilter.hh
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.hh
/gem5/src/mem/ruby/filters/MultiGrainBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiGrainBloomFilter.hh
/gem5/src/mem/ruby/filters/NonCountingBloomFilter.cc
/gem5/src/mem/ruby/filters/NonCountingBloomFilter.hh
/gem5/src/mem/ruby/libruby.cc
/gem5/src/mem/ruby/network/Network.hh
/gem5/src/mem/ruby/network/garnet/NetworkHeader.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/SWallocator_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/VCallocator_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/VirtualChannel_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/flitBuffer_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/flitBuffer_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/flit_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/flit_d.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/Router.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/Router.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/VCarbiter.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/flit.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/flit.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/flitBuffer.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/flitBuffer.hh
/gem5/src/mem/ruby/network/simple/PerfectSwitch.cc
/gem5/src/mem/ruby/network/simple/SimpleNetwork.cc
/gem5/src/mem/ruby/network/simple/SimpleNetwork.hh
/gem5/src/mem/ruby/network/simple/Switch.cc
/gem5/src/mem/ruby/network/simple/Throttle.cc
/gem5/src/mem/ruby/network/simple/Throttle.hh
/gem5/src/mem/ruby/network/simple/Topology.cc
/gem5/src/mem/ruby/profiler/AccessTraceForAddress.cc
/gem5/src/mem/ruby/profiler/AccessTraceForAddress.hh
/gem5/src/mem/ruby/profiler/AddressProfiler.cc
/gem5/src/mem/ruby/profiler/AddressProfiler.hh
/gem5/src/mem/ruby/profiler/CacheProfiler.cc
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/profiler/StoreTrace.cc
/gem5/src/mem/ruby/profiler/StoreTrace.hh
/gem5/src/mem/ruby/recorder/CacheRecorder.cc
/gem5/src/mem/ruby/recorder/TraceRecord.cc
/gem5/src/mem/ruby/recorder/TraceRecord.hh
/gem5/src/mem/ruby/recorder/Tracer.cc
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/slicc_interface/AbstractEntry.hh
/gem5/src/mem/ruby/slicc_interface/NetworkMessage.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.cc
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.hh
/gem5/src/mem/ruby/system/CacheMemory.cc
/gem5/src/mem/ruby/system/CacheMemory.hh
/gem5/src/mem/ruby/system/DMASequencer.cc
/gem5/src/mem/ruby/system/DirectoryMemory.cc
/gem5/src/mem/ruby/system/DirectoryMemory.hh
/gem5/src/mem/ruby/system/MemoryControl.cc
/gem5/src/mem/ruby/system/MemoryControl.hh
/gem5/src/mem/ruby/system/PerfectCacheMemory.hh
/gem5/src/mem/ruby/system/PersistentTable.cc
/gem5/src/mem/ruby/system/PersistentTable.hh
/gem5/src/mem/ruby/system/RubyPort.hh
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/Sequencer.hh
/gem5/src/mem/ruby/system/SparseMemory.cc
/gem5/src/mem/ruby/system/SparseMemory.hh
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/ruby/system/System.hh
/gem5/src/mem/ruby/system/TBETable.hh
/gem5/src/mem/ruby/system/TimerTable.cc
/gem5/src/mem/ruby/system/TimerTable.hh
EnumDeclAST.py
LiteralExprAST.py
/gem5/src/mem/slicc/parser.py
/gem5/src/mem/slicc/symbols/Func.py
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/mem/slicc/symbols/Type.py
7007:79413d1ec307 12-Mar-2010 Nathan Binkert <nate@binkert.org>

slicc: Change the code generation so that the generated code is easier to read

6999:f226c098c393 10-Mar-2010 Nathan Binkert <nate@binkert.org>

slicc: have a central mechanism for creating a code_formatter.
This makes it easier to add global variables like protocol

6882:898047a3672c 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Ruby changes required to use the python config system
This patch includes the necessary changes to connect ruby objects using
the python configuration system. Mainly it consists of removing
unnecessary ruby object pointers and connecting the necessary object
pointers using the generated param objects. This patch includes the
slicc changes necessary to connect generated ruby objects together using
the python configuraiton system.

6877:2a1a3d916ca8 29-Jan-2010 Steve Reinhardt <steve.reinhardt@amd.com>

ruby: Make SLICC-generated objects SimObjects.
Also add SLICC support for state-machine parameter defaults
(passed through to Python as SimObject Param defaults).

6872:b26f60c254c1 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Added message type check to OutPortDeclAST.py

Though OutPort's message type is not used to generate code, this fix checks
that the programmer's intent is correct. Eventually, we may want to
remove the message type from the OutPort declaration statement.

6863:21fbf0412e0d 19-Jan-2010 Derek Hower <drh5@cs.wisc.edu>

ruby: new atomics implementation

This patch changes the way that Ruby handles atomic RMW instructions. This implementation, unlike the prior one, is protocol independent. It works by locking an address from the sequencer immediately after the read portion of an RMW completes. When that address is locked, the coherence controller will only satisfy requests coming from one port (e.g., the mandatory queue) and will ignore all others. After the write portion completed, the line is unlocked. This should also work with multi-line atomics, as long as the blocks are always acquired in the same order.

6862:3d308cbd1657 19-Jan-2010 Derek Hower <drh5@cs.wisc.edu>

merge


/gem5/src/arch/isa_specific.hh
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/RubySlicc_ComponentMapping.sm
/gem5/src/mem/protocol/SConsopts
/gem5/src/mem/ruby/config/MI_example-homogeneous.rb
/gem5/src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb
/gem5/src/mem/ruby/config/cfg.rb
/gem5/src/mem/ruby/config/defaults.rb
/gem5/src/mem/ruby/libruby.cc
/gem5/src/mem/ruby/libruby.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
/gem5/src/mem/ruby/system/CacheMemory.cc
/gem5/src/mem/ruby/system/CacheMemory.hh
/gem5/src/mem/ruby/system/DirectoryMemory.cc
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/Sequencer.hh
/gem5/src/mem/slicc/SConscript
AST.cc
AST.hh
ASTs.hh
ActionDeclAST.cc
ActionDeclAST.hh
AssignStatementAST.cc
AssignStatementAST.hh
CheckAllocateStatementAST.cc
CheckAllocateStatementAST.hh
CheckStopSlotsStatementAST.cc
CheckStopSlotsStatementAST.hh
ChipComponentAccessAST.cc
ChipComponentAccessAST.hh
CopyHeadStatementAST.cc
CopyHeadStatementAST.hh
DeclAST.cc
DeclAST.hh
DeclListAST.cc
DeclListAST.hh
EnqueueStatementAST.cc
EnqueueStatementAST.hh
EnumDeclAST.cc
EnumDeclAST.hh
EnumExprAST.cc
EnumExprAST.hh
ExprAST.cc
ExprAST.hh
ExprStatementAST.cc
ExprStatementAST.hh
FormalParamAST.cc
FormalParamAST.hh
FuncCallExprAST.cc
FuncCallExprAST.hh
FuncDeclAST.cc
FuncDeclAST.hh
IfStatementAST.cc
IfStatementAST.hh
InPortDeclAST.cc
InPortDeclAST.hh
InfixOperatorExprAST.cc
InfixOperatorExprAST.hh
LiteralExprAST.cc
LiteralExprAST.hh
Location.cc
Location.hh
MachineAST.cc
MachineAST.hh
MemberExprAST.cc
MemberExprAST.hh
MethodCallExprAST.cc
MethodCallExprAST.hh
NewExprAST.cc
NewExprAST.hh
ObjDeclAST.cc
ObjDeclAST.hh
OutPortDeclAST.cc
OutPortDeclAST.hh
PairAST.cc
PairAST.hh
PairListAST.cc
PairListAST.hh
PeekStatementAST.cc
PeekStatementAST.hh
ReturnStatementAST.cc
ReturnStatementAST.hh
StatementAST.cc
StatementAST.hh
StatementListAST.cc
StatementListAST.hh
TransitionDeclAST.cc
TransitionDeclAST.hh
TypeAST.cc
TypeAST.hh
TypeDeclAST.cc
TypeDeclAST.hh
TypeFieldAST.cc
TypeFieldAST.hh
TypeFieldEnumAST.cc
TypeFieldEnumAST.hh
TypeFieldMemberAST.cc
TypeFieldMemberAST.hh
TypeFieldMethodAST.cc
TypeFieldMethodAST.hh
VarExprAST.cc
VarExprAST.hh
/gem5/src/mem/slicc/generator/fileio.cc
/gem5/src/mem/slicc/generator/fileio.hh
/gem5/src/mem/slicc/generator/html_gen.cc
/gem5/src/mem/slicc/generator/html_gen.hh
/gem5/src/mem/slicc/generator/mif_gen.cc
/gem5/src/mem/slicc/generator/mif_gen.hh
/gem5/src/mem/slicc/main.cc
/gem5/src/mem/slicc/main.hh
/gem5/src/mem/slicc/parser/lexer.ll
/gem5/src/mem/slicc/parser/parser.py
/gem5/src/mem/slicc/parser/parser.yy
/gem5/src/mem/slicc/slicc_global.hh
/gem5/src/mem/slicc/symbols/Action.hh
/gem5/src/mem/slicc/symbols/Event.hh
/gem5/src/mem/slicc/symbols/Func.cc
/gem5/src/mem/slicc/symbols/Func.hh
/gem5/src/mem/slicc/symbols/State.hh
/gem5/src/mem/slicc/symbols/StateMachine.cc
/gem5/src/mem/slicc/symbols/StateMachine.hh
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/mem/slicc/symbols/Symbol.cc
/gem5/src/mem/slicc/symbols/Symbol.hh
/gem5/src/mem/slicc/symbols/SymbolTable.cc
/gem5/src/mem/slicc/symbols/SymbolTable.hh
/gem5/src/mem/slicc/symbols/Transition.cc
/gem5/src/mem/slicc/symbols/Transition.hh
/gem5/src/mem/slicc/symbols/Type.cc
/gem5/src/mem/slicc/symbols/Type.hh
/gem5/src/mem/slicc/symbols/Type.py
/gem5/src/mem/slicc/symbols/Var.cc
/gem5/src/mem/slicc/symbols/Var.hh
/gem5/src/python/m5/convert.py
/gem5/src/python/m5/environment.py
/gem5/src/python/m5/smartdict.py
/gem5/src/python/m5/util/misc.py
/gem5/tests/configs/memtest-ruby.py
/gem5/tests/configs/ruby_config.py
6780:2d3fc2e6f368 18-Nov-2009 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: slicc method error fix
Added error message when a method call is not supported by an object.

6778:b3f2dfbe8006 18-Nov-2009 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: slicc state machine error fixes
Added error messages when:
- a state does not exist in a machine's list of known states.
- an event does not exist in a machine
- the actions of a certain machine have not been declared

6714:028047200ff7 05-Nov-2009 Steve Reinhardt <steve.reinhardt@amd.com>

slicc: tweak file enumeration for scons
Right now .cc and .hh files are handled separately, but then
they're just munged together at the end by scons, so it
doesn't buy us anything. Might as well munge from the start
since we'll eventually be adding generated Python files
to the list too.

6690:4dc4e494e4d8 26-Oct-2009 Brad Beckmann <Brad.Beckmann@amd.com>

fixed error message generation bug in SLICC ast files

6657:ef5fae93a3b2 22-Sep-2009 Nathan Binkert <nate@binkert.org>

slicc: Pure python implementation of slicc.
This is simply a translation of the C++ slicc into python with very minimal
reorganization of the code. The output can be verified as nearly identical
by doing a "diff -wBur".

Slicc can easily be run manually by using util/slicc


/gem5/src/mem/protocol/SConscript
/gem5/src/mem/slicc/SConscript
/gem5/src/mem/slicc/__init__.py
AST.cc
AST.hh
AST.py
ASTs.hh
ActionDeclAST.cc
ActionDeclAST.hh
ActionDeclAST.py
AssignStatementAST.cc
AssignStatementAST.hh
AssignStatementAST.py
CheckAllocateStatementAST.cc
CheckAllocateStatementAST.hh
CheckAllocateStatementAST.py
CheckStopSlotsStatementAST.cc
CheckStopSlotsStatementAST.hh
CheckStopSlotsStatementAST.py
ChipComponentAccessAST.cc
ChipComponentAccessAST.hh
ChipComponentAccessAST.py
CopyHeadStatementAST.cc
CopyHeadStatementAST.hh
CopyHeadStatementAST.py
DeclAST.cc
DeclAST.hh
DeclAST.py
DeclListAST.cc
DeclListAST.hh
DeclListAST.py
EnqueueStatementAST.cc
EnqueueStatementAST.hh
EnqueueStatementAST.py
EnumDeclAST.cc
EnumDeclAST.hh
EnumDeclAST.py
EnumExprAST.cc
EnumExprAST.hh
EnumExprAST.py
ExprAST.cc
ExprAST.hh
ExprAST.py
ExprStatementAST.cc
ExprStatementAST.hh
ExprStatementAST.py
FormalParamAST.cc
FormalParamAST.hh
FormalParamAST.py
FuncCallExprAST.cc
FuncCallExprAST.hh
FuncCallExprAST.py
FuncDeclAST.cc
FuncDeclAST.hh
FuncDeclAST.py
IfStatementAST.cc
IfStatementAST.hh
IfStatementAST.py
InPortDeclAST.cc
InPortDeclAST.hh
InPortDeclAST.py
InfixOperatorExprAST.cc
InfixOperatorExprAST.hh
InfixOperatorExprAST.py
LiteralExprAST.cc
LiteralExprAST.hh
LiteralExprAST.py
Location.cc
Location.hh
MachineAST.cc
MachineAST.hh
MachineAST.py
MemberExprAST.cc
MemberExprAST.hh
MemberExprAST.py
MethodCallExprAST.cc
MethodCallExprAST.hh
MethodCallExprAST.py
NewExprAST.cc
NewExprAST.hh
NewExprAST.py
ObjDeclAST.cc
ObjDeclAST.hh
ObjDeclAST.py
OutPortDeclAST.cc
OutPortDeclAST.hh
OutPortDeclAST.py
PairAST.cc
PairAST.hh
PairAST.py
PairListAST.cc
PairListAST.hh
PairListAST.py
PeekStatementAST.cc
PeekStatementAST.hh
PeekStatementAST.py
ReturnStatementAST.cc
ReturnStatementAST.hh
ReturnStatementAST.py
StatementAST.cc
StatementAST.hh
StatementAST.py
StatementListAST.cc
StatementListAST.hh
StatementListAST.py
TransitionDeclAST.cc
TransitionDeclAST.hh
TransitionDeclAST.py
TypeAST.cc
TypeAST.hh
TypeAST.py
TypeDeclAST.cc
TypeDeclAST.hh
TypeDeclAST.py
TypeFieldAST.cc
TypeFieldAST.hh
TypeFieldAST.py
TypeFieldEnumAST.cc
TypeFieldEnumAST.hh
TypeFieldEnumAST.py
TypeFieldMemberAST.cc
TypeFieldMemberAST.hh
TypeFieldMemberAST.py
TypeFieldMethodAST.cc
TypeFieldMethodAST.hh
TypeFieldMethodAST.py
VarExprAST.cc
VarExprAST.hh
VarExprAST.py
__init__.py
/gem5/src/mem/slicc/generate/__init__.py
/gem5/src/mem/slicc/generate/dot.py
/gem5/src/mem/slicc/generate/html.py
/gem5/src/mem/slicc/generate/tex.py
/gem5/src/mem/slicc/generator/fileio.cc
/gem5/src/mem/slicc/generator/fileio.hh
/gem5/src/mem/slicc/generator/html_gen.cc
/gem5/src/mem/slicc/generator/html_gen.hh
/gem5/src/mem/slicc/generator/mif_gen.cc
/gem5/src/mem/slicc/generator/mif_gen.hh
/gem5/src/mem/slicc/main.cc
/gem5/src/mem/slicc/main.hh
/gem5/src/mem/slicc/main.py
/gem5/src/mem/slicc/parser.py
/gem5/src/mem/slicc/parser/lexer.ll
/gem5/src/mem/slicc/parser/parser.py
/gem5/src/mem/slicc/parser/parser.yy
/gem5/src/mem/slicc/slicc_global.hh
/gem5/src/mem/slicc/symbols/Action.hh
/gem5/src/mem/slicc/symbols/Action.py
/gem5/src/mem/slicc/symbols/Event.hh
/gem5/src/mem/slicc/symbols/Event.py
/gem5/src/mem/slicc/symbols/Func.cc
/gem5/src/mem/slicc/symbols/Func.hh
/gem5/src/mem/slicc/symbols/Func.py
/gem5/src/mem/slicc/symbols/State.hh
/gem5/src/mem/slicc/symbols/State.py
/gem5/src/mem/slicc/symbols/StateMachine.cc
/gem5/src/mem/slicc/symbols/StateMachine.hh
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/mem/slicc/symbols/Symbol.cc
/gem5/src/mem/slicc/symbols/Symbol.hh
/gem5/src/mem/slicc/symbols/Symbol.py
/gem5/src/mem/slicc/symbols/SymbolTable.cc
/gem5/src/mem/slicc/symbols/SymbolTable.hh
/gem5/src/mem/slicc/symbols/SymbolTable.py
/gem5/src/mem/slicc/symbols/Transition.cc
/gem5/src/mem/slicc/symbols/Transition.hh
/gem5/src/mem/slicc/symbols/Transition.py
/gem5/src/mem/slicc/symbols/Type.cc
/gem5/src/mem/slicc/symbols/Type.hh
/gem5/src/mem/slicc/symbols/Type.py
/gem5/src/mem/slicc/symbols/Var.cc
/gem5/src/mem/slicc/symbols/Var.hh
/gem5/src/mem/slicc/symbols/Var.py
/gem5/src/mem/slicc/symbols/__init__.py
/gem5/src/mem/slicc/util.py
/gem5/util/slicc
6467:5670eee2a866 04-Aug-2009 Derek Hower <drh5@cs.wisc.edu>

slicc: added MOESI_CMP_directory, DMA SequencerMsg, parameterized controllers

This changeset contains a lot of different changes that are too
mingled to separate. They are:

1. Added MOESI_CMP_directory

I made the changes necessary to bring back MOESI_CMP_directory,
including adding a DMA controller. I got rid of MOESI_CMP_directory_m
and made MOESI_CMP_directory use a memory controller. Added a new
configuration for two level protocols in general, and
MOESI_CMP_directory in particular.

2. DMA Sequencer uses a generic SequencerMsg

I will eventually make the cache Sequencer use this type as well. It
doesn't contain an offset field, just a physical address and a length.
MI_example has been updated to deal with this.

3. Parameterized Controllers

SLICC controllers can now take custom parameters to use for mapping,
latencies, etc. Currently, only int parameters are supported.


/gem5/src/mem/gems_common/Map.hh
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MI_example-dma.sm
/gem5/src/mem/protocol/MI_example-msg.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-msg.sm
/gem5/src/mem/protocol/MOESI_CMP_directory.slicc
/gem5/src/mem/protocol/MOESI_CMP_directory_m-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory_m.slicc
/gem5/src/mem/protocol/RubySlicc_ComponentMapping.sm
/gem5/src/mem/protocol/RubySlicc_Exports.sm
/gem5/src/mem/protocol/RubySlicc_Profiler.sm
/gem5/src/mem/protocol/RubySlicc_Types.sm
/gem5/src/mem/protocol/RubySlicc_Util.sm
/gem5/src/mem/ruby/config/MI_example-homogeneous.rb
/gem5/src/mem/ruby/config/MI_example.rb
/gem5/src/mem/ruby/config/MOESI_CMP_directory.rb
/gem5/src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb
/gem5/src/mem/ruby/config/cfg.rb
/gem5/src/mem/ruby/config/defaults.rb
/gem5/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
/gem5/src/mem/ruby/system/DMASequencer.cc
/gem5/src/mem/ruby/system/DirectoryMemory.cc
/gem5/src/mem/ruby/system/DirectoryMemory.hh
/gem5/src/mem/ruby/system/PerfectCacheMemory.hh
/gem5/src/mem/ruby/system/System.hh
/gem5/src/mem/ruby/system/TimerTable.cc
/gem5/src/mem/ruby/system/TimerTable.hh
AST.hh
ActionDeclAST.cc
ActionDeclAST.hh
EnqueueStatementAST.cc
FormalParamAST.cc
FormalParamAST.hh
FuncDeclAST.cc
FuncDeclAST.hh
MachineAST.cc
MachineAST.hh
/gem5/src/mem/slicc/parser/parser.py
/gem5/src/mem/slicc/parser/parser.yy
/gem5/src/mem/slicc/symbols/StateMachine.cc
/gem5/src/mem/slicc/symbols/StateMachine.hh
6372:f1a41ea3bbab 18-Jul-2009 Derek Hower <drh5@cs.wisc.edu>

ruby: removed all refs to old RubyConfig


/gem5/src/mem/ruby/buffers/MessageBuffer.cc
/gem5/src/mem/ruby/common/Address.hh
/gem5/src/mem/ruby/common/NetDest.cc
/gem5/src/mem/ruby/common/NetDest.hh
/gem5/src/mem/ruby/common/Set.cc
/gem5/src/mem/ruby/common/Set.hh
/gem5/src/mem/ruby/common/SubBlock.hh
/gem5/src/mem/ruby/config/RubyConfig.cc
/gem5/src/mem/ruby/config/RubyConfig.hh
/gem5/src/mem/ruby/eventqueue/RubyEventQueue.cc
/gem5/src/mem/ruby/filters/AbstractBloomFilter.hh
/gem5/src/mem/ruby/filters/BlockBloomFilter.hh
/gem5/src/mem/ruby/filters/BulkBloomFilter.hh
/gem5/src/mem/ruby/filters/GenericBloomFilter.cc
/gem5/src/mem/ruby/filters/GenericBloomFilter.hh
/gem5/src/mem/ruby/filters/H3BloomFilter.hh
/gem5/src/mem/ruby/filters/LSB_CountingBloomFilter.hh
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.hh
/gem5/src/mem/ruby/filters/MultiGrainBloomFilter.hh
/gem5/src/mem/ruby/filters/NonCountingBloomFilter.hh
/gem5/src/mem/ruby/network/Network.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkConfig.hh
/gem5/src/mem/ruby/network/simple/PerfectSwitch.cc
/gem5/src/mem/ruby/network/simple/SimpleNetwork.cc
/gem5/src/mem/ruby/network/simple/Throttle.cc
/gem5/src/mem/ruby/network/simple/Topology.cc
/gem5/src/mem/ruby/profiler/AccessTraceForAddress.hh
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/profiler/StoreTrace.hh
/gem5/src/mem/ruby/recorder/Tracer.cc
/gem5/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
/gem5/src/mem/ruby/system/AbstractMemOrCache.hh
/gem5/src/mem/ruby/system/CacheMemory.hh
/gem5/src/mem/ruby/system/DirectoryMemory.cc
/gem5/src/mem/ruby/system/PerfectCacheMemory.hh
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/Sequencer.hh
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/ruby/system/System.hh
/gem5/src/mem/ruby/tester/RaceyPseudoThread.cc
EnqueueStatementAST.cc
/gem5/src/mem/slicc/symbols/StateMachine.cc
/gem5/src/mem/slicc/symbols/Type.cc
6285:ce086eca1ede 06-Jul-2009 Nathan Binkert <nate@binkert.org>

ruby: Import the latest ruby changes from gems.
This was done with an automated process, so there could be things that were
done in this tree in the past that didn't make it. One known regression
is that atomic memory operations do not seem to work properly anymore.


/gem5/src/mem/gems_common/std-includes.hh
/gem5/src/mem/gems_common/util.cc
/gem5/src/mem/gems_common/util.hh
/gem5/src/mem/protocol/MESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-mem.sm
/gem5/src/mem/protocol/MESI_CMP_directory-msg.sm
/gem5/src/mem/protocol/MESI_CMP_directory.slicc
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MI_example-dma.sm
/gem5/src/mem/protocol/MI_example-msg.sm
/gem5/src/mem/protocol/MI_example.slicc
/gem5/src/mem/protocol/RubySlicc_ComponentMapping.sm
/gem5/src/mem/protocol/RubySlicc_Exports.sm
/gem5/src/mem/protocol/RubySlicc_Types.sm
/gem5/src/mem/protocol/standard_1level_CMP-protocol.sm
/gem5/src/mem/ruby/buffers/MessageBuffer.cc
/gem5/src/mem/ruby/buffers/MessageBuffer.hh
/gem5/src/mem/ruby/common/Address.hh
/gem5/src/mem/ruby/common/Consumer.hh
/gem5/src/mem/ruby/common/DataBlock.cc
/gem5/src/mem/ruby/common/DataBlock.hh
/gem5/src/mem/ruby/common/Debug.cc
/gem5/src/mem/ruby/common/Debug.hh
/gem5/src/mem/ruby/common/Driver.hh
/gem5/src/mem/ruby/common/Global.hh
/gem5/src/mem/ruby/common/Set.cc
/gem5/src/mem/ruby/common/SubBlock.cc
/gem5/src/mem/ruby/common/SubBlock.hh
/gem5/src/mem/ruby/common/TypeDefines.hh
/gem5/src/mem/ruby/config/MI_example-homogeneous.rb
/gem5/src/mem/ruby/config/RubyConfig.cc
/gem5/src/mem/ruby/config/RubyConfig.hh
/gem5/src/mem/ruby/config/cfg.rb
/gem5/src/mem/ruby/config/config.hh
/gem5/src/mem/ruby/config/defaults.rb
/gem5/src/mem/ruby/config/libruby_cfg_test.cc
/gem5/src/mem/ruby/config/print_cfg.rb
/gem5/src/mem/ruby/config/rubyconfig.defaults
/gem5/src/mem/ruby/config/tester.defaults
/gem5/src/mem/ruby/eventqueue/RubyEventQueue.cc
/gem5/src/mem/ruby/filters/AbstractBloomFilter.hh
/gem5/src/mem/ruby/filters/BlockBloomFilter.cc
/gem5/src/mem/ruby/filters/BlockBloomFilter.hh
/gem5/src/mem/ruby/filters/BulkBloomFilter.cc
/gem5/src/mem/ruby/filters/BulkBloomFilter.hh
/gem5/src/mem/ruby/filters/GenericBloomFilter.cc
/gem5/src/mem/ruby/filters/GenericBloomFilter.hh
/gem5/src/mem/ruby/filters/H3BloomFilter.cc
/gem5/src/mem/ruby/filters/H3BloomFilter.hh
/gem5/src/mem/ruby/filters/LSB_CountingBloomFilter.cc
/gem5/src/mem/ruby/filters/LSB_CountingBloomFilter.hh
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.hh
/gem5/src/mem/ruby/filters/MultiGrainBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiGrainBloomFilter.hh
/gem5/src/mem/ruby/filters/NonCountingBloomFilter.cc
/gem5/src/mem/ruby/filters/NonCountingBloomFilter.hh
/gem5/src/mem/ruby/init.cc
/gem5/src/mem/ruby/init.hh
/gem5/src/mem/ruby/libruby.cc
/gem5/src/mem/ruby/libruby.hh
/gem5/src/mem/ruby/libruby_internal.hh
/gem5/src/mem/ruby/network/Network.cc
/gem5/src/mem/ruby/network/Network.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/CreditLink_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/GarnetNetwork_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/GarnetNetwork_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/NetworkLink_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/NetworkLink_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/OutVcState_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/OutVcState_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/OutputUnit_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/Router_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/SWallocator_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/VCallocator_d.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/GarnetNetwork.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/GarnetNetwork.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkConfig.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkInterface.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkLink.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/Router.cc
/gem5/src/mem/ruby/network/simple/CustomTopology.cc
/gem5/src/mem/ruby/network/simple/CustomTopology.hh
/gem5/src/mem/ruby/network/simple/HierarchicalSwitchTopology.cc
/gem5/src/mem/ruby/network/simple/HierarchicalSwitchTopology.hh
/gem5/src/mem/ruby/network/simple/PerfectSwitch.cc
/gem5/src/mem/ruby/network/simple/PtToPtTopology.cc
/gem5/src/mem/ruby/network/simple/PtToPtTopology.hh
/gem5/src/mem/ruby/network/simple/SimpleNetwork.cc
/gem5/src/mem/ruby/network/simple/SimpleNetwork.hh
/gem5/src/mem/ruby/network/simple/Switch.cc
/gem5/src/mem/ruby/network/simple/Switch.hh
/gem5/src/mem/ruby/network/simple/Throttle.cc
/gem5/src/mem/ruby/network/simple/Throttle.hh
/gem5/src/mem/ruby/network/simple/Topology.cc
/gem5/src/mem/ruby/network/simple/Topology.hh
/gem5/src/mem/ruby/network/simple/Torus2DTopology.cc
/gem5/src/mem/ruby/network/simple/Torus2DTopology.hh
/gem5/src/mem/ruby/profiler/AddressProfiler.cc
/gem5/src/mem/ruby/profiler/AddressProfiler.hh
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/recorder/CacheRecorder.cc
/gem5/src/mem/ruby/recorder/CacheRecorder.hh
/gem5/src/mem/ruby/recorder/TraceRecord.cc
/gem5/src/mem/ruby/recorder/TraceRecord.hh
/gem5/src/mem/ruby/recorder/Tracer.cc
/gem5/src/mem/ruby/recorder/Tracer.hh
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
/gem5/src/mem/ruby/slicc_interface/AbstractChip.cc
/gem5/src/mem/ruby/slicc_interface/AbstractChip.hh
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.cc
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
/gem5/src/mem/ruby/storebuffer/hfa.hh
/gem5/src/mem/ruby/storebuffer/hfatypes.hh
/gem5/src/mem/ruby/storebuffer/interface.cc
/gem5/src/mem/ruby/storebuffer/interface.hh
/gem5/src/mem/ruby/storebuffer/stb_interface.cc
/gem5/src/mem/ruby/storebuffer/stb_interface.hh
/gem5/src/mem/ruby/storebuffer/storebuffer.cc
/gem5/src/mem/ruby/storebuffer/storebuffer.hh
/gem5/src/mem/ruby/system/AbstractMemOrCache.hh
/gem5/src/mem/ruby/system/CacheMemory.hh
/gem5/src/mem/ruby/system/DMASequencer.cc
/gem5/src/mem/ruby/system/DMASequencer.hh
/gem5/src/mem/ruby/system/DirectoryMemory.cc
/gem5/src/mem/ruby/system/DirectoryMemory.hh
/gem5/src/mem/ruby/system/MemoryControl.cc
/gem5/src/mem/ruby/system/MemoryControl.hh
/gem5/src/mem/ruby/system/MemoryVector.hh
/gem5/src/mem/ruby/system/NodePersistentTable.cc
/gem5/src/mem/ruby/system/NodePersistentTable.hh
/gem5/src/mem/ruby/system/PersistentArbiter.cc
/gem5/src/mem/ruby/system/PersistentArbiter.hh
/gem5/src/mem/ruby/system/PersistentTable.cc
/gem5/src/mem/ruby/system/PersistentTable.hh
/gem5/src/mem/ruby/system/ProcessorInterface.hh
/gem5/src/mem/ruby/system/RubyPort.cc
/gem5/src/mem/ruby/system/RubyPort.hh
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/Sequencer.hh
/gem5/src/mem/ruby/system/StoreBuffer.cc
/gem5/src/mem/ruby/system/StoreBuffer.hh
/gem5/src/mem/ruby/system/StoreCache.cc
/gem5/src/mem/ruby/system/StoreCache.hh
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/ruby/system/System.hh
/gem5/src/mem/ruby/system/TBETable.hh
/gem5/src/mem/ruby/tester/BarrierGenerator.cc
/gem5/src/mem/ruby/tester/BarrierGenerator.hh
/gem5/src/mem/ruby/tester/Check.cc
/gem5/src/mem/ruby/tester/Check.hh
/gem5/src/mem/ruby/tester/CheckTable.cc
/gem5/src/mem/ruby/tester/CheckTable.hh
/gem5/src/mem/ruby/tester/DetermGETXGenerator.cc
/gem5/src/mem/ruby/tester/DetermGETXGenerator.hh
/gem5/src/mem/ruby/tester/DetermInvGenerator.cc
/gem5/src/mem/ruby/tester/DetermInvGenerator.hh
/gem5/src/mem/ruby/tester/DetermSeriesGETSGenerator.cc
/gem5/src/mem/ruby/tester/DetermSeriesGETSGenerator.hh
/gem5/src/mem/ruby/tester/DeterministicDriver.cc
/gem5/src/mem/ruby/tester/DeterministicDriver.hh
/gem5/src/mem/ruby/tester/Driver_Tester.cc
/gem5/src/mem/ruby/tester/Driver_Tester.hh
/gem5/src/mem/ruby/tester/EventQueue_Tester.hh
/gem5/src/mem/ruby/tester/Global_Tester.hh
/gem5/src/mem/ruby/tester/Instruction.cc
/gem5/src/mem/ruby/tester/Instruction.hh
/gem5/src/mem/ruby/tester/RaceyDriver.cc
/gem5/src/mem/ruby/tester/RaceyDriver.hh
/gem5/src/mem/ruby/tester/RaceyPseudoThread.cc
/gem5/src/mem/ruby/tester/RaceyPseudoThread.hh
/gem5/src/mem/ruby/tester/RequestGenerator.cc
/gem5/src/mem/ruby/tester/RequestGenerator.hh
/gem5/src/mem/ruby/tester/SpecifiedGenerator.cc
/gem5/src/mem/ruby/tester/SpecifiedGenerator.hh
/gem5/src/mem/ruby/tester/SyntheticDriver.cc
/gem5/src/mem/ruby/tester/SyntheticDriver.hh
/gem5/src/mem/ruby/tester/Tester.cc
/gem5/src/mem/ruby/tester/Tester.hh
/gem5/src/mem/ruby/tester/main.cc
/gem5/src/mem/ruby/tester/main.hh
/gem5/src/mem/ruby/tester/test_framework.cc
/gem5/src/mem/ruby/tester/test_framework.hh
ASTs.hh
EnqueueStatementAST.cc
MachineAST.cc
MachineAST.hh
MethodCallExprAST.cc
NewExprAST.cc
NewExprAST.hh
ObjDeclAST.cc
/gem5/src/mem/slicc/parser/lexer.ll
/gem5/src/mem/slicc/parser/parser.yy
/gem5/src/mem/slicc/symbols/Func.cc
/gem5/src/mem/slicc/symbols/Func.hh
/gem5/src/mem/slicc/symbols/StateMachine.cc
/gem5/src/mem/slicc/symbols/StateMachine.hh
/gem5/src/mem/slicc/symbols/Symbol.hh
/gem5/src/mem/slicc/symbols/SymbolTable.cc
/gem5/src/mem/slicc/symbols/SymbolTable.hh
/gem5/src/mem/slicc/symbols/Type.cc
/gem5/src/mem/slicc/symbols/Type.hh
/gem5/src/mem/slicc/symbols/Var.hh
6284:a63d1dc4c820 06-Jul-2009 Nathan Binkert <nate@binkert.org>

ruby: replace strings that were missed in original ruby import.


/gem5/src/mem/gems_common/ioutil/attrlex.ll
/gem5/src/mem/gems_common/ioutil/attrparse.yy
/gem5/src/mem/ruby/common/Global.hh
/gem5/src/mem/ruby/common/NetDest.cc
/gem5/src/mem/ruby/common/NetDest.hh
/gem5/src/mem/ruby/common/Set.cc
/gem5/src/mem/ruby/common/Set.hh
/gem5/src/mem/ruby/config/RubyConfig.cc
/gem5/src/mem/ruby/config/RubyConfig.hh
/gem5/src/mem/ruby/eventqueue/RubyEventQueue.hh
/gem5/src/mem/ruby/init.cc
/gem5/src/mem/ruby/init.hh
/gem5/src/mem/ruby/network/Network.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/CreditLink_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/GarnetNetwork_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/GarnetNetwork_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/InputUnit_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/NetworkHeader.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/NetworkInterface_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/NetworkLink_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/NetworkLink_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/OutVcState_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/OutputUnit_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/Router_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/Router_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/RoutingUnit_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/SWallocator_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/SWallocator_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/Switch_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/VCallocator_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/VCallocator_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/VirtualChannel_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/flitBuffer_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/flit_d.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/FlexibleConsumer.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/GarnetNetwork.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/GarnetNetwork.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/InVcState.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkConfig.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkInterface.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkLink.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkLink.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/OutVcState.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/Router.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/Router.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/VCarbiter.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/flit.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/flitBuffer.hh
/gem5/src/mem/ruby/network/simple/PerfectSwitch.cc
/gem5/src/mem/ruby/network/simple/SimpleNetwork.cc
/gem5/src/mem/ruby/network/simple/SimpleNetwork.hh
/gem5/src/mem/ruby/network/simple/Switch.cc
/gem5/src/mem/ruby/network/simple/Throttle.cc
/gem5/src/mem/ruby/network/simple/Topology.cc
/gem5/src/mem/ruby/network/simple/Topology.hh
/gem5/src/mem/ruby/profiler/AddressProfiler.cc
/gem5/src/mem/ruby/profiler/AddressProfiler.hh
/gem5/src/mem/ruby/profiler/CacheProfiler.cc
/gem5/src/mem/ruby/profiler/CacheProfiler.hh
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc
/gem5/src/mem/ruby/slicc_interface/AbstractChip.cc
/gem5/src/mem/ruby/slicc_interface/NetworkMessage.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.cc
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
/gem5/src/mem/ruby/system/AbstractMemOrCache.hh
/gem5/src/mem/ruby/system/CacheMemory.hh
/gem5/src/mem/ruby/system/DirectoryMemory.cc
/gem5/src/mem/ruby/system/DirectoryMemory.hh
/gem5/src/mem/ruby/system/MachineID.hh
/gem5/src/mem/ruby/system/MemoryControl.cc
/gem5/src/mem/ruby/system/MemoryControl.hh
/gem5/src/mem/ruby/system/NodeID.hh
/gem5/src/mem/ruby/system/NodePersistentTable.hh
/gem5/src/mem/ruby/system/PerfectCacheMemory.hh
/gem5/src/mem/ruby/system/PersistentArbiter.hh
/gem5/src/mem/ruby/system/Sequencer.hh
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/ruby/system/System.hh
/gem5/src/mem/ruby/system/TBETable.hh
/gem5/src/mem/ruby/system/TimerTable.hh
/gem5/src/mem/ruby/tester/Instruction.hh
/gem5/src/mem/ruby/tester/SpecifiedGenerator.cc
/gem5/src/mem/ruby/tester/SpecifiedGenerator.hh
AST.cc
AST.hh
ActionDeclAST.cc
ActionDeclAST.hh
AssignStatementAST.cc
AssignStatementAST.hh
ChipComponentAccessAST.cc
ChipComponentAccessAST.hh
DeclAST.cc
DeclAST.hh
DeclListAST.cc
DeclListAST.hh
EnqueueStatementAST.hh
EnumDeclAST.cc
EnumDeclAST.hh
EnumExprAST.cc
EnumExprAST.hh
ExprAST.cc
ExprAST.hh
ExprStatementAST.cc
ExprStatementAST.hh
FormalParamAST.cc
FormalParamAST.hh
FuncCallExprAST.cc
FuncCallExprAST.hh
FuncDeclAST.cc
FuncDeclAST.hh
IfStatementAST.cc
IfStatementAST.hh
InPortDeclAST.cc
InPortDeclAST.hh
InfixOperatorExprAST.cc
InfixOperatorExprAST.hh
LiteralExprAST.cc
LiteralExprAST.hh
Location.cc
Location.hh
MachineAST.cc
MachineAST.hh
MemberExprAST.cc
MemberExprAST.hh
MethodCallExprAST.cc
MethodCallExprAST.hh
ObjDeclAST.cc
ObjDeclAST.hh
OutPortDeclAST.cc
OutPortDeclAST.hh
PairAST.cc
PairAST.hh
PairListAST.cc
PairListAST.hh
PeekStatementAST.cc
PeekStatementAST.hh
ReturnStatementAST.cc
ReturnStatementAST.hh
StatementAST.cc
StatementAST.hh
StatementListAST.cc
StatementListAST.hh
TransitionDeclAST.cc
TransitionDeclAST.hh
TypeAST.cc
TypeAST.hh
TypeDeclAST.cc
TypeDeclAST.hh
TypeFieldAST.cc
TypeFieldAST.hh
TypeFieldEnumAST.cc
TypeFieldEnumAST.hh
TypeFieldMemberAST.cc
TypeFieldMemberAST.hh
TypeFieldMethodAST.cc
TypeFieldMethodAST.hh
VarExprAST.cc
VarExprAST.hh
/gem5/src/mem/slicc/generator/fileio.cc
/gem5/src/mem/slicc/generator/fileio.hh
/gem5/src/mem/slicc/generator/html_gen.cc
/gem5/src/mem/slicc/generator/html_gen.hh
/gem5/src/mem/slicc/generator/mif_gen.hh
/gem5/src/mem/slicc/main.hh
/gem5/src/mem/slicc/symbols/Func.cc
/gem5/src/mem/slicc/symbols/Func.hh
/gem5/src/mem/slicc/symbols/SymbolTable.hh
/gem5/src/mem/slicc/symbols/Transition.hh
/gem5/src/mem/slicc/symbols/Type.cc
/gem5/src/mem/slicc/symbols/Type.hh
/gem5/src/mem/slicc/symbols/Var.hh
6201:39d8a2197b77 13-May-2009 Nathan Binkert <nate@binkert.org>

slicc: work around improper initialization of a global in slicc.

6154:6bb54dcb940e 11-May-2009 Nathan Binkert <nate@binkert.org>

ruby: Make ruby #includes use full paths to the files they're including.
This basically means changing all #include statements and changing
autogenerated code so that it generates the correct paths. Because
slicc generates #includes, I had to hard code the include paths to
mem/protocol.


/gem5/src/mem/gems_common/Allocator.hh
/gem5/src/mem/gems_common/Map.hh
/gem5/src/mem/gems_common/PrioHeap.hh
/gem5/src/mem/gems_common/RefCnt_tester.cc
/gem5/src/mem/gems_common/RefCountable.hh
/gem5/src/mem/gems_common/Vector.hh
/gem5/src/mem/gems_common/ioutil/attrlex.ll
/gem5/src/mem/gems_common/ioutil/attrparse.yy
/gem5/src/mem/gems_common/ioutil/confio.cc
/gem5/src/mem/gems_common/ioutil/confio.hh
/gem5/src/mem/gems_common/ioutil/initvar.cc
/gem5/src/mem/gems_common/ioutil/vardecl.hh
/gem5/src/mem/gems_common/util.cc
/gem5/src/mem/gems_common/util.hh
/gem5/src/mem/ruby/buffers/MessageBuffer.cc
/gem5/src/mem/ruby/buffers/MessageBuffer.hh
/gem5/src/mem/ruby/buffers/MessageBufferNode.cc
/gem5/src/mem/ruby/buffers/MessageBufferNode.hh
/gem5/src/mem/ruby/common/Address.cc
/gem5/src/mem/ruby/common/Address.hh
/gem5/src/mem/ruby/common/BigSet.cc
/gem5/src/mem/ruby/common/BigSet.hh
/gem5/src/mem/ruby/common/Consumer.hh
/gem5/src/mem/ruby/common/DataBlock.cc
/gem5/src/mem/ruby/common/DataBlock.hh
/gem5/src/mem/ruby/common/Debug.cc
/gem5/src/mem/ruby/common/Driver.cc
/gem5/src/mem/ruby/common/Driver.hh
/gem5/src/mem/ruby/common/Global.cc
/gem5/src/mem/ruby/common/Global.hh
/gem5/src/mem/ruby/common/Histogram.cc
/gem5/src/mem/ruby/common/Histogram.hh
/gem5/src/mem/ruby/common/Message.cc
/gem5/src/mem/ruby/common/NetDest.cc
/gem5/src/mem/ruby/common/NetDest.hh
/gem5/src/mem/ruby/common/OptBigSet.cc
/gem5/src/mem/ruby/common/OptBigSet.hh
/gem5/src/mem/ruby/common/Set.cc
/gem5/src/mem/ruby/common/Set.hh
/gem5/src/mem/ruby/common/SubBlock.cc
/gem5/src/mem/ruby/common/SubBlock.hh
/gem5/src/mem/ruby/config/RubyConfig.cc
/gem5/src/mem/ruby/config/RubyConfig.hh
/gem5/src/mem/ruby/eventqueue/RubyEventQueue.cc
/gem5/src/mem/ruby/eventqueue/RubyEventQueue.hh
/gem5/src/mem/ruby/eventqueue/RubyEventQueueNode.cc
/gem5/src/mem/ruby/eventqueue/RubyEventQueueNode.hh
/gem5/src/mem/ruby/init.cc
/gem5/src/mem/ruby/network/Network.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/CreditLink_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/GarnetNetwork_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/GarnetNetwork_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/InputUnit_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/InputUnit_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/NetworkHeader.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/NetworkInterface_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/NetworkLink_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/NetworkLink_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/OutVcState_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/OutVcState_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/OutputUnit_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/OutputUnit_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/Router_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/Router_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/RoutingUnit_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/RoutingUnit_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/SWallocator_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/SWallocator_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/Switch_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/Switch_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/VCallocator_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/VCallocator_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/VirtualChannel_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/VirtualChannel_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/flitBuffer_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/flitBuffer_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/flit_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/flit_d.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/FlexibleConsumer.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/GarnetNetwork.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/GarnetNetwork.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/InVcState.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/InVcState.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkConfig.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkInterface.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkInterface.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkLink.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkLink.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/OutVcState.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/OutVcState.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/Router.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/Router.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/VCarbiter.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/VCarbiter.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/flit.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/flit.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/flitBuffer.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/flitBuffer.hh
/gem5/src/mem/ruby/network/orion/NetworkPower.cc
/gem5/src/mem/ruby/network/orion/SIM_power.hh
/gem5/src/mem/ruby/network/orion/power_arbiter.cc
/gem5/src/mem/ruby/network/orion/power_arbiter.hh
/gem5/src/mem/ruby/network/orion/power_array.cc
/gem5/src/mem/ruby/network/orion/power_bus.cc
/gem5/src/mem/ruby/network/orion/power_crossbar.cc
/gem5/src/mem/ruby/network/orion/power_ll.cc
/gem5/src/mem/ruby/network/orion/power_router_init.cc
/gem5/src/mem/ruby/network/orion/power_router_init.hh
/gem5/src/mem/ruby/network/orion/power_static.cc
/gem5/src/mem/ruby/network/orion/power_static.hh
/gem5/src/mem/ruby/network/orion/power_utils.cc
/gem5/src/mem/ruby/network/simple/PerfectSwitch.cc
/gem5/src/mem/ruby/network/simple/PerfectSwitch.hh
/gem5/src/mem/ruby/network/simple/SimpleNetwork.cc
/gem5/src/mem/ruby/network/simple/SimpleNetwork.hh
/gem5/src/mem/ruby/network/simple/Switch.cc
/gem5/src/mem/ruby/network/simple/Switch.hh
/gem5/src/mem/ruby/network/simple/Throttle.cc
/gem5/src/mem/ruby/network/simple/Throttle.hh
/gem5/src/mem/ruby/network/simple/Topology.cc
/gem5/src/mem/ruby/network/simple/Topology.hh
/gem5/src/mem/ruby/profiler/AccessTraceForAddress.cc
/gem5/src/mem/ruby/profiler/AccessTraceForAddress.hh
/gem5/src/mem/ruby/profiler/AddressProfiler.cc
/gem5/src/mem/ruby/profiler/AddressProfiler.hh
/gem5/src/mem/ruby/profiler/CacheProfiler.cc
/gem5/src/mem/ruby/profiler/CacheProfiler.hh
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/profiler/StoreTrace.cc
/gem5/src/mem/ruby/profiler/StoreTrace.hh
/gem5/src/mem/ruby/profiler/XactProfiler.cc
/gem5/src/mem/ruby/profiler/XactProfiler.hh
/gem5/src/mem/ruby/recorder/CacheRecorder.cc
/gem5/src/mem/ruby/recorder/CacheRecorder.hh
/gem5/src/mem/ruby/recorder/TraceRecord.cc
/gem5/src/mem/ruby/recorder/TraceRecord.hh
/gem5/src/mem/ruby/recorder/Tracer.cc
/gem5/src/mem/ruby/recorder/Tracer.hh
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
/gem5/src/mem/ruby/slicc_interface/AbstractChip.cc
/gem5/src/mem/ruby/slicc_interface/AbstractChip.hh
/gem5/src/mem/ruby/slicc_interface/Message.hh
/gem5/src/mem/ruby/slicc_interface/NetworkMessage.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.cc
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_includes.hh
/gem5/src/mem/ruby/system/AbstractBloomFilter.hh
/gem5/src/mem/ruby/system/AbstractMemOrCache.hh
/gem5/src/mem/ruby/system/AbstractReplacementPolicy.hh
/gem5/src/mem/ruby/system/BlockBloomFilter.cc
/gem5/src/mem/ruby/system/BlockBloomFilter.hh
/gem5/src/mem/ruby/system/BulkBloomFilter.cc
/gem5/src/mem/ruby/system/BulkBloomFilter.hh
/gem5/src/mem/ruby/system/CacheMemory.hh
/gem5/src/mem/ruby/system/DirectoryMemory.cc
/gem5/src/mem/ruby/system/DirectoryMemory.hh
/gem5/src/mem/ruby/system/GenericBloomFilter.cc
/gem5/src/mem/ruby/system/GenericBloomFilter.hh
/gem5/src/mem/ruby/system/H3BloomFilter.cc
/gem5/src/mem/ruby/system/H3BloomFilter.hh
/gem5/src/mem/ruby/system/LRUPolicy.hh
/gem5/src/mem/ruby/system/LSB_CountingBloomFilter.cc
/gem5/src/mem/ruby/system/LSB_CountingBloomFilter.hh
/gem5/src/mem/ruby/system/MachineID.hh
/gem5/src/mem/ruby/system/MemoryControl.cc
/gem5/src/mem/ruby/system/MemoryControl.hh
/gem5/src/mem/ruby/system/MemoryNode.cc
/gem5/src/mem/ruby/system/MemoryNode.hh
/gem5/src/mem/ruby/system/MultiBitSelBloomFilter.cc
/gem5/src/mem/ruby/system/MultiBitSelBloomFilter.hh
/gem5/src/mem/ruby/system/MultiGrainBloomFilter.cc
/gem5/src/mem/ruby/system/MultiGrainBloomFilter.hh
/gem5/src/mem/ruby/system/NodeID.hh
/gem5/src/mem/ruby/system/NodePersistentTable.cc
/gem5/src/mem/ruby/system/NodePersistentTable.hh
/gem5/src/mem/ruby/system/NonCountingBloomFilter.cc
/gem5/src/mem/ruby/system/NonCountingBloomFilter.hh
/gem5/src/mem/ruby/system/PerfectCacheMemory.hh
/gem5/src/mem/ruby/system/PersistentArbiter.cc
/gem5/src/mem/ruby/system/PersistentArbiter.hh
/gem5/src/mem/ruby/system/PersistentTable.cc
/gem5/src/mem/ruby/system/PersistentTable.hh
/gem5/src/mem/ruby/system/PseudoLRUPolicy.hh
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/Sequencer.hh
/gem5/src/mem/ruby/system/StoreBuffer.cc
/gem5/src/mem/ruby/system/StoreBuffer.hh
/gem5/src/mem/ruby/system/StoreCache.cc
/gem5/src/mem/ruby/system/StoreCache.hh
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/ruby/system/System.hh
/gem5/src/mem/ruby/system/TBETable.hh
/gem5/src/mem/ruby/system/TimerTable.cc
/gem5/src/mem/ruby/system/TimerTable.hh
/gem5/src/mem/ruby/tester/BarrierGenerator.cc
/gem5/src/mem/ruby/tester/BarrierGenerator.hh
/gem5/src/mem/ruby/tester/Check.cc
/gem5/src/mem/ruby/tester/Check.hh
/gem5/src/mem/ruby/tester/CheckTable.cc
/gem5/src/mem/ruby/tester/CheckTable.hh
/gem5/src/mem/ruby/tester/DetermGETXGenerator.cc
/gem5/src/mem/ruby/tester/DetermGETXGenerator.hh
/gem5/src/mem/ruby/tester/DetermInvGenerator.cc
/gem5/src/mem/ruby/tester/DetermInvGenerator.hh
/gem5/src/mem/ruby/tester/DetermSeriesGETSGenerator.cc
/gem5/src/mem/ruby/tester/DetermSeriesGETSGenerator.hh
/gem5/src/mem/ruby/tester/DeterministicDriver.cc
/gem5/src/mem/ruby/tester/DeterministicDriver.hh
/gem5/src/mem/ruby/tester/Instruction.cc
/gem5/src/mem/ruby/tester/Instruction.hh
/gem5/src/mem/ruby/tester/RaceyDriver.cc
/gem5/src/mem/ruby/tester/RaceyDriver.hh
/gem5/src/mem/ruby/tester/RequestGenerator.cc
/gem5/src/mem/ruby/tester/RequestGenerator.hh
/gem5/src/mem/ruby/tester/SpecifiedGenerator.cc
/gem5/src/mem/ruby/tester/SpecifiedGenerator.hh
/gem5/src/mem/ruby/tester/SyntheticDriver.cc
/gem5/src/mem/ruby/tester/SyntheticDriver.hh
/gem5/src/mem/ruby/tester/Tester.cc
/gem5/src/mem/ruby/tester/Tester.hh
/gem5/src/mem/ruby/tester/XactAbortRequestGenerator.cc
/gem5/src/mem/ruby/tester/XactAbortRequestGenerator.hh
/gem5/src/mem/ruby/tester/XactRequestGenerator.cc
/gem5/src/mem/ruby/tester/XactRequestGenerator.hh
/gem5/src/mem/ruby/tester/main.cc
/gem5/src/mem/ruby/tester/main.hh
/gem5/src/mem/ruby/tester/test_framework.cc
/gem5/src/mem/ruby/tester/test_framework.hh
AST.cc
AST.hh
ASTs.hh
ActionDeclAST.cc
ActionDeclAST.hh
AssignStatementAST.cc
AssignStatementAST.hh
CheckAllocateStatementAST.cc
CheckAllocateStatementAST.hh
CheckStopSlotsStatementAST.cc
CheckStopSlotsStatementAST.hh
ChipComponentAccessAST.cc
ChipComponentAccessAST.hh
CopyHeadStatementAST.cc
CopyHeadStatementAST.hh
DeclAST.cc
DeclAST.hh
DeclListAST.cc
DeclListAST.hh
EnqueueStatementAST.cc
EnqueueStatementAST.hh
EnumDeclAST.cc
EnumDeclAST.hh
EnumExprAST.cc
EnumExprAST.hh
ExprAST.cc
ExprAST.hh
ExprStatementAST.cc
ExprStatementAST.hh
FormalParamAST.cc
FormalParamAST.hh
FuncCallExprAST.cc
FuncCallExprAST.hh
FuncDeclAST.cc
FuncDeclAST.hh
IfStatementAST.cc
IfStatementAST.hh
InPortDeclAST.cc
InPortDeclAST.hh
InfixOperatorExprAST.cc
InfixOperatorExprAST.hh
LiteralExprAST.cc
LiteralExprAST.hh
Location.cc
Location.hh
MachineAST.cc
MachineAST.hh
MemberExprAST.cc
MemberExprAST.hh
MethodCallExprAST.cc
MethodCallExprAST.hh
ObjDeclAST.cc
ObjDeclAST.hh
OutPortDeclAST.cc
OutPortDeclAST.hh
PairAST.cc
PairAST.hh
PairListAST.cc
PairListAST.hh
PeekStatementAST.cc
PeekStatementAST.hh
ReturnStatementAST.cc
ReturnStatementAST.hh
StatementAST.cc
StatementAST.hh
StatementListAST.cc
StatementListAST.hh
TransitionDeclAST.cc
TransitionDeclAST.hh
TypeAST.cc
TypeAST.hh
TypeDeclAST.cc
TypeDeclAST.hh
TypeFieldAST.cc
TypeFieldAST.hh
TypeFieldEnumAST.cc
TypeFieldEnumAST.hh
TypeFieldMemberAST.cc
TypeFieldMemberAST.hh
TypeFieldMethodAST.cc
TypeFieldMethodAST.hh
VarExprAST.cc
VarExprAST.hh
/gem5/src/mem/slicc/generator/fileio.cc
/gem5/src/mem/slicc/generator/fileio.hh
/gem5/src/mem/slicc/generator/html_gen.cc
/gem5/src/mem/slicc/generator/html_gen.hh
/gem5/src/mem/slicc/generator/mif_gen.cc
/gem5/src/mem/slicc/generator/mif_gen.hh
/gem5/src/mem/slicc/main.cc
/gem5/src/mem/slicc/main.hh
/gem5/src/mem/slicc/parser/lexer.ll
/gem5/src/mem/slicc/parser/parser.yy
/gem5/src/mem/slicc/slicc_global.hh
/gem5/src/mem/slicc/symbols/Action.hh
/gem5/src/mem/slicc/symbols/Event.hh
/gem5/src/mem/slicc/symbols/Func.cc
/gem5/src/mem/slicc/symbols/Func.hh
/gem5/src/mem/slicc/symbols/State.hh
/gem5/src/mem/slicc/symbols/StateMachine.cc
/gem5/src/mem/slicc/symbols/StateMachine.hh
/gem5/src/mem/slicc/symbols/Symbol.cc
/gem5/src/mem/slicc/symbols/Symbol.hh
/gem5/src/mem/slicc/symbols/SymbolTable.cc
/gem5/src/mem/slicc/symbols/SymbolTable.hh
/gem5/src/mem/slicc/symbols/Transition.cc
/gem5/src/mem/slicc/symbols/Transition.hh
/gem5/src/mem/slicc/symbols/Type.cc
/gem5/src/mem/slicc/symbols/Type.hh
/gem5/src/mem/slicc/symbols/Var.cc
/gem5/src/mem/slicc/symbols/Var.hh
6145:15cca6ab723a 11-May-2009 Nathan Binkert <nate@binkert.org>

ruby: Import ruby and slicc from GEMS

We eventually plan to replace the m5 cache hierarchy with the GEMS
hierarchy, but for now we will make both live alongside eachother.


/gem5/src/mem/gems_common/Allocator.hh
/gem5/src/mem/gems_common/Map.hh
/gem5/src/mem/gems_common/PrioHeap.hh
/gem5/src/mem/gems_common/RefCnt.hh
/gem5/src/mem/gems_common/RefCnt_tester.cc
/gem5/src/mem/gems_common/RefCountable.hh
/gem5/src/mem/gems_common/Vector.hh
/gem5/src/mem/gems_common/calc_host.sh
/gem5/src/mem/gems_common/ioutil/attrlex.ll
/gem5/src/mem/gems_common/ioutil/attrparse.yy
/gem5/src/mem/gems_common/ioutil/confio.cc
/gem5/src/mem/gems_common/ioutil/confio.hh
/gem5/src/mem/gems_common/ioutil/embedtext.py
/gem5/src/mem/gems_common/ioutil/initvar.cc
/gem5/src/mem/gems_common/ioutil/initvar.hh
/gem5/src/mem/gems_common/ioutil/vardecl.hh
/gem5/src/mem/gems_common/std-includes.hh
/gem5/src/mem/gems_common/util.cc
/gem5/src/mem/gems_common/util.hh
/gem5/src/mem/protocol/LogTM.sm
/gem5/src/mem/protocol/MESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-mem.sm
/gem5/src/mem/protocol/MESI_CMP_directory-msg.sm
/gem5/src/mem/protocol/MESI_CMP_directory.slicc
/gem5/src/mem/protocol/MESI_CMP_filter_directory-L1cache.sm
/gem5/src/mem/protocol/MESI_CMP_filter_directory-L2cache.sm
/gem5/src/mem/protocol/MESI_CMP_filter_directory-mem.sm
/gem5/src/mem/protocol/MESI_CMP_filter_directory-msg.sm
/gem5/src/mem/protocol/MESI_CMP_filter_directory.slicc
/gem5/src/mem/protocol/MESI_CMP_filter_directory_m-mem.sm
/gem5/src/mem/protocol/MESI_CMP_filter_directory_m.slicc
/gem5/src/mem/protocol/MESI_SCMP_bankdirectory-L1cache.sm
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/gem5/src/mem/ruby/tester/SyntheticDriver.hh
/gem5/src/mem/ruby/tester/Tester.cc
/gem5/src/mem/ruby/tester/Tester.hh
/gem5/src/mem/ruby/tester/XactAbortRequestGenerator.cc
/gem5/src/mem/ruby/tester/XactAbortRequestGenerator.hh
/gem5/src/mem/ruby/tester/XactRequestGenerator.cc
/gem5/src/mem/ruby/tester/XactRequestGenerator.hh
/gem5/src/mem/ruby/tester/main.cc
/gem5/src/mem/ruby/tester/main.hh
/gem5/src/mem/ruby/tester/test_framework.cc
/gem5/src/mem/ruby/tester/test_framework.hh
/gem5/src/mem/slicc/README
AST.cc
AST.hh
ASTs.hh
ActionDeclAST.cc
ActionDeclAST.hh
AssignStatementAST.cc
AssignStatementAST.hh
CheckAllocateStatementAST.cc
CheckAllocateStatementAST.hh
CheckStopSlotsStatementAST.cc
CheckStopSlotsStatementAST.hh
ChipComponentAccessAST.cc
ChipComponentAccessAST.hh
CopyHeadStatementAST.cc
CopyHeadStatementAST.hh
DeclAST.cc
DeclAST.hh
DeclListAST.cc
DeclListAST.hh
EnqueueStatementAST.cc
EnqueueStatementAST.hh
EnumDeclAST.cc
EnumDeclAST.hh
EnumExprAST.cc
EnumExprAST.hh
ExprAST.cc
ExprAST.hh
ExprStatementAST.cc
ExprStatementAST.hh
FormalParamAST.cc
FormalParamAST.hh
FuncCallExprAST.cc
FuncCallExprAST.hh
FuncDeclAST.cc
FuncDeclAST.hh
IfStatementAST.cc
IfStatementAST.hh
InPortDeclAST.cc
InPortDeclAST.hh
InfixOperatorExprAST.cc
InfixOperatorExprAST.hh
LiteralExprAST.cc
LiteralExprAST.hh
Location.cc
Location.hh
MachineAST.cc
MachineAST.hh
MemberExprAST.cc
MemberExprAST.hh
MethodCallExprAST.cc
MethodCallExprAST.hh
ObjDeclAST.cc
ObjDeclAST.hh
OutPortDeclAST.cc
OutPortDeclAST.hh
PairAST.cc
PairAST.hh
PairListAST.cc
PairListAST.hh
PeekStatementAST.cc
PeekStatementAST.hh
ReturnStatementAST.cc
ReturnStatementAST.hh
StatementAST.cc
StatementAST.hh
StatementListAST.cc
StatementListAST.hh
TransitionDeclAST.cc
TransitionDeclAST.hh
TypeAST.cc
TypeAST.hh
TypeDeclAST.cc
TypeDeclAST.hh
TypeFieldAST.cc
TypeFieldAST.hh
TypeFieldEnumAST.cc
TypeFieldEnumAST.hh
TypeFieldMemberAST.cc
TypeFieldMemberAST.hh
TypeFieldMethodAST.cc
TypeFieldMethodAST.hh
VarExprAST.cc
VarExprAST.hh
/gem5/src/mem/slicc/doc/SLICC_V03.txt
/gem5/src/mem/slicc/doc/tutorial.tex
/gem5/src/mem/slicc/generator/fileio.cc
/gem5/src/mem/slicc/generator/fileio.hh
/gem5/src/mem/slicc/generator/html_gen.cc
/gem5/src/mem/slicc/generator/html_gen.hh
/gem5/src/mem/slicc/generator/mif_gen.cc
/gem5/src/mem/slicc/generator/mif_gen.hh
/gem5/src/mem/slicc/main.cc
/gem5/src/mem/slicc/main.hh
/gem5/src/mem/slicc/parser/lexer.ll
/gem5/src/mem/slicc/parser/parser.yy
/gem5/src/mem/slicc/slicc_global.hh
/gem5/src/mem/slicc/symbols/Action.hh
/gem5/src/mem/slicc/symbols/Event.hh
/gem5/src/mem/slicc/symbols/Func.cc
/gem5/src/mem/slicc/symbols/Func.hh
/gem5/src/mem/slicc/symbols/State.hh
/gem5/src/mem/slicc/symbols/StateMachine.cc
/gem5/src/mem/slicc/symbols/StateMachine.hh
/gem5/src/mem/slicc/symbols/Symbol.cc
/gem5/src/mem/slicc/symbols/Symbol.hh
/gem5/src/mem/slicc/symbols/SymbolTable.cc
/gem5/src/mem/slicc/symbols/SymbolTable.hh
/gem5/src/mem/slicc/symbols/Transition.cc
/gem5/src/mem/slicc/symbols/Transition.hh
/gem5/src/mem/slicc/symbols/Type.cc
/gem5/src/mem/slicc/symbols/Type.hh
/gem5/src/mem/slicc/symbols/Var.cc
/gem5/src/mem/slicc/symbols/Var.hh