History log of /gem5/src/mem/slicc/
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14184:11ac1337c5e2 16-Aug-2019 Gabe Black <gabeblack@google.com>

mem: Move ruby protocols into a directory called ruby_protocol.

Now that the gem5 protocols are split out, it would be nice to put them
in their own protocol directory. It's also confusing to have files
called *_protocol which are not in the protocol directory.

Change-Id: I7475ee111630050a2421816dfd290921baab9f71
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20230
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>


/gem5/src/cpu/testers/directedtest/InvalidateGenerator.hh
/gem5/src/cpu/testers/directedtest/SeriesRequestGenerator.hh
/gem5/src/cpu/testers/rubytest/Check.hh
/gem5/src/learning_gem5/part3/MSI-cache.sm
/gem5/src/learning_gem5/part3/SConsopts
/gem5/src/mem/protocol/GPU_RfO-SQC.sm
/gem5/src/mem/protocol/GPU_RfO-TCC.sm
/gem5/src/mem/protocol/GPU_RfO-TCCdir.sm
/gem5/src/mem/protocol/GPU_RfO-TCP.sm
/gem5/src/mem/protocol/GPU_RfO.slicc
/gem5/src/mem/protocol/GPU_VIPER-SQC.sm
/gem5/src/mem/protocol/GPU_VIPER-TCC.sm
/gem5/src/mem/protocol/GPU_VIPER-TCP.sm
/gem5/src/mem/protocol/GPU_VIPER.slicc
/gem5/src/mem/protocol/GPU_VIPER_Baseline.slicc
/gem5/src/mem/protocol/GPU_VIPER_Region-TCC.sm
/gem5/src/mem/protocol/GPU_VIPER_Region.slicc
/gem5/src/mem/protocol/Garnet_standalone-cache.sm
/gem5/src/mem/protocol/Garnet_standalone-dir.sm
/gem5/src/mem/protocol/Garnet_standalone-msg.sm
/gem5/src/mem/protocol/Garnet_standalone.slicc
/gem5/src/mem/protocol/MESI_Three_Level-L0cache.sm
/gem5/src/mem/protocol/MESI_Three_Level-L1cache.sm
/gem5/src/mem/protocol/MESI_Three_Level-msg.sm
/gem5/src/mem/protocol/MESI_Three_Level.slicc
/gem5/src/mem/protocol/MESI_Two_Level-L1cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-L2cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-dir.sm
/gem5/src/mem/protocol/MESI_Two_Level-dma.sm
/gem5/src/mem/protocol/MESI_Two_Level-msg.sm
/gem5/src/mem/protocol/MESI_Two_Level.slicc
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MI_example-dma.sm
/gem5/src/mem/protocol/MI_example-msg.sm
/gem5/src/mem/protocol/MI_example.slicc
/gem5/src/mem/protocol/MOESI_AMD_Base-CorePair.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-L3cache.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-Region-CorePair.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-Region-dir.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-Region-msg.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-RegionBuffer.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-RegionDir.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-dir.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-msg.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-probeFilter.sm
/gem5/src/mem/protocol/MOESI_AMD_Base.slicc
/gem5/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-msg.sm
/gem5/src/mem/protocol/MOESI_CMP_directory.slicc
/gem5/src/mem/protocol/MOESI_CMP_token-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_token-msg.sm
/gem5/src/mem/protocol/MOESI_CMP_token.slicc
/gem5/src/mem/protocol/MOESI_hammer-cache.sm
/gem5/src/mem/protocol/MOESI_hammer-dir.sm
/gem5/src/mem/protocol/MOESI_hammer-dma.sm
/gem5/src/mem/protocol/MOESI_hammer-msg.sm
/gem5/src/mem/protocol/MOESI_hammer.slicc
/gem5/src/mem/protocol/RubySlicc_ComponentMapping.sm
/gem5/src/mem/protocol/RubySlicc_Defines.sm
/gem5/src/mem/protocol/RubySlicc_Exports.sm
/gem5/src/mem/protocol/RubySlicc_MemControl.sm
/gem5/src/mem/protocol/RubySlicc_Types.sm
/gem5/src/mem/protocol/RubySlicc_Util.sm
/gem5/src/mem/protocol/RubySlicc_interfaces.slicc
/gem5/src/mem/protocol/SConscript
/gem5/src/mem/protocol/SConsopts
/gem5/src/mem/ruby/SConscript
/gem5/src/mem/ruby/common/MachineID.hh
/gem5/src/mem/ruby/network/Network.hh
/gem5/src/mem/ruby/network/Topology.hh
/gem5/src/mem/ruby/network/simple/Switch.hh
/gem5/src/mem/ruby/profiler/AccessTraceForAddress.hh
/gem5/src/mem/ruby/profiler/AddressProfiler.cc
/gem5/src/mem/ruby/profiler/AddressProfiler.hh
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/protocol/GPU_RfO-SQC.sm
/gem5/src/mem/ruby/protocol/GPU_RfO-TCC.sm
/gem5/src/mem/ruby/protocol/GPU_RfO-TCCdir.sm
/gem5/src/mem/ruby/protocol/GPU_RfO-TCP.sm
/gem5/src/mem/ruby/protocol/GPU_RfO.slicc
/gem5/src/mem/ruby/protocol/GPU_VIPER-SQC.sm
/gem5/src/mem/ruby/protocol/GPU_VIPER-TCC.sm
/gem5/src/mem/ruby/protocol/GPU_VIPER-TCP.sm
/gem5/src/mem/ruby/protocol/GPU_VIPER.slicc
/gem5/src/mem/ruby/protocol/GPU_VIPER_Baseline.slicc
/gem5/src/mem/ruby/protocol/GPU_VIPER_Region-TCC.sm
/gem5/src/mem/ruby/protocol/GPU_VIPER_Region.slicc
/gem5/src/mem/ruby/protocol/Garnet_standalone-cache.sm
/gem5/src/mem/ruby/protocol/Garnet_standalone-dir.sm
/gem5/src/mem/ruby/protocol/Garnet_standalone-msg.sm
/gem5/src/mem/ruby/protocol/Garnet_standalone.slicc
/gem5/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
/gem5/src/mem/ruby/protocol/MESI_Three_Level-L1cache.sm
/gem5/src/mem/ruby/protocol/MESI_Three_Level-msg.sm
/gem5/src/mem/ruby/protocol/MESI_Three_Level.slicc
/gem5/src/mem/ruby/protocol/MESI_Two_Level-L1cache.sm
/gem5/src/mem/ruby/protocol/MESI_Two_Level-L2cache.sm
/gem5/src/mem/ruby/protocol/MESI_Two_Level-dir.sm
/gem5/src/mem/ruby/protocol/MESI_Two_Level-dma.sm
/gem5/src/mem/ruby/protocol/MESI_Two_Level-msg.sm
/gem5/src/mem/ruby/protocol/MESI_Two_Level.slicc
/gem5/src/mem/ruby/protocol/MI_example-cache.sm
/gem5/src/mem/ruby/protocol/MI_example-dir.sm
/gem5/src/mem/ruby/protocol/MI_example-dma.sm
/gem5/src/mem/ruby/protocol/MI_example-msg.sm
/gem5/src/mem/ruby/protocol/MI_example.slicc
/gem5/src/mem/ruby/protocol/MOESI_AMD_Base-CorePair.sm
/gem5/src/mem/ruby/protocol/MOESI_AMD_Base-L3cache.sm
/gem5/src/mem/ruby/protocol/MOESI_AMD_Base-Region-CorePair.sm
/gem5/src/mem/ruby/protocol/MOESI_AMD_Base-Region-dir.sm
/gem5/src/mem/ruby/protocol/MOESI_AMD_Base-Region-msg.sm
/gem5/src/mem/ruby/protocol/MOESI_AMD_Base-RegionBuffer.sm
/gem5/src/mem/ruby/protocol/MOESI_AMD_Base-RegionDir.sm
/gem5/src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm
/gem5/src/mem/ruby/protocol/MOESI_AMD_Base-msg.sm
/gem5/src/mem/ruby/protocol/MOESI_AMD_Base-probeFilter.sm
/gem5/src/mem/ruby/protocol/MOESI_AMD_Base.slicc
/gem5/src/mem/ruby/protocol/MOESI_CMP_directory-L1cache.sm
/gem5/src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/ruby/protocol/MOESI_CMP_directory-dma.sm
/gem5/src/mem/ruby/protocol/MOESI_CMP_directory-msg.sm
/gem5/src/mem/ruby/protocol/MOESI_CMP_directory.slicc
/gem5/src/mem/ruby/protocol/MOESI_CMP_token-L1cache.sm
/gem5/src/mem/ruby/protocol/MOESI_CMP_token-L2cache.sm
/gem5/src/mem/ruby/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/ruby/protocol/MOESI_CMP_token-dma.sm
/gem5/src/mem/ruby/protocol/MOESI_CMP_token-msg.sm
/gem5/src/mem/ruby/protocol/MOESI_CMP_token.slicc
/gem5/src/mem/ruby/protocol/MOESI_hammer-cache.sm
/gem5/src/mem/ruby/protocol/MOESI_hammer-dir.sm
/gem5/src/mem/ruby/protocol/MOESI_hammer-dma.sm
/gem5/src/mem/ruby/protocol/MOESI_hammer-msg.sm
/gem5/src/mem/ruby/protocol/MOESI_hammer.slicc
/gem5/src/mem/ruby/protocol/RubySlicc_ComponentMapping.sm
/gem5/src/mem/ruby/protocol/RubySlicc_Defines.sm
/gem5/src/mem/ruby/protocol/RubySlicc_Exports.sm
/gem5/src/mem/ruby/protocol/RubySlicc_MemControl.sm
/gem5/src/mem/ruby/protocol/RubySlicc_Types.sm
/gem5/src/mem/ruby/protocol/RubySlicc_Util.sm
/gem5/src/mem/ruby/protocol/RubySlicc_interfaces.slicc
/gem5/src/mem/ruby/protocol/SConscript
/gem5/src/mem/ruby/protocol/SConsopts
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
/gem5/src/mem/ruby/slicc_interface/AbstractController.cc
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/slicc_interface/AbstractEntry.hh
/gem5/src/mem/ruby/slicc_interface/Message.hh
/gem5/src/mem/ruby/slicc_interface/RubyRequest.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
/gem5/src/mem/ruby/structures/CacheMemory.cc
/gem5/src/mem/ruby/structures/CacheMemory.hh
/gem5/src/mem/ruby/structures/DirectoryMemory.hh
/gem5/src/mem/ruby/structures/PerfectCacheMemory.hh
/gem5/src/mem/ruby/structures/PersistentTable.hh
/gem5/src/mem/ruby/system/CacheRecorder.hh
/gem5/src/mem/ruby/system/DMASequencer.cc
/gem5/src/mem/ruby/system/DMASequencer.hh
/gem5/src/mem/ruby/system/GPUCoalescer.hh
/gem5/src/mem/ruby/system/RubyPort.cc
/gem5/src/mem/ruby/system/RubyPort.hh
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/Sequencer.hh
/gem5/src/mem/ruby/system/VIPERCoalescer.hh
main.py
symbols/StateMachine.py
symbols/SymbolTable.py
symbols/Type.py
14097:1f8f4c773c49 27-Feb-2019 Pouya Fotouhi <pfotouhi@ucdavis.edu>

mem-ruby: Adding a new slicc statement - to not evict locked cachelines

Ruby caches block incoming ports with messages on a locked
address to make sure the line would not be replaced by others.
But they do not check the lock upon capacity/conflict misses.

This change adds a new slicc statement "check_on_cache_probe" which takes
two arguments (mandatoryQueue for the controller, and the line subject
to eviction - i.e. address returned by cacheProbe).
If the line is locked, incoming message is delayed for 1 cycle and the
controller skips this request (i.e. does not trigger an event).

Coherence protocols should be updated accordingly. One use case for MESI
Two Level will be added in a separate change.

Signed-off-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>
Change-Id: I79ca2d45518de7a4e382b520a11f8e221b0cb803
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16808
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Srikant Bharadwaj <srikant.bharadwaj@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

13720:18f5d3990ac9 26-Jan-2019 Andreas Sandberg <andreas.sandberg@arm.com>

python: Stop using basestring to test for strings

The base class basestring doesn't exist in Python 3. Use string_types
from six instead.

Change-Id: I7e84903fb7dd4a0af7ae4e9f4ec2e54338f212bb
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15998
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Juha Jäykkä <juha.jaykka@arm.com>

13709:dd6b7ac5801f 26-Jan-2019 Andreas Sandberg <andreas.sandberg@arm.com>

python: Make iterator handling Python 3 compatible

Many functions that used to return lists (e.g., dict.items()) now
return iterators and their iterator counterparts (e.g.,
dict.iteritems()) have been removed. Switch calls to the Python 2.7
iterator methods to use the Python 3 equivalent and add explicit list
conversions where necessary.

Change-Id: I0c18114955af8f4932d81fb689a0adb939dafaba
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15992
Reviewed-by: Juha Jäykkä <juha.jaykka@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

13675:afeab32b3655 24-Jan-2019 Andreas Sandberg <andreas.sandberg@arm.com>

python: Replace dict.has_key with 'key in dict'

Python 3 has removed dict.has_key in favour of 'key in dict'.

Change-Id: I9852a5f57d672bea815308eb647a0ce45624fad5
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15987
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

13672:2969e4d5abf4 12-Feb-2019 Andreas Sandberg <andreas.sandberg@arm.com>

python: Replace orderdict with collections.OrderedDict

Python 2.7 and newer has support for ordered dictionaries in the
standard library. Remove this custom class.

Change-Id: I4b720405aa3c4ce8d5c0b401eefe744a85ac3a3e
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/16362
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

13665:9c7fe3811b88 25-Jan-2019 Andreas Sandberg <andreas.sandberg@arm.com>

python: Don't assume SimObjects live in the global namespace

The importer in Python 3 doesn't like the way we import SimObjects
from the global namespace. Convert the existing SimObject declarations
to import from m5.objects. As a side-effect, this makes these files
consistent with configuration files.

Change-Id: I11153502b430822130722839e1fa767b82a027aa
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15981
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>


/gem5/src/arch/alpha/AlphaSystem.py
/gem5/src/arch/alpha/AlphaTLB.py
/gem5/src/arch/arm/ArmISA.py
/gem5/src/arch/arm/ArmNativeTrace.py
/gem5/src/arch/arm/ArmPMU.py
/gem5/src/arch/arm/ArmSemihosting.py
/gem5/src/arch/arm/ArmSystem.py
/gem5/src/arch/arm/ArmTLB.py
/gem5/src/arch/arm/tracers/TarmacTrace.py
/gem5/src/arch/mips/MipsSystem.py
/gem5/src/arch/mips/MipsTLB.py
/gem5/src/arch/power/PowerTLB.py
/gem5/src/arch/riscv/RiscvSystem.py
/gem5/src/arch/riscv/RiscvTLB.py
/gem5/src/arch/sparc/SparcNativeTrace.py
/gem5/src/arch/sparc/SparcSystem.py
/gem5/src/arch/sparc/SparcTLB.py
/gem5/src/arch/x86/X86LocalApic.py
/gem5/src/arch/x86/X86NativeTrace.py
/gem5/src/arch/x86/X86System.py
/gem5/src/arch/x86/X86TLB.py
/gem5/src/base/vnc/Vnc.py
/gem5/src/cpu/BaseCPU.py
/gem5/src/cpu/CPUTracers.py
/gem5/src/cpu/CheckerCPU.py
/gem5/src/cpu/DummyChecker.py
/gem5/src/cpu/InstPBTrace.py
/gem5/src/cpu/kvm/BaseKvmCPU.py
/gem5/src/cpu/kvm/X86KvmCPU.py
/gem5/src/cpu/minor/MinorCPU.py
/gem5/src/cpu/o3/FUPool.py
/gem5/src/cpu/o3/FuncUnitConfig.py
/gem5/src/cpu/o3/O3CPU.py
/gem5/src/cpu/o3/O3Checker.py
/gem5/src/cpu/o3/probe/ElasticTrace.py
/gem5/src/cpu/o3/probe/SimpleTrace.py
/gem5/src/cpu/simple/AtomicSimpleCPU.py
/gem5/src/cpu/simple/BaseSimpleCPU.py
/gem5/src/cpu/simple/NonCachingSimpleCPU.py
/gem5/src/cpu/simple/TimingSimpleCPU.py
/gem5/src/cpu/simple/probes/SimPoint.py
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.py
/gem5/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.py
/gem5/src/cpu/testers/memtest/MemTest.py
/gem5/src/cpu/testers/rubytest/RubyTester.py
/gem5/src/cpu/testers/traffic_gen/BaseTrafficGen.py
/gem5/src/cpu/testers/traffic_gen/PyTrafficGen.py
/gem5/src/cpu/testers/traffic_gen/TrafficGen.py
/gem5/src/cpu/trace/TraceCPU.py
/gem5/src/dev/BadDevice.py
/gem5/src/dev/Device.py
/gem5/src/dev/Platform.py
/gem5/src/dev/alpha/AlphaBackdoor.py
/gem5/src/dev/alpha/Tsunami.py
/gem5/src/dev/arm/EnergyCtrl.py
/gem5/src/dev/arm/FlashDevice.py
/gem5/src/dev/arm/Gic.py
/gem5/src/dev/arm/NoMali.py
/gem5/src/dev/arm/RealView.py
/gem5/src/dev/arm/UFSHostDevice.py
/gem5/src/dev/arm/VirtIOMMIO.py
/gem5/src/dev/i2c/I2C.py
/gem5/src/dev/mips/Malta.py
/gem5/src/dev/net/Ethernet.py
/gem5/src/dev/pci/CopyEngine.py
/gem5/src/dev/pci/PciDevice.py
/gem5/src/dev/pci/PciHost.py
/gem5/src/dev/serial/Terminal.py
/gem5/src/dev/serial/Uart.py
/gem5/src/dev/sparc/T1000.py
/gem5/src/dev/storage/Ide.py
/gem5/src/dev/virtio/VirtIO.py
/gem5/src/dev/virtio/VirtIO9P.py
/gem5/src/dev/virtio/VirtIOBlock.py
/gem5/src/dev/virtio/VirtIOConsole.py
/gem5/src/dev/x86/Cmos.py
/gem5/src/dev/x86/I8042.py
/gem5/src/dev/x86/I82094AA.py
/gem5/src/dev/x86/I8237.py
/gem5/src/dev/x86/I8254.py
/gem5/src/dev/x86/I8259.py
/gem5/src/dev/x86/Pc.py
/gem5/src/dev/x86/PcSpeaker.py
/gem5/src/dev/x86/SouthBridge.py
/gem5/src/gpu-compute/GPU.py
/gem5/src/gpu-compute/LdsState.py
/gem5/src/learning_gem5/part2/SimpleCache.py
/gem5/src/learning_gem5/part2/SimpleMemobj.py
/gem5/src/mem/AbstractMemory.py
/gem5/src/mem/AddrMapper.py
/gem5/src/mem/Bridge.py
/gem5/src/mem/CommMonitor.py
/gem5/src/mem/DRAMCtrl.py
/gem5/src/mem/ExternalMaster.py
/gem5/src/mem/ExternalSlave.py
/gem5/src/mem/HMCController.py
/gem5/src/mem/MemChecker.py
/gem5/src/mem/MemDelay.py
/gem5/src/mem/MemObject.py
/gem5/src/mem/SerialLink.py
/gem5/src/mem/SimpleMemory.py
/gem5/src/mem/XBar.py
/gem5/src/mem/cache/Cache.py
/gem5/src/mem/cache/prefetch/Prefetcher.py
/gem5/src/mem/cache/tags/Tags.py
/gem5/src/mem/probes/MemFootprintProbe.py
/gem5/src/mem/probes/MemTraceProbe.py
/gem5/src/mem/probes/StackDistProbe.py
/gem5/src/mem/qos/QoSMemCtrl.py
/gem5/src/mem/qos/QoSMemSinkCtrl.py
/gem5/src/mem/ruby/network/BasicRouter.py
/gem5/src/mem/ruby/network/Network.py
/gem5/src/mem/ruby/network/garnet2.0/GarnetLink.py
/gem5/src/mem/ruby/network/garnet2.0/GarnetNetwork.py
/gem5/src/mem/ruby/network/simple/SimpleLink.py
/gem5/src/mem/ruby/network/simple/SimpleNetwork.py
/gem5/src/mem/ruby/slicc_interface/Controller.py
/gem5/src/mem/ruby/structures/LRUReplacementPolicy.py
/gem5/src/mem/ruby/structures/PseudoLRUReplacementPolicy.py
/gem5/src/mem/ruby/structures/RubyCache.py
/gem5/src/mem/ruby/structures/RubyPrefetcher.py
/gem5/src/mem/ruby/system/GPUCoalescer.py
/gem5/src/mem/ruby/system/RubySystem.py
/gem5/src/mem/ruby/system/Sequencer.py
/gem5/src/mem/ruby/system/VIPERCoalescer.py
/gem5/src/mem/ruby/system/WeightedLRUReplacementPolicy.py
symbols/StateMachine.py
/gem5/src/sim/System.py
/gem5/src/sim/TickedObject.py
/gem5/src/sim/power/MathExprPowerModel.py
/gem5/src/sim/power/ThermalModel.py
12765:8c15915ba978 28-May-2018 Jason Lowe-Power <jason@lowepower.com>

ruby: Revamp standalone SLICC script

There was some bitrot in the standalone SLICC script (util/slicc and
src/mem/slicc/main.py). Fix the changes to the SLICC interface and also
add some better documentation.

Change-Id: I91c0ec78d5072fba83edf32b661ae67967af7822
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/10561
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

12662:bcda9eb2aef5 16-Apr-2018 John Alsop <johnathan.alsop@amd.com>

mem-ruby: enable DPRINTFN calls in slicc for temporary debug printing

Change-Id: Ib92f8bb4ab7b61ebc96b935cb8abc42cf5ec6ac8
Reviewed-on: https://gem5-review.googlesource.com/9921
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

12612:a64e6b723e5f 27-Jul-2017 Jason Lowe-Power <jason@lowepower.com>

ruby: Make sure addresses print in hex

Added fix in the invalid transition panic and various places in ruby
random tester.

Change-Id: I879264da58369faf7de49d1a28b2da1cb935ef0a
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/8941
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

12563:8d59ed22ae79 06-Mar-2018 Gabe Black <gabeblack@google.com>

scons: Switch from the print statement to the print function.

Starting with version 3, scons imposes using the print function instead
of the print statement in code it processes. To get things building
again, this change moves all python code within gem5 to use the
function version. Another change by another author separately made this
same change to the site_tools and site_init.py files.

Change-Id: I2de7dc3b1be756baad6f60574c47c8b7e80ea3b0
Reviewed-on: https://gem5-review.googlesource.com/8761
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

12436:c56112090c61 02-Jan-2018 Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-ruby: Remove function that maps responses to a DMA engine

The function map_Address_to_DMA was used to route responses to the
first (and assumed to be the only) DMA engine in the system. This
function is now unused as protocols handle responses and route them to
the right DMA engine.

Change-Id: I2fba913cf2f12321d1a1e38e7ee85bdf26b8a47a
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/7162
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

12392:e0dbdf30a2a5 13-Dec-2017 Jason Lowe-Power <jason@lowepower.com>

misc: Updates for gcc7.2 for x86

GCC 7.2 is much stricter than previous GCC versions. The following changes
are needed:

* There is now a warning if there is an implicit fallthrough between two
case statments. C++17 adds the [[fallthrough]]; declaration. However,
to support non C++17 standards (i.e., C++11), we use M5_FALLTHROUGH.
M5_FALLTHROUGH checks for [[fallthrough]] compliant C++17 compiler and
if that doesn't exist, it defaults to nothing (no older compilers
generate warnings).
* The above resulted in a couple of bugs that were found. This is noted
in the review request on gerrit.
* throw() for dynamic exception specification is deprecated
* There were a couple of new uninitialized variable warnings
* Can no longer perform bitwise operations on a bool.
* Must now include <functional> for std::function
* Compiler bug for void* lambda. Changed to auto as work around. See
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82878

Change-Id: I5d4c782a4e133fa4cdb119e35d9aff68c6e2958e
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/5802
Reviewed-by: Gabe Black <gabeblack@google.com>

12334:e0ab29a34764 30-Nov-2017 Gabe Black <gabeblack@google.com>

misc: Rename misc.(hh|cc) to logging.(hh|cc)

These files aren't a collection of miscellaneous stuff, they're the
definition of the Logger interface, and a few utility macros for
calling into that interface (panic, warn, etc.).

Change-Id: I84267ac3f45896a83c0ef027f8f19c5e9a5667d1
Reviewed-on: https://gem5-review.googlesource.com/6226
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>


/gem5/ext/sst/gem5.cc
/gem5/src/arch/alpha/isa.cc
/gem5/src/arch/alpha/locked_mem.hh
/gem5/src/arch/alpha/mt.hh
/gem5/src/arch/alpha/process.cc
/gem5/src/arch/alpha/pseudo_inst.hh
/gem5/src/arch/alpha/utility.hh
/gem5/src/arch/arm/faults.hh
/gem5/src/arch/arm/isa_device.cc
/gem5/src/arch/arm/miscregs.cc
/gem5/src/arch/arm/process.cc
/gem5/src/arch/arm/pseudo_inst.hh
/gem5/src/arch/arm/types.hh
/gem5/src/arch/arm/utility.hh
/gem5/src/arch/generic/debugfaults.hh
/gem5/src/arch/generic/pseudo_inst.cc
/gem5/src/arch/generic/tlb.hh
/gem5/src/arch/generic/vec_reg.hh
/gem5/src/arch/hsail/gpu_isa.hh
/gem5/src/arch/mips/decoder.hh
/gem5/src/arch/mips/dsp.cc
/gem5/src/arch/mips/dsp.hh
/gem5/src/arch/mips/interrupts.hh
/gem5/src/arch/mips/locked_mem.hh
/gem5/src/arch/mips/mt.hh
/gem5/src/arch/mips/pagetable.hh
/gem5/src/arch/mips/process.cc
/gem5/src/arch/mips/pseudo_inst.hh
/gem5/src/arch/mips/registers.hh
/gem5/src/arch/mips/utility.cc
/gem5/src/arch/mips/utility.hh
/gem5/src/arch/power/interrupts.hh
/gem5/src/arch/power/isa.hh
/gem5/src/arch/power/process.cc
/gem5/src/arch/power/pseudo_inst.hh
/gem5/src/arch/power/utility.cc
/gem5/src/arch/riscv/decoder.hh
/gem5/src/arch/riscv/interrupts.hh
/gem5/src/arch/riscv/isa.hh
/gem5/src/arch/riscv/locked_mem.hh
/gem5/src/arch/riscv/pagetable.hh
/gem5/src/arch/riscv/process.cc
/gem5/src/arch/riscv/pseudo_inst.hh
/gem5/src/arch/sparc/isa/includes.isa
/gem5/src/arch/sparc/mt.hh
/gem5/src/arch/sparc/pagetable.hh
/gem5/src/arch/sparc/process.cc
/gem5/src/arch/sparc/pseudo_inst.hh
/gem5/src/arch/sparc/tlb.hh
/gem5/src/arch/sparc/utility.hh
/gem5/src/arch/x86/bios/intelmp.cc
/gem5/src/arch/x86/decoder.cc
/gem5/src/arch/x86/decoder.hh
/gem5/src/arch/x86/emulenv.cc
/gem5/src/arch/x86/faults.hh
/gem5/src/arch/x86/isa/includes.isa
/gem5/src/arch/x86/process.cc
/gem5/src/arch/x86/regs/int.hh
/gem5/src/base/SConscript
/gem5/src/base/addr_range.hh
/gem5/src/base/bigint.hh
/gem5/src/base/bmpwriter.cc
/gem5/src/base/circlebuf.hh
/gem5/src/base/debug.cc
/gem5/src/base/hostinfo.cc
/gem5/src/base/imgwriter.cc
/gem5/src/base/intmath.hh
/gem5/src/base/loader/ecoff_object.cc
/gem5/src/base/loader/elf_object.cc
/gem5/src/base/loader/object_file.hh
/gem5/src/base/loader/symtab.cc
/gem5/src/base/logging.cc
/gem5/src/base/logging.hh
/gem5/src/base/misc.cc
/gem5/src/base/misc.hh
/gem5/src/base/output.cc
/gem5/src/base/pngwriter.cc
/gem5/src/base/pollevent.cc
/gem5/src/base/random.cc
/gem5/src/base/socket.cc
/gem5/src/base/statistics.cc
/gem5/src/base/stats/text.cc
/gem5/src/base/time.cc
/gem5/src/base/trace.cc
/gem5/src/base/trie.hh
/gem5/src/base/vnc/vncinput.cc
/gem5/src/base/vnc/vncserver.cc
/gem5/src/cpu/base.cc
/gem5/src/cpu/func_unit.cc
/gem5/src/cpu/intr_control.hh
/gem5/src/cpu/kvm/device.cc
/gem5/src/cpu/kvm/perfevent.cc
/gem5/src/cpu/kvm/timer.cc
/gem5/src/cpu/minor/buffers.hh
/gem5/src/cpu/o3/free_list.hh
/gem5/src/cpu/o3/store_set.cc
/gem5/src/cpu/pc_event.hh
/gem5/src/cpu/pred/2bit_local.cc
/gem5/src/cpu/pred/btb.hh
/gem5/src/cpu/pred/ltage.cc
/gem5/src/cpu/pred/sat_counter.hh
/gem5/src/cpu/simple/base.cc
/gem5/src/cpu/static_inst.hh
/gem5/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc
/gem5/src/cpu/testers/rubytest/RubyTester.cc
/gem5/src/cpu/thread_context.cc
/gem5/src/dev/intel_8254_timer.cc
/gem5/src/dev/mc146818.hh
/gem5/src/dev/net/dist_iface.hh
/gem5/src/dev/net/etherbus.cc
/gem5/src/dev/net/etherdump.cc
/gem5/src/dev/net/etherint.cc
/gem5/src/dev/net/etherpkt.cc
/gem5/src/dev/net/ethertap.cc
/gem5/src/dev/net/pktfifo.cc
/gem5/src/dev/net/pktfifo.hh
/gem5/src/dev/pci/device.cc
/gem5/src/dev/platform.cc
/gem5/src/dev/ps2.cc
/gem5/src/dev/serial/serial.cc
/gem5/src/dev/serial/terminal.cc
/gem5/src/dev/storage/disk_image.cc
/gem5/src/dev/storage/simple_disk.cc
/gem5/src/gpu-compute/brig_object.cc
/gem5/src/gpu-compute/gpu_tlb.hh
/gem5/src/gpu-compute/hsa_object.cc
/gem5/src/gpu-compute/misc.hh
/gem5/src/gpu-compute/of_scheduling_policy.hh
/gem5/src/gpu-compute/rr_scheduling_policy.hh
/gem5/src/gpu-compute/simple_pool_manager.cc
/gem5/src/gpu-compute/tlb_coalescer.hh
/gem5/src/gpu-compute/vector_register_file.cc
/gem5/src/gpu-compute/wavefront.hh
/gem5/src/kern/operatingsystem.cc
/gem5/src/mem/cache/base.hh
/gem5/src/mem/cache/cache.cc
/gem5/src/mem/cache/cache.hh
/gem5/src/mem/cache/mshr.cc
/gem5/src/mem/cache/tags/fa_lru.cc
/gem5/src/mem/cache/write_queue_entry.cc
/gem5/src/mem/coherent_xbar.cc
/gem5/src/mem/dramsim2_wrapper.cc
/gem5/src/mem/mem_checker.hh
/gem5/src/mem/noncoherent_xbar.cc
/gem5/src/mem/packet.cc
/gem5/src/mem/packet.hh
/gem5/src/mem/request.hh
/gem5/src/mem/ruby/common/Set.hh
/gem5/src/mem/ruby/network/MessageBuffer.cc
/gem5/src/mem/ruby/network/Network.cc
/gem5/src/mem/ruby/network/fault_model/FaultModel.cc
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
/gem5/src/mem/ruby/structures/AbstractReplacementPolicy.cc
/gem5/src/mem/ruby/system/GPUCoalescer.cc
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/VIPERCoalescer.cc
symbols/StateMachine.py
symbols/Type.py
/gem5/src/mem/snoop_filter.cc
/gem5/src/mem/xbar.cc
/gem5/src/proto/protoio.cc
/gem5/src/python/pybind11/core.cc
/gem5/src/python/pybind11/event.cc
/gem5/src/sim/clocked_object.cc
/gem5/src/sim/drain.cc
/gem5/src/sim/dvfs_handler.cc
/gem5/src/sim/eventq.cc
/gem5/src/sim/faults.cc
/gem5/src/sim/fd_array.cc
/gem5/src/sim/init.cc
/gem5/src/sim/init_signals.cc
/gem5/src/sim/mathexpr.cc
/gem5/src/sim/microcode_rom.cc
/gem5/src/sim/root.cc
/gem5/src/sim/serialize.cc
/gem5/src/sim/sim_object.cc
/gem5/src/sim/simulate.cc
/gem5/src/sim/syscall_emul.hh
/gem5/src/unittest/cprintftest.cc
/gem5/src/unittest/nmtest.cc
/gem5/src/unittest/stattest.cc
/gem5/util/systemc/sc_module.cc
12065:e3e51756dfef 13-Mar-2017 Nikos Nikoleris <nikos.nikoleris@arm.com>

ruby: Add support for address ranges in the directory

Previously the directory covered a flat address range that always
started from address 0. This change adds a vector of address ranges
with interleaving and hashing that each directory keeps track of and
the necessary flexibility to support systems with non continuous
memory ranges.

Change-Id: I6ea1c629bdf4c5137b7d9c89dbaf6c826adfd977
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2903
Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>


/gem5/configs/ruby/GPU_RfO.py
/gem5/configs/ruby/Garnet_standalone.py
/gem5/configs/ruby/MESI_Three_Level.py
/gem5/configs/ruby/MESI_Two_Level.py
/gem5/configs/ruby/MI_example.py
/gem5/configs/ruby/MOESI_AMD_Base.py
/gem5/configs/ruby/MOESI_CMP_directory.py
/gem5/configs/ruby/MOESI_CMP_token.py
/gem5/configs/ruby/MOESI_hammer.py
/gem5/configs/ruby/Ruby.py
/gem5/src/base/addr_range.hh
/gem5/src/mem/protocol/GPU_RfO-TCCdir.sm
/gem5/src/mem/protocol/GPU_VIPER-TCC.sm
/gem5/src/mem/protocol/GPU_VIPER_Region-TCC.sm
/gem5/src/mem/protocol/Garnet_standalone-cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-L2cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-dma.sm
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dma.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-CorePair.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-L3cache.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-Region-CorePair.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-Region-dir.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-RegionBuffer.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-RegionDir.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-probeFilter.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dma.sm
/gem5/src/mem/protocol/MOESI_hammer-cache.sm
/gem5/src/mem/protocol/MOESI_hammer-dma.sm
/gem5/src/mem/protocol/RubySlicc_ComponentMapping.sm
/gem5/src/mem/ruby/network/Network.cc
/gem5/src/mem/ruby/network/Network.hh
/gem5/src/mem/ruby/slicc_interface/AbstractController.cc
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/slicc_interface/Controller.py
/gem5/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
/gem5/src/mem/ruby/structures/DirectoryMemory.cc
/gem5/src/mem/ruby/structures/DirectoryMemory.hh
/gem5/src/mem/ruby/structures/DirectoryMemory.py
symbols/Type.py
11888:d89dc575c7cb 05-Feb-2017 Lena Olson <leolson@google.com>

ruby: fix and/or precedence in slicc

The slicc compiler currently treats && and || with the same precedence.
This is highly non-intuitive to people used to C, and was probably an
error. This patch makes && bind tighter than ||.

For example, previously:
if (A || B && C)
compiled to:
if ((A || B) && C)
With this patch, it compiles to:
if (A || (B && C))

Change-Id: Idbbd5b50cc86a8d6601045adc14a253284d7b791
Signed-off-by: Lena Olson (leolson@google.com)
Reviewed-on: https://gem5-review.googlesource.com/2168
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Joe Gross <criusx@gmail.com>
Reviewed-by: Sooraj Puthoor <puthoorsooraj@gmail.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
[ Rebased onto master ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>

11793:ef606668d247 09-Nov-2016 Brandon Potter <brandon.potter@amd.com>

style: [patch 1/22] use /r/3648/ to reorganize includes


/gem5/src/arch/alpha/faults.cc
/gem5/src/arch/alpha/freebsd/system.cc
/gem5/src/arch/alpha/idle_event.cc
/gem5/src/arch/alpha/ipr.cc
/gem5/src/arch/alpha/isa.cc
/gem5/src/arch/alpha/kernel_stats.cc
/gem5/src/arch/alpha/linux/process.cc
/gem5/src/arch/alpha/linux/system.cc
/gem5/src/arch/alpha/pagetable.cc
/gem5/src/arch/alpha/process.cc
/gem5/src/arch/alpha/remote_gdb.cc
/gem5/src/arch/alpha/stacktrace.cc
/gem5/src/arch/alpha/system.cc
/gem5/src/arch/alpha/utility.cc
/gem5/src/arch/alpha/vtophys.cc
/gem5/src/arch/arm/faults.cc
/gem5/src/arch/arm/insts/macromem.cc
/gem5/src/arch/arm/insts/mem.cc
/gem5/src/arch/arm/insts/mem64.cc
/gem5/src/arch/arm/insts/misc.cc
/gem5/src/arch/arm/insts/pseudo.cc
/gem5/src/arch/arm/insts/static_inst.cc
/gem5/src/arch/arm/interrupts.cc
/gem5/src/arch/arm/isa.cc
/gem5/src/arch/arm/kvm/base_cpu.cc
/gem5/src/arch/arm/linux/process.cc
/gem5/src/arch/arm/linux/system.cc
/gem5/src/arch/arm/miscregs.cc
/gem5/src/arch/arm/nativetrace.cc
/gem5/src/arch/arm/process.cc
/gem5/src/arch/arm/remote_gdb.cc
/gem5/src/arch/arm/stacktrace.cc
/gem5/src/arch/arm/stage2_lookup.cc
/gem5/src/arch/arm/system.cc
/gem5/src/arch/arm/tlb.cc
/gem5/src/arch/arm/utility.cc
/gem5/src/arch/arm/vtophys.cc
/gem5/src/arch/generic/decode_cache.cc
/gem5/src/arch/generic/mmapped_ipr.cc
/gem5/src/arch/generic/pseudo_inst.cc
/gem5/src/arch/mips/bare_iron/system.cc
/gem5/src/arch/mips/dsp.cc
/gem5/src/arch/mips/faults.cc
/gem5/src/arch/mips/idle_event.cc
/gem5/src/arch/mips/interrupts.cc
/gem5/src/arch/mips/isa.cc
/gem5/src/arch/mips/linux/process.cc
/gem5/src/arch/mips/linux/system.cc
/gem5/src/arch/mips/pagetable.cc
/gem5/src/arch/mips/process.cc
/gem5/src/arch/mips/remote_gdb.cc
/gem5/src/arch/mips/stacktrace.cc
/gem5/src/arch/mips/system.cc
/gem5/src/arch/mips/tlb.cc
/gem5/src/arch/mips/utility.cc
/gem5/src/arch/mips/vtophys.cc
/gem5/src/arch/power/insts/branch.cc
/gem5/src/arch/power/insts/mem.cc
/gem5/src/arch/power/insts/static_inst.cc
/gem5/src/arch/power/isa.cc
/gem5/src/arch/power/linux/process.cc
/gem5/src/arch/power/pagetable.cc
/gem5/src/arch/power/process.cc
/gem5/src/arch/power/stacktrace.cc
/gem5/src/arch/power/tlb.cc
/gem5/src/arch/power/utility.cc
/gem5/src/arch/sparc/faults.cc
/gem5/src/arch/sparc/isa.cc
/gem5/src/arch/sparc/linux/process.cc
/gem5/src/arch/sparc/nativetrace.cc
/gem5/src/arch/sparc/pagetable.cc
/gem5/src/arch/sparc/process.cc
/gem5/src/arch/sparc/remote_gdb.cc
/gem5/src/arch/sparc/solaris/process.cc
/gem5/src/arch/sparc/system.cc
/gem5/src/arch/sparc/tlb.cc
/gem5/src/arch/sparc/ua2005.cc
/gem5/src/arch/sparc/utility.cc
/gem5/src/arch/sparc/vtophys.cc
/gem5/src/arch/x86/bios/acpi.cc
/gem5/src/arch/x86/bios/e820.cc
/gem5/src/arch/x86/bios/intelmp.cc
/gem5/src/arch/x86/bios/smbios.cc
/gem5/src/arch/x86/cpuid.cc
/gem5/src/arch/x86/decoder.cc
/gem5/src/arch/x86/emulenv.cc
/gem5/src/arch/x86/faults.cc
/gem5/src/arch/x86/insts/badmicroop.cc
/gem5/src/arch/x86/insts/microfpop.cc
/gem5/src/arch/x86/insts/microldstop.cc
/gem5/src/arch/x86/insts/micromediaop.cc
/gem5/src/arch/x86/insts/microop.cc
/gem5/src/arch/x86/insts/microregop.cc
/gem5/src/arch/x86/insts/static_inst.cc
/gem5/src/arch/x86/interrupts.cc
/gem5/src/arch/x86/isa.cc
/gem5/src/arch/x86/linux/process.cc
/gem5/src/arch/x86/linux/system.cc
/gem5/src/arch/x86/nativetrace.cc
/gem5/src/arch/x86/pagetable.cc
/gem5/src/arch/x86/pagetable_walker.cc
/gem5/src/arch/x86/process.cc
/gem5/src/arch/x86/pseudo_inst.cc
/gem5/src/arch/x86/remote_gdb.cc
/gem5/src/arch/x86/stacktrace.cc
/gem5/src/arch/x86/system.cc
/gem5/src/arch/x86/tlb.cc
/gem5/src/arch/x86/types.cc
/gem5/src/arch/x86/utility.cc
/gem5/src/arch/x86/vtophys.cc
/gem5/src/base/atomicio.cc
/gem5/src/base/bigint.cc
/gem5/src/base/cp_annotate.cc
/gem5/src/base/cprintf.cc
/gem5/src/base/debug.cc
/gem5/src/base/hostinfo.cc
/gem5/src/base/inet.cc
/gem5/src/base/inifile.cc
/gem5/src/base/loader/aout_object.cc
/gem5/src/base/loader/dtb_object.cc
/gem5/src/base/loader/ecoff_object.cc
/gem5/src/base/loader/hex_file.cc
/gem5/src/base/loader/object_file.cc
/gem5/src/base/loader/raw_object.cc
/gem5/src/base/loader/symtab.cc
/gem5/src/base/match.cc
/gem5/src/base/misc.cc
/gem5/src/base/output.cc
/gem5/src/base/pollevent.cc
/gem5/src/base/random.cc
/gem5/src/base/remote_gdb.cc
/gem5/src/base/socket.cc
/gem5/src/base/statistics.cc
/gem5/src/base/stats/text.cc
/gem5/src/base/str.cc
/gem5/src/base/time.cc
/gem5/src/base/trace.cc
/gem5/src/base/vnc/vncinput.cc
/gem5/src/base/vnc/vncserver.cc
/gem5/src/cpu/activity.cc
/gem5/src/cpu/base.cc
/gem5/src/cpu/checker/cpu.cc
/gem5/src/cpu/dummy_checker.cc
/gem5/src/cpu/exetrace.cc
/gem5/src/cpu/func_unit.cc
/gem5/src/cpu/inteltrace.cc
/gem5/src/cpu/intr_control.cc
/gem5/src/cpu/kvm/base.cc
/gem5/src/cpu/kvm/perfevent.cc
/gem5/src/cpu/kvm/timer.cc
/gem5/src/cpu/kvm/vm.cc
/gem5/src/cpu/kvm/x86_cpu.cc
/gem5/src/cpu/minor/activity.cc
/gem5/src/cpu/minor/cpu.cc
/gem5/src/cpu/minor/decode.cc
/gem5/src/cpu/minor/dyn_inst.cc
/gem5/src/cpu/minor/execute.cc
/gem5/src/cpu/minor/fetch1.cc
/gem5/src/cpu/minor/fetch2.cc
/gem5/src/cpu/minor/func_unit.cc
/gem5/src/cpu/minor/lsq.cc
/gem5/src/cpu/minor/pipeline.cc
/gem5/src/cpu/minor/scoreboard.cc
/gem5/src/cpu/nativetrace.cc
/gem5/src/cpu/o3/base_dyn_inst.cc
/gem5/src/cpu/o3/checker.cc
/gem5/src/cpu/o3/cpu.cc
/gem5/src/cpu/o3/deriv.cc
/gem5/src/cpu/o3/free_list.cc
/gem5/src/cpu/o3/fu_pool.cc
/gem5/src/cpu/o3/probe/simple_trace.cc
/gem5/src/cpu/o3/regfile.cc
/gem5/src/cpu/o3/rename_map.cc
/gem5/src/cpu/o3/scoreboard.cc
/gem5/src/cpu/o3/store_set.cc
/gem5/src/cpu/o3/thread_context.cc
/gem5/src/cpu/pc_event.cc
/gem5/src/cpu/pred/2bit_local.cc
/gem5/src/cpu/pred/bi_mode.cc
/gem5/src/cpu/pred/btb.cc
/gem5/src/cpu/pred/tournament.cc
/gem5/src/cpu/profile.cc
/gem5/src/cpu/quiesce_event.cc
/gem5/src/cpu/simple/atomic.cc
/gem5/src/cpu/simple/base.cc
/gem5/src/cpu/simple/probes/simpoint.cc
/gem5/src/cpu/simple/timing.cc
/gem5/src/cpu/simple_thread.cc
/gem5/src/cpu/static_inst.cc
/gem5/src/cpu/testers/directedtest/DirectedGenerator.cc
/gem5/src/cpu/testers/directedtest/InvalidateGenerator.cc
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.cc
/gem5/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
/gem5/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc
/gem5/src/cpu/testers/memtest/memtest.cc
/gem5/src/cpu/testers/rubytest/Check.cc
/gem5/src/cpu/testers/rubytest/CheckTable.cc
/gem5/src/cpu/testers/rubytest/RubyTester.cc
/gem5/src/cpu/thread_context.cc
/gem5/src/cpu/thread_state.cc
/gem5/src/cpu/timing_expr.cc
/gem5/src/dev/alpha/backdoor.cc
/gem5/src/dev/alpha/tsunami.cc
/gem5/src/dev/alpha/tsunami_cchip.cc
/gem5/src/dev/alpha/tsunami_io.cc
/gem5/src/dev/arm/a9scu.cc
/gem5/src/dev/arm/amba_device.cc
/gem5/src/dev/arm/amba_fake.cc
/gem5/src/dev/arm/energy_ctrl.cc
/gem5/src/dev/arm/gic_pl390.cc
/gem5/src/dev/arm/hdlcd.cc
/gem5/src/dev/arm/kmi.cc
/gem5/src/dev/arm/pl011.cc
/gem5/src/dev/arm/pl111.cc
/gem5/src/dev/arm/realview.cc
/gem5/src/dev/arm/rtc_pl031.cc
/gem5/src/dev/arm/timer_cpulocal.cc
/gem5/src/dev/arm/timer_sp804.cc
/gem5/src/dev/arm/vgic.cc
/gem5/src/dev/baddev.cc
/gem5/src/dev/intel_8254_timer.cc
/gem5/src/dev/io_device.cc
/gem5/src/dev/isa_fake.cc
/gem5/src/dev/mc146818.cc
/gem5/src/dev/mips/malta.cc
/gem5/src/dev/mips/malta_cchip.cc
/gem5/src/dev/mips/malta_io.cc
/gem5/src/dev/pci/device.cc
/gem5/src/dev/pci/host.cc
/gem5/src/dev/platform.cc
/gem5/src/dev/ps2.cc
/gem5/src/dev/ps2.hh
/gem5/src/dev/sparc/dtod.cc
/gem5/src/dev/sparc/iob.cc
/gem5/src/dev/sparc/mm_disk.cc
/gem5/src/dev/sparc/t1000.cc
/gem5/src/dev/uart.cc
/gem5/src/dev/uart8250.cc
/gem5/src/dev/virtio/base.cc
/gem5/src/dev/virtio/block.cc
/gem5/src/dev/virtio/console.cc
/gem5/src/dev/virtio/fs9p.cc
/gem5/src/dev/virtio/pci.cc
/gem5/src/dev/x86/cmos.cc
/gem5/src/dev/x86/i8042.cc
/gem5/src/dev/x86/i82094aa.cc
/gem5/src/dev/x86/i8237.cc
/gem5/src/dev/x86/i8254.cc
/gem5/src/dev/x86/i8259.cc
/gem5/src/dev/x86/pc.cc
/gem5/src/dev/x86/south_bridge.cc
/gem5/src/dev/x86/speaker.cc
/gem5/src/kern/linux/linux.cc
/gem5/src/kern/linux/printk.cc
/gem5/src/kern/operatingsystem.cc
/gem5/src/kern/system_events.cc
/gem5/src/mem/abstract_mem.cc
/gem5/src/mem/bridge.cc
/gem5/src/mem/cache/prefetch/base.cc
/gem5/src/mem/cache/prefetch/queued.cc
/gem5/src/mem/cache/prefetch/stride.cc
/gem5/src/mem/coherent_xbar.cc
/gem5/src/mem/comm_monitor.cc
/gem5/src/mem/dram_ctrl.cc
/gem5/src/mem/drampower.cc
/gem5/src/mem/dramsim2.cc
/gem5/src/mem/dramsim2_wrapper.cc
/gem5/src/mem/external_master.cc
/gem5/src/mem/external_slave.cc
/gem5/src/mem/fs_translating_port_proxy.cc
/gem5/src/mem/hmc_controller.cc
/gem5/src/mem/mem_checker.cc
/gem5/src/mem/mem_checker_monitor.cc
/gem5/src/mem/noncoherent_xbar.cc
/gem5/src/mem/packet.cc
/gem5/src/mem/packet_queue.cc
/gem5/src/mem/page_table.cc
/gem5/src/mem/physical.cc
/gem5/src/mem/port.cc
/gem5/src/mem/port_proxy.cc
/gem5/src/mem/probes/base.cc
/gem5/src/mem/ruby/common/Histogram.cc
/gem5/src/mem/ruby/common/NetDest.cc
/gem5/src/mem/ruby/common/SubBlock.cc
/gem5/src/mem/ruby/filters/BlockBloomFilter.cc
/gem5/src/mem/ruby/filters/BulkBloomFilter.cc
/gem5/src/mem/ruby/filters/H3BloomFilter.cc
/gem5/src/mem/ruby/filters/LSB_CountingBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiGrainBloomFilter.cc
/gem5/src/mem/ruby/filters/NonCountingBloomFilter.cc
/gem5/src/mem/ruby/network/MessageBuffer.cc
/gem5/src/mem/ruby/network/Network.cc
/gem5/src/mem/ruby/network/Topology.cc
/gem5/src/mem/ruby/network/simple/PerfectSwitch.cc
/gem5/src/mem/ruby/network/simple/PerfectSwitch.hh
/gem5/src/mem/ruby/network/simple/SimpleNetwork.cc
/gem5/src/mem/ruby/network/simple/Switch.cc
/gem5/src/mem/ruby/network/simple/Throttle.cc
/gem5/src/mem/ruby/profiler/AccessTraceForAddress.cc
/gem5/src/mem/ruby/profiler/AddressProfiler.cc
/gem5/src/mem/ruby/profiler/StoreTrace.cc
/gem5/src/mem/ruby/slicc_interface/AbstractController.cc
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/slicc_interface/RubyRequest.cc
/gem5/src/mem/ruby/structures/BankedArray.cc
/gem5/src/mem/ruby/structures/CacheMemory.cc
/gem5/src/mem/ruby/structures/DirectoryMemory.cc
/gem5/src/mem/ruby/structures/LRUPolicy.cc
/gem5/src/mem/ruby/structures/Prefetcher.cc
/gem5/src/mem/ruby/structures/PseudoLRUPolicy.cc
/gem5/src/mem/ruby/structures/WireBuffer.cc
/gem5/src/mem/ruby/system/CacheRecorder.cc
/gem5/src/mem/ruby/system/DMASequencer.cc
/gem5/src/mem/ruby/system/RubyPort.cc
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/se_translating_port_proxy.cc
/gem5/src/mem/serial_link.cc
/gem5/src/mem/simple_mem.cc
symbols/StateMachine.py
/gem5/src/mem/snoop_filter.cc
/gem5/src/mem/tport.cc
/gem5/src/mem/xbar.cc
/gem5/src/proto/protoio.cc
/gem5/src/python/swig/pyevent.cc
/gem5/src/python/swig/pyevent.hh
/gem5/src/python/swig/pyobject.cc
/gem5/src/sim/arguments.cc
/gem5/src/sim/backtrace_glibc.cc
/gem5/src/sim/clock_domain.cc
/gem5/src/sim/core.cc
/gem5/src/sim/cxx_manager.cc
/gem5/src/sim/debug.cc
/gem5/src/sim/dvfs_handler.cc
/gem5/src/sim/faults.cc
/gem5/src/sim/init.cc
/gem5/src/sim/probe/probe.cc
/gem5/src/sim/process.cc
/gem5/src/sim/pseudo_inst.cc
/gem5/src/sim/py_interact.cc
/gem5/src/sim/root.cc
/gem5/src/sim/serialize.cc
/gem5/src/sim/sim_events.cc
/gem5/src/sim/sim_object.cc
/gem5/src/sim/simulate.cc
/gem5/src/sim/stat_control.cc
/gem5/src/sim/stat_control.hh
/gem5/src/sim/sub_system.cc
/gem5/src/sim/syscall_emul.cc
/gem5/src/sim/system.cc
/gem5/src/sim/voltage_domain.cc
/gem5/src/unittest/circlebuf.cc
/gem5/src/unittest/unittest.cc
11704:c38fcdaa5fe5 26-Oct-2016 Tony Gutierrez <anthony.gutierrez@amd.com>

hsail,gpu-compute: fixes to appease clang++

fixes to appease clang++. tested on:

Ubuntu clang version 3.5.0-4ubuntu2~trusty2
(tags/RELEASE_350/final) (based on LLVM 3.5.0)

Ubuntu clang version 3.6.0-2ubuntu1~trusty1
(tags/RELEASE_360/final) (based on LLVM 3.6.0)

the fixes address the following five issues:

1) the exec continuations in gpu_static_inst.hh were marked
as protected when they should be public. here we mark
them as public

2) the Abs instruction uses std::abs() in its execute method.
because Abs is templated, it can also operate on U32 and U64,
types, which cause Abs::execute() to pass uint32_t and uint64_t
types to std::abs() respectively. this triggers a warning
because std::abs() has no effect in this case. to rememdy this
we add template specialization for the execute() method of Abs
when its template paramter is U32 or U64.

3) Some potocols that utilize the code in cprintf.hh were missing
includes to BoolVec.hh, which defines operator<< for the BoolVec
type. This would cause issues when the generated code would try
to pass a BoolVec type to a method in cprintf.hh that used
operator<< on an instance of a BoolVec.

4) Surprise, clang doesn't like it when you clobber all the bits
in a newly allocated object. I.e., this code:

tlb = new GpuTlbEntry\[size\];
std::memset(tlb, 0, sizeof(GpuTlbEntry) \* size);

Let's use std::vector to track the TLB entries in the GpuTlb now...

5) There were a few variables used only in DPRINTFs, so we mark them
with M5_VAR_USED.

11325:67cc559d513a 06-Feb-2016 Steve Reinhardt <steve.reinhardt@amd.com>

style: eliminate explicit boolean comparisons

Result of running 'hg m5style --skip-all --fix-control -a' to get
rid of '== true' comparisons, plus trivial manual edits to get
rid of '== false'/'== False' comparisons.

Left a couple of explicit comparisons in where they didn't seem
unreasonable:
invalid boolean comparison in src/arch/mips/interrupts.cc:155
>> DPRINTF(Interrupt, "Interrupts OnCpuTimerINterrupt(tc) == true\n");<<
invalid boolean comparison in src/unittest/unittest.hh:110
>> "EXPECT_FALSE(" #expr ")", (expr) == false)<<

11320:42ecb523c64a 06-Feb-2016 Steve Reinhardt <steve.reinhardt@amd.com>

style: remove trailing whitespace

Result of running 'hg m5style --skip-all --fix-white -a'.


/gem5/configs/common/CacheConfig.py
/gem5/configs/common/Simulation.py
/gem5/configs/example/ruby_mem_test.py
/gem5/src/arch/alpha/isa/decoder.isa
/gem5/src/arch/alpha/linux/linux.hh
/gem5/src/arch/alpha/process.cc
/gem5/src/arch/alpha/tlb.cc
/gem5/src/arch/arm/SConscript
/gem5/src/arch/arm/interrupts.cc
/gem5/src/arch/arm/isa/bitfields.isa
/gem5/src/arch/arm/isa/formats/pred.isa
/gem5/src/arch/arm/linux/linux.hh
/gem5/src/arch/arm/stacktrace.cc
/gem5/src/arch/mips/isa/decoder.isa
/gem5/src/arch/mips/linux/linux.hh
/gem5/src/arch/mips/linux/process.cc
/gem5/src/arch/mips/pagetable.hh
/gem5/src/arch/power/SConscript
/gem5/src/arch/sparc/interrupts.cc
/gem5/src/arch/sparc/linux/linux.hh
/gem5/src/arch/sparc/pagetable.hh
/gem5/src/arch/x86/cpuid.cc
/gem5/src/arch/x86/faults.cc
/gem5/src/arch/x86/insts/micromediaop.hh
/gem5/src/arch/x86/isa/insts/general_purpose/system_calls.py
/gem5/src/arch/x86/isa/insts/romutil.py
/gem5/src/arch/x86/isa/insts/simd64/integer/data_transfer/move.py
/gem5/src/arch/x86/isa/microops/base.isa
/gem5/src/arch/x86/isa/microops/mediaop.isa
/gem5/src/arch/x86/isa/microops/regop.isa
/gem5/src/arch/x86/process.cc
/gem5/src/arch/x86/process.hh
/gem5/src/base/cp_annotate.cc
/gem5/src/base/cp_annotate.hh
/gem5/src/base/cprintf.hh
/gem5/src/base/flags.hh
/gem5/src/base/inet.cc
/gem5/src/base/inet.hh
/gem5/src/base/loader/ecoff_object.cc
/gem5/src/base/loader/elf_object.cc
/gem5/src/base/statistics.cc
/gem5/src/cpu/o3/decode_impl.hh
/gem5/src/cpu/simple/timing.cc
/gem5/src/cpu/testers/directedtest/DirectedGenerator.cc
/gem5/src/cpu/testers/directedtest/DirectedGenerator.hh
/gem5/src/cpu/testers/directedtest/InvalidateGenerator.cc
/gem5/src/cpu/testers/directedtest/InvalidateGenerator.hh
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.cc
/gem5/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
/gem5/src/cpu/testers/directedtest/SeriesRequestGenerator.hh
/gem5/src/cpu/testers/networktest/networktest.cc
/gem5/src/cpu/timebuf.hh
/gem5/src/dev/mc146818.cc
/gem5/src/dev/net/i8254xGBe.cc
/gem5/src/dev/net/i8254xGBe.hh
/gem5/src/dev/net/i8254xGBe_defs.hh
/gem5/src/dev/x86/i8042.cc
/gem5/src/dev/x86/i8254.hh
/gem5/src/dev/x86/intdev.hh
/gem5/src/mem/mport.hh
/gem5/src/mem/ruby/network/Topology.cc
/gem5/src/mem/ruby/network/Topology.hh
/gem5/src/mem/ruby/network/fault_model/FaultModel.cc
/gem5/src/mem/ruby/network/fault_model/FaultModel.hh
/gem5/src/mem/ruby/network/fault_model/FaultModel.py
/gem5/src/mem/ruby/network/fault_model/SConscript
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.py
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/Router.hh
/gem5/src/mem/ruby/network/simple/SimpleLink.cc
ast/StallAndWaitStatementAST.py
ast/TypeFieldEnumAST.py
ast/TypeFieldStateAST.py
/gem5/src/python/m5/util/__init__.py
/gem5/src/python/swig/event.i
/gem5/src/sim/Root.py
/gem5/src/sim/eventq.cc
/gem5/src/sim/eventq.hh
/gem5/src/sim/insttracer.hh
/gem5/src/sim/pseudo_inst.cc
/gem5/src/unittest/cprintftest.cc
/gem5/system/alpha/console/console.c
/gem5/tests/configs/memtest-ruby.py
/gem5/util/checkpoint-tester.py
/gem5/util/compile
/gem5/util/m5/m5.c
/gem5/util/qdo
/gem5/util/statetrace/SConstruct
11309:9be8a40026df 20-Jul-2015 David Hashe <david.hashe@amd.com>

ruby: split CPU and GPU latency stats

11308:7d8836fd043d 19-Jan-2016 Tony Gutierrez <anthony.gutierrez@amd.com>

gpu-compute: AMD's baseline GPU model


/gem5/SConstruct
/gem5/build_opts/HSAIL_X86
/gem5/build_opts/X86_MOESI_AMD_Base
/gem5/configs/common/GPUTLBConfig.py
/gem5/configs/common/GPUTLBOptions.py
/gem5/configs/example/apu_se.py
/gem5/configs/example/ruby_gpu_random_test.py
/gem5/configs/ruby/AMD_Base_Constructor.py
/gem5/configs/ruby/GPU_RfO.py
/gem5/configs/ruby/GPU_VIPER.py
/gem5/configs/ruby/GPU_VIPER_Baseline.py
/gem5/configs/ruby/GPU_VIPER_Region.py
/gem5/configs/ruby/MOESI_AMD_Base.py
/gem5/src/SConscript
/gem5/src/arch/SConscript
/gem5/src/arch/hsail/Brig.h
/gem5/src/arch/hsail/Brig_new.hpp
/gem5/src/arch/hsail/SConscript
/gem5/src/arch/hsail/SConsopts
/gem5/src/arch/hsail/gen.py
/gem5/src/arch/hsail/generic_types.cc
/gem5/src/arch/hsail/generic_types.hh
/gem5/src/arch/hsail/gpu_decoder.hh
/gem5/src/arch/hsail/gpu_types.hh
/gem5/src/arch/hsail/insts/branch.cc
/gem5/src/arch/hsail/insts/branch.hh
/gem5/src/arch/hsail/insts/decl.hh
/gem5/src/arch/hsail/insts/gpu_static_inst.cc
/gem5/src/arch/hsail/insts/gpu_static_inst.hh
/gem5/src/arch/hsail/insts/main.cc
/gem5/src/arch/hsail/insts/mem.cc
/gem5/src/arch/hsail/insts/mem.hh
/gem5/src/arch/hsail/insts/mem_impl.hh
/gem5/src/arch/hsail/insts/pseudo_inst.cc
/gem5/src/arch/hsail/operand.cc
/gem5/src/arch/hsail/operand.hh
/gem5/src/gpu-compute/GPU.py
/gem5/src/gpu-compute/LdsState.py
/gem5/src/gpu-compute/SConscript
/gem5/src/gpu-compute/X86GPUTLB.py
/gem5/src/gpu-compute/brig_object.cc
/gem5/src/gpu-compute/brig_object.hh
/gem5/src/gpu-compute/cl_driver.cc
/gem5/src/gpu-compute/cl_driver.hh
/gem5/src/gpu-compute/cl_event.hh
/gem5/src/gpu-compute/code_enums.hh
/gem5/src/gpu-compute/compute_unit.cc
/gem5/src/gpu-compute/compute_unit.hh
/gem5/src/gpu-compute/condition_register_state.cc
/gem5/src/gpu-compute/condition_register_state.hh
/gem5/src/gpu-compute/dispatcher.cc
/gem5/src/gpu-compute/dispatcher.hh
/gem5/src/gpu-compute/exec_stage.cc
/gem5/src/gpu-compute/exec_stage.hh
/gem5/src/gpu-compute/fetch_stage.cc
/gem5/src/gpu-compute/fetch_stage.hh
/gem5/src/gpu-compute/fetch_unit.cc
/gem5/src/gpu-compute/fetch_unit.hh
/gem5/src/gpu-compute/global_memory_pipeline.cc
/gem5/src/gpu-compute/global_memory_pipeline.hh
/gem5/src/gpu-compute/gpu_dyn_inst.cc
/gem5/src/gpu-compute/gpu_dyn_inst.hh
/gem5/src/gpu-compute/gpu_exec_context.cc
/gem5/src/gpu-compute/gpu_exec_context.hh
/gem5/src/gpu-compute/gpu_static_inst.cc
/gem5/src/gpu-compute/gpu_static_inst.hh
/gem5/src/gpu-compute/gpu_tlb.cc
/gem5/src/gpu-compute/gpu_tlb.hh
/gem5/src/gpu-compute/hsa_code.hh
/gem5/src/gpu-compute/hsa_kernel_info.hh
/gem5/src/gpu-compute/hsa_object.cc
/gem5/src/gpu-compute/hsa_object.hh
/gem5/src/gpu-compute/hsail_code.cc
/gem5/src/gpu-compute/hsail_code.hh
/gem5/src/gpu-compute/kernel_cfg.cc
/gem5/src/gpu-compute/kernel_cfg.hh
/gem5/src/gpu-compute/lds_state.cc
/gem5/src/gpu-compute/lds_state.hh
/gem5/src/gpu-compute/local_memory_pipeline.cc
/gem5/src/gpu-compute/local_memory_pipeline.hh
/gem5/src/gpu-compute/misc.hh
/gem5/src/gpu-compute/ndrange.hh
/gem5/src/gpu-compute/of_scheduling_policy.cc
/gem5/src/gpu-compute/of_scheduling_policy.hh
/gem5/src/gpu-compute/pool_manager.cc
/gem5/src/gpu-compute/pool_manager.hh
/gem5/src/gpu-compute/qstruct.hh
/gem5/src/gpu-compute/rr_scheduling_policy.cc
/gem5/src/gpu-compute/rr_scheduling_policy.hh
/gem5/src/gpu-compute/schedule_stage.cc
/gem5/src/gpu-compute/schedule_stage.hh
/gem5/src/gpu-compute/scheduler.cc
/gem5/src/gpu-compute/scheduler.hh
/gem5/src/gpu-compute/scheduling_policy.hh
/gem5/src/gpu-compute/scoreboard_check_stage.cc
/gem5/src/gpu-compute/scoreboard_check_stage.hh
/gem5/src/gpu-compute/shader.cc
/gem5/src/gpu-compute/shader.hh
/gem5/src/gpu-compute/simple_pool_manager.cc
/gem5/src/gpu-compute/simple_pool_manager.hh
/gem5/src/gpu-compute/tlb_coalescer.cc
/gem5/src/gpu-compute/tlb_coalescer.hh
/gem5/src/gpu-compute/vector_register_file.cc
/gem5/src/gpu-compute/vector_register_file.hh
/gem5/src/gpu-compute/vector_register_state.cc
/gem5/src/gpu-compute/vector_register_state.hh
/gem5/src/gpu-compute/wavefront.cc
/gem5/src/gpu-compute/wavefront.hh
/gem5/src/mem/protocol/GPU_RfO-SQC.sm
/gem5/src/mem/protocol/GPU_RfO-TCC.sm
/gem5/src/mem/protocol/GPU_RfO-TCCdir.sm
/gem5/src/mem/protocol/GPU_RfO-TCP.sm
/gem5/src/mem/protocol/GPU_RfO.slicc
/gem5/src/mem/protocol/GPU_VIPER-SQC.sm
/gem5/src/mem/protocol/GPU_VIPER-TCC.sm
/gem5/src/mem/protocol/GPU_VIPER-TCP.sm
/gem5/src/mem/protocol/GPU_VIPER.slicc
/gem5/src/mem/protocol/GPU_VIPER_Baseline.slicc
/gem5/src/mem/protocol/GPU_VIPER_Region-TCC.sm
/gem5/src/mem/protocol/GPU_VIPER_Region.slicc
/gem5/src/mem/protocol/MOESI_AMD_Base-CorePair.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-L3cache.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-Region-CorePair.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-Region-dir.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-Region-msg.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-RegionBuffer.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-RegionDir.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-dir.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-msg.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-probeFilter.sm
/gem5/src/mem/protocol/MOESI_AMD_Base.slicc
/gem5/src/mem/protocol/RubySlicc_ComponentMapping.sm
/gem5/src/mem/protocol/RubySlicc_Exports.sm
/gem5/src/mem/protocol/RubySlicc_Types.sm
/gem5/src/mem/protocol/SConsopts
/gem5/src/mem/ruby/SConscript
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
/gem5/src/mem/ruby/slicc_interface/AbstractController.cc
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
/gem5/src/mem/ruby/structures/CacheMemory.cc
/gem5/src/mem/ruby/structures/CacheMemory.hh
/gem5/src/mem/ruby/structures/RubyCache.py
/gem5/src/mem/ruby/system/GPUCoalescer.cc
/gem5/src/mem/ruby/system/GPUCoalescer.hh
/gem5/src/mem/ruby/system/GPUCoalescer.py
/gem5/src/mem/ruby/system/RubyPort.cc
/gem5/src/mem/ruby/system/RubyPort.hh
/gem5/src/mem/ruby/system/RubySystem.cc
/gem5/src/mem/ruby/system/SConscript
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/Sequencer.hh
/gem5/src/mem/ruby/system/Sequencer.py
/gem5/src/mem/ruby/system/VIPERCoalescer.cc
/gem5/src/mem/ruby/system/VIPERCoalescer.hh
/gem5/src/mem/ruby/system/VIPERCoalescer.py
/gem5/src/mem/ruby/system/WeightedLRUPolicy.cc
/gem5/src/mem/ruby/system/WeightedLRUPolicy.hh
/gem5/src/mem/ruby/system/WeightedLRUReplacementPolicy.py
symbols/StateMachine.py
/gem5/tests/SConscript
/gem5/tests/configs/gpu-randomtest-ruby.py
/gem5/tests/configs/gpu-ruby.py
/gem5/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/config.ini
/gem5/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/simerr
/gem5/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/simout
/gem5/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/stats.txt
/gem5/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER/config.ini
/gem5/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER/simerr
/gem5/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER/simout
/gem5/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER/stats.txt
/gem5/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER_Baseline/config.ini
/gem5/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER_Baseline/simerr
/gem5/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER_Baseline/simout
/gem5/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER_Baseline/stats.txt
/gem5/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER_Region/config.ini
/gem5/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER_Region/simerr
/gem5/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER_Region/simout
/gem5/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER_Region/stats.txt
/gem5/tests/quick/se/04.gpu/test.py
/gem5/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/config.ini
/gem5/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/simerr
/gem5/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/simout
/gem5/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/stats.txt
/gem5/tests/quick/se/60.gpu-randomtest/test.py
/gem5/tests/test-progs/gpu-hello/bin/x86/linux/gpu-hello
/gem5/tests/test-progs/gpu-hello/bin/x86/linux/gpu-hello-kernel.asm
/gem5/tests/test-progs/gpu-hello/src/gpu-hello-kernel.cl
/gem5/tests/test-progs/gpu-hello/src/gpu-hello.cpp
/gem5/util/regress
11283:4cc8b312f026 20-Jul-2015 Tony Gutierrez <anthony.gutierrez@amd.com>

ruby: slicc: have a static MachineType

This patch is imported from reviewboard patch 2551 by Nilay.
This patch moves from a dynamically defined MachineType to a statically
defined one. The need for this patch was felt since a dynamically defined
type prevents us from having types for which no machine definition may
exist.

The following changes have been made:
i. each machine definition now uses a type from the MachineType enumeration
instead of any random identifier. This required changing the grammar and the
*.sm files.
ii. MachineType enumeration defined statically in RubySlicc_Exports.sm.
* * *
normal protocol fixes for nilay's parser machine type fix

11282:afdcebd314be 20-Jul-2015 Tony Gutierrez <anthony.gutierrez@amd.com>

ruby: slicc: remove support for single machine, multiple types

This patch is imported from reviewboard patch 2550 by Nilay.
It was possible to specify multiple machine types with a single state machine.
This seems unnecessary and is being removed.

11209:d5a7a4da9f63 13-Nov-2015 Tony Gutierrez <anthony.gutierrez@amd.com>

slicc: fixes for the Address to Addr changeset (11025)

misc changes now that Address has become Addr including int to address util
function

11118:75c1e564a725 18-Sep-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: print addresses in hex
Changeset 4872dbdea907 replaced Address by Addr, but did not make changes to
print statements. So the addresses which were being printed in hex earlier
along with their line address, were now being printed in decimals. This patch
adds a function printAddress(Addr) that can be used to print the address in hex
along with the lines address. This function has been put to use in some of the
places. At other places, change has been made to print just the address in
hex.

11117:2a1a21f79047 18-Sep-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: slicc: derive DataMember class from Var instead of PairContainer

The DataMember class in Type.py was being derived from PairContainer. A
separate Var object was also created for the DataMember. This meant some
duplication of across the members of these two classes (Var and DataMember).
This patch changes DataMember from Var instead. There is no obvious reason to
derive from PairContainer which can only hold pairs, something that Var class
already supports. The only thing that DataMember has over Var is init_code,
which is being retained. This change would later on help in having pointers
in DataMembers.

11116:d6fb95dbf3e2 17-Sep-2015 Tony Gutierrez <anthony.gutierrez@amd.com>

ruby: update WireBuffer API to match that of MessageBuffer

this patch updates the WireBuffer API to mirror the changes in revision 11111

11113:5a2e1b1b5c43 16-Sep-2015 Joe Gross <joe.gross@amd.com>

ruby: fix message buffer init order

The recent changes to make MessageBuffers SimObjects required them to be
initialized in a particular order, which could break some protocols. Fix this
by calling initNetQueues on the external nodes of each external link in the
constructor of Network.

This patch also refactors the duplicated code for checking network allocation
and setting net queues (which are called by initNetQueues) from the simple and
garnet networks to be in Network.

11111:6da33e720481 16-Sep-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: message buffer, timer table: significant changes

This patch changes MessageBuffer and TimerTable, two structures used for
buffering messages by components in ruby. These structures would no longer
maintain pointers to clock objects. Functions in these structures have been
changed to take as input current time in Tick. Similarly, these structures
will not operate on Cycle valued latencies for different operations. The
corresponding functions would need to be provided with these latencies by
components invoking the relevant functions. These latencies should also be
in Ticks.

I felt the need for these changes while trying to speed up ruby. The ultimate
aim is to eliminate Consumer class and replace it with an EventManager object in
the MessageBuffer and TimerTable classes. This object would be used for
scheduling events. The event itself would contain information on the object and
function to be invoked.

In hindsight, it seems I should have done this while I was moving away from use
of a single global clock in the memory system. That change led to introduction
of clock objects that replaced the global clock object. It never crossed my
mind that having clock object pointers is not a good design. And now I really
don't like the fact that we have separate consumer, receiver and sender
pointers in message buffers.


/gem5/src/mem/protocol/MESI_Three_Level-L0cache.sm
/gem5/src/mem/protocol/MESI_Three_Level-L1cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-L1cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-L2cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-dir.sm
/gem5/src/mem/protocol/MESI_Two_Level-dma.sm
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MI_example-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dma.sm
/gem5/src/mem/protocol/MOESI_hammer-cache.sm
/gem5/src/mem/protocol/MOESI_hammer-dir.sm
/gem5/src/mem/protocol/MOESI_hammer-dma.sm
/gem5/src/mem/protocol/Network_test-cache.sm
/gem5/src/mem/protocol/Network_test-dir.sm
/gem5/src/mem/protocol/RubySlicc_Defines.sm
/gem5/src/mem/protocol/RubySlicc_Exports.sm
/gem5/src/mem/protocol/RubySlicc_Types.sm
/gem5/src/mem/ruby/network/MessageBuffer.cc
/gem5/src/mem/ruby/network/MessageBuffer.hh
/gem5/src/mem/ruby/network/MessageBuffer.py
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
/gem5/src/mem/ruby/network/simple/PerfectSwitch.cc
/gem5/src/mem/ruby/network/simple/SimpleNetwork.py
/gem5/src/mem/ruby/network/simple/Switch.cc
/gem5/src/mem/ruby/network/simple/Throttle.cc
/gem5/src/mem/ruby/slicc_interface/AbstractController.cc
/gem5/src/mem/ruby/structures/TBETable.hh
/gem5/src/mem/ruby/structures/TimerTable.cc
/gem5/src/mem/ruby/structures/TimerTable.hh
/gem5/src/mem/ruby/system/DMASequencer.cc
/gem5/src/mem/ruby/system/RubyPort.cc
/gem5/src/mem/ruby/system/Sequencer.cc
ast/EnqueueStatementAST.py
ast/ObjDeclAST.py
ast/PeekStatementAST.py
ast/StallAndWaitStatementAST.py
symbols/StateMachine.py
11108:6342ddf6d733 16-Sep-2015 David Hashe <david.hashe@amd.com>

ruby: rename System.{hh,cc} to RubySystem.{hh,cc}

The eventual aim of this change is to pass RubySystem pointers through to
objects generated from the SLICC protocol code.

Because some of these objects need to dereference their RubySystem pointers,
they need access to the System.hh header file.

In src/mem/ruby/SConscript, the MakeInclude function creates single-line header
files in the build directory that do nothing except include the corresponding
header file from the source tree.

However, SLICC also generates a list of header files from its symbol table, and
writes it to mem/protocol/Types.hh in the build directory. This code assumes
that the header file name is the same as the class name.

The end result of this is the many of the generated slicc files try to include
RubySystem.hh, when the file they really need is System.hh. The path of least
resistence is just to rename System.hh to RubySystem.hh.


/gem5/src/mem/ruby/common/Address.cc
/gem5/src/mem/ruby/common/DataBlock.cc
/gem5/src/mem/ruby/filters/BlockBloomFilter.cc
/gem5/src/mem/ruby/filters/BulkBloomFilter.cc
/gem5/src/mem/ruby/filters/LSB_CountingBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiGrainBloomFilter.cc
/gem5/src/mem/ruby/filters/NonCountingBloomFilter.cc
/gem5/src/mem/ruby/network/MessageBuffer.cc
/gem5/src/mem/ruby/network/Network.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/OutVcState_d.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc
/gem5/src/mem/ruby/network/simple/SimpleNetwork.cc
/gem5/src/mem/ruby/network/simple/Throttle.cc
/gem5/src/mem/ruby/network/simple/Throttle.hh
/gem5/src/mem/ruby/slicc_interface/AbstractController.cc
/gem5/src/mem/ruby/structures/BankedArray.cc
/gem5/src/mem/ruby/structures/BankedArray.hh
/gem5/src/mem/ruby/structures/CacheMemory.cc
/gem5/src/mem/ruby/structures/DirectoryMemory.cc
/gem5/src/mem/ruby/structures/Prefetcher.cc
/gem5/src/mem/ruby/structures/Prefetcher.hh
/gem5/src/mem/ruby/structures/RubyMemoryControl.cc
/gem5/src/mem/ruby/structures/RubyMemoryControl.hh
/gem5/src/mem/ruby/structures/TimerTable.cc
/gem5/src/mem/ruby/structures/WireBuffer.cc
/gem5/src/mem/ruby/system/CacheRecorder.cc
/gem5/src/mem/ruby/system/DMASequencer.cc
/gem5/src/mem/ruby/system/DMASequencer.hh
/gem5/src/mem/ruby/system/RubyPort.hh
/gem5/src/mem/ruby/system/RubySystem.cc
/gem5/src/mem/ruby/system/RubySystem.hh
/gem5/src/mem/ruby/system/RubySystem.py
/gem5/src/mem/ruby/system/SConscript
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/ruby/system/System.hh
symbols/StateMachine.py
symbols/Type.py
11095:12c36d719139 14-Sep-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: slicc: remove member buffer_expr from Var class
This was added by changeset 51f40b101a56. Instead, buffer_expr would now be
associated with the InPort class.

11089:4808f8c4a47e 08-Sep-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: slicc: remove nextLineHack from Type.py

11084:ee2fcca7b58a 05-Sep-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: declare all protocol message buffers as parameters

MessageBuffer is a SimObject now. There were protocols that still declared
some of the message buffers are variables of the controller, but not as input
parameters. Special handling was required for these variables in the SLICC
compiler. This patch changes this. Now all message buffers are declared as
input parameters.

11062:262d8494b253 30-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: slicc: avoid duplicate code for function argument check
Both FuncCallExprAST and MethodCallExprAST had code for checking the arguments
with which a function is being called. The patch does away with this
duplication. Now the code for checking function call arguments resides in the
Func class.

11061:25b53a7195f7 29-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: eliminate type uint64 and int64
These types are being replaced with uint64_t and int64_t.

11049:dfb0aa3f0649 19-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: reverts to changeset: bf82f1f7b040


/gem5/configs/ruby/Ruby.py
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.hh
/gem5/src/cpu/testers/rubytest/RubyTester.hh
/gem5/src/mem/protocol/MESI_Three_Level-L0cache.sm
/gem5/src/mem/protocol/MESI_Three_Level-L1cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-L1cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-L2cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-dir.sm
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_hammer-cache.sm
/gem5/src/mem/protocol/MOESI_hammer-dir.sm
/gem5/src/mem/protocol/RubySlicc_Types.sm
/gem5/src/mem/ruby/common/DataBlock.hh
/gem5/src/mem/ruby/common/Histogram.cc
/gem5/src/mem/ruby/common/Histogram.hh
/gem5/src/mem/ruby/common/SubBlock.cc
/gem5/src/mem/ruby/common/SubBlock.hh
/gem5/src/mem/ruby/common/TypeDefines.hh
/gem5/src/mem/ruby/filters/H3BloomFilter.cc
/gem5/src/mem/ruby/filters/H3BloomFilter.hh
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.hh
/gem5/src/mem/ruby/network/MessageBuffer.cc
/gem5/src/mem/ruby/network/MessageBuffer.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/flit.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/flit.hh
/gem5/src/mem/ruby/network/simple/PerfectSwitch.cc
/gem5/src/mem/ruby/network/simple/PerfectSwitch.hh
/gem5/src/mem/ruby/network/simple/SimpleNetwork.cc
/gem5/src/mem/ruby/network/simple/SimpleNetwork.hh
/gem5/src/mem/ruby/network/simple/Switch.cc
/gem5/src/mem/ruby/network/simple/Throttle.cc
/gem5/src/mem/ruby/network/simple/Throttle.hh
/gem5/src/mem/ruby/profiler/AccessTraceForAddress.hh
/gem5/src/mem/ruby/profiler/AddressProfiler.cc
/gem5/src/mem/ruby/profiler/AddressProfiler.hh
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/profiler/StoreTrace.cc
/gem5/src/mem/ruby/profiler/StoreTrace.hh
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/structures/AbstractReplacementPolicy.cc
/gem5/src/mem/ruby/structures/AbstractReplacementPolicy.hh
/gem5/src/mem/ruby/structures/BankedArray.cc
/gem5/src/mem/ruby/structures/BankedArray.hh
/gem5/src/mem/ruby/structures/CacheMemory.cc
/gem5/src/mem/ruby/structures/CacheMemory.hh
/gem5/src/mem/ruby/structures/DirectoryMemory.cc
/gem5/src/mem/ruby/structures/DirectoryMemory.hh
/gem5/src/mem/ruby/structures/LRUPolicy.cc
/gem5/src/mem/ruby/structures/LRUPolicy.hh
/gem5/src/mem/ruby/structures/PseudoLRUPolicy.cc
/gem5/src/mem/ruby/structures/PseudoLRUPolicy.hh
/gem5/src/mem/ruby/structures/RubyMemoryControl.cc
/gem5/src/mem/ruby/structures/RubyMemoryControl.hh
/gem5/src/mem/ruby/system/CacheRecorder.cc
/gem5/src/mem/ruby/system/CacheRecorder.hh
/gem5/src/mem/ruby/system/RubySystem.py
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/ruby/system/System.hh
ast/EnumDeclAST.py
ast/FormalParamAST.py
ast/FuncCallExprAST.py
ast/FuncDeclAST.py
ast/InPortDeclAST.py
ast/MethodCallExprAST.py
ast/StateDeclAST.py
parser.py
symbols/Func.py
symbols/StateMachine.py
11044:25b2a428e2eb 14-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: slicc: remove a stray line in StateMachine.py

11031:3815437cb231 14-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: eliminate type uint64 and int64

These types are being replaced with uint64_t and int64_t.

11030:17240f381d6a 14-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: slicc: use default argument value
Before this patch, while one could declare / define a function with default
argument values, but the actual function call would require one to specify
all the arguments. This patch changes the check for function arguments.
Now a function call needs to specify arguments that are at least as much as
those with default values and at most the total number of arguments taken
as input by the function.

11029:32604f9e190b 14-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: slicc: avoid duplicate code for function argument check
Both FuncCallExprAST and MethodCallExprAST had code for checking the arguments
with which a function is being called. The patch does away with this
duplication. Now the code for checking function call arguments resides in the
Func class.

11028:3a5190683bf2 14-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: drop the [] notation for lookup function.

This is in preparation for adding a second arugment to the lookup
function for the CacheMemory class. The change to *.sm files was made using
the following sed command:

sed -i 's/\[\([0-9A-Za-z._()]*\)\]/.lookup(\1)/' src/mem/protocol/*.sm

11025:4872dbdea907 14-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: replace Address by Addr
This patch eliminates the type Address defined by the ruby memory system.
This memory system would now use the type Addr that is in use by the
rest of the system.


/gem5/src/cpu/testers/rubytest/Check.cc
/gem5/src/cpu/testers/rubytest/Check.hh
/gem5/src/cpu/testers/rubytest/CheckTable.cc
/gem5/src/cpu/testers/rubytest/CheckTable.hh
/gem5/src/cpu/testers/rubytest/RubyTester.hh
/gem5/src/mem/protocol/MESI_Three_Level-L0cache.sm
/gem5/src/mem/protocol/MESI_Three_Level-L1cache.sm
/gem5/src/mem/protocol/MESI_Three_Level-msg.sm
/gem5/src/mem/protocol/MESI_Two_Level-L1cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-L2cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-dir.sm
/gem5/src/mem/protocol/MESI_Two_Level-dma.sm
/gem5/src/mem/protocol/MESI_Two_Level-msg.sm
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MI_example-dma.sm
/gem5/src/mem/protocol/MI_example-msg.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-msg.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_token-msg.sm
/gem5/src/mem/protocol/MOESI_hammer-cache.sm
/gem5/src/mem/protocol/MOESI_hammer-dir.sm
/gem5/src/mem/protocol/MOESI_hammer-dma.sm
/gem5/src/mem/protocol/MOESI_hammer-msg.sm
/gem5/src/mem/protocol/Network_test-cache.sm
/gem5/src/mem/protocol/Network_test-dir.sm
/gem5/src/mem/protocol/Network_test-msg.sm
/gem5/src/mem/protocol/RubySlicc_ComponentMapping.sm
/gem5/src/mem/protocol/RubySlicc_Defines.sm
/gem5/src/mem/protocol/RubySlicc_Exports.sm
/gem5/src/mem/protocol/RubySlicc_MemControl.sm
/gem5/src/mem/protocol/RubySlicc_Types.sm
/gem5/src/mem/protocol/RubySlicc_Util.sm
/gem5/src/mem/ruby/common/Address.cc
/gem5/src/mem/ruby/common/Address.hh
/gem5/src/mem/ruby/common/SubBlock.cc
/gem5/src/mem/ruby/common/SubBlock.hh
/gem5/src/mem/ruby/common/TypeDefines.hh
/gem5/src/mem/ruby/filters/AbstractBloomFilter.hh
/gem5/src/mem/ruby/filters/BlockBloomFilter.cc
/gem5/src/mem/ruby/filters/BlockBloomFilter.hh
/gem5/src/mem/ruby/filters/BulkBloomFilter.cc
/gem5/src/mem/ruby/filters/BulkBloomFilter.hh
/gem5/src/mem/ruby/filters/GenericBloomFilter.cc
/gem5/src/mem/ruby/filters/GenericBloomFilter.hh
/gem5/src/mem/ruby/filters/H3BloomFilter.cc
/gem5/src/mem/ruby/filters/H3BloomFilter.hh
/gem5/src/mem/ruby/filters/LSB_CountingBloomFilter.cc
/gem5/src/mem/ruby/filters/LSB_CountingBloomFilter.hh
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.hh
/gem5/src/mem/ruby/filters/MultiGrainBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiGrainBloomFilter.hh
/gem5/src/mem/ruby/filters/NonCountingBloomFilter.cc
/gem5/src/mem/ruby/filters/NonCountingBloomFilter.hh
/gem5/src/mem/ruby/network/MessageBuffer.cc
/gem5/src/mem/ruby/network/MessageBuffer.hh
/gem5/src/mem/ruby/profiler/AccessTraceForAddress.hh
/gem5/src/mem/ruby/profiler/AddressProfiler.cc
/gem5/src/mem/ruby/profiler/AddressProfiler.hh
/gem5/src/mem/ruby/profiler/StoreTrace.cc
/gem5/src/mem/ruby/profiler/StoreTrace.hh
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
/gem5/src/mem/ruby/slicc_interface/AbstractController.cc
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/slicc_interface/RubyRequest.cc
/gem5/src/mem/ruby/slicc_interface/RubyRequest.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
/gem5/src/mem/ruby/structures/CacheMemory.cc
/gem5/src/mem/ruby/structures/CacheMemory.hh
/gem5/src/mem/ruby/structures/DirectoryMemory.cc
/gem5/src/mem/ruby/structures/DirectoryMemory.hh
/gem5/src/mem/ruby/structures/MemoryNode.hh
/gem5/src/mem/ruby/structures/PerfectCacheMemory.hh
/gem5/src/mem/ruby/structures/PersistentTable.cc
/gem5/src/mem/ruby/structures/PersistentTable.hh
/gem5/src/mem/ruby/structures/Prefetcher.cc
/gem5/src/mem/ruby/structures/Prefetcher.hh
/gem5/src/mem/ruby/structures/RubyMemoryControl.cc
/gem5/src/mem/ruby/structures/RubyMemoryControl.hh
/gem5/src/mem/ruby/structures/TBETable.hh
/gem5/src/mem/ruby/structures/TimerTable.cc
/gem5/src/mem/ruby/structures/TimerTable.hh
/gem5/src/mem/ruby/system/CacheRecorder.cc
/gem5/src/mem/ruby/system/CacheRecorder.hh
/gem5/src/mem/ruby/system/DMASequencer.cc
/gem5/src/mem/ruby/system/DMASequencer.hh
/gem5/src/mem/ruby/system/RubyPort.cc
/gem5/src/mem/ruby/system/RubyPort.hh
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/Sequencer.hh
/gem5/src/mem/ruby/system/System.cc
ast/ActionDeclAST.py
ast/InPortDeclAST.py
ast/StallAndWaitStatementAST.py
symbols/StateMachine.py
symbols/Type.py
11021:e8a6637afa4c 14-Aug-2015 Joel Hestness <jthestness@gmail.com>

ruby: Expose MessageBuffers as SimObjects

Expose MessageBuffers from SLICC controllers as SimObjects that can be
manipulated in Python. This patch has numerous benefits:
1) First and foremost, it exposes MessageBuffers as SimObjects that can be
manipulated in Python code. This allows parameters to be set and checked in
Python code to avoid obfuscating parameters within protocol files. Further, now
as SimObjects, MessageBuffer parameters are printed to config output files as a
way to track parameters across simulations (e.g. buffer sizes)

2) Cleans up special-case code for responseFromMemory buffers, and aligns their
instantiation and use with mandatoryQueue buffers. These two special buffers
are the only MessageBuffers that are exposed to components outside of SLICC
controllers, and they're both slave ends of these buffers. They should be
exposed outside of SLICC in the same way, and this patch does it.

3) Distinguishes buffer-specific parameters from buffer-to-network parameters.
Specifically, buffer size, randomization, ordering, recycle latency, and ports
are all specific to a MessageBuffer, while the virtual network ID and type are
intrinsics of how the buffer is connected to network ports. The former are
specified in the Python object, while the latter are specified in the
controller *.sm files. Unlike buffer-specific parameters, which may need to
change depending on the simulated system structure, buffer-to-network
parameters can be specified statically for most or all different simulated
systems.

11020:882ce080c9f7 14-Aug-2015 Joel Hestness <jthestness@gmail.com>

ruby: Change PerfectCacheMemory::lookup to return pointer

CacheMemory and DirectoryMemory lookup functions return pointers to entries
stored in the memory. Bring PerfectCacheMemory in line with this convention,
and clean up SLICC code generation that was in place solely to handle
references like that which was returned by PerfectCacheMemory::lookup.

11016:bc759340631f 11-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: slicc: allow mathematical operations on Ticks

10985:d87a25259254 20-Jul-2015 Brad Beckmann <Brad.Beckmann@amd.com>

slicc: fix error in conflicing symbol declaration

10984:a86f453a7caa 20-Jul-2015 Brad Beckmann <Brad.Beckmann@amd.com>

slicc: enable overloading in functions not in classes

For many years the slicc symbol table has supported overloaded functions in
external classes. This patch extends that support to functions that are not
part of classes (a.k.a. no parent). For example, this support allows slicc
to understand that mapAddressToRange is overloaded and the NodeID is an
optional parameter.

10981:b300dcda5896 20-Jul-2015 Brad Beckmann <Brad.Beckmann@amd.com>

slicc: improved stalling support in protocols

Adds features to allow protocols to reschedule controllers when conditionally
stalling within inport logic or actions. Also insures that resource and
protocol stalls are re-evaluated the next cycle.

10972:53d63eeee46f 20-Jul-2015 David Hashe <david.hashe@amd.com>

slicc: support for arbitrary DPRINTF flags (not just RubySlicc)

This patch allows DPRINTFs to be used in SLICC state machines similar to how
they are used by the rest of gem5. Previously all DPRINTFs in the .sm files
had to use the RubySlicc flag.

10971:3ed88c8334f1 20-Jul-2015 David Hashe <david.hashe@amd.com>

slicc: support for local variable declarations in action blocks

10968:bde347fc89ae 20-Jul-2015 David Hashe <david.hashe@amd.com>

slicc: support for multiple cache entry types in the same state machine

To have multiple Entry types (e.g., a cache Entry type and
a directory Entry type), just declare one of them as a secondary
type by using the pair 'main="false"', e.g.:

structure(DirEntry, desc="...", interface="AbstractCacheEntry",
main="false") {

...and the primary type would be declared:

structure(Entry, desc="...", interface="AbstractCacheEntry") {

10967:b36204de88c0 20-Jul-2015 David Hashe <david.hashe@amd.com>

slicc: Fix bug in enqueue and peek statements.

These were not generating the correct c names for types declared within a
machine scope.

10966:198726a3c723 20-Jul-2015 David Hashe <david.hashe@amd.com>

slicc: fix missing inline function in LocalVariableAST

10965:6f433e7f9767 20-Jul-2015 David Hashe <david.hashe@amd.com>

slicc: improve support for prefix operations

This patch fixes the type handling when prefix operations are used. Previously
prefix operators would assume a void return type, which made it impossible to
combine prefix operations with other expressions. This patch allows SLICC
programmers to use prefix operations more naturally.

10964:2b4fe083d17b 20-Jul-2015 David Hashe <david.hashe@amd.com>

slicc: support for transitions with a wildcard next state

This patches adds support for transitions of the form:

transition(START, EVENTS, *) { ACTIONS }

This allows a machine to collapse states that differ only in the next state
transition to collapse into one, and can help shorten/simplfy some protocols
significantly.

When * is encountered as an end state of a transition, the next state is
determined by calling the machine-specific getNextState function. The next
state is determined before any actions of the transition execute, and
therefore the next state calculation cannot depend on any of the transition
actions.

10963:51f40b101a56 20-Jul-2015 David Hashe <david.hashe@amd.com>

slicc: support for multiple message types on the same buffer

This patch allows SLICC protocols to use more than one message type with a
message buffer. For example, you can declare two in ports as such:

in_port(ResponseQueue_in, ResponseMsg, responseFromDir, rank=3) { ... }
in_port(tgtResponseQueue_in, TgtResponseMsg, responseFromDir, rank=2) { ... }

10962:7233a5f7ac8f 01-Aug-2015 Brad Beckmann <Brad.Beckmann@amd.com>

slicc: fatal->panic on invalid transitions

10953:1b21c87b7c18 20-Jul-2015 David Hashe <david.hashe@amd.com>

slicc: isinstance bugfix

This fix prevents spurious errors when searching for a symbol that may be
located in one of multiple symbol tables.

10920:58fbfddff18d 10-Jul-2015 Brandon Potter <brandon.potter@amd.com>

ruby: replace global g_abs_controls with per-RubySystem var

This is another step in the process of removing global variables
from Ruby to enable multiple RubySystem instances in a single simulation.

The list of abstract controllers is per-RubySystem and should be
represented that way, rather than as a global.

Since this is the last remaining Ruby global variable, the
src/mem/ruby/Common/Global.* files are also removed.

10919:80069a602c83 10-Jul-2015 Brandon Potter <brandon.potter@amd.com>

ruby: replace global g_system_ptr with per-object pointers

This is another step in the process of removing global variables
from Ruby to enable multiple RubySystem instances in a single simulation.

With possibly multiple RubySystem objects, we can no longer use a global
variable to find "the" RubySystem object. Instead, each Ruby component
has to carry a pointer to the RubySystem object to which it belongs.

10917:c38f28fad4c3 10-Jul-2015 Brandon Potter <brandon.potter@amd.com>

ruby: remove extra whitespace and correct misspelled words

10895:287285860dd6 04-Jul-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: drop NetworkMessage class

This patch drops the NetworkMessage class. The relevant data members and functions
have been moved to the Message class, which was the parent of NetworkMessage.

10877:73d4798871a5 25-Jun-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: slicc: remove README

No longer maintained. Updates are only made to the wiki page. So being
dropped.

10524:fff17530cef6 06-Nov-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: interface with classic memory controller
This patch is the final in the series. The whole series and this patch in
particular were written with the aim of interfacing ruby's directory controller
with the memory controller in the classic memory system. This is being done
since ruby's memory controller has not being kept up to date with the changes
going on in DRAMs. Classic's memory controller is more up to date and
supports multiple different types of DRAM. This also brings classic and
ruby ever more close. The patch also changes ruby's memory controller to
expose the same interface.


/gem5/configs/common/MemConfig.py
/gem5/configs/example/fs.py
/gem5/configs/example/ruby_direct_test.py
/gem5/configs/example/ruby_mem_test.py
/gem5/configs/example/ruby_random_test.py
/gem5/configs/example/se.py
/gem5/configs/ruby/MESI_Three_Level.py
/gem5/configs/ruby/MESI_Two_Level.py
/gem5/configs/ruby/MI_example.py
/gem5/configs/ruby/MOESI_CMP_directory.py
/gem5/configs/ruby/MOESI_CMP_token.py
/gem5/configs/ruby/MOESI_hammer.py
/gem5/configs/ruby/Ruby.py
/gem5/src/mem/protocol/MESI_Two_Level-dir.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_hammer-dir.sm
/gem5/src/mem/protocol/RubySlicc_Defines.sm
/gem5/src/mem/protocol/RubySlicc_Types.sm
/gem5/src/mem/ruby/SConscript
/gem5/src/mem/ruby/network/MessageBuffer.cc
/gem5/src/mem/ruby/slicc_interface/AbstractController.cc
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/slicc_interface/Controller.py
/gem5/src/mem/ruby/structures/Cache.py
/gem5/src/mem/ruby/structures/DirectoryMemory.py
/gem5/src/mem/ruby/structures/MemoryControl.cc
/gem5/src/mem/ruby/structures/MemoryControl.hh
/gem5/src/mem/ruby/structures/MemoryControl.py
/gem5/src/mem/ruby/structures/MemoryNode.cc
/gem5/src/mem/ruby/structures/MemoryNode.hh
/gem5/src/mem/ruby/structures/MemoryVector.hh
/gem5/src/mem/ruby/structures/RubyMemoryControl.cc
/gem5/src/mem/ruby/structures/RubyMemoryControl.hh
/gem5/src/mem/ruby/structures/RubyMemoryControl.py
/gem5/src/mem/ruby/structures/SConscript
/gem5/src/mem/ruby/system/RubySystem.py
/gem5/src/mem/ruby/system/Sequencer.py
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/ruby/system/System.hh
symbols/StateMachine.py
/gem5/src/python/swig/pyobject.cc
/gem5/tests/configs/memtest-ruby.py
/gem5/tests/configs/pc-simple-timing-ruby.py
/gem5/tests/configs/rubytest-ruby.py
/gem5/tests/configs/simple-timing-mp-ruby.py
/gem5/tests/configs/simple-timing-ruby.py
10523:5777a3e55603 06-Nov-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: remove the function functionalReadBuffers()
This function was added when I had incorrectly arrived at the conclusion
that such a function can improve the chances of a functional read succeeding.
As was later realized, this is not possible in the current setup. While the
code using this function was dropped long back, this function was not. Hence
the patch.

10521:ca248520649f 06-Nov-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: slicc: allow adding a bool to an int, like C++.

10472:399f35ed5cca 16-Oct-2014 Andreas Hansson <andreas.hansson@arm.com>

mem: Use shared_ptr for Ruby Message classes

This patch transitions the Ruby Message and its derived classes from
the ad-hoc RefCountingPtr to the c++11 shared_ptr. There are no
changes in behaviour, and the code modifications are mainly replacing
"new" with "make_shared".

The cloning of derived messages is slightly changed as they previously
relied on overriding the base-class through covariant return types.

10311:ad9c042dce54 01-Sep-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: message buffers: significant changes

This patch is the final patch in a series of patches. The aim of the series
is to make ruby more configurable than it was. More specifically, the
connections between controllers are not at all possible (unless one is ready
to make significant changes to the coherence protocol). Moreover the buffers
themselves are magically connected to the network inside the slicc code.
These connections are not part of the configuration file.

This patch makes changes so that these connections will now be made in the
python configuration files associated with the protocols. This requires
each state machine to expose the message buffers it uses for input and output.
So, the patch makes these buffers configurable members of the machines.

The patch drops the slicc code that usd to connect these buffers to the
network. Now these buffers are exposed to the python configuration system
as Master and Slave ports. In the configuration files, any master port
can be connected any slave port. The file pyobject.cc has been modified to
take care of allocating the actual message buffer. This is inline with how
other port connections work.


/gem5/configs/ruby/MESI_Three_Level.py
/gem5/configs/ruby/MESI_Two_Level.py
/gem5/configs/ruby/MI_example.py
/gem5/configs/ruby/MOESI_CMP_directory.py
/gem5/configs/ruby/MOESI_CMP_token.py
/gem5/configs/ruby/MOESI_hammer.py
/gem5/configs/ruby/Network_test.py
/gem5/configs/ruby/Ruby.py
/gem5/src/mem/protocol/MESI_Three_Level-L0cache.sm
/gem5/src/mem/protocol/MESI_Three_Level-L1cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-L1cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-L2cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-dir.sm
/gem5/src/mem/protocol/MESI_Two_Level-dma.sm
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MI_example-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dma.sm
/gem5/src/mem/protocol/MOESI_hammer-cache.sm
/gem5/src/mem/protocol/MOESI_hammer-dir.sm
/gem5/src/mem/protocol/MOESI_hammer-dma.sm
/gem5/src/mem/protocol/Network_test-cache.sm
/gem5/src/mem/protocol/Network_test-dir.sm
/gem5/src/mem/ruby/network/Network.cc
/gem5/src/mem/ruby/network/Network.hh
/gem5/src/mem/ruby/network/Network.py
/gem5/src/mem/ruby/network/garnet/BaseGarnetNetwork.cc
/gem5/src/mem/ruby/network/garnet/BaseGarnetNetwork.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/Router.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/flitBuffer.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/flitBuffer.hh
/gem5/src/mem/ruby/network/simple/PerfectSwitch.cc
/gem5/src/mem/ruby/network/simple/PerfectSwitch.hh
/gem5/src/mem/ruby/network/simple/SimpleNetwork.cc
/gem5/src/mem/ruby/network/simple/SimpleNetwork.hh
/gem5/src/mem/ruby/network/simple/Switch.cc
/gem5/src/mem/ruby/network/simple/Switch.hh
/gem5/src/mem/ruby/network/simple/Throttle.cc
/gem5/src/mem/ruby/network/simple/Throttle.hh
/gem5/src/mem/ruby/slicc_interface/AbstractController.cc
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
symbols/StateMachine.py
/gem5/src/python/swig/pyobject.cc
10308:8c0870dbae5c 01-Sep-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: slicc: change the way configurable members are specified
There are two changes this patch makes to the way configurable members of a
state machine are specified in SLICC. The first change is that the data
member declarations will need to be separated by a semi-colon instead of a
comma. Secondly, the default value to be assigned would now use SLICC's
assignment operator i.e. ':='.

10307:6df951dcd7d9 01-Sep-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: slicc: improve the grammar
This patch changes the grammar for SLICC so as to remove some of the
redundant / duplicate rules. In particular rules for object/variable
declaration and class member declaration have been unified. Similarly, the
rules for a general function and a class method have been unified.

One more change is in the priority of two rules. The first rule is on
declaring a function with all the params typed and named. The second rule is
on declaring a function with all the params only typed. Earlier the second
rule had a higher priority. Now the first rule has a higher priority.

10305:76745b567dc3 01-Sep-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: slicc: donot prefix machine name to variables
This changeset does away with prefixing of member variables of state machines
with the identity of the machine itself.

10304:a2f88c6d9e54 01-Sep-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: remove unused toString() from AbstractController

10301:44839e8febbd 01-Sep-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: move files from ruby/system to ruby/structures

The directory ruby/system is crowded and unorganized. Hence, the files the
hold actual physical structures, are being moved to the directory
ruby/structures. This includes Cache Memory, Directory Memory,
Memory Controller, Wire Buffer, TBE Table, Perfect Cache Memory, Timer Table,
Bank Array.

The directory ruby/systems has the glue code that holds these structures
together.


/gem5/src/mem/ruby/SConscript
/gem5/src/mem/ruby/buffers/MessageBuffer.cc
/gem5/src/mem/ruby/buffers/MessageBuffer.hh
/gem5/src/mem/ruby/buffers/MessageBufferNode.cc
/gem5/src/mem/ruby/buffers/MessageBufferNode.hh
/gem5/src/mem/ruby/buffers/SConscript
/gem5/src/mem/ruby/common/MachineID.hh
/gem5/src/mem/ruby/common/NetDest.hh
/gem5/src/mem/ruby/network/MessageBuffer.cc
/gem5/src/mem/ruby/network/MessageBuffer.hh
/gem5/src/mem/ruby/network/MessageBufferNode.cc
/gem5/src/mem/ruby/network/MessageBufferNode.hh
/gem5/src/mem/ruby/network/SConscript
/gem5/src/mem/ruby/network/garnet/BaseGarnetNetwork.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
/gem5/src/mem/ruby/network/simple/PerfectSwitch.cc
/gem5/src/mem/ruby/network/simple/SimpleNetwork.cc
/gem5/src/mem/ruby/network/simple/Switch.cc
/gem5/src/mem/ruby/network/simple/Throttle.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/recorder/CacheRecorder.cc
/gem5/src/mem/ruby/recorder/CacheRecorder.hh
/gem5/src/mem/ruby/recorder/SConscript
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
/gem5/src/mem/ruby/structures/AbstractReplacementPolicy.hh
/gem5/src/mem/ruby/structures/BankedArray.cc
/gem5/src/mem/ruby/structures/BankedArray.hh
/gem5/src/mem/ruby/structures/Cache.py
/gem5/src/mem/ruby/structures/CacheMemory.cc
/gem5/src/mem/ruby/structures/CacheMemory.hh
/gem5/src/mem/ruby/structures/DirectoryMemory.cc
/gem5/src/mem/ruby/structures/DirectoryMemory.hh
/gem5/src/mem/ruby/structures/DirectoryMemory.py
/gem5/src/mem/ruby/structures/LRUPolicy.hh
/gem5/src/mem/ruby/structures/MemoryControl.cc
/gem5/src/mem/ruby/structures/MemoryControl.hh
/gem5/src/mem/ruby/structures/MemoryControl.py
/gem5/src/mem/ruby/structures/MemoryNode.cc
/gem5/src/mem/ruby/structures/MemoryNode.hh
/gem5/src/mem/ruby/structures/MemoryVector.hh
/gem5/src/mem/ruby/structures/PerfectCacheMemory.hh
/gem5/src/mem/ruby/structures/PersistentTable.cc
/gem5/src/mem/ruby/structures/PersistentTable.hh
/gem5/src/mem/ruby/structures/Prefetcher.hh
/gem5/src/mem/ruby/structures/PseudoLRUPolicy.hh
/gem5/src/mem/ruby/structures/RubyMemoryControl.cc
/gem5/src/mem/ruby/structures/RubyMemoryControl.hh
/gem5/src/mem/ruby/structures/RubyMemoryControl.py
/gem5/src/mem/ruby/structures/SConscript
/gem5/src/mem/ruby/structures/SparseMemory.cc
/gem5/src/mem/ruby/structures/SparseMemory.hh
/gem5/src/mem/ruby/structures/TBETable.hh
/gem5/src/mem/ruby/structures/TimerTable.cc
/gem5/src/mem/ruby/structures/TimerTable.hh
/gem5/src/mem/ruby/structures/WireBuffer.cc
/gem5/src/mem/ruby/structures/WireBuffer.hh
/gem5/src/mem/ruby/structures/WireBuffer.py
/gem5/src/mem/ruby/system/AbstractReplacementPolicy.hh
/gem5/src/mem/ruby/system/BankedArray.cc
/gem5/src/mem/ruby/system/BankedArray.hh
/gem5/src/mem/ruby/system/Cache.py
/gem5/src/mem/ruby/system/CacheMemory.cc
/gem5/src/mem/ruby/system/CacheMemory.hh
/gem5/src/mem/ruby/system/CacheRecorder.cc
/gem5/src/mem/ruby/system/CacheRecorder.hh
/gem5/src/mem/ruby/system/DirectoryMemory.cc
/gem5/src/mem/ruby/system/DirectoryMemory.hh
/gem5/src/mem/ruby/system/DirectoryMemory.py
/gem5/src/mem/ruby/system/LRUPolicy.hh
/gem5/src/mem/ruby/system/MachineID.hh
/gem5/src/mem/ruby/system/MemoryControl.cc
/gem5/src/mem/ruby/system/MemoryControl.hh
/gem5/src/mem/ruby/system/MemoryControl.py
/gem5/src/mem/ruby/system/MemoryNode.cc
/gem5/src/mem/ruby/system/MemoryNode.hh
/gem5/src/mem/ruby/system/MemoryVector.hh
/gem5/src/mem/ruby/system/PerfectCacheMemory.hh
/gem5/src/mem/ruby/system/PersistentTable.cc
/gem5/src/mem/ruby/system/PersistentTable.hh
/gem5/src/mem/ruby/system/PseudoLRUPolicy.hh
/gem5/src/mem/ruby/system/RubyMemoryControl.cc
/gem5/src/mem/ruby/system/RubyMemoryControl.hh
/gem5/src/mem/ruby/system/RubyMemoryControl.py
/gem5/src/mem/ruby/system/RubyPort.hh
/gem5/src/mem/ruby/system/SConscript
/gem5/src/mem/ruby/system/Sequencer.hh
/gem5/src/mem/ruby/system/SparseMemory.cc
/gem5/src/mem/ruby/system/SparseMemory.hh
/gem5/src/mem/ruby/system/System.hh
/gem5/src/mem/ruby/system/TBETable.hh
/gem5/src/mem/ruby/system/TimerTable.cc
/gem5/src/mem/ruby/system/TimerTable.hh
/gem5/src/mem/ruby/system/WireBuffer.cc
/gem5/src/mem/ruby/system/WireBuffer.hh
/gem5/src/mem/ruby/system/WireBuffer.py
symbols/Type.py
10231:cb2e6950956d 31-May-2014 Steve Reinhardt <steve.reinhardt@amd.com>

style: eliminate equality tests with true and false

Using '== true' in a boolean expression is totally redundant,
and using '== false' is pretty verbose (and arguably less
readable in most cases) compared to '!'.

It's somewhat of a pet peeve, perhaps, but I had some time
waiting for some tests to run and decided to clean these up.

Unfortunately, SLICC appears not to have the '!' operator,
so I had to leave the '== false' tests in the SLICC code.

10228:1a85c4fc805c 23-May-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: slicc: remove unused ids DNUCA*

10226:056363356d15 23-May-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: message buffer: drop dequeue_getDelayCycles()
The functionality of updating and returning the delay cycles would now be
performed by the dequeue() function itself.

10166:2681ac1d671a 19-Apr-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: slicc: remove old documentation
Has not been maintained at all. Since there is alternate documentation
available on gem5.org, no need to have this separately.

10165:7e9edf4297a9 19-Apr-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: slicc: slight change to rule for transitions
It had an unnecessary pairs token which is being removed.

10155:3b0bcc8c34ca 08-Apr-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: slicc: change enqueue statement
As of now, the enqueue statement can take in any number of 'pairs' as
argument. But we only use the pair in which latency is the key. This
latency is allowed to be either a fixed integer or a member variable of
controller in which the expression appears. This patch drops the use of pairs
in an enqueue statement. Instead, an expression is allowed which will be
interpreted to be the latency of the enqueue. This expression can anything
allowed by slicc including a constant integer or a member variable.

10121:64545628f5a7 20-Mar-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: slicc: code refactor

10085:b9891fbae4c8 23-Feb-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: slicc: remove unused COPY_HEAD functionality

10078:9400a90ec5d1 20-Feb-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: controller: slight code refactoring

10075:7322d2b2ec76 20-Feb-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: slicc: slight code refactoring

10012:ec5a5bfb941d 10-Jan-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: move all statistics to stats.txt, eliminate ruby.stats

10010:4aa1135c05d4 09-Jan-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: fix bug introduced to revision 8523754f8885

10009:8523754f8885 08-Jan-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: slicc: remove variable 'addr' used in calls to doTransition
This variable causes trouble if a variable of same name is declared in a
protocol file. Hence it is being eliminated.

10008:5176f0a71e56 04-Jan-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: add a three level MESI protocol.

The first two levels (L0, L1) are private to the core, the third level (L2)is
possibly shared. The protocol supports clustered designs. For example, one
can have two sets of two cores. Each core has an L0 and L1 cache. There are
two L2 controllers where each set accesses only one of the L2 controllers.

10005:8c2b0dc16ccd 04-Jan-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: add support for clusters

A cluster over here means a set of controllers that can be accessed only by a
certain set of cores. For example, consider a two level hierarchy. Assume
there are 4 L1 controllers (private) and 2 L2 controllers. We can have two
different hierarchies here:

a. the address space is partitioned between the two L2 controllers. Each L1
controller accesses both the L2 controllers. In this case, each L1 controller
is a cluster initself.

b. both the L2 controllers can cache any address. An L1 controller has access
to only one of the L2 controllers. In this case, each L2 controller
along with the L1 controllers that access it, form a cluster.

This patch allows for each controller to have a cluster ID, which is 0 by
default. By setting the cluster ID properly, one can instantiate hierarchies
with clusters. Note that the coherence protocol might have to be changed as
well.

9996:150338b8ba12 20-Dec-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: slicc: replace max_in_port_rank with number of inports

This patch replaces max_in_port_rank with the number of inports. The use of
max_in_port_rank was causing spurious re-builds and incorrect initialization
of variables in ruby related regression tests. This was due to the variable
value being used across threads while compiling when it was not meant to be.

Since the number of inports is state machine specific value, this problem
should get solved.

9856:69bb50791e25 06-Sep-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: converts sparse memory stats to gem5 style

9820:2f9aecba2362 07-Aug-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: slicc: remove double trigger, continueProcessing
These constructs are not in use and are not being maintained by any one.
In addition, it is not known if doubleTrigger works correctly with Ruby now.

9819:e4b12145f4eb 07-Aug-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: slicc: move some code to AbstractController
Some of the code in StateMachine.py file is added to all the controllers and
is independent of the controller definition. This code is being moved to the
AbstractController class which is the parent class of all controllers.

9804:6a043adb1e8d 11-Jul-2013 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: removed the very old double trigger hack

Committed by: Nilay Vaish <nilay@cs.wisc.edu>

9801:04414c223a6a 28-Jun-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: append transition comment only when in opt/debug

9773:915be89faf30 25-Jun-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: profiler: lots of inter-related changes
The patch started of with removing the global variables from the profiler for
profiling the miss latency of requests made to the cache. The corrresponding
histograms have been moved to the Sequencer. These are combined together when
the histograms are printed. Separate histograms are now maintained for
tracking latency of all requests together, of hits only and of misses only.

A particular set of histograms used to use the type GenericMachineType defined
in one of the protocol files. This patch removes this type. Now, everything
that relied on this type would use MachineType instead. To do this, SLICC has
been changed so that multiple machine types can be declared by a controller
in its preamble.

9767:82758c79a71f 18-Jun-2013 Lena Olson <lena@cs.wisc.edu>

ruby: fix slicc compiler to complain about duplicate symbols

Previously, .sm files were allowed to use the same name for a type and a
variable. This is unnecessarily confusing and has some bad side effects, like
not being able to declare later variables in the same scope with the same type.
This causes the compiler to complain and die on things like Address Address.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>

9745:884ad4638236 09-Jun-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: stats: use gem5's stats for cache and memory controllers
This moves event and transition count statistics for cache controllers to
gem5's statistics. It does the same for the statistics associated with the
memory controller in ruby.

All the cache/directory/dma controllers individually collect the event and
transition counts. A callback function, collateStats(), has been added that
is invoked on the controller version 0 of each controller class. This
function adds all the individual controller statistics to a vector
variables. All the code for registering the statistical variables and
collating them is generated by SLICC. The patch removes the files
*_Profiler.{cc,hh} and *_ProfileDumper.{cc,hh} which were earlier used for
collecting and dumping statistics respectively.

9703:782b7284de21 21-May-2013 Malek Musleh <malek.musleh@gmail.com>

ruby: slicc: fix error msg in TypeFieldMemberAST.py

9692:67d9da312ef0 21-May-2013 Nilay Vaish <nilay@cs.wisc.edu>, Malek Musleh <malek.musleh@gmail.com>

ruby: add stats to .sm files, remove cache profiler
This patch changes the way cache statistics are collected in ruby.

As of now, there is separate entity called CacheProfiler which holds
statistical variables for caches. The CacheMemory class defines different
functions for accessing the CacheProfiler. These functions are then invoked
in the .sm files. I find this approach opaque and prone to error. Secondly,
we probably should not be paying the cost of a function call for recording
statistics.

Instead, this patch allows for accessing statistical variables in the
.sm files. The collection would become transparent. Secondly, it would happen
in place, so no function calls. The patch also removes the CacheProfiler class.

9631:5ebde5544529 09-Apr-2013 Joel Hestness <jthestness@gmail.com>

Ruby: Add field to slicc machine for generic type

This allows you to have (i.e.) an L2 cache that is not named "L2Cache"
but is still a GenericMachineType_L2Cache. This is particularly
helpful if the protocol has multiple L2 controllers.

9630:a3525ee464b8 09-Apr-2013 Joel Hestness <hestness@cs.wisc.edu>

Ruby: Order profilers based on version

When Ruby stats are printed for events and transitions, they include stats
for all of the controllers of the same type, but they are not necessarily
printed in order of the controller ID "version", because of the way the
profilers were added to the profiler vector. This patch fixes the push order
problem so that the stats are printed in ascending order 0->(# controllers),
so statistics parsers may correctly assume the controller to which the stats
belong.

9628:195d92059654 09-Apr-2013 Jason Power <powerjg@cs.wisc.edu>

Ruby: Fix typo in Slicc if-statement AST error

The error in the SLICC code was hidden by the python error in SLICC parser
before this patch

9604:ce3382ab8772 22-Mar-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: slicc: set sender, receiver clock objs for optional queue

9597:f9b731fc6064 22-Mar-2013 Nilay Vaish <nilay@cs.wisc.edu>

slicc: remove check if the L1Cache has a sequencer

9596:aa73a81cf92c 22-Mar-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: move stall and wakeup functions to AbstractController
These functions are currently implemented in one of the files related to Slicc.
Since these are purely C++ functions, they are better suited to be in the base
class.

9595:470016acf37d 22-Mar-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: connect two controllers using only message buffers
This patch modifies ruby so that two controllers can be connected to each
other with only message buffers in between. Before this patch, all the
controllers had to be connected to the network for them to communicate
with each other. With this patch, one can have protocols where a controller
is not connected to the network, but communicates with another controller
through a message buffer.

9561:bc043a0455e3 19-Feb-2013 Nilay Vaish <nilay@cs.wisc.edu>

slicc: remove unused variable message_buffer_names

9508:dde110931867 10-Feb-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: enable multiple clock domains
This patch allows ruby to have multiple clock domains. As I understand
with this patch, controllers can have different frequencies. The entire
network needs to run at a single frequency.

The idea is that with in an object, time is treated in terms of cycles.
But the messages that are passed from one entity to another should contain
the time in Ticks. As of now, this is only true for the message buffers,
but not for the links in the network. As I understand the code, all the
entities in different networks (simple, garnet-fixed, garnet-flexible) should
be clocked at the same frequency.

Another problem is that the directory controller has to operate at the same
frequency as the ruby system. This is because the memory controller does
not make use of the Message Buffer, and instead implements a buffer of its
own. So, it has no idea of the frequency at which the directory controller
is operating and uses ruby system's frequency for scheduling events.

9507:d2ab6d889fc7 10-Feb-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: replace Time with Cycles (final patch in the series)
This patch is as of now the final patch in the series of patches that replace
Time with Cycles.This patch further replaces Time with Cycles in Sequencer,
Profiler, different protocols and related entities.

Though Time has not been completely removed, the places where it is in use
seem benign as of now.

9500:9c3e3d1c7a87 10-Feb-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: replace Time with Cycles in Message class
Concomitant changes are being committed as well, including the io operator<<
for the Cycles class.

9499:b03b556a8fbb 10-Feb-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: replaces Time with Cycles in many places
The patch started of with replacing Time with Cycles in the Consumer class.
But to get ruby to compile, the rest of the changes had to be carried out.
Subsequent patches will further this process, till we completely replace
Time with Cycles.


/gem5/src/mem/protocol/MESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MESI_CMP_directory-dma.sm
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MI_example-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dma.sm
/gem5/src/mem/protocol/MOESI_hammer-cache.sm
/gem5/src/mem/protocol/MOESI_hammer-dir.sm
/gem5/src/mem/protocol/MOESI_hammer-dma.sm
/gem5/src/mem/protocol/Network_test-cache.sm
/gem5/src/mem/protocol/RubySlicc_Exports.sm
/gem5/src/mem/protocol/RubySlicc_Types.sm
/gem5/src/mem/protocol/RubySlicc_Util.sm
/gem5/src/mem/ruby/buffers/MessageBuffer.cc
/gem5/src/mem/ruby/buffers/MessageBuffer.hh
/gem5/src/mem/ruby/buffers/MessageBufferNode.hh
/gem5/src/mem/ruby/common/Consumer.cc
/gem5/src/mem/ruby/common/Consumer.hh
/gem5/src/mem/ruby/network/BasicLink.hh
/gem5/src/mem/ruby/network/BasicLink.py
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/SWallocator_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/VCallocator_d.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.py
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/Router.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/Router.hh
/gem5/src/mem/ruby/network/simple/PerfectSwitch.cc
/gem5/src/mem/ruby/network/simple/Switch.cc
/gem5/src/mem/ruby/network/simple/Switch.hh
/gem5/src/mem/ruby/network/simple/Throttle.cc
/gem5/src/mem/ruby/network/simple/Throttle.hh
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/slicc_interface/Controller.py
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
/gem5/src/mem/ruby/system/Cache.py
/gem5/src/mem/ruby/system/CacheMemory.hh
/gem5/src/mem/ruby/system/RubyMemoryControl.cc
/gem5/src/mem/ruby/system/RubyMemoryControl.hh
/gem5/src/mem/ruby/system/RubyMemoryControl.py
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/TimerTable.cc
/gem5/src/mem/ruby/system/TimerTable.hh
/gem5/src/mem/ruby/system/WireBuffer.cc
/gem5/src/mem/ruby/system/WireBuffer.hh
ast/EnqueueStatementAST.py
ast/FuncCallExprAST.py
ast/InfixOperatorExprAST.py
symbols/StateMachine.py
symbols/Type.py
9496:28d88a0fda74 10-Feb-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: record fully busy cycle with in the controller
This patch does several things. First, the counter for fully busy cycles for a
controller is now kept with in the controller, instead of being part of the profiler.
Second, the topology class no longer keeps an array of controllers which was only
used for printing stats. Instead, ruby system will now ask each controller to print
the stats. Thirdly, the statistical variable for recording how many different types
were created is being moved in to the controller from the profiler. Note that for
printing, the profiler will collate results from different controllers.

9483:c2d205f278fc 28-Jan-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: remove call to curCycle in panic()
The panic() function already prints the current tick value. This call to
curCycle() is as such redundant. Since we are trying to move towards multiple
clock domains, this call will print misleading time.

9466:23e13ad7091f 14-Jan-2013 Nilay Vaish <nilay@cs.wisc.edu>

Ruby: remove reference to g_system_ptr from class Message
This patch was initiated so as to remove reference to g_system_ptr,
the pointer to Ruby System that is used for getting the current time.
That simple change actual requires changing a lot many things in slicc and
garnet. All these changes are related to how time is handled.

In most of the places, g_system_ptr has been replaced by another clock
object. The changes have been done under the assumption that all the
components in the memory system are on the same clock frequency, but the
actual clocks might be distributed.


/gem5/src/mem/ruby/common/Global.hh
/gem5/src/mem/ruby/network/garnet/BaseGarnetNetwork.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/RoutingUnit_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/SWallocator_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/VCallocator_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/VirtualChannel_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/VirtualChannel_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/flitBuffer_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/flitBuffer_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/flit_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/flit_d.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/Router.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/flit.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/flit.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/flitBuffer.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/flitBuffer.hh
/gem5/src/mem/ruby/network/orion/NetworkPower.cc
/gem5/src/mem/ruby/slicc_interface/Message.hh
/gem5/src/mem/ruby/slicc_interface/NetworkMessage.hh
/gem5/src/mem/ruby/slicc_interface/RubyRequest.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
/gem5/src/mem/ruby/structures/Prefetcher.hh
/gem5/src/mem/ruby/system/DMASequencer.cc
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/WireBuffer.cc
ast/EnqueueStatementAST.py
symbols/Type.py
9465:4ae4f3f4b870 14-Jan-2013 Nilay Vaish <nilay@cs.wisc.edu>

Ruby: use ClockedObject in Consumer class
Many Ruby structures inherit from the Consumer, which is used for scheduling
events. The Consumer used to relay on an Event Manager for scheduling events
and on g_system_ptr for time. With this patch, the Consumer will now use a
ClockedObject to schedule events and to query for current time. This resulted
in several structures being converted from SimObjects to ClockedObjects. Also,
the MessageBuffer class now requires a pointer to a ClockedObject so as to
query for time.


/gem5/src/mem/protocol/RubySlicc_Profiler.sm
/gem5/src/mem/protocol/RubySlicc_Types.sm
/gem5/src/mem/ruby/buffers/MessageBuffer.cc
/gem5/src/mem/ruby/buffers/MessageBuffer.hh
/gem5/src/mem/ruby/common/Consumer.cc
/gem5/src/mem/ruby/common/Consumer.hh
/gem5/src/mem/ruby/network/BasicRouter.cc
/gem5/src/mem/ruby/network/BasicRouter.hh
/gem5/src/mem/ruby/network/BasicRouter.py
/gem5/src/mem/ruby/network/Network.cc
/gem5/src/mem/ruby/network/Network.hh
/gem5/src/mem/ruby/network/Network.py
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/FlexibleConsumer.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.py
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.hh
/gem5/src/mem/ruby/network/simple/PerfectSwitch.cc
/gem5/src/mem/ruby/network/simple/PerfectSwitch.hh
/gem5/src/mem/ruby/network/simple/Switch.cc
/gem5/src/mem/ruby/network/simple/Throttle.cc
/gem5/src/mem/ruby/network/simple/Throttle.hh
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/slicc_interface/AbstractController.cc
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/slicc_interface/Controller.py
/gem5/src/mem/ruby/slicc_interface/Message.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.cc
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.hh
/gem5/src/mem/ruby/system/MemoryControl.hh
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/TimerTable.cc
/gem5/src/mem/ruby/system/TimerTable.hh
ast/AST.py
symbols/StateMachine.py
9366:bf8eb26c7b7e 11-Dec-2012 Nilay Vaish <nilay@cs.wisc.edu>

ruby: add support for prefetching to MESI protocol

9364:e5fc9d588132 11-Dec-2012 Nilay Vaish <nilay@cs.wisc.edu>

ruby: change slicc to allow for constructor args
The patch adds support to slicc for recognizing arguments that should be
passed to the constructor of a class. I did not like the fact that an explicit
check was being carried on the type 'TBETable' to figure out the arguments to
be passed to the constructor.
The patch also moves some of the member variables that are declared for all
the controllers to the base class AbstractController.

9338:97b4a2be1e5b 02-Nov-2012 Andreas Sandberg <Andreas.Sandberg@arm.com>

sim: Include object header files in SWIG interfaces

When casting objects in the generated SWIG interfaces, SWIG uses
classical C-style casts ( (Foo *)bar; ). In some cases, this can
degenerate into the equivalent of a reinterpret_cast (mainly if only a
forward declaration of the type is available). This usually works for
most compilers, but it is known to break if multiple inheritance is
used anywhere in the object hierarchy.

This patch introduces the cxx_header attribute to Python SimObject
definitions, which should be used to specify a header to include in
the SWIG interface. The header should include the declaration of the
wrapped object. We currently don't enforce header the use of the
header attribute, but a warning will be generated for objects that do
not use it.


/gem5/src/SConscript
/gem5/src/arch/alpha/AlphaInterrupts.py
/gem5/src/arch/alpha/AlphaSystem.py
/gem5/src/arch/alpha/AlphaTLB.py
/gem5/src/arch/arm/ArmInterrupts.py
/gem5/src/arch/arm/ArmNativeTrace.py
/gem5/src/arch/arm/ArmSystem.py
/gem5/src/arch/arm/ArmTLB.py
/gem5/src/arch/mips/MipsInterrupts.py
/gem5/src/arch/mips/MipsSystem.py
/gem5/src/arch/mips/MipsTLB.py
/gem5/src/arch/power/PowerInterrupts.py
/gem5/src/arch/power/PowerTLB.py
/gem5/src/arch/sparc/SparcInterrupts.py
/gem5/src/arch/sparc/SparcNativeTrace.py
/gem5/src/arch/sparc/SparcSystem.py
/gem5/src/arch/sparc/SparcTLB.py
/gem5/src/arch/x86/X86LocalApic.py
/gem5/src/arch/x86/X86NativeTrace.py
/gem5/src/arch/x86/X86System.py
/gem5/src/arch/x86/X86TLB.py
/gem5/src/arch/x86/bios/ACPI.py
/gem5/src/arch/x86/bios/E820.py
/gem5/src/arch/x86/bios/IntelMP.py
/gem5/src/arch/x86/bios/SMBios.py
/gem5/src/base/CPA.py
/gem5/src/base/vnc/Vnc.py
/gem5/src/cpu/BaseCPU.py
/gem5/src/cpu/CheckerCPU.py
/gem5/src/cpu/ExeTracer.py
/gem5/src/cpu/FuncUnit.py
/gem5/src/cpu/IntelTrace.py
/gem5/src/cpu/IntrControl.py
/gem5/src/cpu/LegionTrace.py
/gem5/src/cpu/NativeTrace.py
/gem5/src/cpu/inorder/InOrderCPU.py
/gem5/src/cpu/inorder/InOrderTrace.py
/gem5/src/cpu/inteltrace.hh
/gem5/src/cpu/o3/FUPool.py
/gem5/src/cpu/simple/AtomicSimpleCPU.py
/gem5/src/cpu/simple/BaseSimpleCPU.py
/gem5/src/cpu/simple/TimingSimpleCPU.py
/gem5/src/cpu/static_inst.hh
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.py
/gem5/src/cpu/testers/memtest/MemTest.py
/gem5/src/cpu/testers/networktest/NetworkTest.py
/gem5/src/cpu/testers/rubytest/RubyTester.py
/gem5/src/cpu/testers/traffic_gen/TrafficGen.py
/gem5/src/dev/BadDevice.py
/gem5/src/dev/CopyEngine.py
/gem5/src/dev/Device.py
/gem5/src/dev/DiskImage.py
/gem5/src/dev/Ethernet.py
/gem5/src/dev/Ide.py
/gem5/src/dev/Pci.py
/gem5/src/dev/Platform.py
/gem5/src/dev/SimpleDisk.py
/gem5/src/dev/Terminal.py
/gem5/src/dev/Uart.py
/gem5/src/dev/alpha/AlphaBackdoor.py
/gem5/src/dev/alpha/Tsunami.py
/gem5/src/dev/alpha/tsunami_io.hh
/gem5/src/dev/arm/RealView.py
/gem5/src/dev/arm/pl011.hh
/gem5/src/dev/arm/realview.hh
/gem5/src/dev/arm/timer_cpulocal.hh
/gem5/src/dev/copy_engine.hh
/gem5/src/dev/mips/Malta.py
/gem5/src/dev/mips/malta_io.hh
/gem5/src/dev/sparc/T1000.py
/gem5/src/dev/x86/Cmos.py
/gem5/src/dev/x86/I8042.py
/gem5/src/dev/x86/I82094AA.py
/gem5/src/dev/x86/I8237.py
/gem5/src/dev/x86/I8254.py
/gem5/src/dev/x86/I8259.py
/gem5/src/dev/x86/Pc.py
/gem5/src/dev/x86/PcSpeaker.py
/gem5/src/dev/x86/SouthBridge.py
/gem5/src/dev/x86/X86IntPin.py
/gem5/src/dev/x86/speaker.hh
/gem5/src/mem/AbstractMemory.py
/gem5/src/mem/AddrMapper.py
/gem5/src/mem/Bridge.py
/gem5/src/mem/Bus.py
/gem5/src/mem/CommMonitor.py
/gem5/src/mem/MemObject.py
/gem5/src/mem/SimpleDRAM.py
/gem5/src/mem/SimpleMemory.py
/gem5/src/mem/cache/BaseCache.py
/gem5/src/mem/cache/prefetch/Prefetcher.py
/gem5/src/mem/cache/tags/iic_repl/Repl.py
/gem5/src/mem/ruby/network/BasicLink.py
/gem5/src/mem/ruby/network/BasicRouter.py
/gem5/src/mem/ruby/network/Network.py
/gem5/src/mem/ruby/network/fault_model/FaultModel.py
/gem5/src/mem/ruby/network/garnet/BaseGarnetNetwork.py
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.py
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetRouter_d.py
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.py
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.py
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetRouter.py
/gem5/src/mem/ruby/network/simple/SimpleLink.py
/gem5/src/mem/ruby/network/simple/SimpleNetwork.py
/gem5/src/mem/ruby/profiler/Profiler.py
/gem5/src/mem/ruby/slicc_interface/Controller.py
/gem5/src/mem/ruby/system/Cache.py
/gem5/src/mem/ruby/system/DirectoryMemory.py
/gem5/src/mem/ruby/system/MemoryControl.py
/gem5/src/mem/ruby/system/RubyMemoryControl.py
/gem5/src/mem/ruby/system/RubySystem.py
/gem5/src/mem/ruby/system/Sequencer.py
/gem5/src/mem/ruby/system/WireBuffer.py
symbols/StateMachine.py
/gem5/src/python/m5/SimObject.py
/gem5/src/sim/BaseTLB.py
/gem5/src/sim/ClockedObject.py
/gem5/src/sim/InstTracer.py
/gem5/src/sim/Process.py
/gem5/src/sim/Root.py
/gem5/src/sim/System.py
9302:c2e70a9bc340 15-Oct-2012 Nilay Vaish <nilay@cs.wisc.edu>

ruby: improved support for functional accesses
This patch adds support to different entities in the ruby memory system
for more reliable functional read/write accesses. Only the simple network
has been augmented as of now. Later on Garnet will also support functional
accesses.
The patch adds functional access code to all the different types of messages
that protocols can send around. These messages are functionally accessed
by going through the buffers maintained by the network entities.
The patch also rectifies some of the bugs found in coherence protocols while
testing the patch.

With this patch applied, functional writes always succeed. But functional
reads can still fail.


/gem5/configs/example/ruby_mem_test.py
/gem5/src/mem/protocol/MESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MESI_CMP_directory-msg.sm
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MI_example-msg.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-msg.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_token-msg.sm
/gem5/src/mem/protocol/MOESI_hammer-cache.sm
/gem5/src/mem/protocol/MOESI_hammer-dir.sm
/gem5/src/mem/protocol/MOESI_hammer-msg.sm
/gem5/src/mem/protocol/Network_test-msg.sm
/gem5/src/mem/protocol/RubySlicc_Exports.sm
/gem5/src/mem/protocol/RubySlicc_MemControl.sm
/gem5/src/mem/ruby/buffers/MessageBuffer.cc
/gem5/src/mem/ruby/buffers/MessageBuffer.hh
/gem5/src/mem/ruby/buffers/MessageBufferNode.hh
/gem5/src/mem/ruby/network/Network.hh
/gem5/src/mem/ruby/network/simple/PerfectSwitch.cc
/gem5/src/mem/ruby/network/simple/SimpleNetwork.cc
/gem5/src/mem/ruby/network/simple/SimpleNetwork.hh
/gem5/src/mem/ruby/network/simple/Switch.cc
/gem5/src/mem/ruby/network/simple/Switch.hh
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/slicc_interface/Message.hh
/gem5/src/mem/ruby/slicc_interface/NetworkMessage.hh
/gem5/src/mem/ruby/slicc_interface/RubyRequest.cc
/gem5/src/mem/ruby/slicc_interface/RubyRequest.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
/gem5/src/mem/ruby/system/MemoryControl.cc
/gem5/src/mem/ruby/system/MemoryControl.hh
/gem5/src/mem/ruby/system/RubyMemoryControl.cc
/gem5/src/mem/ruby/system/RubyMemoryControl.hh
/gem5/src/mem/ruby/system/System.cc
ast/TypeDeclAST.py
symbols/StateMachine.py
symbols/SymbolTable.py
symbols/Type.py
9298:9a087e046c58 15-Oct-2012 Nilay Vaish <nilay@cs.wisc.edu>

ruby: allow function definition in slicc structs
This patch adds support for function definitions to appear in slicc structs.
This is required for supporting functional accesses for different types of
messages. Subsequent patches will use this to development.

9273:05b12cb19cc8 02-Oct-2012 Nilay Vaish <nilay@cs.wisc.edu>

ruby: rename template_hack to template
I don't like using the word hack. Hence, the patch.

9271:3859f5d4f2c6 02-Oct-2012 Nilay Vaish <nilay@cs.wisc.edu>

ruby: remove some unused things in slicc
This patch removes the parts of slicc that were required for multi-chip
protocols. Going ahead, it seems multi-chip protocols would be implemented
by playing with the network itself.

9230:33eb3c8a98b9 18-Sep-2012 Nilay Vaish <nilay@cs.wisc.edu>

ruby: avoid using g_system_ptr for event scheduling
This patch removes the use of g_system_ptr for event scheduling. Each consumer
object now needs to specify upfront an EventManager object it would use for
scheduling events. This makes the ruby memory system more amenable for a
multi-threaded simulation.

9219:258753d3bc47 12-Sep-2012 Jason Power <power.jg@gmail.com>

Ruby: Modify Scons so that we can put .sm files in extras
Also allows for header files which are required in slicc generated
code to be in a directory other than src/mem/ruby/slicc_interface.

9206:f6483789d23a 10-Sep-2012 Nilay Vaish <nilay@cs.wisc.edu>

Ruby System: Convert to Clocked Object
This patch moves Ruby System from being a SimObject to recently introduced
ClockedObject.

9205:cc41d310241f 10-Sep-2012 Nilay Vaish <nilay@cs.wisc.edu>

Ruby Slicc: remove the call to cin.get() function
If I understand correctly, this was put in place so that a debugger can be
attached when the protocol aborts. While this sounds useful, it is a problem
when the simulation is not being actively monitored. I think it is better to
remove this.

9171:ae88ecf37145 27-Aug-2012 Nilay Vaish <nilay@cs.wisc.edu>

Ruby: Remove RubyEventQueue
This patch removes RubyEventQueue. Consumer objects now rely on RubySystem
or themselves for scheduling events.


/gem5/src/cpu/testers/directedtest/RubyDirectedTester.cc
/gem5/src/cpu/testers/rubytest/Check.cc
/gem5/src/cpu/testers/rubytest/RubyTester.cc
/gem5/src/mem/ruby/buffers/MessageBuffer.cc
/gem5/src/mem/ruby/buffers/MessageBuffer.hh
/gem5/src/mem/ruby/common/Consumer.cc
/gem5/src/mem/ruby/common/Consumer.hh
/gem5/src/mem/ruby/common/Global.cc
/gem5/src/mem/ruby/common/Global.hh
/gem5/src/mem/ruby/common/SConscript
/gem5/src/mem/ruby/common/TypeDefines.hh
/gem5/src/mem/ruby/eventqueue/RubyEventQueue.cc
/gem5/src/mem/ruby/eventqueue/RubyEventQueue.hh
/gem5/src/mem/ruby/eventqueue/RubyEventQueueNode.cc
/gem5/src/mem/ruby/eventqueue/RubyEventQueueNode.hh
/gem5/src/mem/ruby/eventqueue/SConscript
/gem5/src/mem/ruby/network/garnet/BaseGarnetNetwork.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/OutVcState_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/SWallocator_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/VCallocator_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/VirtualChannel_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/VirtualChannel_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/flitBuffer_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/flit_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/flit_d.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/Router.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/flit.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/flitBuffer.cc
/gem5/src/mem/ruby/network/orion/NetworkPower.cc
/gem5/src/mem/ruby/network/simple/PerfectSwitch.cc
/gem5/src/mem/ruby/network/simple/Throttle.cc
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/profiler/StoreTrace.cc
/gem5/src/mem/ruby/profiler/StoreTrace.hh
/gem5/src/mem/ruby/slicc_interface/Message.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
/gem5/src/mem/ruby/system/CacheMemory.cc
/gem5/src/mem/ruby/system/CacheMemory.hh
/gem5/src/mem/ruby/system/RubyMemoryControl.cc
/gem5/src/mem/ruby/system/RubyPort.cc
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/Sequencer.hh
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/ruby/system/System.hh
/gem5/src/mem/ruby/system/TimerTable.cc
/gem5/src/mem/ruby/system/TimerTable.hh
/gem5/src/mem/ruby/system/WireBuffer.cc
/gem5/src/mem/ruby/system/WireBuffer.hh
ast/AST.py
ast/FuncCallExprAST.py
symbols/StateMachine.py
symbols/Type.py
9106:aa9b75db7ea0 11-Jul-2012 Brad Beckmann <Brad.Beckmann@amd.com>

imported patch jason/slicc-external-structure-fix

9105:b576c490e7d1 11-Jul-2012 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: banked cache array resource model

This patch models a cache as separate tag and data arrays. The patch exposes
the banked array as another resource that is checked by SLICC before a
transition is allowed to execute. This is similar to how TBE entries and slots
in output ports are modeled.

9104:27d56b644e78 11-Jul-2012 Joel Hestness <hestness@cs.utexas.edu>

ruby: tag and data cache access support

Updates to Ruby to support statistics counting of cache accesses. This feature
serves multiple purposes beyond simple stats collection. It provides the
foundation for ruby to model the cache tag and data arrays as physical
resources, as well as provide the necessary input data for McPAT power
modeling.

9102:5464eb9a684b 11-Jul-2012 Nuwan Jayasena <Nuwan.Jayasena@amd.com>

ruby: memory controllers now inherit from an abstract "MemoryControl" class

8946:fb6c89334b86 14-Apr-2012 Andreas Hansson <andreas.hansson@arm.com>

clang/gcc: Fix compilation issues with clang 3.0 and gcc 4.6

This patch addresses a number of minor issues that cause problems when
compiling with clang >= 3.0 and gcc >= 4.6. Most importantly, it
avoids using the deprecated ext/hash_map and instead uses
unordered_map (and similarly so for the hash_set). To make use of the
new STL containers, g++ and clang has to be invoked with "-std=c++0x",
and this is now added for all gcc versions >= 4.6, and for clang >=
3.0. For gcc >= 4.3 and <= 4.5 and clang <= 3.0 we use the tr1
unordered_map to avoid the deprecation warning.

The addition of c++0x in turn causes a few problems, as the
compiler is more stringent and adds a number of new warnings. Below,
the most important issues are enumerated:

1) the use of namespaces is more strict, e.g. for isnan, and all
headers opening the entire namespace std are now fixed.

2) another other issue caused by the more stringent compiler is the
narrowing of the embedded python, which used to be a char array,
and is now unsigned char since there were values larger than 128.

3) a particularly odd issue that arose with the new c++0x behaviour is
found in range.hh, where the operator< causes gcc to complain about
the template type parsing (the "<" is interpreted as the beginning
of a template argument), and the problem seems to be related to the
begin/end members introduced for the range-type iteration, which is
a new feature in c++11.

As a minor update, this patch also fixes the build flags for the clang
debug target that used to be shared with gcc and incorrectly use
"-ggdb".

8943:f954ee138ca3 12-Apr-2012 Andreas Hansson <andreas.hansson@arm.com>

Ruby: Ensure order-dependent iteration uses an ordered map

This patch fixes a bug in Ruby that caused non-deterministic
simulation when changing the underlying hash map implementation. The
reason is order-dependent behaviour in combination with iteration over
the hash map contents. The two locations where a sorted container is
assumed are now changed to make use of a std::map instead of the
unordered hash map.

With this change, the stats changes slightly and the follow-on
changeset will update the relevant statistics.

8938:7925057dc4d8 06-Apr-2012 Lisa Hsu <Lisa.Hsu@amd.com>

slicc: Controllers attached to Sequencers no longer have to be named L1Cache.

8936:c04af06738e0 06-Apr-2012 Brad Beckmann <Brad.Beckmann@amd.com>

slicc: fixed error message when the type has no inheritance

8683:9feb100066e1 11-Jan-2012 Nilay Vaish <nilay@cs.wisc.edu>

Ruby: Add infrastructure for recording cache contents
This patch changes CacheRecorder, CacheMemory, CacheControllers
so that the contents of a cache can be recorded for checkpointing
purposes.

8651:c3d878fbdaea 06-Jan-2012 Nilay Vaish <nilay@cs.wisc.edu>

AbstractController: Remove some of the unused functions

8644:acf68e5a8cd7 31-Dec-2011 Nilay Vaish<nilay@cs.wisc.edu>

SLICC: Use pointers for directory entries
SLICC uses pointers for cache and TBE entries but not for directory entries.
This patch changes the protocols, SLICC and Ruby memory system so that even
directory entries are referenced using pointers.

8641:4d3ecac1abec 13-Dec-2011 Nathan Binkert <nate@binkert.org>

gcc: fix unused variable warnings from GCC 4.6.1

8608:02d7ac5fb855 03-Nov-2011 Nilay Vaish<nilay@cs.wisc.edu>

Ruby: Remove some unused typedefs
This patch removes some of the unused typedefs. It also moves
some of the typedefs from Global.hh to TypeDefines.hh. The patch
also eliminates the file NodeID.hh.


/gem5/src/cpu/testers/rubytest/Check.hh
/gem5/src/mem/protocol/RubySlicc_Types.sm
/gem5/src/mem/ruby/SConscript
/gem5/src/mem/ruby/common/Address.hh
/gem5/src/mem/ruby/common/DataBlock.hh
/gem5/src/mem/ruby/common/Driver.hh
/gem5/src/mem/ruby/common/Global.hh
/gem5/src/mem/ruby/common/Histogram.hh
/gem5/src/mem/ruby/common/NetDest.hh
/gem5/src/mem/ruby/common/Set.hh
/gem5/src/mem/ruby/common/TypeDefines.hh
/gem5/src/mem/ruby/eventqueue/RubyEventQueue.hh
/gem5/src/mem/ruby/network/Network.hh
/gem5/src/mem/ruby/network/Topology.hh
/gem5/src/mem/ruby/network/garnet/NetworkHeader.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/InVcState.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/OutVcState.hh
/gem5/src/mem/ruby/network/simple/PerfectSwitch.cc
/gem5/src/mem/ruby/network/simple/PerfectSwitch.hh
/gem5/src/mem/ruby/network/simple/SimpleNetwork.hh
/gem5/src/mem/ruby/network/simple/Throttle.cc
/gem5/src/mem/ruby/network/simple/Throttle.hh
/gem5/src/mem/ruby/profiler/AccessTraceForAddress.hh
/gem5/src/mem/ruby/profiler/AddressProfiler.hh
/gem5/src/mem/ruby/profiler/CacheProfiler.hh
/gem5/src/mem/ruby/profiler/MemCntrlProfiler.hh
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/recorder/CacheRecorder.hh
/gem5/src/mem/ruby/recorder/TraceRecord.hh
/gem5/src/mem/ruby/recorder/Tracer.hh
/gem5/src/mem/ruby/slicc_interface/Message.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
/gem5/src/mem/ruby/system/MachineID.hh
/gem5/src/mem/ruby/system/NodeID.hh
symbols/StateMachine.py
symbols/Type.py
8602:836f8fad4a4c 28-Oct-2011 Nilay Vaish<nilay@cs.wisc.edu>

Ruby: Reorganize mapping of components
In RubySlicc_ComponentMapping.hh, certain '#define's have been used for
mapping MachineType to GenericMachineType. These '#define's are being
eliminated and the code will now be generated by SLICC instead. Also
are being eliminated some of the unused functions from
RubySlicc_ComponentMapping.sm.

8532:8f27cf8971fe 01-Sep-2011 Lisa Hsu <Lisa.Hsu@amd.com>

Functional Accesses: Update states to support Broadcast/Snooping protocols.

In the current implementation of Functional Accesses, it's very hard to
implement broadcast or snooping protocols where the memory has no idea if it
has exclusive access to a cache block or not. Without this knowledge, making
sure the RW vs. RO permissions are right are next to impossible. So we add a
new state called Backing_Store to enable the conveyance that this is the backup
storage for a block, so that it can be written if it is the only possibly RW
block in the system, or written even if there is another RW block in the
system, without causing problems.

Also, a small change to actually set the m_name field for each Controller so
that debugging can be easier. Now you can access a controller's name just by
controller->getName().

8531:bfc59fbde824 29-Aug-2011 Nilay Vaish<nilay@cs.wisc.edu>

SLICC: Pass arguments by reference
Arguments to functions were being passed by value. This patch
changes SLICC so that arguments are passed by reference.

8478:435179113834 27-Jul-2011 Nilay Vaish<nilay@cs.wisc.edu>

SLICC: Put functions of a controller in its .cc file
Currently, functions associated with a controller go into separate files.
This patch puts all the functions in the controller's .cc file. This should
hopefully take away some time from compilation.

8454:fad37c6670a6 05-Jul-2011 Nathan Binkert <nate@binkert.org>

slicc: add a protocol statement and an include statement
All protocols must specify their name
The include statement allows any file to include another file.

8453:82fc1267d3bb 05-Jul-2011 Nathan Binkert <nate@binkert.org>

slicc: cleanup slicc code and make it less verbose

8452:3f2c329e9046 05-Jul-2011 Nathan Binkert <nate@binkert.org>

grammar: better encapsulation of a grammar and parsing
This makes it possible to use the grammar multiple times and use the multiple
instances concurrently. This makes implementing an include statement as part
of a grammar possible.

8436:5648986156db 30-Jun-2011 Brad Beckmann <Brad.Beckmann@amd.com>, Nilay Vaish <nilay@cs.wisc.edu>

Ruby: Add support for functional accesses
This patch rpovides functional access support in Ruby. Currently only
the M5Port of RubyPort supports functional accesses. The support for
functional through the PioPort will be added as a separate patch.


/gem5/configs/example/ruby_direct_test.py
/gem5/configs/example/ruby_fs.py
/gem5/configs/example/ruby_mem_test.py
/gem5/configs/example/ruby_network_test.py
/gem5/configs/example/ruby_random_test.py
/gem5/configs/example/se.py
/gem5/configs/ruby/MESI_CMP_directory.py
/gem5/configs/ruby/MI_example.py
/gem5/configs/ruby/MOESI_CMP_directory.py
/gem5/configs/ruby/MOESI_CMP_token.py
/gem5/configs/ruby/MOESI_hammer.py
/gem5/configs/ruby/Ruby.py
/gem5/src/cpu/testers/memtest/MemTest.py
/gem5/src/cpu/testers/memtest/memtest.cc
/gem5/src/cpu/testers/memtest/memtest.hh
/gem5/src/mem/packet.cc
/gem5/src/mem/packet.hh
/gem5/src/mem/protocol/MESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MESI_CMP_directory-dma.sm
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MI_example-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dma.sm
/gem5/src/mem/protocol/MOESI_hammer-cache.sm
/gem5/src/mem/protocol/MOESI_hammer-dir.sm
/gem5/src/mem/protocol/MOESI_hammer-dma.sm
/gem5/src/mem/protocol/RubySlicc_Exports.sm
/gem5/src/mem/ruby/network/Network.cc
/gem5/src/mem/ruby/network/Network.py
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.py
/gem5/src/mem/ruby/recorder/Tracer.cc
/gem5/src/mem/ruby/recorder/Tracer.py
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/slicc_interface/Controller.py
/gem5/src/mem/ruby/slicc_interface/SConscript
/gem5/src/mem/ruby/system/Cache.py
/gem5/src/mem/ruby/system/DirectoryMemory.cc
/gem5/src/mem/ruby/system/DirectoryMemory.py
/gem5/src/mem/ruby/system/RubyPort.cc
/gem5/src/mem/ruby/system/RubyPort.hh
/gem5/src/mem/ruby/system/RubySystem.py
/gem5/src/mem/ruby/system/SConscript
/gem5/src/mem/ruby/system/Sequencer.py
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/ruby/system/System.hh
ast/MemberExprAST.py
/gem5/tests/configs/memtest-ruby.py
/gem5/tests/configs/rubytest-ruby.py
/gem5/tests/configs/simple-timing-mp-ruby.py
/gem5/tests/configs/simple-timing-ruby.py
8341:30daf1dd5c91 08-Jun-2011 Nilay Vaish<nilay@cs.wisc.edu>

Ruby: Correctly set access permissions for directory entries
The access permissions for the directory entries are not being set correctly.
This is because pointers are not used for handling directory entries.
function. get and set functions for access permissions have been added to the
Controller state machine. The changePermission() function provided by the
AbstractEntry and AbstractCacheEntry classes has been exposed to SLICC
code once again. The set_permission() functionality has been removed.

NOTE: Each protocol will have to define these get and set functions in order
to compile successfully.

8337:b9ba22cb23f2 03-Jun-2011 Nilay Vaish<nilay@cs.wisc.edu>

SLICC: Remove machine name as prefix to functions
Currently, the machine name is appended before any of the functions
defined with in the sm files. This is not necessary and it also
means that these functions cannot be used outside the sm files.
This patch does away with the prefixes. Note that the generated
C++ files in which the code for these functions is present are
still named such that the machine name is the prefix.

8308:79cf09f5a234 18-May-2011 Tushar Krishna <tushar@csail.mit.edu>

slicc: added vnet_type field to identify response vnets from others

Identifying response vnets versus other vnets will allow garnet to
determine which vnets will carry data packets, and which will carry
ctrl packets, and use appropriate buffer sizes (since data packets are larger
than ctrl packets). This in turn allows the orion power model to accurately
estimate buffer power.

8266:66a3187a6714 02-May-2011 Korey Sewell <ksewell@umich.edu>

ruby: dbg: use system ticks instead of cycles

8245:a9d06c894afe 20-Apr-2011 Nathan Binkert <nate@binkert.org>

fix some build problems from prior changesets

8232:b28d06a175be 15-Apr-2011 Nathan Binkert <nate@binkert.org>

trace: reimplement the DTRACE function so it doesn't use a vector
At the same time, rename the trace flags to debug flags since they
have broader usage than simply tracing. This means that
--trace-flags is now --debug-flags and --trace-help is now --debug-help


/gem5/src/SConscript
/gem5/src/arch/alpha/interrupts.hh
/gem5/src/arch/alpha/kernel_stats.cc
/gem5/src/arch/alpha/linux/process.cc
/gem5/src/arch/alpha/linux/system.cc
/gem5/src/arch/alpha/process.cc
/gem5/src/arch/alpha/remote_gdb.cc
/gem5/src/arch/alpha/stacktrace.hh
/gem5/src/arch/alpha/system.cc
/gem5/src/arch/alpha/tlb.cc
/gem5/src/arch/alpha/vtophys.cc
/gem5/src/arch/arm/faults.cc
/gem5/src/arch/arm/isa.cc
/gem5/src/arch/arm/isa.hh
/gem5/src/arch/arm/isa/includes.isa
/gem5/src/arch/arm/nativetrace.cc
/gem5/src/arch/arm/predecoder.cc
/gem5/src/arch/arm/process.cc
/gem5/src/arch/arm/remote_gdb.cc
/gem5/src/arch/arm/stacktrace.hh
/gem5/src/arch/arm/tlb.cc
/gem5/src/arch/arm/types.hh
/gem5/src/arch/mips/faults.cc
/gem5/src/arch/mips/isa.cc
/gem5/src/arch/mips/isa/includes.isa
/gem5/src/arch/mips/linux/process.cc
/gem5/src/arch/mips/locked_mem.hh
/gem5/src/arch/mips/process.cc
/gem5/src/arch/mips/stacktrace.hh
/gem5/src/arch/mips/tlb.cc
/gem5/src/arch/power/process.cc
/gem5/src/arch/power/stacktrace.hh
/gem5/src/arch/power/tlb.cc
/gem5/src/arch/sparc/interrupts.hh
/gem5/src/arch/sparc/isa.cc
/gem5/src/arch/sparc/isa/includes.isa
/gem5/src/arch/sparc/process.cc
/gem5/src/arch/sparc/remote_gdb.cc
/gem5/src/arch/sparc/stacktrace.hh
/gem5/src/arch/sparc/tlb.cc
/gem5/src/arch/sparc/ua2005.cc
/gem5/src/arch/sparc/vtophys.cc
/gem5/src/arch/x86/faults.cc
/gem5/src/arch/x86/insts/microregop.cc
/gem5/src/arch/x86/insts/static_inst.hh
/gem5/src/arch/x86/interrupts.cc
/gem5/src/arch/x86/isa/includes.isa
/gem5/src/arch/x86/nativetrace.cc
/gem5/src/arch/x86/pagetable_walker.cc
/gem5/src/arch/x86/predecoder.cc
/gem5/src/arch/x86/predecoder.hh
/gem5/src/arch/x86/process.cc
/gem5/src/arch/x86/stacktrace.hh
/gem5/src/arch/x86/tlb.cc
/gem5/src/arch/x86/vtophys.cc
/gem5/src/base/debug.cc
/gem5/src/base/debug.hh
/gem5/src/base/loader/aout_object.cc
/gem5/src/base/loader/ecoff_object.cc
/gem5/src/base/loader/elf_object.cc
/gem5/src/base/loader/raw_object.cc
/gem5/src/base/mysql.cc
/gem5/src/base/remote_gdb.cc
/gem5/src/base/trace.cc
/gem5/src/base/trace.hh
/gem5/src/base/vnc/vncserver.cc
/gem5/src/cpu/SConscript
/gem5/src/cpu/activity.cc
/gem5/src/cpu/base.cc
/gem5/src/cpu/base_dyn_inst_impl.hh
/gem5/src/cpu/exetrace.cc
/gem5/src/cpu/exetrace.hh
/gem5/src/cpu/inorder/cpu.cc
/gem5/src/cpu/inorder/first_stage.cc
/gem5/src/cpu/inorder/inorder_dyn_inst.cc
/gem5/src/cpu/inorder/inorder_dyn_inst.hh
/gem5/src/cpu/inorder/inorder_trace.cc
/gem5/src/cpu/inorder/pipeline_stage.cc
/gem5/src/cpu/inorder/reg_dep_map.cc
/gem5/src/cpu/inorder/resource.cc
/gem5/src/cpu/inorder/resource_pool.cc
/gem5/src/cpu/inorder/resource_sked.cc
/gem5/src/cpu/inorder/resources/agen_unit.cc
/gem5/src/cpu/inorder/resources/bpred_unit.cc
/gem5/src/cpu/inorder/resources/branch_predictor.cc
/gem5/src/cpu/inorder/resources/cache_unit.cc
/gem5/src/cpu/inorder/resources/decode_unit.cc
/gem5/src/cpu/inorder/resources/execution_unit.cc
/gem5/src/cpu/inorder/resources/fetch_seq_unit.cc
/gem5/src/cpu/inorder/resources/fetch_unit.cc
/gem5/src/cpu/inorder/resources/graduation_unit.cc
/gem5/src/cpu/inorder/resources/inst_buffer.cc
/gem5/src/cpu/inorder/resources/mult_div_unit.cc
/gem5/src/cpu/inorder/resources/use_def.cc
/gem5/src/cpu/inorder/thread_context.cc
/gem5/src/cpu/inteltrace.hh
/gem5/src/cpu/intr_control.cc
/gem5/src/cpu/nativetrace.cc
/gem5/src/cpu/o3/bpred_unit_impl.hh
/gem5/src/cpu/o3/commit_impl.hh
/gem5/src/cpu/o3/cpu.cc
/gem5/src/cpu/o3/decode_impl.hh
/gem5/src/cpu/o3/fetch_impl.hh
/gem5/src/cpu/o3/free_list.cc
/gem5/src/cpu/o3/free_list.hh
/gem5/src/cpu/o3/iew.hh
/gem5/src/cpu/o3/iew_impl.hh
/gem5/src/cpu/o3/inst_queue_impl.hh
/gem5/src/cpu/o3/lsq_impl.hh
/gem5/src/cpu/o3/lsq_unit.hh
/gem5/src/cpu/o3/lsq_unit_impl.hh
/gem5/src/cpu/o3/mem_dep_unit.hh
/gem5/src/cpu/o3/mem_dep_unit_impl.hh
/gem5/src/cpu/o3/regfile.hh
/gem5/src/cpu/o3/rename_impl.hh
/gem5/src/cpu/o3/rename_map.cc
/gem5/src/cpu/o3/rob_impl.hh
/gem5/src/cpu/o3/scoreboard.cc
/gem5/src/cpu/o3/scoreboard.hh
/gem5/src/cpu/o3/store_set.cc
/gem5/src/cpu/o3/thread_context_impl.hh
/gem5/src/cpu/pc_event.cc
/gem5/src/cpu/pred/2bit_local.cc
/gem5/src/cpu/pred/btb.cc
/gem5/src/cpu/quiesce_event.cc
/gem5/src/cpu/simple/atomic.cc
/gem5/src/cpu/simple/base.cc
/gem5/src/cpu/simple/timing.cc
/gem5/src/cpu/simple_thread.hh
/gem5/src/cpu/testers/directedtest/InvalidateGenerator.cc
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.cc
/gem5/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
/gem5/src/cpu/testers/memtest/memtest.cc
/gem5/src/cpu/testers/networktest/networktest.cc
/gem5/src/cpu/testers/rubytest/Check.cc
/gem5/src/cpu/testers/rubytest/CheckTable.cc
/gem5/src/cpu/testers/rubytest/RubyTester.cc
/gem5/src/cpu/thread_context.cc
/gem5/src/dev/alpha/backdoor.cc
/gem5/src/dev/alpha/tsunami_cchip.cc
/gem5/src/dev/alpha/tsunami_io.cc
/gem5/src/dev/alpha/tsunami_pchip.cc
/gem5/src/dev/copy_engine.cc
/gem5/src/dev/disk_image.cc
/gem5/src/dev/etherbus.cc
/gem5/src/dev/etherlink.cc
/gem5/src/dev/ethertap.cc
/gem5/src/dev/i8254xGBe.cc
/gem5/src/dev/i8254xGBe.hh
/gem5/src/dev/ide_ctrl.cc
/gem5/src/dev/ide_disk.cc
/gem5/src/dev/intel_8254_timer.cc
/gem5/src/dev/intel_8254_timer.hh
/gem5/src/dev/io_device.cc
/gem5/src/dev/isa_fake.cc
/gem5/src/dev/mc146818.cc
/gem5/src/dev/ns_gige.cc
/gem5/src/dev/pciconfigall.cc
/gem5/src/dev/pcidev.cc
/gem5/src/dev/simple_disk.cc
/gem5/src/dev/sinic.cc
/gem5/src/dev/sparc/iob.cc
/gem5/src/dev/sparc/mm_disk.cc
/gem5/src/dev/terminal.cc
/gem5/src/dev/uart8250.cc
/gem5/src/dev/x86/cmos.cc
/gem5/src/dev/x86/i8042.cc
/gem5/src/dev/x86/i82094aa.cc
/gem5/src/dev/x86/i8254.cc
/gem5/src/dev/x86/i8259.cc
/gem5/src/dev/x86/speaker.cc
/gem5/src/kern/linux/events.cc
/gem5/src/kern/linux/linux.cc
/gem5/src/kern/system_events.cc
/gem5/src/kern/tru64/tru64.hh
/gem5/src/kern/tru64/tru64_events.cc
/gem5/src/mem/bridge.cc
/gem5/src/mem/bus.cc
/gem5/src/mem/cache/base.cc
/gem5/src/mem/cache/base.hh
/gem5/src/mem/cache/cache_impl.hh
/gem5/src/mem/cache/mshr.cc
/gem5/src/mem/cache/prefetch/base.cc
/gem5/src/mem/cache/prefetch/ghb.cc
/gem5/src/mem/cache/prefetch/stride.cc
/gem5/src/mem/cache/tags/iic.cc
/gem5/src/mem/cache/tags/lru.cc
/gem5/src/mem/page_table.cc
/gem5/src/mem/physical.cc
/gem5/src/mem/port.cc
/gem5/src/mem/ruby/buffers/MessageBuffer.cc
/gem5/src/mem/ruby/common/NetDest.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/Router.cc
/gem5/src/mem/ruby/network/simple/PerfectSwitch.cc
/gem5/src/mem/ruby/network/simple/Throttle.cc
/gem5/src/mem/ruby/network/simple/Topology.cc
/gem5/src/mem/ruby/system/CacheMemory.cc
/gem5/src/mem/ruby/system/DMASequencer.cc
/gem5/src/mem/ruby/system/DirectoryMemory.cc
/gem5/src/mem/ruby/system/RubyPort.cc
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/SparseMemory.cc
symbols/StateMachine.py
/gem5/src/mem/tport.cc
/gem5/src/python/m5/debug.py
/gem5/src/python/m5/main.py
/gem5/src/python/m5/trace.py
/gem5/src/python/swig/debug.i
/gem5/src/python/swig/trace.i
/gem5/src/sim/eventq.cc
/gem5/src/sim/eventq.hh
/gem5/src/sim/faults.cc
/gem5/src/sim/pseudo_inst.cc
/gem5/src/sim/root.cc
/gem5/src/sim/sim_object.cc
/gem5/src/sim/syscall_emul.cc
/gem5/src/sim/syscall_emul.hh
/gem5/src/sim/system.cc
8229:78bf55f23338 15-Apr-2011 Nathan Binkert <nate@binkert.org>

includes: sort all includes


/gem5/src/arch/alpha/faults.cc
/gem5/src/arch/alpha/isa.hh
/gem5/src/arch/alpha/isa/main.isa
/gem5/src/arch/alpha/linux/system.cc
/gem5/src/arch/alpha/mt.hh
/gem5/src/arch/alpha/process.cc
/gem5/src/arch/alpha/remote_gdb.cc
/gem5/src/arch/alpha/remote_gdb.hh
/gem5/src/arch/alpha/tlb.cc
/gem5/src/arch/alpha/tru64/process.cc
/gem5/src/arch/alpha/types.hh
/gem5/src/arch/alpha/utility.hh
/gem5/src/arch/arm/faults.cc
/gem5/src/arch/arm/faults.hh
/gem5/src/arch/arm/insts/macromem.cc
/gem5/src/arch/arm/insts/static_inst.cc
/gem5/src/arch/arm/insts/vfp.hh
/gem5/src/arch/arm/intregs.hh
/gem5/src/arch/arm/isa/includes.isa
/gem5/src/arch/arm/linux/atag.hh
/gem5/src/arch/arm/linux/linux.cc
/gem5/src/arch/arm/linux/process.cc
/gem5/src/arch/arm/linux/process.hh
/gem5/src/arch/arm/linux/system.cc
/gem5/src/arch/arm/locked_mem.hh
/gem5/src/arch/arm/pagetable.hh
/gem5/src/arch/arm/predecoder.hh
/gem5/src/arch/arm/process.hh
/gem5/src/arch/arm/registers.hh
/gem5/src/arch/arm/remote_gdb.cc
/gem5/src/arch/arm/system.cc
/gem5/src/arch/arm/system.hh
/gem5/src/arch/arm/table_walker.cc
/gem5/src/arch/arm/table_walker.hh
/gem5/src/arch/arm/tlb.hh
/gem5/src/arch/arm/vtophys.hh
/gem5/src/arch/generic/debugfaults.hh
/gem5/src/arch/generic/types.hh
/gem5/src/arch/mips/dsp.cc
/gem5/src/arch/mips/dsp.hh
/gem5/src/arch/mips/isa.cc
/gem5/src/arch/mips/isa.hh
/gem5/src/arch/mips/isa/includes.isa
/gem5/src/arch/mips/isa_traits.hh
/gem5/src/arch/mips/linux/linux.cc
/gem5/src/arch/mips/linux/process.cc
/gem5/src/arch/mips/linux/process.hh
/gem5/src/arch/mips/linux/system.cc
/gem5/src/arch/mips/mt.hh
/gem5/src/arch/mips/process.cc
/gem5/src/arch/mips/process.hh
/gem5/src/arch/mips/system.cc
/gem5/src/arch/mips/system.hh
/gem5/src/arch/mips/tlb.cc
/gem5/src/arch/mips/tlb.hh
/gem5/src/arch/mips/utility.cc
/gem5/src/arch/mips/utility.hh
/gem5/src/arch/mips/vtophys.hh
/gem5/src/arch/power/insts/floating.hh
/gem5/src/arch/power/insts/integer.hh
/gem5/src/arch/power/isa/includes.isa
/gem5/src/arch/power/linux/linux.cc
/gem5/src/arch/power/linux/process.cc
/gem5/src/arch/power/linux/process.hh
/gem5/src/arch/power/process.hh
/gem5/src/arch/power/tlb.hh
/gem5/src/arch/power/vtophys.hh
/gem5/src/arch/sparc/isa.hh
/gem5/src/arch/sparc/isa/includes.isa
/gem5/src/arch/sparc/isa_traits.hh
/gem5/src/arch/sparc/linux/linux.cc
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/gem5/src/sim/stat_control.cc
/gem5/src/sim/syscall_emul.cc
/gem5/src/sim/syscall_emul.hh
/gem5/src/sim/system.cc
/gem5/src/sim/tlb.cc
/gem5/src/sim/vptr.hh
/gem5/src/unittest/cprintftest.cc
/gem5/src/unittest/cprintftime.cc
/gem5/src/unittest/initest.cc
/gem5/src/unittest/rangemaptest.cc
/gem5/src/unittest/stattest.cc
/gem5/src/unittest/symtest.cc
/gem5/util/ccdrv/devtime.c
/gem5/util/m5/m5.c
/gem5/util/statetrace/arch/amd64/tracechild.cc
/gem5/util/statetrace/arch/amd64/tracechild.hh
/gem5/util/statetrace/arch/arm/tracechild.cc
/gem5/util/statetrace/arch/arm/tracechild.hh
/gem5/util/statetrace/arch/i686/tracechild.cc
/gem5/util/statetrace/arch/i686/tracechild.hh
/gem5/util/statetrace/arch/sparc/tracechild.cc
/gem5/util/statetrace/arch/sparc/tracechild.hh
/gem5/util/statetrace/base/regstate.hh
/gem5/util/statetrace/base/statetrace.cc
/gem5/util/statetrace/base/tracechild.cc
/gem5/util/tap/tap.cc
/gem5/util/term/term.c
8192:be38f7b6ad9e 31-Mar-2011 Lisa Hsu <Lisa.Hsu@amd.com>

Ruby: Simplify SLICC and Entry/TBE handling.
Before this changeset, all local variables of type Entry and TBE were considered
to be pointers, but an immediate use of said variables would not be automatically
deferenced in SLICC-generated code. Instead, deferences occurred when such
variables were passed to functions, and were automatically dereferenced in
the bodies of the functions (e.g. the implicitly passed cache_entry).

This is a more general way to do it, which leaves in place the
assumption that parameters to functions and local variables of type AbstractCacheEntry
and TBE are always pointers, but instead of dereferencing to access member variables
on a contextual basis, the dereferencing automatically occurs on a type basis at the
moment a member is being accessed. So, now, things you can do that you couldn't before
include:

Entry foo := getCacheEntry(address);
cache_entry.DataBlk := foo.DataBlk;

or

cache_entry.DataBlk := getCacheEntry(address).DataBlk;

or even

cache_entry.DataBlk := static_cast(Entry, pointer, cache.lookup(address)).DataBlk;

8191:777459f7c61f 31-Mar-2011 Lisa Hsu <Lisa.Hsu@amd.com>

Ruby: Add new object called WireBuffer to mimic a Wire.
This is a substitute for MessageBuffers between controllers where you don't
want messages to actually go through the Network, because requests/responses can
always get reordered wrt to one another (even if you turn off Randomization and turn on Ordered)
because you are, after all, going through a network with contention. For systems where you model
multiple controllers that are very tightly coupled and do not actually go through a network,
it is a pain to have to write a coherence protocol to account for mixed up request/response orderings
despite the fact that it's completely unrealistic. This is *not* meant as a substitute for real
MessageBuffers when messages do in fact go over a network.

8189:d5ad24eb015f 31-Mar-2011 Lisa Hsu <Lisa.Hsu@amd.com>

Ruby: enable multiple sequencers in one controller.

8188:20dbef14192d 31-Mar-2011 Lisa Hsu <Lisa.Hsu@amd.com>

Ruby: pass Packet->Req->contextId() to Ruby.
It is useful for Ruby to understand from whence request packets came.
This has all request packets going into Ruby pass the contextId value, if
it exists. This supplants the old libruby proc_id value passed around in
all the Messages, so I've also removed the unused unsigned proc_id; member
generated by SLICC for all Message types.

8187:99428f716e7b 31-Mar-2011 Lisa Hsu <Lisa.Hsu@amd.com>

Ruby: Bug in SLICC forgot semicolon at end of code.

8170:c1c6f36e118e 20-Mar-2011 Nilay Vaish<nilay@cs.wisc.edu>

SLICC: Remove WakeUp* import calls from ast/__init__.py
I had recently committed a patch that removed the WakeUp*.py files from the
slicc/ast directory. I had forgotten to remove the import calls for these
files from slicc/ast/__init__.py. This resulted in error while running
regressions on zizzer. This patch does the needful.

8159:de9e34de70ff 19-Mar-2011 Brad Beckmann <Brad.Beckmann@amd.com>

slicc: improved invalid transition message

8156:9a6a02a235f1 18-Mar-2011 Nilay Vaish<nilay@cs.wisc.edu>

SLICC: Remove external_type for structures
In SLICC, in order to define a type a data type for which it should not
generate any code, the keyword external_type is used. For those data types for
which code should be generated, the keyword structure is used. This patch
eliminates the use of keyword external_type for defining structures. structure
key word can now have an optional attribute external, which would be used for
figuring out whether or not to generate the code for this structure. Also, now
structures can have functions as well data members in them.

8155:099771c7725d 18-Mar-2011 Nilay Vaish<nilay@cs.wisc.edu>

SLICC: Remove the keyword wake_up_dependents
In order to add stall and wait facility for protocols, a keyword
wake_up_dependents was introduced. This patch removes the keyword,
instead this functionality is now implemented as function call.

8154:f3d1493787d4 18-Mar-2011 Nilay Vaish<nilay@cs.wisc.edu>

SLICC: Remove the keyword wake_up_all_dependents
In order to add stall and wait facility for protocols, a keyword
wake_up_all_dependents was introduced. This patch removes the keyword,
instead this functionality is now implemented as function call.

8086:bf0335d98250 23-Feb-2011 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: automate permission setting

This patch integrates permissions with cache and memory states, and then
automates the setting of permissions within the generated code. No longer
does one need to manually set the permissions within the setState funciton.
This patch will faciliate easier functional access support by always correctly
setting permissions for both cache and memory states.

8085:d1eb504fd302 23-Feb-2011 Brad Beckmann <Brad.Beckmann@amd.com>

MOESI_hammer: cache probe address clean up

8055:e1fd27c723a2 23-Feb-2011 Korey Sewell <ksewell@umich.edu>

ruby: extend dprintfs for RubyGenerated TraceFlag
"executing" isnt a very descriptive debug message and in going through the
output you get multiple messages that say "executing" but nothing to help
you parse through the code/execution.

So instead, at least print out the name of the action that is taking
place in these functions.

7922:7532067f818e 07-Feb-2011 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: support to stallAndWait the mandatory queue

By stalling and waiting the mandatory queue instead of recycling it, one can
ensure that no incoming messages are starved when the mandatory queue puts
signficant of pressure on the L1 cache controller (i.e. the ruby memtester).

7839:9e556fb25900 17-Jan-2011 Nilay Vaish<nilay@cs.wisc.edu>

Change interface between coherence protocols and CacheMemory
The purpose of this patch is to change the way CacheMemory interfaces with
coherence protocols. Currently, whenever a cache controller (defined in the
protocol under consideration) needs to carry out any operation on a cache
block, it looks up the tag hash map and figures out whether or not the block
exists in the cache. In case it does exist, the operation is carried out
(which requires another lookup). As observed through profiling of different
protocols, multiple such lookups take place for a given cache block. It was
noted that the tag lookup takes anything from 10% to 20% of the simulation
time. In order to reduce this time, this patch is being posted.

I have to acknowledge that the many of the thoughts that went in to this
patch belong to Brad.

Changes to CacheMemory, TBETable and AbstractCacheEntry classes:
1. The lookup function belonging to CacheMemory class now returns a pointer
to a cache block entry, instead of a reference. The pointer is NULL in case
the block being looked up is not present in the cache. Similar change has
been carried out in the lookup function of the TBETable class.
2. Function for setting and getting access permission of a cache block have
been moved from CacheMemory class to AbstractCacheEntry class.
3. The allocate function in CacheMemory class now returns pointer to the
allocated cache entry.

Changes to SLICC:
1. Each action now has implicit variables - cache_entry and tbe. cache_entry,
if != NULL, must point to the cache entry for the address on which the action
is being carried out. Similarly, tbe should also point to the transaction
buffer entry of the address on which the action is being carried out.
2. If a cache entry or a transaction buffer entry is passed on as an
argument to a function, it is presumed that a pointer is being passed on.
3. The cache entry and the tbe pointers received __implicitly__ by the
actions, are passed __explicitly__ to the trigger function.
4. While performing an action, set/unset_cache_entry, set/unset_tbe are to
be used for setting / unsetting cache entry and tbe pointers respectively.
5. is_valid() and is_invalid() has been made available for testing whether
a given pointer 'is not NULL' and 'is NULL' respectively.
6. Local variables are now available, but they are assumed to be pointers
always.
7. It is now possible for an object of the derieved class to make calls to
a function defined in the interface.
8. An OOD token has been introduced in SLICC. It is same as the NULL token
used in C/C++. If you are wondering, OOD stands for Out Of Domain.
9. static_cast can now taken an optional parameter that asks for casting the
given variable to a pointer of the given type.
10. Functions can be annotated with 'return_by_pointer=yes' to return a
pointer.
11. StateMachine has two new variables, EntryType and TBEType. EntryType is
set to the type which inherits from 'AbstractCacheEntry'. There can only be
one such type in the machine. TBEType is set to the type for which 'TBE' is
used as the name.

All the protocols have been modified to conform with the new interface.

7832:de7601e6e19d 10-Jan-2011 Nathan Binkert <nate@binkert.org>

ruby: get rid of ruby's Debug.hh

Get rid of the Debug class
Get rid of ASSERT and use assert
Use DPRINTFR for ProtocolTrace


/gem5/configs/ruby/Ruby.py
/gem5/src/mem/SConscript
/gem5/src/mem/ruby/buffers/MessageBuffer.cc
/gem5/src/mem/ruby/buffers/MessageBuffer.hh
/gem5/src/mem/ruby/common/Debug.cc
/gem5/src/mem/ruby/common/Debug.hh
/gem5/src/mem/ruby/common/Debug.py
/gem5/src/mem/ruby/common/Global.cc
/gem5/src/mem/ruby/common/Global.hh
/gem5/src/mem/ruby/common/SConscript
/gem5/src/mem/ruby/common/Set.cc
/gem5/src/mem/ruby/eventqueue/RubyEventQueue.cc
/gem5/src/mem/ruby/filters/BulkBloomFilter.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/flit_d.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/flit.hh
/gem5/src/mem/ruby/network/simple/SimpleNetwork.cc
/gem5/src/mem/ruby/network/simple/Throttle.cc
/gem5/src/mem/ruby/network/simple/Topology.cc
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
/gem5/src/mem/ruby/storebuffer/storebuffer.cc
/gem5/src/mem/ruby/system/RubySystem.py
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/ruby/tester/DeterministicDriver.cc
/gem5/src/mem/ruby/tester/RaceyDriver.cc
/gem5/src/mem/ruby/tester/RaceyPseudoThread.cc
/gem5/src/mem/ruby/tester/test_framework.cc
symbols/StateMachine.py
symbols/Type.py
7805:f249937228b5 23-Dec-2010 Nilay Vaish<nilay@cs.wisc.edu>

This patch removes the WARN_* and ERROR_* from src/mem/ruby/common/Debug.hh file. These statements have been replaced with warn(), panic() and fatal() defined in src/base/misc.hh

7793:f6cbeb8712d3 08-Dec-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: remove Ruby asserts for m5.fast

This diff is for changing the way ASSERT is handled in Ruby. m5.fast
compiles out the assert statements by using the macro NDEBUG. Ruby uses the
macro RUBY_NO_ASSERT to do so. This macro has been removed and NDEBUG has
been put in its place.

7780:42da07116e12 01-Dec-2010 Nilay Vaish <nilay@cs.wisc.edu>

ruby: Converted old ruby debug calls to M5 debug calls

This patch developed by Nilay Vaish converts all the old GEMS-style ruby
debug calls to the appropriate M5 debug calls.


/gem5/src/cpu/testers/rubytest/CheckTable.cc
/gem5/src/mem/SConscript
/gem5/src/mem/protocol/MESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-perfectDir.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_hammer-cache.sm
/gem5/src/mem/protocol/MOESI_hammer-dir.sm
/gem5/src/mem/ruby/SConsopts
/gem5/src/mem/ruby/buffers/MessageBuffer.cc
/gem5/src/mem/ruby/common/Debug.cc
/gem5/src/mem/ruby/common/Debug.hh
/gem5/src/mem/ruby/common/NetDest.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/Router.cc
/gem5/src/mem/ruby/network/simple/PerfectSwitch.cc
/gem5/src/mem/ruby/network/simple/Throttle.cc
/gem5/src/mem/ruby/network/simple/Topology.cc
/gem5/src/mem/ruby/storebuffer/storebuffer.cc
/gem5/src/mem/ruby/system/CacheMemory.cc
/gem5/src/mem/ruby/system/DirectoryMemory.cc
/gem5/src/mem/ruby/system/SConscript
/gem5/src/mem/ruby/system/SparseMemory.cc
/gem5/src/mem/ruby/tester/RaceyPseudoThread.cc
ast/FuncCallExprAST.py
symbols/StateMachine.py
7672:d609cd948ca0 09-Sep-2010 Nathan Binkert <nate@binkert.org>

code_formatter: make it easier to insert whitespace
a newline by just doing "code()". indent() and dedent() now take a
"count" parameter to indent/dedent multiple levels.

7567:238f99c9f441 20-Aug-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Stall and wait input messages instead of recycling

This patch allows messages to be stalled in their input buffers and wait
until a corresponding address changes state. In order to make this work,
all in_ports must be ranked in order of dependence and those in_ports that
may unblock an address, must wake up the stalled messages. Alot of this
complexity is handled in slicc and the specification files simply
annotate the in_ports.

7566:6919df046bba 20-Aug-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Recycle latency fix for hammer

Patch allows each individual message buffer to have different recycle latencies
and allows the overall recycle latency to be specified at the cmd line. The
patch also adds profiling info to make sure no one processor's requests are
recycled too much.

7542:49327b849c7f 20-Aug-2010 Brad Beckmann <Brad.Beckmann@amd.com>

slicc: Consolidated the protocol stats printing

Created a separate ProfileDumper that consolidates the generated stats for
each controller of a certain type.

7454:3a3e8e8cce1b 11-Jun-2010 Nathan Binkert <nate@binkert.org>

ruby: get rid of Vector and use STL
add a couple of helper functions to base for deleteing all pointers in
a container and outputting containers to a stream


/gem5/src/base/stl_helpers.hh
/gem5/src/cpu/rubytest/CheckTable.cc
/gem5/src/cpu/rubytest/CheckTable.hh
/gem5/src/cpu/rubytest/RubyTester.cc
/gem5/src/cpu/rubytest/RubyTester.hh
/gem5/src/mem/gems_common/Map.hh
/gem5/src/mem/gems_common/PrioHeap.hh
/gem5/src/mem/gems_common/Vector.hh
/gem5/src/mem/ruby/buffers/MessageBuffer.hh
/gem5/src/mem/ruby/common/DataBlock.hh
/gem5/src/mem/ruby/common/Histogram.cc
/gem5/src/mem/ruby/common/Histogram.hh
/gem5/src/mem/ruby/common/NetDest.cc
/gem5/src/mem/ruby/common/NetDest.hh
/gem5/src/mem/ruby/common/SubBlock.cc
/gem5/src/mem/ruby/common/SubBlock.hh
/gem5/src/mem/ruby/eventqueue/RubyEventQueue.hh
/gem5/src/mem/ruby/filters/BlockBloomFilter.cc
/gem5/src/mem/ruby/filters/BlockBloomFilter.hh
/gem5/src/mem/ruby/filters/BulkBloomFilter.cc
/gem5/src/mem/ruby/filters/BulkBloomFilter.hh
/gem5/src/mem/ruby/filters/H3BloomFilter.cc
/gem5/src/mem/ruby/filters/H3BloomFilter.hh
/gem5/src/mem/ruby/filters/LSB_CountingBloomFilter.cc
/gem5/src/mem/ruby/filters/LSB_CountingBloomFilter.hh
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.hh
/gem5/src/mem/ruby/filters/MultiGrainBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiGrainBloomFilter.hh
/gem5/src/mem/ruby/filters/NonCountingBloomFilter.cc
/gem5/src/mem/ruby/filters/NonCountingBloomFilter.hh
/gem5/src/mem/ruby/network/Network.cc
/gem5/src/mem/ruby/network/Network.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/RoutingUnit_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/RoutingUnit_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/SWallocator_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/SWallocator_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/VCallocator_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/VCallocator_d.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/Router.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/Router.hh
/gem5/src/mem/ruby/network/simple/PerfectSwitch.cc
/gem5/src/mem/ruby/network/simple/PerfectSwitch.hh
/gem5/src/mem/ruby/network/simple/SimpleNetwork.cc
/gem5/src/mem/ruby/network/simple/SimpleNetwork.hh
/gem5/src/mem/ruby/network/simple/Switch.cc
/gem5/src/mem/ruby/network/simple/Switch.hh
/gem5/src/mem/ruby/network/simple/Throttle.cc
/gem5/src/mem/ruby/network/simple/Throttle.hh
/gem5/src/mem/ruby/network/simple/Topology.cc
/gem5/src/mem/ruby/network/simple/Topology.hh
/gem5/src/mem/ruby/profiler/AddressProfiler.cc
/gem5/src/mem/ruby/profiler/CacheProfiler.cc
/gem5/src/mem/ruby/profiler/CacheProfiler.hh
/gem5/src/mem/ruby/profiler/MemCntrlProfiler.cc
/gem5/src/mem/ruby/profiler/MemCntrlProfiler.hh
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/system/CacheMemory.cc
/gem5/src/mem/ruby/system/CacheMemory.hh
/gem5/src/mem/ruby/system/MemoryVector.hh
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/ruby/system/System.hh
/gem5/src/mem/ruby/system/TimerTable.cc
/gem5/src/mem/ruby/tester/DeterministicDriver.cc
/gem5/src/mem/ruby/tester/DeterministicDriver.hh
/gem5/src/mem/ruby/tester/RaceyDriver.cc
/gem5/src/mem/ruby/tester/RaceyDriver.hh
symbols/StateMachine.py
7453:1a5db3dd0f62 11-Jun-2010 Nathan Binkert <nate@binkert.org>

ruby: get rid of RefCnt and Allocator stuff use base/refcnt.hh

This was somewhat tricky because the RefCnt API was somewhat odd. The
biggest confusion was that the the RefCnt object's constructor that
took a TYPE& cloned the object. I created an explicit virtual clone()
function for things that took advantage of this version of the
constructor. I was conservative and used clone() when I was in doubt
of whether or not it was necessary. I still think that there are
probably too many instances of clone(), but hopefully not too many.

I converted several instances of const MsgPtr & to a simple MsgPtr.
If the function wants to avoid the overhead of creating another
reference, then it should just use a regular pointer instead of a ref
counting ptr.

There were a couple of instances where refcounted objects were created
on the stack. This seems pretty dangerous since if you ever
accidentally make a reference to that object with a ref counting
pointer, bad things are bound to happen.

7056:b66b558578bd 02-Apr-2010 Nathan Binkert <nate@binkert.org>

ruby: get rid of gems_common/util.hh and .cc and use stuff in src/base

7055:4e24742201d7 02-Apr-2010 Nathan Binkert <nate@binkert.org>

ruby: get "using namespace" out of headers
In addition to obvious changes, this required a slight change to the slicc
grammar to allow types with :: in them. Otherwise slicc barfs on std::string
which we need for the headers that slicc generates.


/gem5/src/cpu/rubytest/Check.cc
/gem5/src/cpu/rubytest/Check.hh
/gem5/src/cpu/rubytest/CheckTable.cc
/gem5/src/cpu/rubytest/RubyTester.cc
/gem5/src/cpu/rubytest/RubyTester.hh
/gem5/src/mem/gems_common/Vector.hh
/gem5/src/mem/protocol/MESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MESI_SCMP_bankdirectory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L2cache.sm
/gem5/src/mem/protocol/MSI_MOSI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MSI_MOSI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MSI_MOSI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MSI_MOSI_CMP_directory-msg.sm
/gem5/src/mem/protocol/RubySlicc_Exports.sm
/gem5/src/mem/protocol/RubySlicc_Profiler.sm
/gem5/src/mem/protocol/RubySlicc_Util.sm
/gem5/src/mem/ruby/buffers/MessageBuffer.cc
/gem5/src/mem/ruby/common/Address.cc
/gem5/src/mem/ruby/common/Address.hh
/gem5/src/mem/ruby/common/Driver.hh
/gem5/src/mem/ruby/common/NetDest.cc
/gem5/src/mem/ruby/common/NetDest.hh
/gem5/src/mem/ruby/common/Set.cc
/gem5/src/mem/ruby/common/Set.hh
/gem5/src/mem/ruby/common/SubBlock.cc
/gem5/src/mem/ruby/common/SubBlock.hh
/gem5/src/mem/ruby/eventqueue/RubyEventQueue.cc
/gem5/src/mem/ruby/filters/AbstractBloomFilter.hh
/gem5/src/mem/ruby/filters/BlockBloomFilter.cc
/gem5/src/mem/ruby/filters/BlockBloomFilter.hh
/gem5/src/mem/ruby/filters/BulkBloomFilter.cc
/gem5/src/mem/ruby/filters/BulkBloomFilter.hh
/gem5/src/mem/ruby/filters/GenericBloomFilter.cc
/gem5/src/mem/ruby/filters/GenericBloomFilter.hh
/gem5/src/mem/ruby/filters/H3BloomFilter.cc
/gem5/src/mem/ruby/filters/H3BloomFilter.hh
/gem5/src/mem/ruby/filters/LSB_CountingBloomFilter.cc
/gem5/src/mem/ruby/filters/LSB_CountingBloomFilter.hh
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.hh
/gem5/src/mem/ruby/filters/MultiGrainBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiGrainBloomFilter.hh
/gem5/src/mem/ruby/filters/NonCountingBloomFilter.cc
/gem5/src/mem/ruby/filters/NonCountingBloomFilter.hh
/gem5/src/mem/ruby/libruby.cc
/gem5/src/mem/ruby/network/Network.hh
/gem5/src/mem/ruby/network/garnet/NetworkHeader.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/SWallocator_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/VCallocator_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/VirtualChannel_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/flitBuffer_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/flitBuffer_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/flit_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/flit_d.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/Router.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/Router.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/VCarbiter.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/flit.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/flit.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/flitBuffer.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/flitBuffer.hh
/gem5/src/mem/ruby/network/simple/PerfectSwitch.cc
/gem5/src/mem/ruby/network/simple/SimpleNetwork.cc
/gem5/src/mem/ruby/network/simple/SimpleNetwork.hh
/gem5/src/mem/ruby/network/simple/Switch.cc
/gem5/src/mem/ruby/network/simple/Throttle.cc
/gem5/src/mem/ruby/network/simple/Throttle.hh
/gem5/src/mem/ruby/network/simple/Topology.cc
/gem5/src/mem/ruby/profiler/AccessTraceForAddress.cc
/gem5/src/mem/ruby/profiler/AccessTraceForAddress.hh
/gem5/src/mem/ruby/profiler/AddressProfiler.cc
/gem5/src/mem/ruby/profiler/AddressProfiler.hh
/gem5/src/mem/ruby/profiler/CacheProfiler.cc
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/profiler/StoreTrace.cc
/gem5/src/mem/ruby/profiler/StoreTrace.hh
/gem5/src/mem/ruby/recorder/CacheRecorder.cc
/gem5/src/mem/ruby/recorder/TraceRecord.cc
/gem5/src/mem/ruby/recorder/TraceRecord.hh
/gem5/src/mem/ruby/recorder/Tracer.cc
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/slicc_interface/AbstractEntry.hh
/gem5/src/mem/ruby/slicc_interface/NetworkMessage.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.cc
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.hh
/gem5/src/mem/ruby/system/CacheMemory.cc
/gem5/src/mem/ruby/system/CacheMemory.hh
/gem5/src/mem/ruby/system/DMASequencer.cc
/gem5/src/mem/ruby/system/DirectoryMemory.cc
/gem5/src/mem/ruby/system/DirectoryMemory.hh
/gem5/src/mem/ruby/system/MemoryControl.cc
/gem5/src/mem/ruby/system/MemoryControl.hh
/gem5/src/mem/ruby/system/PerfectCacheMemory.hh
/gem5/src/mem/ruby/system/PersistentTable.cc
/gem5/src/mem/ruby/system/PersistentTable.hh
/gem5/src/mem/ruby/system/RubyPort.hh
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/Sequencer.hh
/gem5/src/mem/ruby/system/SparseMemory.cc
/gem5/src/mem/ruby/system/SparseMemory.hh
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/ruby/system/System.hh
/gem5/src/mem/ruby/system/TBETable.hh
/gem5/src/mem/ruby/system/TimerTable.cc
/gem5/src/mem/ruby/system/TimerTable.hh
ast/EnumDeclAST.py
ast/LiteralExprAST.py
parser.py
symbols/Func.py
symbols/StateMachine.py
symbols/Type.py
7025:9adf5b0ccc79 22-Mar-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Ruby support for sparse memory

The patch includes direct support for the MI example protocol.

7007:79413d1ec307 12-Mar-2010 Nathan Binkert <nate@binkert.org>

slicc: Change the code generation so that the generated code is easier to read

7002:48a19d52d939 10-Mar-2010 Nathan Binkert <nate@binkert.org>

ruby: get rid of std-includes.hh
Do not use "using namespace std;" in headers
Include header files as needed


/gem5/src/cpu/rubytest/CheckTable.hh
/gem5/src/mem/gems_common/Map.hh
/gem5/src/mem/gems_common/PrioHeap.hh
/gem5/src/mem/gems_common/RefCnt.hh
/gem5/src/mem/gems_common/Vector.hh
/gem5/src/mem/gems_common/std-includes.hh
/gem5/src/mem/gems_common/util.cc
/gem5/src/mem/gems_common/util.hh
/gem5/src/mem/ruby/buffers/MessageBuffer.hh
/gem5/src/mem/ruby/buffers/MessageBufferNode.cc
/gem5/src/mem/ruby/buffers/MessageBufferNode.hh
/gem5/src/mem/ruby/common/Address.hh
/gem5/src/mem/ruby/common/Consumer.hh
/gem5/src/mem/ruby/common/DataBlock.hh
/gem5/src/mem/ruby/common/Debug.cc
/gem5/src/mem/ruby/common/Debug.hh
/gem5/src/mem/ruby/common/Global.hh
/gem5/src/mem/ruby/common/Histogram.cc
/gem5/src/mem/ruby/common/Histogram.hh
/gem5/src/mem/ruby/eventqueue/RubyEventQueue.hh
/gem5/src/mem/ruby/eventqueue/RubyEventQueueNode.cc
/gem5/src/mem/ruby/eventqueue/RubyEventQueueNode.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
/gem5/src/mem/ruby/network/simple/PerfectSwitch.cc
/gem5/src/mem/ruby/network/simple/PerfectSwitch.hh
/gem5/src/mem/ruby/network/simple/Switch.cc
/gem5/src/mem/ruby/network/simple/Switch.hh
/gem5/src/mem/ruby/network/simple/Topology.cc
/gem5/src/mem/ruby/network/simple/Topology.hh
/gem5/src/mem/ruby/profiler/CacheProfiler.hh
/gem5/src/mem/ruby/profiler/MemCntrlProfiler.cc
/gem5/src/mem/ruby/profiler/MemCntrlProfiler.hh
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/recorder/CacheRecorder.hh
/gem5/src/mem/ruby/recorder/Tracer.cc
/gem5/src/mem/ruby/recorder/Tracer.hh
/gem5/src/mem/ruby/slicc_interface/Message.hh
/gem5/src/mem/ruby/system/MachineID.hh
/gem5/src/mem/ruby/system/MemoryNode.cc
/gem5/src/mem/ruby/system/MemoryNode.hh
/gem5/src/mem/ruby/system/NodeID.hh
/gem5/src/mem/ruby/system/PseudoLRUPolicy.hh
symbols/StateMachine.py
symbols/Type.py
6999:f226c098c393 10-Mar-2010 Nathan Binkert <nate@binkert.org>

slicc: have a central mechanism for creating a code_formatter.
This makes it easier to add global variables like protocol

6969:1ab268977bbb 10-Feb-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Fixed slicc to initialize the m_is_blocking flag

6907:b05de761960e 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Allows boolean and string defaults for StateMachine parameters

6902:b5baf1dc44b4 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Added Cache and MemCntrl profiler calls

6888:de8e755aca4f 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Converted MOESI_hammer dma cntrl to new config system

6882:898047a3672c 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Ruby changes required to use the python config system
This patch includes the necessary changes to connect ruby objects using
the python configuration system. Mainly it consists of removing
unnecessary ruby object pointers and connecting the necessary object
pointers using the generated param objects. This patch includes the
slicc changes necessary to connect generated ruby objects together using
the python configuraiton system.

6881:5a61a8a9009a 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: connects sm queues to the network

6877:2a1a3d916ca8 29-Jan-2010 Steve Reinhardt <steve.reinhardt@amd.com>

ruby: Make SLICC-generated objects SimObjects.
Also add SLICC support for state-machine parameter defaults
(passed through to Python as SimObject Param defaults).

6872:b26f60c254c1 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Added message type check to OutPortDeclAST.py

Though OutPort's message type is not used to generate code, this fix checks
that the programmer's intent is correct. Eventually, we may want to
remove the message type from the OutPort declaration statement.

6863:21fbf0412e0d 19-Jan-2010 Derek Hower <drh5@cs.wisc.edu>

ruby: new atomics implementation

This patch changes the way that Ruby handles atomic RMW instructions. This implementation, unlike the prior one, is protocol independent. It works by locking an address from the sequencer immediately after the read portion of an RMW completes. When that address is locked, the coherence controller will only satisfy requests coming from one port (e.g., the mandatory queue) and will ignore all others. After the write portion completed, the line is unlocked. This should also work with multi-line atomics, as long as the blocks are always acquired in the same order.

6862:3d308cbd1657 19-Jan-2010 Derek Hower <drh5@cs.wisc.edu>

merge


/gem5/src/arch/isa_specific.hh
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/RubySlicc_ComponentMapping.sm
/gem5/src/mem/protocol/SConsopts
/gem5/src/mem/ruby/config/MI_example-homogeneous.rb
/gem5/src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb
/gem5/src/mem/ruby/config/cfg.rb
/gem5/src/mem/ruby/config/defaults.rb
/gem5/src/mem/ruby/libruby.cc
/gem5/src/mem/ruby/libruby.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
/gem5/src/mem/ruby/system/CacheMemory.cc
/gem5/src/mem/ruby/system/CacheMemory.hh
/gem5/src/mem/ruby/system/DirectoryMemory.cc
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/Sequencer.hh
SConscript
ast/AST.cc
ast/AST.hh
ast/ASTs.hh
ast/ActionDeclAST.cc
ast/ActionDeclAST.hh
ast/AssignStatementAST.cc
ast/AssignStatementAST.hh
ast/CheckAllocateStatementAST.cc
ast/CheckAllocateStatementAST.hh
ast/CheckStopSlotsStatementAST.cc
ast/CheckStopSlotsStatementAST.hh
ast/ChipComponentAccessAST.cc
ast/ChipComponentAccessAST.hh
ast/CopyHeadStatementAST.cc
ast/CopyHeadStatementAST.hh
ast/DeclAST.cc
ast/DeclAST.hh
ast/DeclListAST.cc
ast/DeclListAST.hh
ast/EnqueueStatementAST.cc
ast/EnqueueStatementAST.hh
ast/EnumDeclAST.cc
ast/EnumDeclAST.hh
ast/EnumExprAST.cc
ast/EnumExprAST.hh
ast/ExprAST.cc
ast/ExprAST.hh
ast/ExprStatementAST.cc
ast/ExprStatementAST.hh
ast/FormalParamAST.cc
ast/FormalParamAST.hh
ast/FuncCallExprAST.cc
ast/FuncCallExprAST.hh
ast/FuncDeclAST.cc
ast/FuncDeclAST.hh
ast/IfStatementAST.cc
ast/IfStatementAST.hh
ast/InPortDeclAST.cc
ast/InPortDeclAST.hh
ast/InfixOperatorExprAST.cc
ast/InfixOperatorExprAST.hh
ast/LiteralExprAST.cc
ast/LiteralExprAST.hh
ast/Location.cc
ast/Location.hh
ast/MachineAST.cc
ast/MachineAST.hh
ast/MemberExprAST.cc
ast/MemberExprAST.hh
ast/MethodCallExprAST.cc
ast/MethodCallExprAST.hh
ast/NewExprAST.cc
ast/NewExprAST.hh
ast/ObjDeclAST.cc
ast/ObjDeclAST.hh
ast/OutPortDeclAST.cc
ast/OutPortDeclAST.hh
ast/PairAST.cc
ast/PairAST.hh
ast/PairListAST.cc
ast/PairListAST.hh
ast/PeekStatementAST.cc
ast/PeekStatementAST.hh
ast/ReturnStatementAST.cc
ast/ReturnStatementAST.hh
ast/StatementAST.cc
ast/StatementAST.hh
ast/StatementListAST.cc
ast/StatementListAST.hh
ast/TransitionDeclAST.cc
ast/TransitionDeclAST.hh
ast/TypeAST.cc
ast/TypeAST.hh
ast/TypeDeclAST.cc
ast/TypeDeclAST.hh
ast/TypeFieldAST.cc
ast/TypeFieldAST.hh
ast/TypeFieldEnumAST.cc
ast/TypeFieldEnumAST.hh
ast/TypeFieldMemberAST.cc
ast/TypeFieldMemberAST.hh
ast/TypeFieldMethodAST.cc
ast/TypeFieldMethodAST.hh
ast/VarExprAST.cc
ast/VarExprAST.hh
generator/fileio.cc
generator/fileio.hh
generator/html_gen.cc
generator/html_gen.hh
generator/mif_gen.cc
generator/mif_gen.hh
main.cc
main.hh
parser/lexer.ll
parser/parser.py
parser/parser.yy
slicc_global.hh
symbols/Action.hh
symbols/Event.hh
symbols/Func.cc
symbols/Func.hh
symbols/State.hh
symbols/StateMachine.cc
symbols/StateMachine.hh
symbols/StateMachine.py
symbols/Symbol.cc
symbols/Symbol.hh
symbols/SymbolTable.cc
symbols/SymbolTable.hh
symbols/Transition.cc
symbols/Transition.hh
symbols/Type.cc
symbols/Type.hh
symbols/Type.py
symbols/Var.cc
symbols/Var.hh
/gem5/src/python/m5/convert.py
/gem5/src/python/m5/environment.py
/gem5/src/python/m5/smartdict.py
/gem5/src/python/m5/util/misc.py
/gem5/tests/configs/memtest-ruby.py
/gem5/tests/configs/ruby_config.py
6851:9952fc5e0a70 07-Oct-2009 Derek Hower <drh5@cs.wisc.edu>

merge

6850:d480ef5b9028 21-Sep-2009 Polina Dudnik <pdudnik@gmail.com>

Atomics bug fix

6847:44cf8bfb66ff 25-Sep-2009 Derek Hower <drh5@cs.wisc.edu>

slicc: removed unused atomics code from StateMachine

6846:60e0df8086f0 17-Sep-2009 Polina Dudnik <pdudnik@cs.wisc.edu>

Functionality migrated to sequencer.

6825:104115ebc206 21-Aug-2009 pdudnik@gmail.com

[mq]: first_patch

6794:b431ec0ad43d 18-Nov-2009 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: added error message to isinstance check
Added error message when a symbol is not an instance of a particular expected
type.

6793:bc8c8617c4f0 18-Nov-2009 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Added boolean to State Machine parameters
* * *
ruby: Removed primitive .hh includes

6780:2d3fc2e6f368 18-Nov-2009 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: slicc method error fix
Added error message when a method call is not supported by an object.

6779:4e611eba2b13 18-Nov-2009 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: slicc action error fix
Small fix to the State Machine error message when duplicate actions are defined.

6778:b3f2dfbe8006 18-Nov-2009 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: slicc state machine error fixes
Added error messages when:
- a state does not exist in a machine's list of known states.
- an event does not exist in a machine
- the actions of a certain machine have not been declared

6714:028047200ff7 05-Nov-2009 Steve Reinhardt <steve.reinhardt@amd.com>

slicc: tweak file enumeration for scons
Right now .cc and .hh files are handled separately, but then
they're just munged together at the end by scons, so it
doesn't buy us anything. Might as well munge from the start
since we'll eventually be adding generated Python files
to the list too.

6690:4dc4e494e4d8 26-Oct-2009 Brad Beckmann <Brad.Beckmann@amd.com>

fixed error message generation bug in SLICC ast files

6657:ef5fae93a3b2 22-Sep-2009 Nathan Binkert <nate@binkert.org>

slicc: Pure python implementation of slicc.
This is simply a translation of the C++ slicc into python with very minimal
reorganization of the code. The output can be verified as nearly identical
by doing a "diff -wBur".

Slicc can easily be run manually by using util/slicc


/gem5/src/mem/protocol/SConscript
SConscript
__init__.py
ast/AST.cc
ast/AST.hh
ast/AST.py
ast/ASTs.hh
ast/ActionDeclAST.cc
ast/ActionDeclAST.hh
ast/ActionDeclAST.py
ast/AssignStatementAST.cc
ast/AssignStatementAST.hh
ast/AssignStatementAST.py
ast/CheckAllocateStatementAST.cc
ast/CheckAllocateStatementAST.hh
ast/CheckAllocateStatementAST.py
ast/CheckStopSlotsStatementAST.cc
ast/CheckStopSlotsStatementAST.hh
ast/CheckStopSlotsStatementAST.py
ast/ChipComponentAccessAST.cc
ast/ChipComponentAccessAST.hh
ast/ChipComponentAccessAST.py
ast/CopyHeadStatementAST.cc
ast/CopyHeadStatementAST.hh
ast/CopyHeadStatementAST.py
ast/DeclAST.cc
ast/DeclAST.hh
ast/DeclAST.py
ast/DeclListAST.cc
ast/DeclListAST.hh
ast/DeclListAST.py
ast/EnqueueStatementAST.cc
ast/EnqueueStatementAST.hh
ast/EnqueueStatementAST.py
ast/EnumDeclAST.cc
ast/EnumDeclAST.hh
ast/EnumDeclAST.py
ast/EnumExprAST.cc
ast/EnumExprAST.hh
ast/EnumExprAST.py
ast/ExprAST.cc
ast/ExprAST.hh
ast/ExprAST.py
ast/ExprStatementAST.cc
ast/ExprStatementAST.hh
ast/ExprStatementAST.py
ast/FormalParamAST.cc
ast/FormalParamAST.hh
ast/FormalParamAST.py
ast/FuncCallExprAST.cc
ast/FuncCallExprAST.hh
ast/FuncCallExprAST.py
ast/FuncDeclAST.cc
ast/FuncDeclAST.hh
ast/FuncDeclAST.py
ast/IfStatementAST.cc
ast/IfStatementAST.hh
ast/IfStatementAST.py
ast/InPortDeclAST.cc
ast/InPortDeclAST.hh
ast/InPortDeclAST.py
ast/InfixOperatorExprAST.cc
ast/InfixOperatorExprAST.hh
ast/InfixOperatorExprAST.py
ast/LiteralExprAST.cc
ast/LiteralExprAST.hh
ast/LiteralExprAST.py
ast/Location.cc
ast/Location.hh
ast/MachineAST.cc
ast/MachineAST.hh
ast/MachineAST.py
ast/MemberExprAST.cc
ast/MemberExprAST.hh
ast/MemberExprAST.py
ast/MethodCallExprAST.cc
ast/MethodCallExprAST.hh
ast/MethodCallExprAST.py
ast/NewExprAST.cc
ast/NewExprAST.hh
ast/NewExprAST.py
ast/ObjDeclAST.cc
ast/ObjDeclAST.hh
ast/ObjDeclAST.py
ast/OutPortDeclAST.cc
ast/OutPortDeclAST.hh
ast/OutPortDeclAST.py
ast/PairAST.cc
ast/PairAST.hh
ast/PairAST.py
ast/PairListAST.cc
ast/PairListAST.hh
ast/PairListAST.py
ast/PeekStatementAST.cc
ast/PeekStatementAST.hh
ast/PeekStatementAST.py
ast/ReturnStatementAST.cc
ast/ReturnStatementAST.hh
ast/ReturnStatementAST.py
ast/StatementAST.cc
ast/StatementAST.hh
ast/StatementAST.py
ast/StatementListAST.cc
ast/StatementListAST.hh
ast/StatementListAST.py
ast/TransitionDeclAST.cc
ast/TransitionDeclAST.hh
ast/TransitionDeclAST.py
ast/TypeAST.cc
ast/TypeAST.hh
ast/TypeAST.py
ast/TypeDeclAST.cc
ast/TypeDeclAST.hh
ast/TypeDeclAST.py
ast/TypeFieldAST.cc
ast/TypeFieldAST.hh
ast/TypeFieldAST.py
ast/TypeFieldEnumAST.cc
ast/TypeFieldEnumAST.hh
ast/TypeFieldEnumAST.py
ast/TypeFieldMemberAST.cc
ast/TypeFieldMemberAST.hh
ast/TypeFieldMemberAST.py
ast/TypeFieldMethodAST.cc
ast/TypeFieldMethodAST.hh
ast/TypeFieldMethodAST.py
ast/VarExprAST.cc
ast/VarExprAST.hh
ast/VarExprAST.py
ast/__init__.py
generate/__init__.py
generate/dot.py
generate/html.py
generate/tex.py
generator/fileio.cc
generator/fileio.hh
generator/html_gen.cc
generator/html_gen.hh
generator/mif_gen.cc
generator/mif_gen.hh
main.cc
main.hh
main.py
parser.py
parser/lexer.ll
parser/parser.py
parser/parser.yy
slicc_global.hh
symbols/Action.hh
symbols/Action.py
symbols/Event.hh
symbols/Event.py
symbols/Func.cc
symbols/Func.hh
symbols/Func.py
symbols/State.hh
symbols/State.py
symbols/StateMachine.cc
symbols/StateMachine.hh
symbols/StateMachine.py
symbols/Symbol.cc
symbols/Symbol.hh
symbols/Symbol.py
symbols/SymbolTable.cc
symbols/SymbolTable.hh
symbols/SymbolTable.py
symbols/Transition.cc
symbols/Transition.hh
symbols/Transition.py
symbols/Type.cc
symbols/Type.hh
symbols/Type.py
symbols/Var.cc
symbols/Var.hh
symbols/Var.py
symbols/__init__.py
util.py
/gem5/util/slicc
6627:c7fb413a369f 28-Aug-2009 pdudnik@gmail.com

Reset the atomics flags if RMW_Read is not followed by a RMW_Read or RMW_Write

6510:336a194c8500 15-Aug-2009 pdudnik@gmail.com

Made servicing_atomic a counter and added started writes:
a function for setting the flag to indicate that
the rmw_writes started issuing

6509:d7894bb9c4b5 14-Aug-2009 pdudnik@gmail.com

Bug fix: indicate when writes started coming in

6507:df6d844345f4 14-Aug-2009 pdudnik@gmail.com

Added proc_id to CacheMsg for SMT.

Not yet necessary, but in case each of the threads
is allowed to initiate an atomic, will come in handy

6506:e9e7ca667575 14-Aug-2009 pdudnik@gmail.com

Multi-line RMW handling

6472:d7bb25f0687a 05-Aug-2009 Derek Hower <drh5@cs.wisc.edu>

merge

6467:5670eee2a866 04-Aug-2009 Derek Hower <drh5@cs.wisc.edu>

slicc: added MOESI_CMP_directory, DMA SequencerMsg, parameterized controllers

This changeset contains a lot of different changes that are too
mingled to separate. They are:

1. Added MOESI_CMP_directory

I made the changes necessary to bring back MOESI_CMP_directory,
including adding a DMA controller. I got rid of MOESI_CMP_directory_m
and made MOESI_CMP_directory use a memory controller. Added a new
configuration for two level protocols in general, and
MOESI_CMP_directory in particular.

2. DMA Sequencer uses a generic SequencerMsg

I will eventually make the cache Sequencer use this type as well. It
doesn't contain an offset field, just a physical address and a length.
MI_example has been updated to deal with this.

3. Parameterized Controllers

SLICC controllers can now take custom parameters to use for mapping,
latencies, etc. Currently, only int parameters are supported.


/gem5/src/mem/gems_common/Map.hh
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MI_example-dma.sm
/gem5/src/mem/protocol/MI_example-msg.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-msg.sm
/gem5/src/mem/protocol/MOESI_CMP_directory.slicc
/gem5/src/mem/protocol/MOESI_CMP_directory_m-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory_m.slicc
/gem5/src/mem/protocol/RubySlicc_ComponentMapping.sm
/gem5/src/mem/protocol/RubySlicc_Exports.sm
/gem5/src/mem/protocol/RubySlicc_Profiler.sm
/gem5/src/mem/protocol/RubySlicc_Types.sm
/gem5/src/mem/protocol/RubySlicc_Util.sm
/gem5/src/mem/ruby/config/MI_example-homogeneous.rb
/gem5/src/mem/ruby/config/MI_example.rb
/gem5/src/mem/ruby/config/MOESI_CMP_directory.rb
/gem5/src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb
/gem5/src/mem/ruby/config/cfg.rb
/gem5/src/mem/ruby/config/defaults.rb
/gem5/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
/gem5/src/mem/ruby/system/DMASequencer.cc
/gem5/src/mem/ruby/system/DirectoryMemory.cc
/gem5/src/mem/ruby/system/DirectoryMemory.hh
/gem5/src/mem/ruby/system/PerfectCacheMemory.hh
/gem5/src/mem/ruby/system/System.hh
/gem5/src/mem/ruby/system/TimerTable.cc
/gem5/src/mem/ruby/system/TimerTable.hh
ast/AST.hh
ast/ActionDeclAST.cc
ast/ActionDeclAST.hh
ast/EnqueueStatementAST.cc
ast/FormalParamAST.cc
ast/FormalParamAST.hh
ast/FuncDeclAST.cc
ast/FuncDeclAST.hh
ast/MachineAST.cc
ast/MachineAST.hh
parser/parser.py
parser/parser.yy
symbols/StateMachine.cc
symbols/StateMachine.hh
6439:0e78ffeebffd 04-Aug-2009 Nathan Binkert <nate@binkert.org>

slicc: better error messages when the python parser fails

6386:82ee4a597908 22-Jul-2009 Polina Dudnik <pdudnik@gmail.com>

Fixed the licences plus minor fixes for compilation

6372:f1a41ea3bbab 18-Jul-2009 Derek Hower <drh5@cs.wisc.edu>

ruby: removed all refs to old RubyConfig


/gem5/src/mem/ruby/buffers/MessageBuffer.cc
/gem5/src/mem/ruby/common/Address.hh
/gem5/src/mem/ruby/common/NetDest.cc
/gem5/src/mem/ruby/common/NetDest.hh
/gem5/src/mem/ruby/common/Set.cc
/gem5/src/mem/ruby/common/Set.hh
/gem5/src/mem/ruby/common/SubBlock.hh
/gem5/src/mem/ruby/config/RubyConfig.cc
/gem5/src/mem/ruby/config/RubyConfig.hh
/gem5/src/mem/ruby/eventqueue/RubyEventQueue.cc
/gem5/src/mem/ruby/filters/AbstractBloomFilter.hh
/gem5/src/mem/ruby/filters/BlockBloomFilter.hh
/gem5/src/mem/ruby/filters/BulkBloomFilter.hh
/gem5/src/mem/ruby/filters/GenericBloomFilter.cc
/gem5/src/mem/ruby/filters/GenericBloomFilter.hh
/gem5/src/mem/ruby/filters/H3BloomFilter.hh
/gem5/src/mem/ruby/filters/LSB_CountingBloomFilter.hh
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.hh
/gem5/src/mem/ruby/filters/MultiGrainBloomFilter.hh
/gem5/src/mem/ruby/filters/NonCountingBloomFilter.hh
/gem5/src/mem/ruby/network/Network.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkConfig.hh
/gem5/src/mem/ruby/network/simple/PerfectSwitch.cc
/gem5/src/mem/ruby/network/simple/SimpleNetwork.cc
/gem5/src/mem/ruby/network/simple/Throttle.cc
/gem5/src/mem/ruby/network/simple/Topology.cc
/gem5/src/mem/ruby/profiler/AccessTraceForAddress.hh
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/profiler/StoreTrace.hh
/gem5/src/mem/ruby/recorder/Tracer.cc
/gem5/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
/gem5/src/mem/ruby/system/AbstractMemOrCache.hh
/gem5/src/mem/ruby/system/CacheMemory.hh
/gem5/src/mem/ruby/system/DirectoryMemory.cc
/gem5/src/mem/ruby/system/PerfectCacheMemory.hh
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/Sequencer.hh
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/ruby/system/System.hh
/gem5/src/mem/ruby/tester/RaceyPseudoThread.cc
ast/EnqueueStatementAST.cc
symbols/StateMachine.cc
symbols/Type.cc
6369:82ac95f4d9f0 18-Jul-2009 Derek Hower <drh5@cs.wisc.edu>

merge

6366:c6254810bb6c 18-Jul-2009 Derek Hower <drh5@cs.wisc.edu>

slicc: made coherence profilers per-controller

6356:ceb2e719e36c 13-Jul-2009 pdudnik@gmail.com

Changed the state machine to generate code such that multiple processors can make atomic requests at once

6352:849c8cc5c995 13-Jul-2009 pdudnik@gmail.com

Added atomics implementation which would work for MI_example

6288:083a6806dd96 06-Jul-2009 Nathan Binkert <nate@binkert.org>

ruby: apply some fixes that were overwritten by the recent ruby import.

6287:d60118c43d60 06-Jul-2009 Nathan Binkert <nate@binkert.org>

slicc: update parser.py for changes in slicc language.

6286:40b142645016 06-Jul-2009 Nathan Binkert <nate@binkert.org>

scons: update SCons files for changes in ruby.

6285:ce086eca1ede 06-Jul-2009 Nathan Binkert <nate@binkert.org>

ruby: Import the latest ruby changes from gems.
This was done with an automated process, so there could be things that were
done in this tree in the past that didn't make it. One known regression
is that atomic memory operations do not seem to work properly anymore.


/gem5/src/mem/gems_common/std-includes.hh
/gem5/src/mem/gems_common/util.cc
/gem5/src/mem/gems_common/util.hh
/gem5/src/mem/protocol/MESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-mem.sm
/gem5/src/mem/protocol/MESI_CMP_directory-msg.sm
/gem5/src/mem/protocol/MESI_CMP_directory.slicc
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MI_example-dma.sm
/gem5/src/mem/protocol/MI_example-msg.sm
/gem5/src/mem/protocol/MI_example.slicc
/gem5/src/mem/protocol/RubySlicc_ComponentMapping.sm
/gem5/src/mem/protocol/RubySlicc_Exports.sm
/gem5/src/mem/protocol/RubySlicc_Types.sm
/gem5/src/mem/protocol/standard_1level_CMP-protocol.sm
/gem5/src/mem/ruby/buffers/MessageBuffer.cc
/gem5/src/mem/ruby/buffers/MessageBuffer.hh
/gem5/src/mem/ruby/common/Address.hh
/gem5/src/mem/ruby/common/Consumer.hh
/gem5/src/mem/ruby/common/DataBlock.cc
/gem5/src/mem/ruby/common/DataBlock.hh
/gem5/src/mem/ruby/common/Debug.cc
/gem5/src/mem/ruby/common/Debug.hh
/gem5/src/mem/ruby/common/Driver.hh
/gem5/src/mem/ruby/common/Global.hh
/gem5/src/mem/ruby/common/Set.cc
/gem5/src/mem/ruby/common/SubBlock.cc
/gem5/src/mem/ruby/common/SubBlock.hh
/gem5/src/mem/ruby/common/TypeDefines.hh
/gem5/src/mem/ruby/config/MI_example-homogeneous.rb
/gem5/src/mem/ruby/config/RubyConfig.cc
/gem5/src/mem/ruby/config/RubyConfig.hh
/gem5/src/mem/ruby/config/cfg.rb
/gem5/src/mem/ruby/config/config.hh
/gem5/src/mem/ruby/config/defaults.rb
/gem5/src/mem/ruby/config/libruby_cfg_test.cc
/gem5/src/mem/ruby/config/print_cfg.rb
/gem5/src/mem/ruby/config/rubyconfig.defaults
/gem5/src/mem/ruby/config/tester.defaults
/gem5/src/mem/ruby/eventqueue/RubyEventQueue.cc
/gem5/src/mem/ruby/filters/AbstractBloomFilter.hh
/gem5/src/mem/ruby/filters/BlockBloomFilter.cc
/gem5/src/mem/ruby/filters/BlockBloomFilter.hh
/gem5/src/mem/ruby/filters/BulkBloomFilter.cc
/gem5/src/mem/ruby/filters/BulkBloomFilter.hh
/gem5/src/mem/ruby/filters/GenericBloomFilter.cc
/gem5/src/mem/ruby/filters/GenericBloomFilter.hh
/gem5/src/mem/ruby/filters/H3BloomFilter.cc
/gem5/src/mem/ruby/filters/H3BloomFilter.hh
/gem5/src/mem/ruby/filters/LSB_CountingBloomFilter.cc
/gem5/src/mem/ruby/filters/LSB_CountingBloomFilter.hh
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.hh
/gem5/src/mem/ruby/filters/MultiGrainBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiGrainBloomFilter.hh
/gem5/src/mem/ruby/filters/NonCountingBloomFilter.cc
/gem5/src/mem/ruby/filters/NonCountingBloomFilter.hh
/gem5/src/mem/ruby/init.cc
/gem5/src/mem/ruby/init.hh
/gem5/src/mem/ruby/libruby.cc
/gem5/src/mem/ruby/libruby.hh
/gem5/src/mem/ruby/libruby_internal.hh
/gem5/src/mem/ruby/network/Network.cc
/gem5/src/mem/ruby/network/Network.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/CreditLink_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/GarnetNetwork_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/GarnetNetwork_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/NetworkLink_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/NetworkLink_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/OutVcState_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/OutVcState_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/OutputUnit_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/Router_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/SWallocator_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/VCallocator_d.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/GarnetNetwork.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/GarnetNetwork.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkConfig.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkInterface.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkLink.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/Router.cc
/gem5/src/mem/ruby/network/simple/CustomTopology.cc
/gem5/src/mem/ruby/network/simple/CustomTopology.hh
/gem5/src/mem/ruby/network/simple/HierarchicalSwitchTopology.cc
/gem5/src/mem/ruby/network/simple/HierarchicalSwitchTopology.hh
/gem5/src/mem/ruby/network/simple/PerfectSwitch.cc
/gem5/src/mem/ruby/network/simple/PtToPtTopology.cc
/gem5/src/mem/ruby/network/simple/PtToPtTopology.hh
/gem5/src/mem/ruby/network/simple/SimpleNetwork.cc
/gem5/src/mem/ruby/network/simple/SimpleNetwork.hh
/gem5/src/mem/ruby/network/simple/Switch.cc
/gem5/src/mem/ruby/network/simple/Switch.hh
/gem5/src/mem/ruby/network/simple/Throttle.cc
/gem5/src/mem/ruby/network/simple/Throttle.hh
/gem5/src/mem/ruby/network/simple/Topology.cc
/gem5/src/mem/ruby/network/simple/Topology.hh
/gem5/src/mem/ruby/network/simple/Torus2DTopology.cc
/gem5/src/mem/ruby/network/simple/Torus2DTopology.hh
/gem5/src/mem/ruby/profiler/AddressProfiler.cc
/gem5/src/mem/ruby/profiler/AddressProfiler.hh
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/recorder/CacheRecorder.cc
/gem5/src/mem/ruby/recorder/CacheRecorder.hh
/gem5/src/mem/ruby/recorder/TraceRecord.cc
/gem5/src/mem/ruby/recorder/TraceRecord.hh
/gem5/src/mem/ruby/recorder/Tracer.cc
/gem5/src/mem/ruby/recorder/Tracer.hh
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
/gem5/src/mem/ruby/slicc_interface/AbstractChip.cc
/gem5/src/mem/ruby/slicc_interface/AbstractChip.hh
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.cc
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
/gem5/src/mem/ruby/storebuffer/hfa.hh
/gem5/src/mem/ruby/storebuffer/hfatypes.hh
/gem5/src/mem/ruby/storebuffer/interface.cc
/gem5/src/mem/ruby/storebuffer/interface.hh
/gem5/src/mem/ruby/storebuffer/stb_interface.cc
/gem5/src/mem/ruby/storebuffer/stb_interface.hh
/gem5/src/mem/ruby/storebuffer/storebuffer.cc
/gem5/src/mem/ruby/storebuffer/storebuffer.hh
/gem5/src/mem/ruby/system/AbstractMemOrCache.hh
/gem5/src/mem/ruby/system/CacheMemory.hh
/gem5/src/mem/ruby/system/DMASequencer.cc
/gem5/src/mem/ruby/system/DMASequencer.hh
/gem5/src/mem/ruby/system/DirectoryMemory.cc
/gem5/src/mem/ruby/system/DirectoryMemory.hh
/gem5/src/mem/ruby/system/MemoryControl.cc
/gem5/src/mem/ruby/system/MemoryControl.hh
/gem5/src/mem/ruby/system/MemoryVector.hh
/gem5/src/mem/ruby/system/NodePersistentTable.cc
/gem5/src/mem/ruby/system/NodePersistentTable.hh
/gem5/src/mem/ruby/system/PersistentArbiter.cc
/gem5/src/mem/ruby/system/PersistentArbiter.hh
/gem5/src/mem/ruby/system/PersistentTable.cc
/gem5/src/mem/ruby/system/PersistentTable.hh
/gem5/src/mem/ruby/system/ProcessorInterface.hh
/gem5/src/mem/ruby/system/RubyPort.cc
/gem5/src/mem/ruby/system/RubyPort.hh
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/Sequencer.hh
/gem5/src/mem/ruby/system/StoreBuffer.cc
/gem5/src/mem/ruby/system/StoreBuffer.hh
/gem5/src/mem/ruby/system/StoreCache.cc
/gem5/src/mem/ruby/system/StoreCache.hh
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/ruby/system/System.hh
/gem5/src/mem/ruby/system/TBETable.hh
/gem5/src/mem/ruby/tester/BarrierGenerator.cc
/gem5/src/mem/ruby/tester/BarrierGenerator.hh
/gem5/src/mem/ruby/tester/Check.cc
/gem5/src/mem/ruby/tester/Check.hh
/gem5/src/mem/ruby/tester/CheckTable.cc
/gem5/src/mem/ruby/tester/CheckTable.hh
/gem5/src/mem/ruby/tester/DetermGETXGenerator.cc
/gem5/src/mem/ruby/tester/DetermGETXGenerator.hh
/gem5/src/mem/ruby/tester/DetermInvGenerator.cc
/gem5/src/mem/ruby/tester/DetermInvGenerator.hh
/gem5/src/mem/ruby/tester/DetermSeriesGETSGenerator.cc
/gem5/src/mem/ruby/tester/DetermSeriesGETSGenerator.hh
/gem5/src/mem/ruby/tester/DeterministicDriver.cc
/gem5/src/mem/ruby/tester/DeterministicDriver.hh
/gem5/src/mem/ruby/tester/Driver_Tester.cc
/gem5/src/mem/ruby/tester/Driver_Tester.hh
/gem5/src/mem/ruby/tester/EventQueue_Tester.hh
/gem5/src/mem/ruby/tester/Global_Tester.hh
/gem5/src/mem/ruby/tester/Instruction.cc
/gem5/src/mem/ruby/tester/Instruction.hh
/gem5/src/mem/ruby/tester/RaceyDriver.cc
/gem5/src/mem/ruby/tester/RaceyDriver.hh
/gem5/src/mem/ruby/tester/RaceyPseudoThread.cc
/gem5/src/mem/ruby/tester/RaceyPseudoThread.hh
/gem5/src/mem/ruby/tester/RequestGenerator.cc
/gem5/src/mem/ruby/tester/RequestGenerator.hh
/gem5/src/mem/ruby/tester/SpecifiedGenerator.cc
/gem5/src/mem/ruby/tester/SpecifiedGenerator.hh
/gem5/src/mem/ruby/tester/SyntheticDriver.cc
/gem5/src/mem/ruby/tester/SyntheticDriver.hh
/gem5/src/mem/ruby/tester/Tester.cc
/gem5/src/mem/ruby/tester/Tester.hh
/gem5/src/mem/ruby/tester/main.cc
/gem5/src/mem/ruby/tester/main.hh
/gem5/src/mem/ruby/tester/test_framework.cc
/gem5/src/mem/ruby/tester/test_framework.hh
ast/ASTs.hh
ast/EnqueueStatementAST.cc
ast/MachineAST.cc
ast/MachineAST.hh
ast/MethodCallExprAST.cc
ast/NewExprAST.cc
ast/NewExprAST.hh
ast/ObjDeclAST.cc
parser/lexer.ll
parser/parser.yy
symbols/Func.cc
symbols/Func.hh
symbols/StateMachine.cc
symbols/StateMachine.hh
symbols/Symbol.hh
symbols/SymbolTable.cc
symbols/SymbolTable.hh
symbols/Type.cc
symbols/Type.hh
symbols/Var.hh
6284:a63d1dc4c820 06-Jul-2009 Nathan Binkert <nate@binkert.org>

ruby: replace strings that were missed in original ruby import.


/gem5/src/mem/gems_common/ioutil/attrlex.ll
/gem5/src/mem/gems_common/ioutil/attrparse.yy
/gem5/src/mem/ruby/common/Global.hh
/gem5/src/mem/ruby/common/NetDest.cc
/gem5/src/mem/ruby/common/NetDest.hh
/gem5/src/mem/ruby/common/Set.cc
/gem5/src/mem/ruby/common/Set.hh
/gem5/src/mem/ruby/config/RubyConfig.cc
/gem5/src/mem/ruby/config/RubyConfig.hh
/gem5/src/mem/ruby/eventqueue/RubyEventQueue.hh
/gem5/src/mem/ruby/init.cc
/gem5/src/mem/ruby/init.hh
/gem5/src/mem/ruby/network/Network.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/CreditLink_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/GarnetNetwork_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/GarnetNetwork_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/InputUnit_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/NetworkHeader.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/NetworkInterface_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/NetworkLink_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/NetworkLink_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/OutVcState_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/OutputUnit_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/Router_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/Router_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/RoutingUnit_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/SWallocator_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/SWallocator_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/Switch_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/VCallocator_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/VCallocator_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/VirtualChannel_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/flitBuffer_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/flit_d.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/FlexibleConsumer.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/GarnetNetwork.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/GarnetNetwork.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/InVcState.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkConfig.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkInterface.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkLink.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkLink.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/OutVcState.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/Router.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/Router.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/VCarbiter.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/flit.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/flitBuffer.hh
/gem5/src/mem/ruby/network/simple/PerfectSwitch.cc
/gem5/src/mem/ruby/network/simple/SimpleNetwork.cc
/gem5/src/mem/ruby/network/simple/SimpleNetwork.hh
/gem5/src/mem/ruby/network/simple/Switch.cc
/gem5/src/mem/ruby/network/simple/Throttle.cc
/gem5/src/mem/ruby/network/simple/Topology.cc
/gem5/src/mem/ruby/network/simple/Topology.hh
/gem5/src/mem/ruby/profiler/AddressProfiler.cc
/gem5/src/mem/ruby/profiler/AddressProfiler.hh
/gem5/src/mem/ruby/profiler/CacheProfiler.cc
/gem5/src/mem/ruby/profiler/CacheProfiler.hh
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc
/gem5/src/mem/ruby/slicc_interface/AbstractChip.cc
/gem5/src/mem/ruby/slicc_interface/NetworkMessage.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.cc
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
/gem5/src/mem/ruby/system/AbstractMemOrCache.hh
/gem5/src/mem/ruby/system/CacheMemory.hh
/gem5/src/mem/ruby/system/DirectoryMemory.cc
/gem5/src/mem/ruby/system/DirectoryMemory.hh
/gem5/src/mem/ruby/system/MachineID.hh
/gem5/src/mem/ruby/system/MemoryControl.cc
/gem5/src/mem/ruby/system/MemoryControl.hh
/gem5/src/mem/ruby/system/NodeID.hh
/gem5/src/mem/ruby/system/NodePersistentTable.hh
/gem5/src/mem/ruby/system/PerfectCacheMemory.hh
/gem5/src/mem/ruby/system/PersistentArbiter.hh
/gem5/src/mem/ruby/system/Sequencer.hh
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/ruby/system/System.hh
/gem5/src/mem/ruby/system/TBETable.hh
/gem5/src/mem/ruby/system/TimerTable.hh
/gem5/src/mem/ruby/tester/Instruction.hh
/gem5/src/mem/ruby/tester/SpecifiedGenerator.cc
/gem5/src/mem/ruby/tester/SpecifiedGenerator.hh
ast/AST.cc
ast/AST.hh
ast/ActionDeclAST.cc
ast/ActionDeclAST.hh
ast/AssignStatementAST.cc
ast/AssignStatementAST.hh
ast/ChipComponentAccessAST.cc
ast/ChipComponentAccessAST.hh
ast/DeclAST.cc
ast/DeclAST.hh
ast/DeclListAST.cc
ast/DeclListAST.hh
ast/EnqueueStatementAST.hh
ast/EnumDeclAST.cc
ast/EnumDeclAST.hh
ast/EnumExprAST.cc
ast/EnumExprAST.hh
ast/ExprAST.cc
ast/ExprAST.hh
ast/ExprStatementAST.cc
ast/ExprStatementAST.hh
ast/FormalParamAST.cc
ast/FormalParamAST.hh
ast/FuncCallExprAST.cc
ast/FuncCallExprAST.hh
ast/FuncDeclAST.cc
ast/FuncDeclAST.hh
ast/IfStatementAST.cc
ast/IfStatementAST.hh
ast/InPortDeclAST.cc
ast/InPortDeclAST.hh
ast/InfixOperatorExprAST.cc
ast/InfixOperatorExprAST.hh
ast/LiteralExprAST.cc
ast/LiteralExprAST.hh
ast/Location.cc
ast/Location.hh
ast/MachineAST.cc
ast/MachineAST.hh
ast/MemberExprAST.cc
ast/MemberExprAST.hh
ast/MethodCallExprAST.cc
ast/MethodCallExprAST.hh
ast/ObjDeclAST.cc
ast/ObjDeclAST.hh
ast/OutPortDeclAST.cc
ast/OutPortDeclAST.hh
ast/PairAST.cc
ast/PairAST.hh
ast/PairListAST.cc
ast/PairListAST.hh
ast/PeekStatementAST.cc
ast/PeekStatementAST.hh
ast/ReturnStatementAST.cc
ast/ReturnStatementAST.hh
ast/StatementAST.cc
ast/StatementAST.hh
ast/StatementListAST.cc
ast/StatementListAST.hh
ast/TransitionDeclAST.cc
ast/TransitionDeclAST.hh
ast/TypeAST.cc
ast/TypeAST.hh
ast/TypeDeclAST.cc
ast/TypeDeclAST.hh
ast/TypeFieldAST.cc
ast/TypeFieldAST.hh
ast/TypeFieldEnumAST.cc
ast/TypeFieldEnumAST.hh
ast/TypeFieldMemberAST.cc
ast/TypeFieldMemberAST.hh
ast/TypeFieldMethodAST.cc
ast/TypeFieldMethodAST.hh
ast/VarExprAST.cc
ast/VarExprAST.hh
generator/fileio.cc
generator/fileio.hh
generator/html_gen.cc
generator/html_gen.hh
generator/mif_gen.hh
main.hh
symbols/Func.cc
symbols/Func.hh
symbols/SymbolTable.hh
symbols/Transition.hh
symbols/Type.cc
symbols/Type.hh
symbols/Var.hh
6216:2f4020838149 17-May-2009 Nathan Binkert <nate@binkert.org>

includes: sort includes again


/gem5/src/arch/alpha/isa_traits.hh
/gem5/src/arch/alpha/predecoder.hh
/gem5/src/arch/arm/utility.hh
/gem5/src/arch/mips/dsp.hh
/gem5/src/arch/mips/isa_traits.hh
/gem5/src/arch/mips/utility.hh
/gem5/src/arch/sparc/isa_traits.hh
/gem5/src/arch/sparc/predecoder.hh
/gem5/src/arch/sparc/regfile.hh
/gem5/src/arch/x86/bios/acpi.hh
/gem5/src/arch/x86/bios/e820.hh
/gem5/src/arch/x86/bios/intelmp.cc
/gem5/src/arch/x86/bios/smbios.cc
/gem5/src/arch/x86/bios/smbios.hh
/gem5/src/arch/x86/intmessage.hh
/gem5/src/arch/x86/miscregfile.hh
/gem5/src/arch/x86/pagetable.hh
/gem5/src/arch/x86/pagetable_walker.hh
/gem5/src/arch/x86/predecoder.cc
/gem5/src/arch/x86/regfile.hh
/gem5/src/arch/x86/utility.hh
/gem5/src/arch/x86/x86_traits.hh
/gem5/src/base/cp_annotate.hh
/gem5/src/base/crc.cc
/gem5/src/base/inet.cc
/gem5/src/base/inet.hh
/gem5/src/base/intmath.hh
/gem5/src/base/misc.cc
/gem5/src/base/pollevent.cc
/gem5/src/base/res_list.hh
/gem5/src/base/statistics.hh
/gem5/src/base/stats/mysql.cc
/gem5/src/base/stats/output.cc
/gem5/src/cpu/exetrace.hh
/gem5/src/cpu/inorder/comm.hh
/gem5/src/cpu/inorder/inorder_trace.hh
/gem5/src/cpu/inteltrace.hh
/gem5/src/cpu/legiontrace.hh
/gem5/src/cpu/nativetrace.hh
/gem5/src/cpu/o3/2bit_local_pred.hh
/gem5/src/cpu/o3/bpred_unit.hh
/gem5/src/cpu/o3/comm.hh
/gem5/src/cpu/o3/fetch_impl.hh
/gem5/src/cpu/o3/inst_queue.hh
/gem5/src/cpu/o3/ras.hh
/gem5/src/cpu/o3/store_set.hh
/gem5/src/cpu/o3/tournament_pred.hh
/gem5/src/cpu/ozone/ea_list.hh
/gem5/src/cpu/ozone/inst_queue.hh
/gem5/src/cpu/ozone/null_predictor.hh
/gem5/src/cpu/simple/base.cc
/gem5/src/cpu/simple_thread.hh
/gem5/src/cpu/static_inst.hh
/gem5/src/cpu/thread_context.hh
/gem5/src/dev/alpha/backdoor.hh
/gem5/src/dev/etherlink.hh
/gem5/src/dev/etherpkt.hh
/gem5/src/dev/intel_8254_timer.hh
/gem5/src/dev/mips/backdoor.hh
/gem5/src/dev/ns_gige.cc
/gem5/src/dev/sinic.cc
/gem5/src/dev/x86/intdev.hh
/gem5/src/dev/x86/south_bridge.cc
/gem5/src/kern/tru64/dump_mbuf.cc
/gem5/src/kern/tru64/mbuf.hh
/gem5/src/mem/bus.hh
/gem5/src/mem/cache/cache_impl.hh
/gem5/src/mem/cache/mshr.cc
/gem5/src/mem/cache/tags/fa_lru.cc
/gem5/src/mem/cache/tags/fa_lru.hh
/gem5/src/mem/cache/tags/iic_repl/gen.cc
/gem5/src/mem/cache/tags/iic_repl/repl.hh
/gem5/src/mem/cache/tags/lru.hh
/gem5/src/mem/gems_common/util.cc
/gem5/src/mem/packet.hh
/gem5/src/mem/page_table.hh
/gem5/src/mem/physical.cc
/gem5/src/mem/ruby/common/Debug.hh
/gem5/src/mem/ruby/common/Global.hh
/gem5/src/mem/ruby/network/orion/power_ll.cc
/gem5/src/mem/ruby/network/orion/power_utils.cc
/gem5/src/mem/rubymem.cc
slicc_global.hh
/gem5/src/python/swig/core.i
/gem5/src/python/swig/event.i
/gem5/src/python/swig/pyobject.hh
/gem5/src/python/swig/sim_object.i
/gem5/src/sim/arguments.hh
/gem5/src/sim/eventq.hh
/gem5/src/sim/init.cc
/gem5/src/sim/insttracer.hh
/gem5/src/sim/sim_object.cc
/gem5/src/sim/simulate.cc
/gem5/src/sim/syscall_emul.hh
/gem5/src/unittest/rangemaptest.cc
/gem5/src/unittest/rangemultimaptest.cc
/gem5/util/statetrace/arch/tracechild_amd64.hh
/gem5/util/statetrace/arch/tracechild_i386.hh
/gem5/util/statetrace/arch/tracechild_sparc.hh
6204:b247610d8882 13-May-2009 Nathan Binkert <nate@binkert.org>

ruby: remove random uint typedef and use unsigned

6201:39d8a2197b77 13-May-2009 Nathan Binkert <nate@binkert.org>

slicc: work around improper initialization of a global in slicc.

6200:0e8d74461d51 13-May-2009 Nathan Binkert <nate@binkert.org>

slicc: clean up the slicc environment so things build properly on mac.

6168:ba6fe02228db 11-May-2009 Nathan Binkert <nate@binkert.org>

ruby: add RUBY sticky option that must be set to add ruby to the build
Default is false

6164:29b7b7aba911 11-May-2009 Steve Reinhardt <steve.reinhardt@amd.com>

ruby: Check stderr and not stdin before hanging on an assert.

6157:eaf2fd8f54c0 11-May-2009 Nathan Binkert <nate@binkert.org>

ruby: Migrate all of ruby and slicc to SCons.
Add the PROTOCOL sticky option sets the coherence protocol that slicc
will parse and therefore ruby will use. This whole process was made
difficult by the fact that the set of files that are output by slicc
are not easily known ahead of time. The easiest thing wound up being
to write a parser for slicc that would tell me. Incidentally this
means we now have a slicc grammar written in python.

6154:6bb54dcb940e 11-May-2009 Nathan Binkert <nate@binkert.org>

ruby: Make ruby #includes use full paths to the files they're including.
This basically means changing all #include statements and changing
autogenerated code so that it generates the correct paths. Because
slicc generates #includes, I had to hard code the include paths to
mem/protocol.


/gem5/src/mem/gems_common/Allocator.hh
/gem5/src/mem/gems_common/Map.hh
/gem5/src/mem/gems_common/PrioHeap.hh
/gem5/src/mem/gems_common/RefCnt_tester.cc
/gem5/src/mem/gems_common/RefCountable.hh
/gem5/src/mem/gems_common/Vector.hh
/gem5/src/mem/gems_common/ioutil/attrlex.ll
/gem5/src/mem/gems_common/ioutil/attrparse.yy
/gem5/src/mem/gems_common/ioutil/confio.cc
/gem5/src/mem/gems_common/ioutil/confio.hh
/gem5/src/mem/gems_common/ioutil/initvar.cc
/gem5/src/mem/gems_common/ioutil/vardecl.hh
/gem5/src/mem/gems_common/util.cc
/gem5/src/mem/gems_common/util.hh
/gem5/src/mem/ruby/buffers/MessageBuffer.cc
/gem5/src/mem/ruby/buffers/MessageBuffer.hh
/gem5/src/mem/ruby/buffers/MessageBufferNode.cc
/gem5/src/mem/ruby/buffers/MessageBufferNode.hh
/gem5/src/mem/ruby/common/Address.cc
/gem5/src/mem/ruby/common/Address.hh
/gem5/src/mem/ruby/common/BigSet.cc
/gem5/src/mem/ruby/common/BigSet.hh
/gem5/src/mem/ruby/common/Consumer.hh
/gem5/src/mem/ruby/common/DataBlock.cc
/gem5/src/mem/ruby/common/DataBlock.hh
/gem5/src/mem/ruby/common/Debug.cc
/gem5/src/mem/ruby/common/Driver.cc
/gem5/src/mem/ruby/common/Driver.hh
/gem5/src/mem/ruby/common/Global.cc
/gem5/src/mem/ruby/common/Global.hh
/gem5/src/mem/ruby/common/Histogram.cc
/gem5/src/mem/ruby/common/Histogram.hh
/gem5/src/mem/ruby/common/Message.cc
/gem5/src/mem/ruby/common/NetDest.cc
/gem5/src/mem/ruby/common/NetDest.hh
/gem5/src/mem/ruby/common/OptBigSet.cc
/gem5/src/mem/ruby/common/OptBigSet.hh
/gem5/src/mem/ruby/common/Set.cc
/gem5/src/mem/ruby/common/Set.hh
/gem5/src/mem/ruby/common/SubBlock.cc
/gem5/src/mem/ruby/common/SubBlock.hh
/gem5/src/mem/ruby/config/RubyConfig.cc
/gem5/src/mem/ruby/config/RubyConfig.hh
/gem5/src/mem/ruby/eventqueue/RubyEventQueue.cc
/gem5/src/mem/ruby/eventqueue/RubyEventQueue.hh
/gem5/src/mem/ruby/eventqueue/RubyEventQueueNode.cc
/gem5/src/mem/ruby/eventqueue/RubyEventQueueNode.hh
/gem5/src/mem/ruby/init.cc
/gem5/src/mem/ruby/network/Network.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/CreditLink_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/GarnetNetwork_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/GarnetNetwork_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/InputUnit_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/InputUnit_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/NetworkHeader.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/NetworkInterface_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/NetworkLink_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/NetworkLink_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/OutVcState_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/OutVcState_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/OutputUnit_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/OutputUnit_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/Router_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/Router_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/RoutingUnit_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/RoutingUnit_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/SWallocator_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/SWallocator_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/Switch_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/Switch_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/VCallocator_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/VCallocator_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/VirtualChannel_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/VirtualChannel_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/flitBuffer_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/flitBuffer_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/flit_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/flit_d.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/FlexibleConsumer.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/GarnetNetwork.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/GarnetNetwork.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/InVcState.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/InVcState.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkConfig.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkInterface.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkInterface.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkLink.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkLink.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/OutVcState.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/OutVcState.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/Router.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/Router.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/VCarbiter.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/VCarbiter.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/flit.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/flit.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/flitBuffer.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/flitBuffer.hh
/gem5/src/mem/ruby/network/orion/NetworkPower.cc
/gem5/src/mem/ruby/network/orion/SIM_power.hh
/gem5/src/mem/ruby/network/orion/power_arbiter.cc
/gem5/src/mem/ruby/network/orion/power_arbiter.hh
/gem5/src/mem/ruby/network/orion/power_array.cc
/gem5/src/mem/ruby/network/orion/power_bus.cc
/gem5/src/mem/ruby/network/orion/power_crossbar.cc
/gem5/src/mem/ruby/network/orion/power_ll.cc
/gem5/src/mem/ruby/network/orion/power_router_init.cc
/gem5/src/mem/ruby/network/orion/power_router_init.hh
/gem5/src/mem/ruby/network/orion/power_static.cc
/gem5/src/mem/ruby/network/orion/power_static.hh
/gem5/src/mem/ruby/network/orion/power_utils.cc
/gem5/src/mem/ruby/network/simple/PerfectSwitch.cc
/gem5/src/mem/ruby/network/simple/PerfectSwitch.hh
/gem5/src/mem/ruby/network/simple/SimpleNetwork.cc
/gem5/src/mem/ruby/network/simple/SimpleNetwork.hh
/gem5/src/mem/ruby/network/simple/Switch.cc
/gem5/src/mem/ruby/network/simple/Switch.hh
/gem5/src/mem/ruby/network/simple/Throttle.cc
/gem5/src/mem/ruby/network/simple/Throttle.hh
/gem5/src/mem/ruby/network/simple/Topology.cc
/gem5/src/mem/ruby/network/simple/Topology.hh
/gem5/src/mem/ruby/profiler/AccessTraceForAddress.cc
/gem5/src/mem/ruby/profiler/AccessTraceForAddress.hh
/gem5/src/mem/ruby/profiler/AddressProfiler.cc
/gem5/src/mem/ruby/profiler/AddressProfiler.hh
/gem5/src/mem/ruby/profiler/CacheProfiler.cc
/gem5/src/mem/ruby/profiler/CacheProfiler.hh
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/profiler/StoreTrace.cc
/gem5/src/mem/ruby/profiler/StoreTrace.hh
/gem5/src/mem/ruby/profiler/XactProfiler.cc
/gem5/src/mem/ruby/profiler/XactProfiler.hh
/gem5/src/mem/ruby/recorder/CacheRecorder.cc
/gem5/src/mem/ruby/recorder/CacheRecorder.hh
/gem5/src/mem/ruby/recorder/TraceRecord.cc
/gem5/src/mem/ruby/recorder/TraceRecord.hh
/gem5/src/mem/ruby/recorder/Tracer.cc
/gem5/src/mem/ruby/recorder/Tracer.hh
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
/gem5/src/mem/ruby/slicc_interface/AbstractChip.cc
/gem5/src/mem/ruby/slicc_interface/AbstractChip.hh
/gem5/src/mem/ruby/slicc_interface/Message.hh
/gem5/src/mem/ruby/slicc_interface/NetworkMessage.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.cc
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_includes.hh
/gem5/src/mem/ruby/system/AbstractBloomFilter.hh
/gem5/src/mem/ruby/system/AbstractMemOrCache.hh
/gem5/src/mem/ruby/system/AbstractReplacementPolicy.hh
/gem5/src/mem/ruby/system/BlockBloomFilter.cc
/gem5/src/mem/ruby/system/BlockBloomFilter.hh
/gem5/src/mem/ruby/system/BulkBloomFilter.cc
/gem5/src/mem/ruby/system/BulkBloomFilter.hh
/gem5/src/mem/ruby/system/CacheMemory.hh
/gem5/src/mem/ruby/system/DirectoryMemory.cc
/gem5/src/mem/ruby/system/DirectoryMemory.hh
/gem5/src/mem/ruby/system/GenericBloomFilter.cc
/gem5/src/mem/ruby/system/GenericBloomFilter.hh
/gem5/src/mem/ruby/system/H3BloomFilter.cc
/gem5/src/mem/ruby/system/H3BloomFilter.hh
/gem5/src/mem/ruby/system/LRUPolicy.hh
/gem5/src/mem/ruby/system/LSB_CountingBloomFilter.cc
/gem5/src/mem/ruby/system/LSB_CountingBloomFilter.hh
/gem5/src/mem/ruby/system/MachineID.hh
/gem5/src/mem/ruby/system/MemoryControl.cc
/gem5/src/mem/ruby/system/MemoryControl.hh
/gem5/src/mem/ruby/system/MemoryNode.cc
/gem5/src/mem/ruby/system/MemoryNode.hh
/gem5/src/mem/ruby/system/MultiBitSelBloomFilter.cc
/gem5/src/mem/ruby/system/MultiBitSelBloomFilter.hh
/gem5/src/mem/ruby/system/MultiGrainBloomFilter.cc
/gem5/src/mem/ruby/system/MultiGrainBloomFilter.hh
/gem5/src/mem/ruby/system/NodeID.hh
/gem5/src/mem/ruby/system/NodePersistentTable.cc
/gem5/src/mem/ruby/system/NodePersistentTable.hh
/gem5/src/mem/ruby/system/NonCountingBloomFilter.cc
/gem5/src/mem/ruby/system/NonCountingBloomFilter.hh
/gem5/src/mem/ruby/system/PerfectCacheMemory.hh
/gem5/src/mem/ruby/system/PersistentArbiter.cc
/gem5/src/mem/ruby/system/PersistentArbiter.hh
/gem5/src/mem/ruby/system/PersistentTable.cc
/gem5/src/mem/ruby/system/PersistentTable.hh
/gem5/src/mem/ruby/system/PseudoLRUPolicy.hh
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/Sequencer.hh
/gem5/src/mem/ruby/system/StoreBuffer.cc
/gem5/src/mem/ruby/system/StoreBuffer.hh
/gem5/src/mem/ruby/system/StoreCache.cc
/gem5/src/mem/ruby/system/StoreCache.hh
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/ruby/system/System.hh
/gem5/src/mem/ruby/system/TBETable.hh
/gem5/src/mem/ruby/system/TimerTable.cc
/gem5/src/mem/ruby/system/TimerTable.hh
/gem5/src/mem/ruby/tester/BarrierGenerator.cc
/gem5/src/mem/ruby/tester/BarrierGenerator.hh
/gem5/src/mem/ruby/tester/Check.cc
/gem5/src/mem/ruby/tester/Check.hh
/gem5/src/mem/ruby/tester/CheckTable.cc
/gem5/src/mem/ruby/tester/CheckTable.hh
/gem5/src/mem/ruby/tester/DetermGETXGenerator.cc
/gem5/src/mem/ruby/tester/DetermGETXGenerator.hh
/gem5/src/mem/ruby/tester/DetermInvGenerator.cc
/gem5/src/mem/ruby/tester/DetermInvGenerator.hh
/gem5/src/mem/ruby/tester/DetermSeriesGETSGenerator.cc
/gem5/src/mem/ruby/tester/DetermSeriesGETSGenerator.hh
/gem5/src/mem/ruby/tester/DeterministicDriver.cc
/gem5/src/mem/ruby/tester/DeterministicDriver.hh
/gem5/src/mem/ruby/tester/Instruction.cc
/gem5/src/mem/ruby/tester/Instruction.hh
/gem5/src/mem/ruby/tester/RaceyDriver.cc
/gem5/src/mem/ruby/tester/RaceyDriver.hh
/gem5/src/mem/ruby/tester/RequestGenerator.cc
/gem5/src/mem/ruby/tester/RequestGenerator.hh
/gem5/src/mem/ruby/tester/SpecifiedGenerator.cc
/gem5/src/mem/ruby/tester/SpecifiedGenerator.hh
/gem5/src/mem/ruby/tester/SyntheticDriver.cc
/gem5/src/mem/ruby/tester/SyntheticDriver.hh
/gem5/src/mem/ruby/tester/Tester.cc
/gem5/src/mem/ruby/tester/Tester.hh
/gem5/src/mem/ruby/tester/XactAbortRequestGenerator.cc
/gem5/src/mem/ruby/tester/XactAbortRequestGenerator.hh
/gem5/src/mem/ruby/tester/XactRequestGenerator.cc
/gem5/src/mem/ruby/tester/XactRequestGenerator.hh
/gem5/src/mem/ruby/tester/main.cc
/gem5/src/mem/ruby/tester/main.hh
/gem5/src/mem/ruby/tester/test_framework.cc
/gem5/src/mem/ruby/tester/test_framework.hh
ast/AST.cc
ast/AST.hh
ast/ASTs.hh
ast/ActionDeclAST.cc
ast/ActionDeclAST.hh
ast/AssignStatementAST.cc
ast/AssignStatementAST.hh
ast/CheckAllocateStatementAST.cc
ast/CheckAllocateStatementAST.hh
ast/CheckStopSlotsStatementAST.cc
ast/CheckStopSlotsStatementAST.hh
ast/ChipComponentAccessAST.cc
ast/ChipComponentAccessAST.hh
ast/CopyHeadStatementAST.cc
ast/CopyHeadStatementAST.hh
ast/DeclAST.cc
ast/DeclAST.hh
ast/DeclListAST.cc
ast/DeclListAST.hh
ast/EnqueueStatementAST.cc
ast/EnqueueStatementAST.hh
ast/EnumDeclAST.cc
ast/EnumDeclAST.hh
ast/EnumExprAST.cc
ast/EnumExprAST.hh
ast/ExprAST.cc
ast/ExprAST.hh
ast/ExprStatementAST.cc
ast/ExprStatementAST.hh
ast/FormalParamAST.cc
ast/FormalParamAST.hh
ast/FuncCallExprAST.cc
ast/FuncCallExprAST.hh
ast/FuncDeclAST.cc
ast/FuncDeclAST.hh
ast/IfStatementAST.cc
ast/IfStatementAST.hh
ast/InPortDeclAST.cc
ast/InPortDeclAST.hh
ast/InfixOperatorExprAST.cc
ast/InfixOperatorExprAST.hh
ast/LiteralExprAST.cc
ast/LiteralExprAST.hh
ast/Location.cc
ast/Location.hh
ast/MachineAST.cc
ast/MachineAST.hh
ast/MemberExprAST.cc
ast/MemberExprAST.hh
ast/MethodCallExprAST.cc
ast/MethodCallExprAST.hh
ast/ObjDeclAST.cc
ast/ObjDeclAST.hh
ast/OutPortDeclAST.cc
ast/OutPortDeclAST.hh
ast/PairAST.cc
ast/PairAST.hh
ast/PairListAST.cc
ast/PairListAST.hh
ast/PeekStatementAST.cc
ast/PeekStatementAST.hh
ast/ReturnStatementAST.cc
ast/ReturnStatementAST.hh
ast/StatementAST.cc
ast/StatementAST.hh
ast/StatementListAST.cc
ast/StatementListAST.hh
ast/TransitionDeclAST.cc
ast/TransitionDeclAST.hh
ast/TypeAST.cc
ast/TypeAST.hh
ast/TypeDeclAST.cc
ast/TypeDeclAST.hh
ast/TypeFieldAST.cc
ast/TypeFieldAST.hh
ast/TypeFieldEnumAST.cc
ast/TypeFieldEnumAST.hh
ast/TypeFieldMemberAST.cc
ast/TypeFieldMemberAST.hh
ast/TypeFieldMethodAST.cc
ast/TypeFieldMethodAST.hh
ast/VarExprAST.cc
ast/VarExprAST.hh
generator/fileio.cc
generator/fileio.hh
generator/html_gen.cc
generator/html_gen.hh
generator/mif_gen.cc
generator/mif_gen.hh
main.cc
main.hh
parser/lexer.ll
parser/parser.yy
slicc_global.hh
symbols/Action.hh
symbols/Event.hh
symbols/Func.cc
symbols/Func.hh
symbols/State.hh
symbols/StateMachine.cc
symbols/StateMachine.hh
symbols/Symbol.cc
symbols/Symbol.hh
symbols/SymbolTable.cc
symbols/SymbolTable.hh
symbols/Transition.cc
symbols/Transition.hh
symbols/Type.cc
symbols/Type.hh
symbols/Var.cc
symbols/Var.hh
6145:15cca6ab723a 11-May-2009 Nathan Binkert <nate@binkert.org>

ruby: Import ruby and slicc from GEMS

We eventually plan to replace the m5 cache hierarchy with the GEMS
hierarchy, but for now we will make both live alongside eachother.


/gem5/src/mem/gems_common/Allocator.hh
/gem5/src/mem/gems_common/Map.hh
/gem5/src/mem/gems_common/PrioHeap.hh
/gem5/src/mem/gems_common/RefCnt.hh
/gem5/src/mem/gems_common/RefCnt_tester.cc
/gem5/src/mem/gems_common/RefCountable.hh
/gem5/src/mem/gems_common/Vector.hh
/gem5/src/mem/gems_common/calc_host.sh
/gem5/src/mem/gems_common/ioutil/attrlex.ll
/gem5/src/mem/gems_common/ioutil/attrparse.yy
/gem5/src/mem/gems_common/ioutil/confio.cc
/gem5/src/mem/gems_common/ioutil/confio.hh
/gem5/src/mem/gems_common/ioutil/embedtext.py
/gem5/src/mem/gems_common/ioutil/initvar.cc
/gem5/src/mem/gems_common/ioutil/initvar.hh
/gem5/src/mem/gems_common/ioutil/vardecl.hh
/gem5/src/mem/gems_common/std-includes.hh
/gem5/src/mem/gems_common/util.cc
/gem5/src/mem/gems_common/util.hh
/gem5/src/mem/protocol/LogTM.sm
/gem5/src/mem/protocol/MESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-mem.sm
/gem5/src/mem/protocol/MESI_CMP_directory-msg.sm
/gem5/src/mem/protocol/MESI_CMP_directory.slicc
/gem5/src/mem/protocol/MESI_CMP_filter_directory-L1cache.sm
/gem5/src/mem/protocol/MESI_CMP_filter_directory-L2cache.sm
/gem5/src/mem/protocol/MESI_CMP_filter_directory-mem.sm
/gem5/src/mem/protocol/MESI_CMP_filter_directory-msg.sm
/gem5/src/mem/protocol/MESI_CMP_filter_directory.slicc
/gem5/src/mem/protocol/MESI_CMP_filter_directory_m-mem.sm
/gem5/src/mem/protocol/MESI_CMP_filter_directory_m.slicc
/gem5/src/mem/protocol/MESI_SCMP_bankdirectory-L1cache.sm
/gem5/src/mem/protocol/MESI_SCMP_bankdirectory-L2cache.sm
/gem5/src/mem/protocol/MESI_SCMP_bankdirectory-mem.sm
/gem5/src/mem/protocol/MESI_SCMP_bankdirectory-msg.sm
/gem5/src/mem/protocol/MESI_SCMP_bankdirectory.slicc
/gem5/src/mem/protocol/MESI_SCMP_bankdirectory_m-mem.sm
/gem5/src/mem/protocol/MESI_SCMP_bankdirectory_m.slicc
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MI_example-msg.sm
/gem5/src/mem/protocol/MI_example.slicc
/gem5/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-msg.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-perfectDir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory.slicc
/gem5/src/mem/protocol/MOESI_CMP_directory_m-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory_m.slicc
/gem5/src/mem/protocol/MOESI_CMP_token-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_token-msg.sm
/gem5/src/mem/protocol/MOESI_CMP_token.slicc
/gem5/src/mem/protocol/MOESI_SMP_directory-cache.sm
/gem5/src/mem/protocol/MOESI_SMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_SMP_directory-msg.sm
/gem5/src/mem/protocol/MOESI_SMP_directory.slicc
/gem5/src/mem/protocol/MOESI_SMP_token-cache.sm
/gem5/src/mem/protocol/MOESI_SMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_SMP_token-msg.sm
/gem5/src/mem/protocol/MOESI_SMP_token.slicc
/gem5/src/mem/protocol/MOSI_SMP_bcast-cache.sm
/gem5/src/mem/protocol/MOSI_SMP_bcast-dir.sm
/gem5/src/mem/protocol/MOSI_SMP_bcast-msg.sm
/gem5/src/mem/protocol/MOSI_SMP_bcast.slicc
/gem5/src/mem/protocol/MOSI_SMP_bcast_1level-cache.sm
/gem5/src/mem/protocol/MOSI_SMP_bcast_1level.slicc
/gem5/src/mem/protocol/MOSI_SMP_bcast_m-dir.sm
/gem5/src/mem/protocol/MOSI_SMP_bcast_m.slicc
/gem5/src/mem/protocol/MOSI_SMP_directory_1level-cache.sm
/gem5/src/mem/protocol/MOSI_SMP_directory_1level-dir.sm
/gem5/src/mem/protocol/MOSI_SMP_directory_1level-msg.sm
/gem5/src/mem/protocol/MOSI_SMP_directory_1level.slicc
/gem5/src/mem/protocol/MSI_MOSI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MSI_MOSI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MSI_MOSI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MSI_MOSI_CMP_directory-msg.sm
/gem5/src/mem/protocol/MSI_MOSI_CMP_directory.slicc
/gem5/src/mem/protocol/RubySlicc_ComponentMapping.sm
/gem5/src/mem/protocol/RubySlicc_Defines.sm
/gem5/src/mem/protocol/RubySlicc_Exports.sm
/gem5/src/mem/protocol/RubySlicc_MemControl.sm
/gem5/src/mem/protocol/RubySlicc_Profiler.sm
/gem5/src/mem/protocol/RubySlicc_Types.sm
/gem5/src/mem/protocol/RubySlicc_Util.sm
/gem5/src/mem/protocol/RubySlicc_interfaces.slicc
/gem5/src/mem/protocol/doc/MSI_MOSI_CMP_directory_2level-protocol-description.txt
/gem5/src/mem/protocol/doc/MSI_dir_L1_MOSI_dir_L2_SNUCA_CMP-protocol-description.txt
/gem5/src/mem/protocol/standard_1level_SMP-protocol.sm
/gem5/src/mem/protocol/standard_CMP-protocol.sm
/gem5/src/mem/protocol/standard_SMP-protocol.sm
/gem5/src/mem/ruby/Decomissioning_note
/gem5/src/mem/ruby/FakeSimicsDataTypes.hh
/gem5/src/mem/ruby/README.debugging
/gem5/src/mem/ruby/buffers/MessageBuffer.cc
/gem5/src/mem/ruby/buffers/MessageBuffer.hh
/gem5/src/mem/ruby/buffers/MessageBufferNode.cc
/gem5/src/mem/ruby/buffers/MessageBufferNode.hh
/gem5/src/mem/ruby/common/Address.cc
/gem5/src/mem/ruby/common/Address.hh
/gem5/src/mem/ruby/common/BigSet.cc
/gem5/src/mem/ruby/common/BigSet.hh
/gem5/src/mem/ruby/common/Consumer.hh
/gem5/src/mem/ruby/common/DataBlock.cc
/gem5/src/mem/ruby/common/DataBlock.hh
/gem5/src/mem/ruby/common/Debug.cc
/gem5/src/mem/ruby/common/Debug.def
/gem5/src/mem/ruby/common/Debug.hh
/gem5/src/mem/ruby/common/Driver.cc
/gem5/src/mem/ruby/common/Driver.hh
/gem5/src/mem/ruby/common/Global.cc
/gem5/src/mem/ruby/common/Global.hh
/gem5/src/mem/ruby/common/Histogram.cc
/gem5/src/mem/ruby/common/Histogram.hh
/gem5/src/mem/ruby/common/Message.cc
/gem5/src/mem/ruby/common/NetDest.cc
/gem5/src/mem/ruby/common/NetDest.hh
/gem5/src/mem/ruby/common/OptBigSet.cc
/gem5/src/mem/ruby/common/OptBigSet.hh
/gem5/src/mem/ruby/common/Set.cc
/gem5/src/mem/ruby/common/Set.hh
/gem5/src/mem/ruby/common/SubBlock.cc
/gem5/src/mem/ruby/common/SubBlock.hh
/gem5/src/mem/ruby/config/RubyConfig.cc
/gem5/src/mem/ruby/config/RubyConfig.hh
/gem5/src/mem/ruby/config/config.include
/gem5/src/mem/ruby/config/rubyconfig.defaults
/gem5/src/mem/ruby/config/tester.defaults
/gem5/src/mem/ruby/eventqueue/EventQueue.cc
/gem5/src/mem/ruby/eventqueue/EventQueue.hh
/gem5/src/mem/ruby/eventqueue/EventQueueNode.cc
/gem5/src/mem/ruby/eventqueue/EventQueueNode.hh
/gem5/src/mem/ruby/eventqueue/EventQueue_tester.cc
/gem5/src/mem/ruby/init.cc
/gem5/src/mem/ruby/init.hh
/gem5/src/mem/ruby/interfaces/OpalInterface.cc
/gem5/src/mem/ruby/interfaces/OpalInterface.hh
/gem5/src/mem/ruby/interfaces/mf_api.hh
/gem5/src/mem/ruby/network/Network.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/CreditLink_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/GarnetNetwork_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/GarnetNetwork_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/InputUnit_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/InputUnit_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/NetworkHeader.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/NetworkInterface_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/NetworkLink_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/NetworkLink_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/OutVcState_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/OutVcState_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/OutputUnit_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/OutputUnit_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/Router_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/Router_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/RoutingUnit_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/RoutingUnit_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/SWallocator_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/SWallocator_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/Switch_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/Switch_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/VCallocator_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/VCallocator_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/VirtualChannel_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/VirtualChannel_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/flitBuffer_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/flitBuffer_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/flit_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/flit_d.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/FlexibleConsumer.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/GarnetNetwork.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/GarnetNetwork.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/InVcState.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/InVcState.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkConfig.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkInterface.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkInterface.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkLink.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkLink.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/OutVcState.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/OutVcState.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/Router.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/Router.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/VCarbiter.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/VCarbiter.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/flit.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/flit.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/flitBuffer.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/flitBuffer.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/netconfig.defaults
/gem5/src/mem/ruby/network/orion/NetworkPower.cc
/gem5/src/mem/ruby/network/orion/NetworkPower.hh
/gem5/src/mem/ruby/network/orion/SIM_port.hh
/gem5/src/mem/ruby/network/orion/SIM_power.hh
/gem5/src/mem/ruby/network/orion/SIM_power_test.hh
/gem5/src/mem/ruby/network/orion/parm_technology.hh
/gem5/src/mem/ruby/network/orion/power_arbiter.cc
/gem5/src/mem/ruby/network/orion/power_arbiter.hh
/gem5/src/mem/ruby/network/orion/power_array.cc
/gem5/src/mem/ruby/network/orion/power_array.hh
/gem5/src/mem/ruby/network/orion/power_bus.cc
/gem5/src/mem/ruby/network/orion/power_bus.hh
/gem5/src/mem/ruby/network/orion/power_crossbar.cc
/gem5/src/mem/ruby/network/orion/power_crossbar.hh
/gem5/src/mem/ruby/network/orion/power_ll.cc
/gem5/src/mem/ruby/network/orion/power_ll.hh
/gem5/src/mem/ruby/network/orion/power_router_init.cc
/gem5/src/mem/ruby/network/orion/power_router_init.hh
/gem5/src/mem/ruby/network/orion/power_static.cc
/gem5/src/mem/ruby/network/orion/power_static.hh
/gem5/src/mem/ruby/network/orion/power_utils.cc
/gem5/src/mem/ruby/network/orion/power_utils.hh
/gem5/src/mem/ruby/network/simple/Network_Files/GarnetFileMaker.py
/gem5/src/mem/ruby/network/simple/Network_Files/NUCA_Procs-16_ProcsPerChip-16_L2Banks-16_Memories-16.txt
/gem5/src/mem/ruby/network/simple/Network_Files/NUCA_Procs-16_ProcsPerChip-16_L2Banks-16_Memories-4.txt
/gem5/src/mem/ruby/network/simple/Network_Files/NUCA_Procs-16_ProcsPerChip-16_L2Banks-16_Memories-8.txt
/gem5/src/mem/ruby/network/simple/Network_Files/NUCA_Procs-16_ProcsPerChip-1_L2Banks-16_Memories-16.txt
/gem5/src/mem/ruby/network/simple/Network_Files/NUCA_Procs-16_ProcsPerChip-4_L2Banks-16_Memories-16.txt
/gem5/src/mem/ruby/network/simple/Network_Files/NUCA_Procs-16_ProcsPerChip-4_L2Banks-16_Memories-4.txt
/gem5/src/mem/ruby/network/simple/Network_Files/NUCA_Procs-16_ProcsPerChip-4_L2Banks-32_Memories-4.txt
/gem5/src/mem/ruby/network/simple/Network_Files/NUCA_Procs-16_ProcsPerChip-4_L2Banks-4_Memories-16.txt
/gem5/src/mem/ruby/network/simple/Network_Files/NUCA_Procs-16_ProcsPerChip-4_L2Banks-4_Memories-4.txt
/gem5/src/mem/ruby/network/simple/Network_Files/NUCA_Procs-1_ProcsPerChip-1_L2Banks-1_Memories-1.txt
/gem5/src/mem/ruby/network/simple/Network_Files/NUCA_Procs-1_ProcsPerChip-1_L2Banks-256_Memories-1.txt
/gem5/src/mem/ruby/network/simple/Network_Files/NUCA_Procs-1_ProcsPerChip-1_L2Banks-32_Memories-1.txt
/gem5/src/mem/ruby/network/simple/Network_Files/NUCA_Procs-1_ProcsPerChip-1_L2Banks-64_Memories-1.txt
/gem5/src/mem/ruby/network/simple/Network_Files/NUCA_Procs-2_ProcsPerChip-1_L2Banks-2_Memories-2.txt
/gem5/src/mem/ruby/network/simple/Network_Files/NUCA_Procs-2_ProcsPerChip-2_L2Banks-2_Memories-2.txt
/gem5/src/mem/ruby/network/simple/Network_Files/NUCA_Procs-32_ProcsPerChip-32_L2Banks-32_Memories-16.txt
/gem5/src/mem/ruby/network/simple/Network_Files/NUCA_Procs-32_ProcsPerChip-32_L2Banks-32_Memories-4.txt
/gem5/src/mem/ruby/network/simple/Network_Files/NUCA_Procs-4_ProcsPerChip-1_L2Banks-4_Memories-4.txt
/gem5/src/mem/ruby/network/simple/Network_Files/NUCA_Procs-4_ProcsPerChip-4_L2Banks-4_Memories-4.txt
/gem5/src/mem/ruby/network/simple/Network_Files/NUCA_Procs-7_ProcsPerChip-7_L2Banks-7_Memories-7.txt
/gem5/src/mem/ruby/network/simple/Network_Files/NUCA_Procs-8_ProcsPerChip-1_L2Banks-8_Memories-8.txt
/gem5/src/mem/ruby/network/simple/Network_Files/NUCA_Procs-8_ProcsPerChip-4_L2Banks-8_Memories-8.txt
/gem5/src/mem/ruby/network/simple/Network_Files/NUCA_Procs-8_ProcsPerChip-8_L2Banks-256_Memories-8.txt
/gem5/src/mem/ruby/network/simple/Network_Files/NUCA_Procs-8_ProcsPerChip-8_L2Banks-8_Memories-8.txt
/gem5/src/mem/ruby/network/simple/Network_Files/NetworkFileMaker.py
/gem5/src/mem/ruby/network/simple/Network_Files/TLC_Procs-8_ProcsPerChip-8_L2Banks-256_Memories-8.txt
/gem5/src/mem/ruby/network/simple/Network_Files/TOKEN_CMP_Procs-16_ProcsPerChip-16_L2Banks-16_Memories-16.txt
/gem5/src/mem/ruby/network/simple/Network_Files/TOKEN_CMP_Procs-16_ProcsPerChip-4_L2Banks-16_Memories-16.txt
/gem5/src/mem/ruby/network/simple/PerfectSwitch.cc
/gem5/src/mem/ruby/network/simple/PerfectSwitch.hh
/gem5/src/mem/ruby/network/simple/SimpleNetwork.cc
/gem5/src/mem/ruby/network/simple/SimpleNetwork.hh
/gem5/src/mem/ruby/network/simple/Switch.cc
/gem5/src/mem/ruby/network/simple/Switch.hh
/gem5/src/mem/ruby/network/simple/Throttle.cc
/gem5/src/mem/ruby/network/simple/Throttle.hh
/gem5/src/mem/ruby/network/simple/Topology.cc
/gem5/src/mem/ruby/network/simple/Topology.hh
/gem5/src/mem/ruby/profiler/AccessTraceForAddress.cc
/gem5/src/mem/ruby/profiler/AccessTraceForAddress.hh
/gem5/src/mem/ruby/profiler/AddressProfiler.cc
/gem5/src/mem/ruby/profiler/AddressProfiler.hh
/gem5/src/mem/ruby/profiler/CacheProfiler.cc
/gem5/src/mem/ruby/profiler/CacheProfiler.hh
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/profiler/StoreTrace.cc
/gem5/src/mem/ruby/profiler/StoreTrace.hh
/gem5/src/mem/ruby/profiler/XactProfiler.cc
/gem5/src/mem/ruby/profiler/XactProfiler.hh
/gem5/src/mem/ruby/recorder/CacheRecorder.cc
/gem5/src/mem/ruby/recorder/CacheRecorder.hh
/gem5/src/mem/ruby/recorder/TraceRecord.cc
/gem5/src/mem/ruby/recorder/TraceRecord.hh
/gem5/src/mem/ruby/recorder/Tracer.cc
/gem5/src/mem/ruby/recorder/Tracer.hh
/gem5/src/mem/ruby/simics/commands.cc
/gem5/src/mem/ruby/simics/commands.hh
/gem5/src/mem/ruby/simics/interface.cc
/gem5/src/mem/ruby/simics/interface.hh
/gem5/src/mem/ruby/simics/simics_api_dummy.c
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
/gem5/src/mem/ruby/slicc_interface/AbstractChip.cc
/gem5/src/mem/ruby/slicc_interface/AbstractChip.hh
/gem5/src/mem/ruby/slicc_interface/AbstractProtocol.hh
/gem5/src/mem/ruby/slicc_interface/Message.hh
/gem5/src/mem/ruby/slicc_interface/NetworkMessage.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.cc
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_includes.hh
/gem5/src/mem/ruby/system/AbstractBloomFilter.hh
/gem5/src/mem/ruby/system/AbstractMemOrCache.hh
/gem5/src/mem/ruby/system/AbstractReplacementPolicy.hh
/gem5/src/mem/ruby/system/BlockBloomFilter.cc
/gem5/src/mem/ruby/system/BlockBloomFilter.hh
/gem5/src/mem/ruby/system/BulkBloomFilter.cc
/gem5/src/mem/ruby/system/BulkBloomFilter.hh
/gem5/src/mem/ruby/system/CacheMemory.hh
/gem5/src/mem/ruby/system/DirectoryMemory.cc
/gem5/src/mem/ruby/system/DirectoryMemory.hh
/gem5/src/mem/ruby/system/GenericBloomFilter.cc
/gem5/src/mem/ruby/system/GenericBloomFilter.hh
/gem5/src/mem/ruby/system/H3BloomFilter.cc
/gem5/src/mem/ruby/system/H3BloomFilter.hh
/gem5/src/mem/ruby/system/LRUPolicy.hh
/gem5/src/mem/ruby/system/LSB_CountingBloomFilter.cc
/gem5/src/mem/ruby/system/LSB_CountingBloomFilter.hh
/gem5/src/mem/ruby/system/MachineID.hh
/gem5/src/mem/ruby/system/MemoryControl.cc
/gem5/src/mem/ruby/system/MemoryControl.hh
/gem5/src/mem/ruby/system/MemoryNode.cc
/gem5/src/mem/ruby/system/MemoryNode.hh
/gem5/src/mem/ruby/system/MultiBitSelBloomFilter.cc
/gem5/src/mem/ruby/system/MultiBitSelBloomFilter.hh
/gem5/src/mem/ruby/system/MultiGrainBloomFilter.cc
/gem5/src/mem/ruby/system/MultiGrainBloomFilter.hh
/gem5/src/mem/ruby/system/NodeID.hh
/gem5/src/mem/ruby/system/NodePersistentTable.cc
/gem5/src/mem/ruby/system/NodePersistentTable.hh
/gem5/src/mem/ruby/system/NonCountingBloomFilter.cc
/gem5/src/mem/ruby/system/NonCountingBloomFilter.hh
/gem5/src/mem/ruby/system/PerfectCacheMemory.hh
/gem5/src/mem/ruby/system/PersistentArbiter.cc
/gem5/src/mem/ruby/system/PersistentArbiter.hh
/gem5/src/mem/ruby/system/PersistentTable.cc
/gem5/src/mem/ruby/system/PersistentTable.hh
/gem5/src/mem/ruby/system/PseudoLRUPolicy.hh
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/Sequencer.hh
/gem5/src/mem/ruby/system/StoreBuffer.cc
/gem5/src/mem/ruby/system/StoreBuffer.hh
/gem5/src/mem/ruby/system/StoreCache.cc
/gem5/src/mem/ruby/system/StoreCache.hh
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/ruby/system/System.hh
/gem5/src/mem/ruby/system/TBETable.hh
/gem5/src/mem/ruby/system/TimerTable.cc
/gem5/src/mem/ruby/system/TimerTable.hh
/gem5/src/mem/ruby/tester/BarrierGenerator.cc
/gem5/src/mem/ruby/tester/BarrierGenerator.hh
/gem5/src/mem/ruby/tester/Check.cc
/gem5/src/mem/ruby/tester/Check.hh
/gem5/src/mem/ruby/tester/CheckTable.cc
/gem5/src/mem/ruby/tester/CheckTable.hh
/gem5/src/mem/ruby/tester/DetermGETXGenerator.cc
/gem5/src/mem/ruby/tester/DetermGETXGenerator.hh
/gem5/src/mem/ruby/tester/DetermInvGenerator.cc
/gem5/src/mem/ruby/tester/DetermInvGenerator.hh
/gem5/src/mem/ruby/tester/DetermSeriesGETSGenerator.cc
/gem5/src/mem/ruby/tester/DetermSeriesGETSGenerator.hh
/gem5/src/mem/ruby/tester/DeterministicDriver.cc
/gem5/src/mem/ruby/tester/DeterministicDriver.hh
/gem5/src/mem/ruby/tester/Instruction.cc
/gem5/src/mem/ruby/tester/Instruction.hh
/gem5/src/mem/ruby/tester/RaceyDriver.cc
/gem5/src/mem/ruby/tester/RaceyDriver.hh
/gem5/src/mem/ruby/tester/RequestGenerator.cc
/gem5/src/mem/ruby/tester/RequestGenerator.hh
/gem5/src/mem/ruby/tester/SpecifiedGenerator.cc
/gem5/src/mem/ruby/tester/SpecifiedGenerator.hh
/gem5/src/mem/ruby/tester/SyntheticDriver.cc
/gem5/src/mem/ruby/tester/SyntheticDriver.hh
/gem5/src/mem/ruby/tester/Tester.cc
/gem5/src/mem/ruby/tester/Tester.hh
/gem5/src/mem/ruby/tester/XactAbortRequestGenerator.cc
/gem5/src/mem/ruby/tester/XactAbortRequestGenerator.hh
/gem5/src/mem/ruby/tester/XactRequestGenerator.cc
/gem5/src/mem/ruby/tester/XactRequestGenerator.hh
/gem5/src/mem/ruby/tester/main.cc
/gem5/src/mem/ruby/tester/main.hh
/gem5/src/mem/ruby/tester/test_framework.cc
/gem5/src/mem/ruby/tester/test_framework.hh
README
ast/AST.cc
ast/AST.hh
ast/ASTs.hh
ast/ActionDeclAST.cc
ast/ActionDeclAST.hh
ast/AssignStatementAST.cc
ast/AssignStatementAST.hh
ast/CheckAllocateStatementAST.cc
ast/CheckAllocateStatementAST.hh
ast/CheckStopSlotsStatementAST.cc
ast/CheckStopSlotsStatementAST.hh
ast/ChipComponentAccessAST.cc
ast/ChipComponentAccessAST.hh
ast/CopyHeadStatementAST.cc
ast/CopyHeadStatementAST.hh
ast/DeclAST.cc
ast/DeclAST.hh
ast/DeclListAST.cc
ast/DeclListAST.hh
ast/EnqueueStatementAST.cc
ast/EnqueueStatementAST.hh
ast/EnumDeclAST.cc
ast/EnumDeclAST.hh
ast/EnumExprAST.cc
ast/EnumExprAST.hh
ast/ExprAST.cc
ast/ExprAST.hh
ast/ExprStatementAST.cc
ast/ExprStatementAST.hh
ast/FormalParamAST.cc
ast/FormalParamAST.hh
ast/FuncCallExprAST.cc
ast/FuncCallExprAST.hh
ast/FuncDeclAST.cc
ast/FuncDeclAST.hh
ast/IfStatementAST.cc
ast/IfStatementAST.hh
ast/InPortDeclAST.cc
ast/InPortDeclAST.hh
ast/InfixOperatorExprAST.cc
ast/InfixOperatorExprAST.hh
ast/LiteralExprAST.cc
ast/LiteralExprAST.hh
ast/Location.cc
ast/Location.hh
ast/MachineAST.cc
ast/MachineAST.hh
ast/MemberExprAST.cc
ast/MemberExprAST.hh
ast/MethodCallExprAST.cc
ast/MethodCallExprAST.hh
ast/ObjDeclAST.cc
ast/ObjDeclAST.hh
ast/OutPortDeclAST.cc
ast/OutPortDeclAST.hh
ast/PairAST.cc
ast/PairAST.hh
ast/PairListAST.cc
ast/PairListAST.hh
ast/PeekStatementAST.cc
ast/PeekStatementAST.hh
ast/ReturnStatementAST.cc
ast/ReturnStatementAST.hh
ast/StatementAST.cc
ast/StatementAST.hh
ast/StatementListAST.cc
ast/StatementListAST.hh
ast/TransitionDeclAST.cc
ast/TransitionDeclAST.hh
ast/TypeAST.cc
ast/TypeAST.hh
ast/TypeDeclAST.cc
ast/TypeDeclAST.hh
ast/TypeFieldAST.cc
ast/TypeFieldAST.hh
ast/TypeFieldEnumAST.cc
ast/TypeFieldEnumAST.hh
ast/TypeFieldMemberAST.cc
ast/TypeFieldMemberAST.hh
ast/TypeFieldMethodAST.cc
ast/TypeFieldMethodAST.hh
ast/VarExprAST.cc
ast/VarExprAST.hh
doc/SLICC_V03.txt
doc/tutorial.tex
generator/fileio.cc
generator/fileio.hh
generator/html_gen.cc
generator/html_gen.hh
generator/mif_gen.cc
generator/mif_gen.hh
main.cc
main.hh
parser/lexer.ll
parser/parser.yy
slicc_global.hh
symbols/Action.hh
symbols/Event.hh
symbols/Func.cc
symbols/Func.hh
symbols/State.hh
symbols/StateMachine.cc
symbols/StateMachine.hh
symbols/Symbol.cc
symbols/Symbol.hh
symbols/SymbolTable.cc
symbols/SymbolTable.hh
symbols/Transition.cc
symbols/Transition.hh
symbols/Type.cc
symbols/Type.hh
symbols/Var.cc
symbols/Var.hh