History log of /gem5/src/mem/ruby/network/
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14217:68c3d00f780a 26-Aug-2019 Srikant Bharadwaj <srikant.bharadwaj@amd.com>

ruby: Fix the way stall map size is checked for availability

To ensure that enqueuer observes the practical availability. We
check the message buffer queue size at the start of the cycle.
We also add the size of the stall queue to consider the total
queue size. However, messages can be moved from regular queue
to stall map. This leads to messages being considered twice leading
to false flow control. This patch fixes it by storing the stall map
size at the beginning of the cycle and considering it for checking
availability.

Change-Id: I6ea94f34fe5279b91f74e106d43263e55ec4bf06
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20389
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

14184:11ac1337c5e2 16-Aug-2019 Gabe Black <gabeblack@google.com>

mem: Move ruby protocols into a directory called ruby_protocol.

Now that the gem5 protocols are split out, it would be nice to put them
in their own protocol directory. It's also confusing to have files
called *_protocol which are not in the protocol directory.

Change-Id: I7475ee111630050a2421816dfd290921baab9f71
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20230
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>


/gem5/src/cpu/testers/directedtest/InvalidateGenerator.hh
/gem5/src/cpu/testers/directedtest/SeriesRequestGenerator.hh
/gem5/src/cpu/testers/rubytest/Check.hh
/gem5/src/learning_gem5/part3/MSI-cache.sm
/gem5/src/learning_gem5/part3/SConsopts
/gem5/src/mem/protocol/GPU_RfO-SQC.sm
/gem5/src/mem/protocol/GPU_RfO-TCC.sm
/gem5/src/mem/protocol/GPU_RfO-TCCdir.sm
/gem5/src/mem/protocol/GPU_RfO-TCP.sm
/gem5/src/mem/protocol/GPU_RfO.slicc
/gem5/src/mem/protocol/GPU_VIPER-SQC.sm
/gem5/src/mem/protocol/GPU_VIPER-TCC.sm
/gem5/src/mem/protocol/GPU_VIPER-TCP.sm
/gem5/src/mem/protocol/GPU_VIPER.slicc
/gem5/src/mem/protocol/GPU_VIPER_Baseline.slicc
/gem5/src/mem/protocol/GPU_VIPER_Region-TCC.sm
/gem5/src/mem/protocol/GPU_VIPER_Region.slicc
/gem5/src/mem/protocol/Garnet_standalone-cache.sm
/gem5/src/mem/protocol/Garnet_standalone-dir.sm
/gem5/src/mem/protocol/Garnet_standalone-msg.sm
/gem5/src/mem/protocol/Garnet_standalone.slicc
/gem5/src/mem/protocol/MESI_Three_Level-L0cache.sm
/gem5/src/mem/protocol/MESI_Three_Level-L1cache.sm
/gem5/src/mem/protocol/MESI_Three_Level-msg.sm
/gem5/src/mem/protocol/MESI_Three_Level.slicc
/gem5/src/mem/protocol/MESI_Two_Level-L1cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-L2cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-dir.sm
/gem5/src/mem/protocol/MESI_Two_Level-dma.sm
/gem5/src/mem/protocol/MESI_Two_Level-msg.sm
/gem5/src/mem/protocol/MESI_Two_Level.slicc
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MI_example-dma.sm
/gem5/src/mem/protocol/MI_example-msg.sm
/gem5/src/mem/protocol/MI_example.slicc
/gem5/src/mem/protocol/MOESI_AMD_Base-CorePair.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-L3cache.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-Region-CorePair.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-Region-dir.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-Region-msg.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-RegionBuffer.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-RegionDir.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-dir.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-msg.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-probeFilter.sm
/gem5/src/mem/protocol/MOESI_AMD_Base.slicc
/gem5/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-msg.sm
/gem5/src/mem/protocol/MOESI_CMP_directory.slicc
/gem5/src/mem/protocol/MOESI_CMP_token-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_token-msg.sm
/gem5/src/mem/protocol/MOESI_CMP_token.slicc
/gem5/src/mem/protocol/MOESI_hammer-cache.sm
/gem5/src/mem/protocol/MOESI_hammer-dir.sm
/gem5/src/mem/protocol/MOESI_hammer-dma.sm
/gem5/src/mem/protocol/MOESI_hammer-msg.sm
/gem5/src/mem/protocol/MOESI_hammer.slicc
/gem5/src/mem/protocol/RubySlicc_ComponentMapping.sm
/gem5/src/mem/protocol/RubySlicc_Defines.sm
/gem5/src/mem/protocol/RubySlicc_Exports.sm
/gem5/src/mem/protocol/RubySlicc_MemControl.sm
/gem5/src/mem/protocol/RubySlicc_Types.sm
/gem5/src/mem/protocol/RubySlicc_Util.sm
/gem5/src/mem/protocol/RubySlicc_interfaces.slicc
/gem5/src/mem/protocol/SConscript
/gem5/src/mem/protocol/SConsopts
/gem5/src/mem/ruby/SConscript
/gem5/src/mem/ruby/common/MachineID.hh
Network.hh
Topology.hh
simple/Switch.hh
/gem5/src/mem/ruby/profiler/AccessTraceForAddress.hh
/gem5/src/mem/ruby/profiler/AddressProfiler.cc
/gem5/src/mem/ruby/profiler/AddressProfiler.hh
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/protocol/GPU_RfO-SQC.sm
/gem5/src/mem/ruby/protocol/GPU_RfO-TCC.sm
/gem5/src/mem/ruby/protocol/GPU_RfO-TCCdir.sm
/gem5/src/mem/ruby/protocol/GPU_RfO-TCP.sm
/gem5/src/mem/ruby/protocol/GPU_RfO.slicc
/gem5/src/mem/ruby/protocol/GPU_VIPER-SQC.sm
/gem5/src/mem/ruby/protocol/GPU_VIPER-TCC.sm
/gem5/src/mem/ruby/protocol/GPU_VIPER-TCP.sm
/gem5/src/mem/ruby/protocol/GPU_VIPER.slicc
/gem5/src/mem/ruby/protocol/GPU_VIPER_Baseline.slicc
/gem5/src/mem/ruby/protocol/GPU_VIPER_Region-TCC.sm
/gem5/src/mem/ruby/protocol/GPU_VIPER_Region.slicc
/gem5/src/mem/ruby/protocol/Garnet_standalone-cache.sm
/gem5/src/mem/ruby/protocol/Garnet_standalone-dir.sm
/gem5/src/mem/ruby/protocol/Garnet_standalone-msg.sm
/gem5/src/mem/ruby/protocol/Garnet_standalone.slicc
/gem5/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
/gem5/src/mem/ruby/protocol/MESI_Three_Level-L1cache.sm
/gem5/src/mem/ruby/protocol/MESI_Three_Level-msg.sm
/gem5/src/mem/ruby/protocol/MESI_Three_Level.slicc
/gem5/src/mem/ruby/protocol/MESI_Two_Level-L1cache.sm
/gem5/src/mem/ruby/protocol/MESI_Two_Level-L2cache.sm
/gem5/src/mem/ruby/protocol/MESI_Two_Level-dir.sm
/gem5/src/mem/ruby/protocol/MESI_Two_Level-dma.sm
/gem5/src/mem/ruby/protocol/MESI_Two_Level-msg.sm
/gem5/src/mem/ruby/protocol/MESI_Two_Level.slicc
/gem5/src/mem/ruby/protocol/MI_example-cache.sm
/gem5/src/mem/ruby/protocol/MI_example-dir.sm
/gem5/src/mem/ruby/protocol/MI_example-dma.sm
/gem5/src/mem/ruby/protocol/MI_example-msg.sm
/gem5/src/mem/ruby/protocol/MI_example.slicc
/gem5/src/mem/ruby/protocol/MOESI_AMD_Base-CorePair.sm
/gem5/src/mem/ruby/protocol/MOESI_AMD_Base-L3cache.sm
/gem5/src/mem/ruby/protocol/MOESI_AMD_Base-Region-CorePair.sm
/gem5/src/mem/ruby/protocol/MOESI_AMD_Base-Region-dir.sm
/gem5/src/mem/ruby/protocol/MOESI_AMD_Base-Region-msg.sm
/gem5/src/mem/ruby/protocol/MOESI_AMD_Base-RegionBuffer.sm
/gem5/src/mem/ruby/protocol/MOESI_AMD_Base-RegionDir.sm
/gem5/src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm
/gem5/src/mem/ruby/protocol/MOESI_AMD_Base-msg.sm
/gem5/src/mem/ruby/protocol/MOESI_AMD_Base-probeFilter.sm
/gem5/src/mem/ruby/protocol/MOESI_AMD_Base.slicc
/gem5/src/mem/ruby/protocol/MOESI_CMP_directory-L1cache.sm
/gem5/src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/ruby/protocol/MOESI_CMP_directory-dma.sm
/gem5/src/mem/ruby/protocol/MOESI_CMP_directory-msg.sm
/gem5/src/mem/ruby/protocol/MOESI_CMP_directory.slicc
/gem5/src/mem/ruby/protocol/MOESI_CMP_token-L1cache.sm
/gem5/src/mem/ruby/protocol/MOESI_CMP_token-L2cache.sm
/gem5/src/mem/ruby/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/ruby/protocol/MOESI_CMP_token-dma.sm
/gem5/src/mem/ruby/protocol/MOESI_CMP_token-msg.sm
/gem5/src/mem/ruby/protocol/MOESI_CMP_token.slicc
/gem5/src/mem/ruby/protocol/MOESI_hammer-cache.sm
/gem5/src/mem/ruby/protocol/MOESI_hammer-dir.sm
/gem5/src/mem/ruby/protocol/MOESI_hammer-dma.sm
/gem5/src/mem/ruby/protocol/MOESI_hammer-msg.sm
/gem5/src/mem/ruby/protocol/MOESI_hammer.slicc
/gem5/src/mem/ruby/protocol/RubySlicc_ComponentMapping.sm
/gem5/src/mem/ruby/protocol/RubySlicc_Defines.sm
/gem5/src/mem/ruby/protocol/RubySlicc_Exports.sm
/gem5/src/mem/ruby/protocol/RubySlicc_MemControl.sm
/gem5/src/mem/ruby/protocol/RubySlicc_Types.sm
/gem5/src/mem/ruby/protocol/RubySlicc_Util.sm
/gem5/src/mem/ruby/protocol/RubySlicc_interfaces.slicc
/gem5/src/mem/ruby/protocol/SConscript
/gem5/src/mem/ruby/protocol/SConsopts
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
/gem5/src/mem/ruby/slicc_interface/AbstractController.cc
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/slicc_interface/AbstractEntry.hh
/gem5/src/mem/ruby/slicc_interface/Message.hh
/gem5/src/mem/ruby/slicc_interface/RubyRequest.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
/gem5/src/mem/ruby/structures/CacheMemory.cc
/gem5/src/mem/ruby/structures/CacheMemory.hh
/gem5/src/mem/ruby/structures/DirectoryMemory.hh
/gem5/src/mem/ruby/structures/PerfectCacheMemory.hh
/gem5/src/mem/ruby/structures/PersistentTable.hh
/gem5/src/mem/ruby/system/CacheRecorder.hh
/gem5/src/mem/ruby/system/DMASequencer.cc
/gem5/src/mem/ruby/system/DMASequencer.hh
/gem5/src/mem/ruby/system/GPUCoalescer.hh
/gem5/src/mem/ruby/system/RubyPort.cc
/gem5/src/mem/ruby/system/RubyPort.hh
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/Sequencer.hh
/gem5/src/mem/ruby/system/VIPERCoalescer.hh
/gem5/src/mem/slicc/main.py
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/mem/slicc/symbols/SymbolTable.py
/gem5/src/mem/slicc/symbols/Type.py
13973:2f953d25716b 25-Feb-2019 Tiago Muck <tiago.muck@arm.com>

mem-ruby: Do not change blocked msg enqueue info

Updating the message counter and enqueue times when adding blocked
messages back to the queue does not make a lot of sense since these
messages are not new arrivals.
More importantly, this may lead to starvation. See the scenario below:

1) Request A for a blocked line X arrives
2) A is handled; X is blocked so A is stalled
3) Request B for X arrives; Reponse for X arrives
4) Response is handled; X unblocked; A added back to the request queue
5) B is handled ahead of A (since A's arrival was updated);
X may become blocked again

If new requests keep comming for X, A may will be stalled forever.

Change-Id: Icad79f3f716a870e91cb3455437b8b3c35f130ac
Signed-off-by: Tiago Muck <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18412
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

13892:0182a0601f66 22-Apr-2019 Gabe Black <gabeblack@google.com>

mem: Minimize the use of MemObject.

MemObject doesn't provide anything beyond its base ClockedObject any
more, so this change removes it from most inheritance hierarchies.
Occasionally MemObject is replaced with SimObject when I was fairly
confident that the extra functionality of ClockedObject wasn't needed.

Change-Id: Ic014ab61e56402e62548e8c831eb16e26523fdce
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18289
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>


/gem5/src/arch/arm/ArmTLB.py
/gem5/src/arch/arm/table_walker.cc
/gem5/src/arch/arm/table_walker.hh
/gem5/src/arch/generic/BaseTLB.py
/gem5/src/arch/generic/tlb.hh
/gem5/src/arch/x86/X86TLB.py
/gem5/src/arch/x86/pagetable_walker.cc
/gem5/src/arch/x86/pagetable_walker.hh
/gem5/src/cpu/BaseCPU.py
/gem5/src/cpu/base.cc
/gem5/src/cpu/base.hh
/gem5/src/cpu/o3/checker.cc
/gem5/src/cpu/o3/cpu.hh
/gem5/src/cpu/simple/base.cc
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.cc
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.hh
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.py
/gem5/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc
/gem5/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh
/gem5/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.py
/gem5/src/cpu/testers/memtest/MemTest.py
/gem5/src/cpu/testers/memtest/memtest.cc
/gem5/src/cpu/testers/memtest/memtest.hh
/gem5/src/cpu/testers/rubytest/RubyTester.cc
/gem5/src/cpu/testers/rubytest/RubyTester.hh
/gem5/src/cpu/testers/rubytest/RubyTester.py
/gem5/src/cpu/testers/traffic_gen/BaseTrafficGen.py
/gem5/src/cpu/testers/traffic_gen/base.cc
/gem5/src/cpu/testers/traffic_gen/base.hh
/gem5/src/cpu/thread_state.hh
/gem5/src/dev/Device.py
/gem5/src/dev/dma_device.cc
/gem5/src/dev/dma_device.hh
/gem5/src/dev/io_device.cc
/gem5/src/dev/io_device.hh
/gem5/src/dev/x86/intdev.hh
/gem5/src/doc/memory_system.doxygen
/gem5/src/gpu-compute/GPU.py
/gem5/src/gpu-compute/LdsState.py
/gem5/src/gpu-compute/X86GPUTLB.py
/gem5/src/gpu-compute/compute_unit.cc
/gem5/src/gpu-compute/compute_unit.hh
/gem5/src/gpu-compute/gpu_tlb.cc
/gem5/src/gpu-compute/gpu_tlb.hh
/gem5/src/gpu-compute/lds_state.cc
/gem5/src/gpu-compute/lds_state.hh
/gem5/src/gpu-compute/tlb_coalescer.cc
/gem5/src/gpu-compute/tlb_coalescer.hh
/gem5/src/mem/AbstractMemory.py
/gem5/src/mem/AddrMapper.py
/gem5/src/mem/Bridge.py
/gem5/src/mem/CommMonitor.py
/gem5/src/mem/ExternalMaster.py
/gem5/src/mem/ExternalSlave.py
/gem5/src/mem/MemChecker.py
/gem5/src/mem/MemDelay.py
/gem5/src/mem/SerialLink.py
/gem5/src/mem/XBar.py
/gem5/src/mem/abstract_mem.cc
/gem5/src/mem/abstract_mem.hh
/gem5/src/mem/addr_mapper.cc
/gem5/src/mem/addr_mapper.hh
/gem5/src/mem/bridge.cc
/gem5/src/mem/bridge.hh
/gem5/src/mem/cache/Cache.py
/gem5/src/mem/cache/base.cc
/gem5/src/mem/cache/base.hh
/gem5/src/mem/comm_monitor.cc
/gem5/src/mem/comm_monitor.hh
/gem5/src/mem/dram_ctrl.cc
/gem5/src/mem/dramsim2.cc
/gem5/src/mem/external_master.cc
/gem5/src/mem/external_master.hh
/gem5/src/mem/external_slave.cc
/gem5/src/mem/external_slave.hh
/gem5/src/mem/mem_checker_monitor.cc
/gem5/src/mem/mem_checker_monitor.hh
/gem5/src/mem/mem_delay.cc
/gem5/src/mem/mem_delay.hh
/gem5/src/mem/mport.hh
/gem5/src/mem/packet.hh
/gem5/src/mem/port.cc
/gem5/src/mem/port.hh
/gem5/src/mem/qos/mem_sink.cc
/gem5/src/mem/qport.hh
dummy_port.hh
/gem5/src/mem/ruby/slicc_interface/AbstractController.cc
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/slicc_interface/Controller.py
/gem5/src/mem/ruby/system/RubyPort.cc
/gem5/src/mem/ruby/system/RubyPort.hh
/gem5/src/mem/ruby/system/Sequencer.py
/gem5/src/mem/ruby/system/WeightedLRUReplacementPolicy.py
/gem5/src/mem/serial_link.cc
/gem5/src/mem/serial_link.hh
/gem5/src/mem/simple_mem.cc
/gem5/src/mem/tport.cc
/gem5/src/mem/tport.hh
/gem5/src/mem/xbar.cc
/gem5/src/mem/xbar.hh
/gem5/src/python/m5/SimObject.py
/gem5/src/sim/System.py
/gem5/src/sim/cxx_manager.cc
/gem5/src/sim/system.cc
/gem5/src/sim/system.hh
13799:15badf7874ee 19-Mar-2019 Andrea Mondelli <Andrea.Mondelli@ucf.edu>

misc: missing override specifier

Missing specifier of overridden virtual function
declared in sim_object.hh

Removed redundant "virtual" keyword

Change-Id: I42aa3349b537c9e62607bce20cf1b3aabdb99bf2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17468
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

13784:1941dc118243 07-Mar-2019 Gabe Black <gabeblack@google.com>

arch, cpu, dev, gpu, mem, sim, python: start using getPort.

Replace the getMasterPort, getSlavePort, and getEthPort functions
with getPort, and remove extraneous mechanisms that are no longer
necessary.

Change-Id: Iab7e3c02d2f3a0cf33e7e824e18c28646b5bc318
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17040
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>


/gem5/src/arch/arm/table_walker.cc
/gem5/src/arch/arm/table_walker.hh
/gem5/src/arch/arm/tlb.cc
/gem5/src/arch/arm/tlb.hh
/gem5/src/arch/generic/tlb.hh
/gem5/src/arch/x86/interrupts.hh
/gem5/src/arch/x86/pagetable_walker.cc
/gem5/src/arch/x86/pagetable_walker.hh
/gem5/src/arch/x86/tlb.cc
/gem5/src/arch/x86/tlb.hh
/gem5/src/cpu/base.cc
/gem5/src/cpu/base.hh
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.cc
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.hh
/gem5/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc
/gem5/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh
/gem5/src/cpu/testers/memtest/memtest.cc
/gem5/src/cpu/testers/memtest/memtest.hh
/gem5/src/cpu/testers/rubytest/RubyTester.cc
/gem5/src/cpu/testers/rubytest/RubyTester.hh
/gem5/src/cpu/testers/traffic_gen/base.cc
/gem5/src/cpu/testers/traffic_gen/base.hh
/gem5/src/cpu/trace/trace_cpu.cc
/gem5/src/dev/dma_device.cc
/gem5/src/dev/dma_device.hh
/gem5/src/dev/io_device.cc
/gem5/src/dev/io_device.hh
/gem5/src/dev/net/Ethernet.py
/gem5/src/dev/net/SConscript
/gem5/src/dev/net/dist_etherlink.cc
/gem5/src/dev/net/dist_etherlink.hh
/gem5/src/dev/net/etherbus.cc
/gem5/src/dev/net/etherbus.hh
/gem5/src/dev/net/etherdevice.hh
/gem5/src/dev/net/etherlink.cc
/gem5/src/dev/net/etherlink.hh
/gem5/src/dev/net/etherobject.hh
/gem5/src/dev/net/etherswitch.cc
/gem5/src/dev/net/etherswitch.hh
/gem5/src/dev/net/ethertap.cc
/gem5/src/dev/net/ethertap.hh
/gem5/src/dev/net/i8254xGBe.cc
/gem5/src/dev/net/i8254xGBe.hh
/gem5/src/dev/net/ns_gige.cc
/gem5/src/dev/net/ns_gige.hh
/gem5/src/dev/net/python.cc
/gem5/src/dev/net/sinic.cc
/gem5/src/dev/net/sinic.hh
/gem5/src/dev/pci/copy_engine.cc
/gem5/src/dev/pci/copy_engine.hh
/gem5/src/dev/x86/i82094aa.cc
/gem5/src/dev/x86/i82094aa.hh
/gem5/src/gpu-compute/compute_unit.hh
/gem5/src/gpu-compute/dispatcher.cc
/gem5/src/gpu-compute/dispatcher.hh
/gem5/src/gpu-compute/gpu_tlb.cc
/gem5/src/gpu-compute/gpu_tlb.hh
/gem5/src/gpu-compute/lds_state.hh
/gem5/src/gpu-compute/tlb_coalescer.cc
/gem5/src/gpu-compute/tlb_coalescer.hh
/gem5/src/learning_gem5/part2/simple_cache.cc
/gem5/src/learning_gem5/part2/simple_cache.hh
/gem5/src/learning_gem5/part2/simple_memobj.cc
/gem5/src/learning_gem5/part2/simple_memobj.hh
/gem5/src/mem/addr_mapper.cc
/gem5/src/mem/addr_mapper.hh
/gem5/src/mem/bridge.cc
/gem5/src/mem/bridge.hh
/gem5/src/mem/cache/base.cc
/gem5/src/mem/cache/base.hh
/gem5/src/mem/comm_monitor.cc
/gem5/src/mem/comm_monitor.hh
/gem5/src/mem/dram_ctrl.cc
/gem5/src/mem/dram_ctrl.hh
/gem5/src/mem/dramsim2.cc
/gem5/src/mem/dramsim2.hh
/gem5/src/mem/external_master.cc
/gem5/src/mem/external_master.hh
/gem5/src/mem/external_slave.cc
/gem5/src/mem/external_slave.hh
/gem5/src/mem/mem_checker_monitor.cc
/gem5/src/mem/mem_checker_monitor.hh
/gem5/src/mem/mem_delay.cc
/gem5/src/mem/mem_delay.hh
/gem5/src/mem/mem_object.cc
/gem5/src/mem/mem_object.hh
/gem5/src/mem/qos/mem_sink.cc
/gem5/src/mem/qos/mem_sink.hh
MessageBuffer.hh
Network.hh
dummy_port.hh
/gem5/src/mem/ruby/slicc_interface/AbstractController.cc
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/system/RubyPort.cc
/gem5/src/mem/ruby/system/RubyPort.hh
/gem5/src/mem/serial_link.cc
/gem5/src/mem/serial_link.hh
/gem5/src/mem/simple_mem.cc
/gem5/src/mem/simple_mem.hh
/gem5/src/mem/xbar.cc
/gem5/src/mem/xbar.hh
/gem5/src/python/SConscript
/gem5/src/python/pybind11/pybind.hh
/gem5/src/python/pybind11/pyobject.cc
/gem5/src/sim/SConscript
/gem5/src/sim/cxx_manager.cc
/gem5/src/sim/init.cc
/gem5/src/sim/python.cc
/gem5/src/sim/system.cc
/gem5/src/sim/system.hh
13773:fc2f9a60cb2d 14-Mar-2019 Ryan Gambord <gambordr@oregonstate.edu>

mem: Removed circular include ref

If BasicLink.hh is modified, the style checker forces a reordering of
the includes, which results in build errors because it ends up including
Topology.hh before including its xxxParams.hh files, which include
forward declarations of the BasicLink family of classes, and so
Topology.hh throws errors that BasicLink etc. are not declared.

Change-Id: I664a0652e53f0cc61763c2190a980c655b85d397
Signed-off-by: Ryan Gambord <gambordr@oregonstate.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17270
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

13736:e678df1f0bf2 22-Feb-2019 Srikant Bharadwaj <srikant.bharadwaj@amd.com>

ruby: Fix garnet's round robin arbitration for vc selection

Garnet utilizes round robin policy to select a VC for
transmission ar Network Interface and Routers. The current logic
for round robin is only fair if all the virtual networks are active
at a given router. If the router or network interface is not
receiving traffic in from any vnet then the priority is always taken
up by the next vnet in numerically (or loops back to 0).

This fix changes the way we perform round robin arbitration. When
a VC is selected in a cycle, the round robin pointer is set to the VC
next to it and is iterated from there on. If any VC does not have a
flit in a given cycle, it will lose its turn until the next round.
At maximum traffic this will model round robin correctly even if
a certain VNET is not active at that unit.

Change-Id: I9bf805221054f9f25bee14b57ff521f4ce4ca980
Reviewed-on: https://gem5-review.googlesource.com/c/16688
Reviewed-by: Jieming Yin <Jieming.Yin@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

13709:dd6b7ac5801f 26-Jan-2019 Andreas Sandberg <andreas.sandberg@arm.com>

python: Make iterator handling Python 3 compatible

Many functions that used to return lists (e.g., dict.items()) now
return iterators and their iterator counterparts (e.g.,
dict.iteritems()) have been removed. Switch calls to the Python 2.7
iterator methods to use the Python 3 equivalent and add explicit list
conversions where necessary.

Change-Id: I0c18114955af8f4932d81fb689a0adb939dafaba
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15992
Reviewed-by: Juha Jäykkä <juha.jaykka@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

13665:9c7fe3811b88 25-Jan-2019 Andreas Sandberg <andreas.sandberg@arm.com>

python: Don't assume SimObjects live in the global namespace

The importer in Python 3 doesn't like the way we import SimObjects
from the global namespace. Convert the existing SimObject declarations
to import from m5.objects. As a side-effect, this makes these files
consistent with configuration files.

Change-Id: I11153502b430822130722839e1fa767b82a027aa
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15981
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>


/gem5/src/arch/alpha/AlphaSystem.py
/gem5/src/arch/alpha/AlphaTLB.py
/gem5/src/arch/arm/ArmISA.py
/gem5/src/arch/arm/ArmNativeTrace.py
/gem5/src/arch/arm/ArmPMU.py
/gem5/src/arch/arm/ArmSemihosting.py
/gem5/src/arch/arm/ArmSystem.py
/gem5/src/arch/arm/ArmTLB.py
/gem5/src/arch/arm/tracers/TarmacTrace.py
/gem5/src/arch/mips/MipsSystem.py
/gem5/src/arch/mips/MipsTLB.py
/gem5/src/arch/power/PowerTLB.py
/gem5/src/arch/riscv/RiscvSystem.py
/gem5/src/arch/riscv/RiscvTLB.py
/gem5/src/arch/sparc/SparcNativeTrace.py
/gem5/src/arch/sparc/SparcSystem.py
/gem5/src/arch/sparc/SparcTLB.py
/gem5/src/arch/x86/X86LocalApic.py
/gem5/src/arch/x86/X86NativeTrace.py
/gem5/src/arch/x86/X86System.py
/gem5/src/arch/x86/X86TLB.py
/gem5/src/base/vnc/Vnc.py
/gem5/src/cpu/BaseCPU.py
/gem5/src/cpu/CPUTracers.py
/gem5/src/cpu/CheckerCPU.py
/gem5/src/cpu/DummyChecker.py
/gem5/src/cpu/InstPBTrace.py
/gem5/src/cpu/kvm/BaseKvmCPU.py
/gem5/src/cpu/kvm/X86KvmCPU.py
/gem5/src/cpu/minor/MinorCPU.py
/gem5/src/cpu/o3/FUPool.py
/gem5/src/cpu/o3/FuncUnitConfig.py
/gem5/src/cpu/o3/O3CPU.py
/gem5/src/cpu/o3/O3Checker.py
/gem5/src/cpu/o3/probe/ElasticTrace.py
/gem5/src/cpu/o3/probe/SimpleTrace.py
/gem5/src/cpu/simple/AtomicSimpleCPU.py
/gem5/src/cpu/simple/BaseSimpleCPU.py
/gem5/src/cpu/simple/NonCachingSimpleCPU.py
/gem5/src/cpu/simple/TimingSimpleCPU.py
/gem5/src/cpu/simple/probes/SimPoint.py
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.py
/gem5/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.py
/gem5/src/cpu/testers/memtest/MemTest.py
/gem5/src/cpu/testers/rubytest/RubyTester.py
/gem5/src/cpu/testers/traffic_gen/BaseTrafficGen.py
/gem5/src/cpu/testers/traffic_gen/PyTrafficGen.py
/gem5/src/cpu/testers/traffic_gen/TrafficGen.py
/gem5/src/cpu/trace/TraceCPU.py
/gem5/src/dev/BadDevice.py
/gem5/src/dev/Device.py
/gem5/src/dev/Platform.py
/gem5/src/dev/alpha/AlphaBackdoor.py
/gem5/src/dev/alpha/Tsunami.py
/gem5/src/dev/arm/EnergyCtrl.py
/gem5/src/dev/arm/FlashDevice.py
/gem5/src/dev/arm/Gic.py
/gem5/src/dev/arm/NoMali.py
/gem5/src/dev/arm/RealView.py
/gem5/src/dev/arm/UFSHostDevice.py
/gem5/src/dev/arm/VirtIOMMIO.py
/gem5/src/dev/i2c/I2C.py
/gem5/src/dev/mips/Malta.py
/gem5/src/dev/net/Ethernet.py
/gem5/src/dev/pci/CopyEngine.py
/gem5/src/dev/pci/PciDevice.py
/gem5/src/dev/pci/PciHost.py
/gem5/src/dev/serial/Terminal.py
/gem5/src/dev/serial/Uart.py
/gem5/src/dev/sparc/T1000.py
/gem5/src/dev/storage/Ide.py
/gem5/src/dev/virtio/VirtIO.py
/gem5/src/dev/virtio/VirtIO9P.py
/gem5/src/dev/virtio/VirtIOBlock.py
/gem5/src/dev/virtio/VirtIOConsole.py
/gem5/src/dev/x86/Cmos.py
/gem5/src/dev/x86/I8042.py
/gem5/src/dev/x86/I82094AA.py
/gem5/src/dev/x86/I8237.py
/gem5/src/dev/x86/I8254.py
/gem5/src/dev/x86/I8259.py
/gem5/src/dev/x86/Pc.py
/gem5/src/dev/x86/PcSpeaker.py
/gem5/src/dev/x86/SouthBridge.py
/gem5/src/gpu-compute/GPU.py
/gem5/src/gpu-compute/LdsState.py
/gem5/src/learning_gem5/part2/SimpleCache.py
/gem5/src/learning_gem5/part2/SimpleMemobj.py
/gem5/src/mem/AbstractMemory.py
/gem5/src/mem/AddrMapper.py
/gem5/src/mem/Bridge.py
/gem5/src/mem/CommMonitor.py
/gem5/src/mem/DRAMCtrl.py
/gem5/src/mem/ExternalMaster.py
/gem5/src/mem/ExternalSlave.py
/gem5/src/mem/HMCController.py
/gem5/src/mem/MemChecker.py
/gem5/src/mem/MemDelay.py
/gem5/src/mem/MemObject.py
/gem5/src/mem/SerialLink.py
/gem5/src/mem/SimpleMemory.py
/gem5/src/mem/XBar.py
/gem5/src/mem/cache/Cache.py
/gem5/src/mem/cache/prefetch/Prefetcher.py
/gem5/src/mem/cache/tags/Tags.py
/gem5/src/mem/probes/MemFootprintProbe.py
/gem5/src/mem/probes/MemTraceProbe.py
/gem5/src/mem/probes/StackDistProbe.py
/gem5/src/mem/qos/QoSMemCtrl.py
/gem5/src/mem/qos/QoSMemSinkCtrl.py
BasicRouter.py
Network.py
garnet2.0/GarnetLink.py
garnet2.0/GarnetNetwork.py
simple/SimpleLink.py
simple/SimpleNetwork.py
/gem5/src/mem/ruby/slicc_interface/Controller.py
/gem5/src/mem/ruby/structures/LRUReplacementPolicy.py
/gem5/src/mem/ruby/structures/PseudoLRUReplacementPolicy.py
/gem5/src/mem/ruby/structures/RubyCache.py
/gem5/src/mem/ruby/structures/RubyPrefetcher.py
/gem5/src/mem/ruby/system/GPUCoalescer.py
/gem5/src/mem/ruby/system/RubySystem.py
/gem5/src/mem/ruby/system/Sequencer.py
/gem5/src/mem/ruby/system/VIPERCoalescer.py
/gem5/src/mem/ruby/system/WeightedLRUReplacementPolicy.py
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/sim/System.py
/gem5/src/sim/TickedObject.py
/gem5/src/sim/power/MathExprPowerModel.py
/gem5/src/sim/power/ThermalModel.py
13661:c6e84ef6a309 19-Jan-2019 Pouya Fotouhi <pfotouhi@ucdavis.edu>

mem-ruby: Fixing Topology

The constructor assumes the number of nodes (i.e. controllers) equal to
the number of external nodes.
This is a not necessarily valid for all cases (e.g MESI_Three_Level -
where L0s are directly connected to L1s).
MachineType_base_number(MachineType_NUM) provides the total number of
controllers.

Signed-off-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>
Change-Id: Id906099dc967ec70aa34dedb0b55351031ff242c
Reviewed-on: https://gem5-review.googlesource.com/c/15716
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

13449:2f7efa89c58b 26-Nov-2018 Gabe Black <gabeblack@google.com>

arch, base, cpu, gpu, mem: Replace assert(0 or false with panic.

Neither assert(0) nor assert(false) give any hint as to why control
getting to them is bad, and their more descriptive versions,
assert(0 && "description") and assert(false && "description"), jury
rig assert to add an error message when the utility function panic()
already does that directly with better formatting options.

This change replaces that flavor of call to assert with panic, except
in the actual code which processes the formatting that panic uses (to
avoid infinitely recurring error handling), and in some *.sm files
since I don't know what rules those have to follow and don't want to
accidentaly break them.

Change-Id: I8addfbfaf77eaed94ec8191f2ae4efb477cefdd0
Reviewed-on: https://gem5-review.googlesource.com/c/14636
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

13062:6f9defe1c11e 19-Sep-2018 Xianwei Zhang <xianwei.zhang@amd.com>

mem-ruby: Fix a bug in MessageBuffer randomization

In the previous implementation, messages are randomly inserted with
delays only if both RubySystem and MessageBuffer randomization flags
are set true. However, to find race conditions and cover more slicc
transitions, ruby random testers rely on setting RubySystem flag to
turn on randomization on all message buffers.
As a fix, this patch enables a message buffer to have randomization
when either RubySystem or its own flag is set.

Change-Id: I1e076908ff07e5846ebad4f4fc1c8f28d40bbfd4
Reviewed-on: https://gem5-review.googlesource.com/12784
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

12492:4e76959883a6 05-Feb-2018 Daniel R. Carvalho <odanrc@yahoo.com.br>

mem: Standardize mem folder header guards

Standardize all header guards in the mem directory according to the most
frequent patterns. In general they have the form:
mem: __FOLDER_TREE_FILE_NAME_HH__
ruby: __FOLDER_TREE_FILENAME_HH__

Change-Id: I983853e292deb302becf151bf0e970057dc24774
Reviewed-on: https://gem5-review.googlesource.com/7881
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

12334:e0ab29a34764 30-Nov-2017 Gabe Black <gabeblack@google.com>

misc: Rename misc.(hh|cc) to logging.(hh|cc)

These files aren't a collection of miscellaneous stuff, they're the
definition of the Logger interface, and a few utility macros for
calling into that interface (panic, warn, etc.).

Change-Id: I84267ac3f45896a83c0ef027f8f19c5e9a5667d1
Reviewed-on: https://gem5-review.googlesource.com/6226
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>


/gem5/ext/sst/gem5.cc
/gem5/src/arch/alpha/isa.cc
/gem5/src/arch/alpha/locked_mem.hh
/gem5/src/arch/alpha/mt.hh
/gem5/src/arch/alpha/process.cc
/gem5/src/arch/alpha/pseudo_inst.hh
/gem5/src/arch/alpha/utility.hh
/gem5/src/arch/arm/faults.hh
/gem5/src/arch/arm/isa_device.cc
/gem5/src/arch/arm/miscregs.cc
/gem5/src/arch/arm/process.cc
/gem5/src/arch/arm/pseudo_inst.hh
/gem5/src/arch/arm/types.hh
/gem5/src/arch/arm/utility.hh
/gem5/src/arch/generic/debugfaults.hh
/gem5/src/arch/generic/pseudo_inst.cc
/gem5/src/arch/generic/tlb.hh
/gem5/src/arch/generic/vec_reg.hh
/gem5/src/arch/hsail/gpu_isa.hh
/gem5/src/arch/mips/decoder.hh
/gem5/src/arch/mips/dsp.cc
/gem5/src/arch/mips/dsp.hh
/gem5/src/arch/mips/interrupts.hh
/gem5/src/arch/mips/locked_mem.hh
/gem5/src/arch/mips/mt.hh
/gem5/src/arch/mips/pagetable.hh
/gem5/src/arch/mips/process.cc
/gem5/src/arch/mips/pseudo_inst.hh
/gem5/src/arch/mips/registers.hh
/gem5/src/arch/mips/utility.cc
/gem5/src/arch/mips/utility.hh
/gem5/src/arch/power/interrupts.hh
/gem5/src/arch/power/isa.hh
/gem5/src/arch/power/process.cc
/gem5/src/arch/power/pseudo_inst.hh
/gem5/src/arch/power/utility.cc
/gem5/src/arch/riscv/decoder.hh
/gem5/src/arch/riscv/interrupts.hh
/gem5/src/arch/riscv/isa.hh
/gem5/src/arch/riscv/locked_mem.hh
/gem5/src/arch/riscv/pagetable.hh
/gem5/src/arch/riscv/process.cc
/gem5/src/arch/riscv/pseudo_inst.hh
/gem5/src/arch/sparc/isa/includes.isa
/gem5/src/arch/sparc/mt.hh
/gem5/src/arch/sparc/pagetable.hh
/gem5/src/arch/sparc/process.cc
/gem5/src/arch/sparc/pseudo_inst.hh
/gem5/src/arch/sparc/tlb.hh
/gem5/src/arch/sparc/utility.hh
/gem5/src/arch/x86/bios/intelmp.cc
/gem5/src/arch/x86/decoder.cc
/gem5/src/arch/x86/decoder.hh
/gem5/src/arch/x86/emulenv.cc
/gem5/src/arch/x86/faults.hh
/gem5/src/arch/x86/isa/includes.isa
/gem5/src/arch/x86/process.cc
/gem5/src/arch/x86/regs/int.hh
/gem5/src/base/SConscript
/gem5/src/base/addr_range.hh
/gem5/src/base/bigint.hh
/gem5/src/base/bmpwriter.cc
/gem5/src/base/circlebuf.hh
/gem5/src/base/debug.cc
/gem5/src/base/hostinfo.cc
/gem5/src/base/imgwriter.cc
/gem5/src/base/intmath.hh
/gem5/src/base/loader/ecoff_object.cc
/gem5/src/base/loader/elf_object.cc
/gem5/src/base/loader/object_file.hh
/gem5/src/base/loader/symtab.cc
/gem5/src/base/logging.cc
/gem5/src/base/logging.hh
/gem5/src/base/misc.cc
/gem5/src/base/misc.hh
/gem5/src/base/output.cc
/gem5/src/base/pngwriter.cc
/gem5/src/base/pollevent.cc
/gem5/src/base/random.cc
/gem5/src/base/socket.cc
/gem5/src/base/statistics.cc
/gem5/src/base/stats/text.cc
/gem5/src/base/time.cc
/gem5/src/base/trace.cc
/gem5/src/base/trie.hh
/gem5/src/base/vnc/vncinput.cc
/gem5/src/base/vnc/vncserver.cc
/gem5/src/cpu/base.cc
/gem5/src/cpu/func_unit.cc
/gem5/src/cpu/intr_control.hh
/gem5/src/cpu/kvm/device.cc
/gem5/src/cpu/kvm/perfevent.cc
/gem5/src/cpu/kvm/timer.cc
/gem5/src/cpu/minor/buffers.hh
/gem5/src/cpu/o3/free_list.hh
/gem5/src/cpu/o3/store_set.cc
/gem5/src/cpu/pc_event.hh
/gem5/src/cpu/pred/2bit_local.cc
/gem5/src/cpu/pred/btb.hh
/gem5/src/cpu/pred/ltage.cc
/gem5/src/cpu/pred/sat_counter.hh
/gem5/src/cpu/simple/base.cc
/gem5/src/cpu/static_inst.hh
/gem5/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc
/gem5/src/cpu/testers/rubytest/RubyTester.cc
/gem5/src/cpu/thread_context.cc
/gem5/src/dev/intel_8254_timer.cc
/gem5/src/dev/mc146818.hh
/gem5/src/dev/net/dist_iface.hh
/gem5/src/dev/net/etherbus.cc
/gem5/src/dev/net/etherdump.cc
/gem5/src/dev/net/etherint.cc
/gem5/src/dev/net/etherpkt.cc
/gem5/src/dev/net/ethertap.cc
/gem5/src/dev/net/pktfifo.cc
/gem5/src/dev/net/pktfifo.hh
/gem5/src/dev/pci/device.cc
/gem5/src/dev/platform.cc
/gem5/src/dev/ps2.cc
/gem5/src/dev/serial/serial.cc
/gem5/src/dev/serial/terminal.cc
/gem5/src/dev/storage/disk_image.cc
/gem5/src/dev/storage/simple_disk.cc
/gem5/src/gpu-compute/brig_object.cc
/gem5/src/gpu-compute/gpu_tlb.hh
/gem5/src/gpu-compute/hsa_object.cc
/gem5/src/gpu-compute/misc.hh
/gem5/src/gpu-compute/of_scheduling_policy.hh
/gem5/src/gpu-compute/rr_scheduling_policy.hh
/gem5/src/gpu-compute/simple_pool_manager.cc
/gem5/src/gpu-compute/tlb_coalescer.hh
/gem5/src/gpu-compute/vector_register_file.cc
/gem5/src/gpu-compute/wavefront.hh
/gem5/src/kern/operatingsystem.cc
/gem5/src/mem/cache/base.hh
/gem5/src/mem/cache/cache.cc
/gem5/src/mem/cache/cache.hh
/gem5/src/mem/cache/mshr.cc
/gem5/src/mem/cache/tags/fa_lru.cc
/gem5/src/mem/cache/write_queue_entry.cc
/gem5/src/mem/coherent_xbar.cc
/gem5/src/mem/dramsim2_wrapper.cc
/gem5/src/mem/mem_checker.hh
/gem5/src/mem/noncoherent_xbar.cc
/gem5/src/mem/packet.cc
/gem5/src/mem/packet.hh
/gem5/src/mem/request.hh
/gem5/src/mem/ruby/common/Set.hh
MessageBuffer.cc
Network.cc
fault_model/FaultModel.cc
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
/gem5/src/mem/ruby/structures/AbstractReplacementPolicy.cc
/gem5/src/mem/ruby/system/GPUCoalescer.cc
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/VIPERCoalescer.cc
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/mem/slicc/symbols/Type.py
/gem5/src/mem/snoop_filter.cc
/gem5/src/mem/xbar.cc
/gem5/src/proto/protoio.cc
/gem5/src/python/pybind11/core.cc
/gem5/src/python/pybind11/event.cc
/gem5/src/sim/clocked_object.cc
/gem5/src/sim/drain.cc
/gem5/src/sim/dvfs_handler.cc
/gem5/src/sim/eventq.cc
/gem5/src/sim/faults.cc
/gem5/src/sim/fd_array.cc
/gem5/src/sim/init.cc
/gem5/src/sim/init_signals.cc
/gem5/src/sim/mathexpr.cc
/gem5/src/sim/microcode_rom.cc
/gem5/src/sim/root.cc
/gem5/src/sim/serialize.cc
/gem5/src/sim/sim_object.cc
/gem5/src/sim/simulate.cc
/gem5/src/sim/syscall_emul.hh
/gem5/src/unittest/cprintftest.cc
/gem5/src/unittest/nmtest.cc
/gem5/src/unittest/stattest.cc
/gem5/util/systemc/sc_module.cc
12071:fd0b4bd769dd 06-Jun-2017 Javier Cano-Cano <javier.cano555@gmail.com>

mem-garnet: Fix garnet stats

This patch fix some statistics that in presence of a resetStats
instruction were not reseted. This bug makes impossible to obtain
reliable network statistics when the simulation doesn't start from tick
zero.

Change-Id: Ibec45f08d95bf0a533d94b70ec960719206ae945
Maintainer: Tushar Krishna <tushar@ece.gatech.edu>
Reviewed-on: https://gem5-review.googlesource.com/3700
Reviewed-by: Jieming Yin <bjm419@gmail.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

12065:e3e51756dfef 13-Mar-2017 Nikos Nikoleris <nikos.nikoleris@arm.com>

ruby: Add support for address ranges in the directory

Previously the directory covered a flat address range that always
started from address 0. This change adds a vector of address ranges
with interleaving and hashing that each directory keeps track of and
the necessary flexibility to support systems with non continuous
memory ranges.

Change-Id: I6ea1c629bdf4c5137b7d9c89dbaf6c826adfd977
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2903
Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>


/gem5/configs/ruby/GPU_RfO.py
/gem5/configs/ruby/Garnet_standalone.py
/gem5/configs/ruby/MESI_Three_Level.py
/gem5/configs/ruby/MESI_Two_Level.py
/gem5/configs/ruby/MI_example.py
/gem5/configs/ruby/MOESI_AMD_Base.py
/gem5/configs/ruby/MOESI_CMP_directory.py
/gem5/configs/ruby/MOESI_CMP_token.py
/gem5/configs/ruby/MOESI_hammer.py
/gem5/configs/ruby/Ruby.py
/gem5/src/base/addr_range.hh
/gem5/src/mem/protocol/GPU_RfO-TCCdir.sm
/gem5/src/mem/protocol/GPU_VIPER-TCC.sm
/gem5/src/mem/protocol/GPU_VIPER_Region-TCC.sm
/gem5/src/mem/protocol/Garnet_standalone-cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-L2cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-dma.sm
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dma.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-CorePair.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-L3cache.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-Region-CorePair.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-Region-dir.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-RegionBuffer.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-RegionDir.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-probeFilter.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dma.sm
/gem5/src/mem/protocol/MOESI_hammer-cache.sm
/gem5/src/mem/protocol/MOESI_hammer-dma.sm
/gem5/src/mem/protocol/RubySlicc_ComponentMapping.sm
Network.cc
Network.hh
/gem5/src/mem/ruby/slicc_interface/AbstractController.cc
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/slicc_interface/Controller.py
/gem5/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
/gem5/src/mem/ruby/structures/DirectoryMemory.cc
/gem5/src/mem/ruby/structures/DirectoryMemory.hh
/gem5/src/mem/ruby/structures/DirectoryMemory.py
/gem5/src/mem/slicc/symbols/Type.py
11831:3c38d3e74980 12-Feb-2017 Tushar Krishna <tushar@ece.gatech.edu>

ruby: fix round robin arbiter in garnet2.0
The rr arbiter pointer in garnet was getting updated on every request,
even if there is no grant. This was leading to a huge variance in wait
time at a router at high injection rates.
This patch corrects it to update upon a grant.

11800:54436a1784dc 09-Nov-2016 Brandon Potter <brandon.potter@amd.com>

style: [patch 3/22] reduce include dependencies in some headers

Used cppclean to help identify useless includes and removed them. This
involved erroneously included headers, but also cases where forward
declarations could have been used rather than a full include.


/gem5/src/arch/alpha/process.cc
/gem5/src/arch/alpha/process.hh
/gem5/src/arch/arm/process.cc
/gem5/src/arch/arm/process.hh
/gem5/src/arch/mips/process.cc
/gem5/src/arch/mips/process.hh
/gem5/src/arch/power/interrupts.hh
/gem5/src/arch/power/process.cc
/gem5/src/arch/power/process.hh
/gem5/src/arch/power/remote_gdb.cc
/gem5/src/arch/riscv/interrupts.hh
/gem5/src/arch/riscv/process.cc
/gem5/src/arch/riscv/process.hh
/gem5/src/arch/sparc/process.cc
/gem5/src/arch/sparc/process.hh
/gem5/src/arch/x86/isa_traits.hh
/gem5/src/arch/x86/pagetable.hh
/gem5/src/arch/x86/process.cc
/gem5/src/arch/x86/pseudo_inst.cc
/gem5/src/arch/x86/system.cc
/gem5/src/arch/x86/system.hh
/gem5/src/arch/x86/tlb.cc
/gem5/src/arch/x86/tlb.hh
/gem5/src/arch/x86/utility.cc
/gem5/src/arch/x86/utility.hh
/gem5/src/base/bitfield.hh
/gem5/src/base/bitunion.hh
/gem5/src/base/time.cc
/gem5/src/base/vnc/vncinput.cc
/gem5/src/cpu/minor/buffers.hh
/gem5/src/cpu/testers/directedtest/InvalidateGenerator.cc
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.cc
/gem5/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
/gem5/src/cpu/testers/memtest/memtest.cc
/gem5/src/cpu/testers/rubytest/Check.cc
/gem5/src/cpu/testers/rubytest/CheckTable.cc
/gem5/src/cpu/testers/rubytest/RubyTester.cc
/gem5/src/dev/arm/flash_device.cc
/gem5/src/dev/mc146818.hh
/gem5/src/dev/net/dist_iface.hh
/gem5/src/dev/net/etherbus.cc
/gem5/src/dev/net/etherswitch.cc
/gem5/src/gpu-compute/vector_register_file.hh
/gem5/src/kern/linux/linux.cc
/gem5/src/kern/linux/linux.hh
/gem5/src/mem/cache/prefetch/stride.cc
/gem5/src/mem/external_master.cc
/gem5/src/mem/external_slave.cc
/gem5/src/mem/mem_checker.hh
/gem5/src/mem/multi_level_page_table.hh
/gem5/src/mem/multi_level_page_table_impl.hh
/gem5/src/mem/page_table.cc
/gem5/src/mem/page_table.hh
MessageBuffer.hh
/gem5/src/mem/ruby/structures/AbstractReplacementPolicy.cc
/gem5/src/mem/se_translating_port_proxy.hh
/gem5/src/mem/simple_mem.cc
/gem5/src/python/swig/pyevent.cc
/gem5/src/sim/SConscript
/gem5/src/sim/arguments.cc
/gem5/src/sim/arguments.hh
/gem5/src/sim/byteswap.hh
/gem5/src/sim/clock_domain.cc
/gem5/src/sim/clocked_object.hh
/gem5/src/sim/cxx_config.hh
/gem5/src/sim/cxx_config_ini.cc
/gem5/src/sim/cxx_config_ini.hh
/gem5/src/sim/cxx_manager.cc
/gem5/src/sim/drain.hh
/gem5/src/sim/dvfs_handler.cc
/gem5/src/sim/dvfs_handler.hh
/gem5/src/sim/eventq.hh
/gem5/src/sim/fd_entry.hh
/gem5/src/sim/init_signals.cc
/gem5/src/sim/insttracer.hh
/gem5/src/sim/microcode_rom.cc
/gem5/src/sim/microcode_rom.hh
/gem5/src/sim/power/mathexpr_powermodel.hh
/gem5/src/sim/power/power_model.cc
/gem5/src/sim/power/power_model.hh
/gem5/src/sim/power/thermal_domain.cc
/gem5/src/sim/power/thermal_domain.hh
/gem5/src/sim/power/thermal_entity.hh
/gem5/src/sim/power/thermal_model.hh
/gem5/src/sim/probe/probe.cc
/gem5/src/sim/probe/probe.hh
/gem5/src/sim/process.cc
/gem5/src/sim/process.hh
/gem5/src/sim/process_impl.hh
/gem5/src/sim/root.cc
/gem5/src/sim/serialize.hh
/gem5/src/sim/sim_exit.hh
/gem5/src/sim/sim_object.cc
/gem5/src/sim/sim_object.hh
/gem5/src/sim/simulate.hh
/gem5/src/sim/stat_register.cc
/gem5/src/sim/stat_register.hh
/gem5/src/sim/sub_system.hh
/gem5/src/sim/syscall_emul.cc
/gem5/src/sim/syscall_emul.hh
/gem5/src/sim/syscall_return.hh
/gem5/src/sim/system.hh
/gem5/src/sim/ticked_object.cc
/gem5/src/sim/ticked_object.hh
/gem5/src/sim/voltage_domain.cc
/gem5/src/sim/vptr.hh
11797:f61fbb7ceb88 19-Jan-2017 Matthew Poremba <matthew.poremba@amd.com>

ruby: Check MessageBuffer space in garnet NetworkInterface

Garnet's NetworkInterface does not consider the size of MessageBuffers when
ejecting a Message from the network. Add a size check for the MessageBuffer
and only enqueue if space is available. If space is not available, the
message if placed in a queue and the credit is held. A callback from the
MessageBuffer is implemented to wake the NetworkInterface. If there are
messages in the stalled queue, they are processed first, in a FIFO manner
and if succesfully ejected, the credit is finally sent back upstream. The
maximum size of the stall queue is equal to the number of valid VNETs
with MessageBuffers attached.

11796:315e133f45df 19-Jan-2017 Matthew Poremba <matthew.poremba@amd.com>

ruby: Add occupancy stats to MessageBuffers

This patch is an updated version of /r/3297.

"The most important statistic for measuring memory hierarchy performance is
throughput, which is affected by independent variables, buffer sizing and
communication latency. It is difficult/impossible to debug performance issues
through series buffers without knowing which are the bottlenecks. For finite
buffers, this patch adds statistics for the average number of messages in the
buffer, the occupancy of the buffer slots, and number of message stalls."

11795:588a45268ce4 19-Jan-2017 Matthew Poremba <matthew.poremba@amd.com>

ruby: Check all VNETs for injection in garnet NetworkInterface

The NetworkInterface wakeup currently iterates over all VNETs and breaks the
loop if a VNET is unable to allocate a VC. This can cause a deadlock if a
lower numbered VNET is unable to allocate a VC while a higher numbered VNET
has idle VCs. This seems like a bug as Garnet 1.0 uses a while loop over an
if-statement, suggesting the break was intended for this while loop. This
patch removes the break statement, which allows up to one message to be
dequeued from a VNET and injected into the network.

11793:ef606668d247 09-Nov-2016 Brandon Potter <brandon.potter@amd.com>

style: [patch 1/22] use /r/3648/ to reorganize includes


/gem5/src/arch/alpha/faults.cc
/gem5/src/arch/alpha/freebsd/system.cc
/gem5/src/arch/alpha/idle_event.cc
/gem5/src/arch/alpha/ipr.cc
/gem5/src/arch/alpha/isa.cc
/gem5/src/arch/alpha/kernel_stats.cc
/gem5/src/arch/alpha/linux/process.cc
/gem5/src/arch/alpha/linux/system.cc
/gem5/src/arch/alpha/pagetable.cc
/gem5/src/arch/alpha/process.cc
/gem5/src/arch/alpha/remote_gdb.cc
/gem5/src/arch/alpha/stacktrace.cc
/gem5/src/arch/alpha/system.cc
/gem5/src/arch/alpha/utility.cc
/gem5/src/arch/alpha/vtophys.cc
/gem5/src/arch/arm/faults.cc
/gem5/src/arch/arm/insts/macromem.cc
/gem5/src/arch/arm/insts/mem.cc
/gem5/src/arch/arm/insts/mem64.cc
/gem5/src/arch/arm/insts/misc.cc
/gem5/src/arch/arm/insts/pseudo.cc
/gem5/src/arch/arm/insts/static_inst.cc
/gem5/src/arch/arm/interrupts.cc
/gem5/src/arch/arm/isa.cc
/gem5/src/arch/arm/kvm/base_cpu.cc
/gem5/src/arch/arm/linux/process.cc
/gem5/src/arch/arm/linux/system.cc
/gem5/src/arch/arm/miscregs.cc
/gem5/src/arch/arm/nativetrace.cc
/gem5/src/arch/arm/process.cc
/gem5/src/arch/arm/remote_gdb.cc
/gem5/src/arch/arm/stacktrace.cc
/gem5/src/arch/arm/stage2_lookup.cc
/gem5/src/arch/arm/system.cc
/gem5/src/arch/arm/tlb.cc
/gem5/src/arch/arm/utility.cc
/gem5/src/arch/arm/vtophys.cc
/gem5/src/arch/generic/decode_cache.cc
/gem5/src/arch/generic/mmapped_ipr.cc
/gem5/src/arch/generic/pseudo_inst.cc
/gem5/src/arch/mips/bare_iron/system.cc
/gem5/src/arch/mips/dsp.cc
/gem5/src/arch/mips/faults.cc
/gem5/src/arch/mips/idle_event.cc
/gem5/src/arch/mips/interrupts.cc
/gem5/src/arch/mips/isa.cc
/gem5/src/arch/mips/linux/process.cc
/gem5/src/arch/mips/linux/system.cc
/gem5/src/arch/mips/pagetable.cc
/gem5/src/arch/mips/process.cc
/gem5/src/arch/mips/remote_gdb.cc
/gem5/src/arch/mips/stacktrace.cc
/gem5/src/arch/mips/system.cc
/gem5/src/arch/mips/tlb.cc
/gem5/src/arch/mips/utility.cc
/gem5/src/arch/mips/vtophys.cc
/gem5/src/arch/power/insts/branch.cc
/gem5/src/arch/power/insts/mem.cc
/gem5/src/arch/power/insts/static_inst.cc
/gem5/src/arch/power/isa.cc
/gem5/src/arch/power/linux/process.cc
/gem5/src/arch/power/pagetable.cc
/gem5/src/arch/power/process.cc
/gem5/src/arch/power/stacktrace.cc
/gem5/src/arch/power/tlb.cc
/gem5/src/arch/power/utility.cc
/gem5/src/arch/sparc/faults.cc
/gem5/src/arch/sparc/isa.cc
/gem5/src/arch/sparc/linux/process.cc
/gem5/src/arch/sparc/nativetrace.cc
/gem5/src/arch/sparc/pagetable.cc
/gem5/src/arch/sparc/process.cc
/gem5/src/arch/sparc/remote_gdb.cc
/gem5/src/arch/sparc/solaris/process.cc
/gem5/src/arch/sparc/system.cc
/gem5/src/arch/sparc/tlb.cc
/gem5/src/arch/sparc/ua2005.cc
/gem5/src/arch/sparc/utility.cc
/gem5/src/arch/sparc/vtophys.cc
/gem5/src/arch/x86/bios/acpi.cc
/gem5/src/arch/x86/bios/e820.cc
/gem5/src/arch/x86/bios/intelmp.cc
/gem5/src/arch/x86/bios/smbios.cc
/gem5/src/arch/x86/cpuid.cc
/gem5/src/arch/x86/decoder.cc
/gem5/src/arch/x86/emulenv.cc
/gem5/src/arch/x86/faults.cc
/gem5/src/arch/x86/insts/badmicroop.cc
/gem5/src/arch/x86/insts/microfpop.cc
/gem5/src/arch/x86/insts/microldstop.cc
/gem5/src/arch/x86/insts/micromediaop.cc
/gem5/src/arch/x86/insts/microop.cc
/gem5/src/arch/x86/insts/microregop.cc
/gem5/src/arch/x86/insts/static_inst.cc
/gem5/src/arch/x86/interrupts.cc
/gem5/src/arch/x86/isa.cc
/gem5/src/arch/x86/linux/process.cc
/gem5/src/arch/x86/linux/system.cc
/gem5/src/arch/x86/nativetrace.cc
/gem5/src/arch/x86/pagetable.cc
/gem5/src/arch/x86/pagetable_walker.cc
/gem5/src/arch/x86/process.cc
/gem5/src/arch/x86/pseudo_inst.cc
/gem5/src/arch/x86/remote_gdb.cc
/gem5/src/arch/x86/stacktrace.cc
/gem5/src/arch/x86/system.cc
/gem5/src/arch/x86/tlb.cc
/gem5/src/arch/x86/types.cc
/gem5/src/arch/x86/utility.cc
/gem5/src/arch/x86/vtophys.cc
/gem5/src/base/atomicio.cc
/gem5/src/base/bigint.cc
/gem5/src/base/cp_annotate.cc
/gem5/src/base/cprintf.cc
/gem5/src/base/debug.cc
/gem5/src/base/hostinfo.cc
/gem5/src/base/inet.cc
/gem5/src/base/inifile.cc
/gem5/src/base/loader/aout_object.cc
/gem5/src/base/loader/dtb_object.cc
/gem5/src/base/loader/ecoff_object.cc
/gem5/src/base/loader/hex_file.cc
/gem5/src/base/loader/object_file.cc
/gem5/src/base/loader/raw_object.cc
/gem5/src/base/loader/symtab.cc
/gem5/src/base/match.cc
/gem5/src/base/misc.cc
/gem5/src/base/output.cc
/gem5/src/base/pollevent.cc
/gem5/src/base/random.cc
/gem5/src/base/remote_gdb.cc
/gem5/src/base/socket.cc
/gem5/src/base/statistics.cc
/gem5/src/base/stats/text.cc
/gem5/src/base/str.cc
/gem5/src/base/time.cc
/gem5/src/base/trace.cc
/gem5/src/base/vnc/vncinput.cc
/gem5/src/base/vnc/vncserver.cc
/gem5/src/cpu/activity.cc
/gem5/src/cpu/base.cc
/gem5/src/cpu/checker/cpu.cc
/gem5/src/cpu/dummy_checker.cc
/gem5/src/cpu/exetrace.cc
/gem5/src/cpu/func_unit.cc
/gem5/src/cpu/inteltrace.cc
/gem5/src/cpu/intr_control.cc
/gem5/src/cpu/kvm/base.cc
/gem5/src/cpu/kvm/perfevent.cc
/gem5/src/cpu/kvm/timer.cc
/gem5/src/cpu/kvm/vm.cc
/gem5/src/cpu/kvm/x86_cpu.cc
/gem5/src/cpu/minor/activity.cc
/gem5/src/cpu/minor/cpu.cc
/gem5/src/cpu/minor/decode.cc
/gem5/src/cpu/minor/dyn_inst.cc
/gem5/src/cpu/minor/execute.cc
/gem5/src/cpu/minor/fetch1.cc
/gem5/src/cpu/minor/fetch2.cc
/gem5/src/cpu/minor/func_unit.cc
/gem5/src/cpu/minor/lsq.cc
/gem5/src/cpu/minor/pipeline.cc
/gem5/src/cpu/minor/scoreboard.cc
/gem5/src/cpu/nativetrace.cc
/gem5/src/cpu/o3/base_dyn_inst.cc
/gem5/src/cpu/o3/checker.cc
/gem5/src/cpu/o3/cpu.cc
/gem5/src/cpu/o3/deriv.cc
/gem5/src/cpu/o3/free_list.cc
/gem5/src/cpu/o3/fu_pool.cc
/gem5/src/cpu/o3/probe/simple_trace.cc
/gem5/src/cpu/o3/regfile.cc
/gem5/src/cpu/o3/rename_map.cc
/gem5/src/cpu/o3/scoreboard.cc
/gem5/src/cpu/o3/store_set.cc
/gem5/src/cpu/o3/thread_context.cc
/gem5/src/cpu/pc_event.cc
/gem5/src/cpu/pred/2bit_local.cc
/gem5/src/cpu/pred/bi_mode.cc
/gem5/src/cpu/pred/btb.cc
/gem5/src/cpu/pred/tournament.cc
/gem5/src/cpu/profile.cc
/gem5/src/cpu/quiesce_event.cc
/gem5/src/cpu/simple/atomic.cc
/gem5/src/cpu/simple/base.cc
/gem5/src/cpu/simple/probes/simpoint.cc
/gem5/src/cpu/simple/timing.cc
/gem5/src/cpu/simple_thread.cc
/gem5/src/cpu/static_inst.cc
/gem5/src/cpu/testers/directedtest/DirectedGenerator.cc
/gem5/src/cpu/testers/directedtest/InvalidateGenerator.cc
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.cc
/gem5/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
/gem5/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc
/gem5/src/cpu/testers/memtest/memtest.cc
/gem5/src/cpu/testers/rubytest/Check.cc
/gem5/src/cpu/testers/rubytest/CheckTable.cc
/gem5/src/cpu/testers/rubytest/RubyTester.cc
/gem5/src/cpu/thread_context.cc
/gem5/src/cpu/thread_state.cc
/gem5/src/cpu/timing_expr.cc
/gem5/src/dev/alpha/backdoor.cc
/gem5/src/dev/alpha/tsunami.cc
/gem5/src/dev/alpha/tsunami_cchip.cc
/gem5/src/dev/alpha/tsunami_io.cc
/gem5/src/dev/arm/a9scu.cc
/gem5/src/dev/arm/amba_device.cc
/gem5/src/dev/arm/amba_fake.cc
/gem5/src/dev/arm/energy_ctrl.cc
/gem5/src/dev/arm/gic_pl390.cc
/gem5/src/dev/arm/hdlcd.cc
/gem5/src/dev/arm/kmi.cc
/gem5/src/dev/arm/pl011.cc
/gem5/src/dev/arm/pl111.cc
/gem5/src/dev/arm/realview.cc
/gem5/src/dev/arm/rtc_pl031.cc
/gem5/src/dev/arm/timer_cpulocal.cc
/gem5/src/dev/arm/timer_sp804.cc
/gem5/src/dev/arm/vgic.cc
/gem5/src/dev/baddev.cc
/gem5/src/dev/intel_8254_timer.cc
/gem5/src/dev/io_device.cc
/gem5/src/dev/isa_fake.cc
/gem5/src/dev/mc146818.cc
/gem5/src/dev/mips/malta.cc
/gem5/src/dev/mips/malta_cchip.cc
/gem5/src/dev/mips/malta_io.cc
/gem5/src/dev/pci/device.cc
/gem5/src/dev/pci/host.cc
/gem5/src/dev/platform.cc
/gem5/src/dev/ps2.cc
/gem5/src/dev/ps2.hh
/gem5/src/dev/sparc/dtod.cc
/gem5/src/dev/sparc/iob.cc
/gem5/src/dev/sparc/mm_disk.cc
/gem5/src/dev/sparc/t1000.cc
/gem5/src/dev/uart.cc
/gem5/src/dev/uart8250.cc
/gem5/src/dev/virtio/base.cc
/gem5/src/dev/virtio/block.cc
/gem5/src/dev/virtio/console.cc
/gem5/src/dev/virtio/fs9p.cc
/gem5/src/dev/virtio/pci.cc
/gem5/src/dev/x86/cmos.cc
/gem5/src/dev/x86/i8042.cc
/gem5/src/dev/x86/i82094aa.cc
/gem5/src/dev/x86/i8237.cc
/gem5/src/dev/x86/i8254.cc
/gem5/src/dev/x86/i8259.cc
/gem5/src/dev/x86/pc.cc
/gem5/src/dev/x86/south_bridge.cc
/gem5/src/dev/x86/speaker.cc
/gem5/src/kern/linux/linux.cc
/gem5/src/kern/linux/printk.cc
/gem5/src/kern/operatingsystem.cc
/gem5/src/kern/system_events.cc
/gem5/src/mem/abstract_mem.cc
/gem5/src/mem/bridge.cc
/gem5/src/mem/cache/prefetch/base.cc
/gem5/src/mem/cache/prefetch/queued.cc
/gem5/src/mem/cache/prefetch/stride.cc
/gem5/src/mem/coherent_xbar.cc
/gem5/src/mem/comm_monitor.cc
/gem5/src/mem/dram_ctrl.cc
/gem5/src/mem/drampower.cc
/gem5/src/mem/dramsim2.cc
/gem5/src/mem/dramsim2_wrapper.cc
/gem5/src/mem/external_master.cc
/gem5/src/mem/external_slave.cc
/gem5/src/mem/fs_translating_port_proxy.cc
/gem5/src/mem/hmc_controller.cc
/gem5/src/mem/mem_checker.cc
/gem5/src/mem/mem_checker_monitor.cc
/gem5/src/mem/noncoherent_xbar.cc
/gem5/src/mem/packet.cc
/gem5/src/mem/packet_queue.cc
/gem5/src/mem/page_table.cc
/gem5/src/mem/physical.cc
/gem5/src/mem/port.cc
/gem5/src/mem/port_proxy.cc
/gem5/src/mem/probes/base.cc
/gem5/src/mem/ruby/common/Histogram.cc
/gem5/src/mem/ruby/common/NetDest.cc
/gem5/src/mem/ruby/common/SubBlock.cc
/gem5/src/mem/ruby/filters/BlockBloomFilter.cc
/gem5/src/mem/ruby/filters/BulkBloomFilter.cc
/gem5/src/mem/ruby/filters/H3BloomFilter.cc
/gem5/src/mem/ruby/filters/LSB_CountingBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiGrainBloomFilter.cc
/gem5/src/mem/ruby/filters/NonCountingBloomFilter.cc
MessageBuffer.cc
Network.cc
Topology.cc
simple/PerfectSwitch.cc
simple/PerfectSwitch.hh
simple/SimpleNetwork.cc
simple/Switch.cc
simple/Throttle.cc
/gem5/src/mem/ruby/profiler/AccessTraceForAddress.cc
/gem5/src/mem/ruby/profiler/AddressProfiler.cc
/gem5/src/mem/ruby/profiler/StoreTrace.cc
/gem5/src/mem/ruby/slicc_interface/AbstractController.cc
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/slicc_interface/RubyRequest.cc
/gem5/src/mem/ruby/structures/BankedArray.cc
/gem5/src/mem/ruby/structures/CacheMemory.cc
/gem5/src/mem/ruby/structures/DirectoryMemory.cc
/gem5/src/mem/ruby/structures/LRUPolicy.cc
/gem5/src/mem/ruby/structures/Prefetcher.cc
/gem5/src/mem/ruby/structures/PseudoLRUPolicy.cc
/gem5/src/mem/ruby/structures/WireBuffer.cc
/gem5/src/mem/ruby/system/CacheRecorder.cc
/gem5/src/mem/ruby/system/DMASequencer.cc
/gem5/src/mem/ruby/system/RubyPort.cc
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/se_translating_port_proxy.cc
/gem5/src/mem/serial_link.cc
/gem5/src/mem/simple_mem.cc
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/mem/snoop_filter.cc
/gem5/src/mem/tport.cc
/gem5/src/mem/xbar.cc
/gem5/src/proto/protoio.cc
/gem5/src/python/swig/pyevent.cc
/gem5/src/python/swig/pyevent.hh
/gem5/src/python/swig/pyobject.cc
/gem5/src/sim/arguments.cc
/gem5/src/sim/backtrace_glibc.cc
/gem5/src/sim/clock_domain.cc
/gem5/src/sim/core.cc
/gem5/src/sim/cxx_manager.cc
/gem5/src/sim/debug.cc
/gem5/src/sim/dvfs_handler.cc
/gem5/src/sim/faults.cc
/gem5/src/sim/init.cc
/gem5/src/sim/probe/probe.cc
/gem5/src/sim/process.cc
/gem5/src/sim/pseudo_inst.cc
/gem5/src/sim/py_interact.cc
/gem5/src/sim/root.cc
/gem5/src/sim/serialize.cc
/gem5/src/sim/sim_events.cc
/gem5/src/sim/sim_object.cc
/gem5/src/sim/simulate.cc
/gem5/src/sim/stat_control.cc
/gem5/src/sim/stat_control.hh
/gem5/src/sim/sub_system.cc
/gem5/src/sim/syscall_emul.cc
/gem5/src/sim/system.cc
/gem5/src/sim/voltage_domain.cc
/gem5/src/unittest/circlebuf.cc
/gem5/src/unittest/unittest.cc
11779:25dd0fd23474 20-Dec-2016 Joel Hestness <jthestness@gmail.com>

ruby: Make MessageBuffers actually finite sized

When Ruby controllers stall messages in MessageBuffers, the buffer moves those
messages off the priority heap and into a per-address stall map. When buffers
are finite-sized, the test areNSlotsAvailable() only checks the size of the
priority heap, but ignores the stall map, so the map is allowed to grow
unbounded if the controller stalls numerous messages. This patch fixes the
problem by tracking the stall map size and testing the total number of messages
in the buffer appropriately.

11762:29d401db3746 15-Dec-2016 Jieming Yin <jieming.yin@amd.com>

ruby: Detect garnet network-level deadlock.

This patch detects garnet network deadlock by monitoring
network interfaces. If a network interface continuously
fails to allocate virtual channels for a message, a
possible deadlock is detected.

11732:e15e445c21a6 02-Dec-2016 Matthew Poremba <matthew.poremba@amd.com>

ruby: Fix overflow reported by ASAN in MessageBuffer.

In MessageBuffer the m_not_avail_count member is incremented but not used.
This causes an overflow reported by ASAN. This patch changes from an int to
Stats::Scalar, since the count is useful in debugging finite MessageBuffers.

11715:31b2c4b52047 21-Nov-2016 Jieming Yin <jieming.yin@amd.com>

ruby: Fix potential bugs in garnet2.0

1. Delete unused variable from struct LinkEntry
2. Correct GarnetExtLink and GarnetIntLink inheritance

11667:ebf2acd02fc5 06-Oct-2016 Tushar Krishna <tushar@ece.gatech.edu>

ruby: Add M5_VAR_USED before variables used only inside assert in garnet2.0.
This removes errors when building gem5.fast

11666:10d59d546ea2 06-Oct-2016 Tushar Krishna <tushar@ece.gatech.edu>

ruby: garnet2.0
Revamped version of garnet with more optimized single-cycle routers,
more configurability, and cleaner code.

11665:db895719c482 06-Oct-2016 Tushar Krishna <tushar@ece.gatech.edu>

ruby: remove the original garnet code.
Only garnet2.0 will be supported henceforth.


garnet/BaseGarnetNetwork.cc
garnet/BaseGarnetNetwork.hh
garnet/BaseGarnetNetwork.py
garnet/NetworkHeader.hh
garnet/SConscript
garnet/fixed-pipeline/CreditLink_d.hh
garnet/fixed-pipeline/GarnetLink_d.cc
garnet/fixed-pipeline/GarnetLink_d.hh
garnet/fixed-pipeline/GarnetLink_d.py
garnet/fixed-pipeline/GarnetNetwork_d.cc
garnet/fixed-pipeline/GarnetNetwork_d.hh
garnet/fixed-pipeline/GarnetNetwork_d.py
garnet/fixed-pipeline/InputUnit_d.cc
garnet/fixed-pipeline/InputUnit_d.hh
garnet/fixed-pipeline/NetworkInterface_d.cc
garnet/fixed-pipeline/NetworkInterface_d.hh
garnet/fixed-pipeline/NetworkLink_d.cc
garnet/fixed-pipeline/NetworkLink_d.hh
garnet/fixed-pipeline/OutVcState_d.cc
garnet/fixed-pipeline/OutVcState_d.hh
garnet/fixed-pipeline/OutputUnit_d.cc
garnet/fixed-pipeline/OutputUnit_d.hh
garnet/fixed-pipeline/Router_d.cc
garnet/fixed-pipeline/Router_d.hh
garnet/fixed-pipeline/RoutingUnit_d.cc
garnet/fixed-pipeline/RoutingUnit_d.hh
garnet/fixed-pipeline/SConscript
garnet/fixed-pipeline/SWallocator_d.cc
garnet/fixed-pipeline/SWallocator_d.hh
garnet/fixed-pipeline/Switch_d.cc
garnet/fixed-pipeline/Switch_d.hh
garnet/fixed-pipeline/VCallocator_d.cc
garnet/fixed-pipeline/VCallocator_d.hh
garnet/fixed-pipeline/VirtualChannel_d.cc
garnet/fixed-pipeline/VirtualChannel_d.hh
garnet/fixed-pipeline/flitBuffer_d.cc
garnet/fixed-pipeline/flitBuffer_d.hh
garnet/fixed-pipeline/flit_d.cc
garnet/fixed-pipeline/flit_d.hh
garnet/flexible-pipeline/FlexibleConsumer.hh
garnet/flexible-pipeline/GarnetLink.cc
garnet/flexible-pipeline/GarnetLink.hh
garnet/flexible-pipeline/GarnetLink.py
garnet/flexible-pipeline/GarnetNetwork.cc
garnet/flexible-pipeline/GarnetNetwork.hh
garnet/flexible-pipeline/GarnetNetwork.py
garnet/flexible-pipeline/InVcState.cc
garnet/flexible-pipeline/InVcState.hh
garnet/flexible-pipeline/NetworkInterface.cc
garnet/flexible-pipeline/NetworkInterface.hh
garnet/flexible-pipeline/NetworkLink.cc
garnet/flexible-pipeline/NetworkLink.hh
garnet/flexible-pipeline/OutVcState.cc
garnet/flexible-pipeline/OutVcState.hh
garnet/flexible-pipeline/Router.cc
garnet/flexible-pipeline/Router.hh
garnet/flexible-pipeline/SConscript
garnet/flexible-pipeline/VCarbiter.cc
garnet/flexible-pipeline/VCarbiter.hh
garnet/flexible-pipeline/flit.cc
garnet/flexible-pipeline/flit.hh
garnet/flexible-pipeline/flitBuffer.cc
garnet/flexible-pipeline/flitBuffer.hh
11664:2365e9e396f7 06-Oct-2016 Tushar Krishna <tushar@ece.gatech.edu>

config: add port directions and per-router delay in topology.
This patch adds port direction names to the links during topology
creation, which can be used for better printed names for the links
or for users to code up their own adaptive routing algorithms.
It also adds support for every router to have an independent latency
value to support heterogeneous topologies with the subsequent
garnet2.0 patch.

11663:cf870cd20cfc 06-Oct-2016 Tushar Krishna <tushar@ece.gatech.edu>

config: make internal links in network topology unidirectional.
This patch makes the internal links within the network topology
unidirectional, thus allowing any deadlock-free routing algorithms to
be specified from the topology itself using weights.
This patch also renames Mesh.py and MeshDirCorners.py to
Mesh_XY.py and MeshDirCorners_XY.py (Mesh with XY routing).
It also adds a Mesh_westfirst.py and CrossbarGarnet.py topologies.

11556:7aa1142a5730 01-Jul-2016 Matthew Poremba <Matthew.Poremba@amd.com>

ruby: Fix double statistic registration in garnet

Currently garnet will not run due to double statistic registration of new
stats in ClockedObject. This occurs because a temporary array named 'cls'
is being added as a child to garnet internal and external link SimObjects.
This patch simply renames the temporary array which prevents it from
being added as a child object and avoids the assertion that a statistic
was already registered.

Committed by Jason Lowe-Power <jason@lowepower.com>

11523:81332eb10367 06-Jun-2016 David Guillen Fandos <david.guillen@arm.com>

stats: Fixing regStats function for some SimObjects

Fixing an issue with regStats not calling the parent class method
for most SimObjects in Gem5. This causes issues if one adds new
stats in the base class (since they are never initialized properly!).

Change-Id: Iebc5aa66f58816ef4295dc8e48a357558d76a77c
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

11430:bd1c6789c33f 07-Apr-2016 Andreas Sandberg <andreas.sandberg@arm.com>

Revert to 74c1e6513bd0 (sim: Thermal support for Linux)

11422:4f749e00b667 18-Nov-2014 Akash Bagdia <akash.bagdia@ARM.com>

power: Add power states to ClockedObject

Add 4 power states to the ClockedObject, provides necessary access functions
to check and update the power state. Default power state is UNDEFINED, it is
responsibility of the respective simulation model to provide the startup state
and any other logic for state change.

Add number of transition stat.
Add distribution of time spent in clock gated state.
Add power state residency stat.

Add dump call back function to allow stats update of distribution and residency
stats.

11325:67cc559d513a 06-Feb-2016 Steve Reinhardt <steve.reinhardt@amd.com>

style: eliminate explicit boolean comparisons

Result of running 'hg m5style --skip-all --fix-control -a' to get
rid of '== true' comparisons, plus trivial manual edits to get
rid of '== false'/'== False' comparisons.

Left a couple of explicit comparisons in where they didn't seem
unreasonable:
invalid boolean comparison in src/arch/mips/interrupts.cc:155
>> DPRINTF(Interrupt, "Interrupts OnCpuTimerINterrupt(tc) == true\n");<<
invalid boolean comparison in src/unittest/unittest.hh:110
>> "EXPECT_FALSE(" #expr ")", (expr) == false)<<

11321:02e930db812d 06-Feb-2016 Steve Reinhardt <steve.reinhardt@amd.com>

style: fix missing spaces in control statements

Result of running 'hg m5style --skip-all --fix-control -a'.


/gem5/src/arch/alpha/process.cc
/gem5/src/arch/arm/insts/macromem.cc
/gem5/src/arch/arm/insts/vfp.hh
/gem5/src/arch/arm/kvm/arm_cpu.cc
/gem5/src/arch/arm/linux/system.cc
/gem5/src/arch/arm/tlb.cc
/gem5/src/arch/generic/tlb.cc
/gem5/src/arch/mips/isa.cc
/gem5/src/arch/x86/bios/intelmp.cc
/gem5/src/arch/x86/cpuid.cc
/gem5/src/arch/x86/decoder.cc
/gem5/src/arch/x86/insts/microldstop.cc
/gem5/src/arch/x86/insts/microregop.cc
/gem5/src/arch/x86/insts/static_inst.cc
/gem5/src/arch/x86/insts/static_inst.hh
/gem5/src/arch/x86/nativetrace.cc
/gem5/src/arch/x86/pagetable_walker.cc
/gem5/src/arch/x86/process.cc
/gem5/src/arch/x86/types.hh
/gem5/src/base/atomicio.hh
/gem5/src/base/cp_annotate.cc
/gem5/src/base/fenv.c
/gem5/src/base/loader/elf_object.cc
/gem5/src/base/statistics.cc
/gem5/src/cpu/base.cc
/gem5/src/cpu/kvm/perfevent.cc
/gem5/src/cpu/kvm/x86_cpu.cc
/gem5/src/cpu/minor/decode.cc
/gem5/src/cpu/nativetrace.cc
/gem5/src/cpu/nativetrace.hh
/gem5/src/cpu/o3/inst_queue_impl.hh
/gem5/src/cpu/o3/rename_impl.hh
/gem5/src/cpu/pred/bpred_unit.cc
/gem5/src/cpu/simple/atomic.cc
/gem5/src/cpu/simple/base.cc
/gem5/src/cpu/simple/timing.cc
/gem5/src/dev/alpha/tsunami_cchip.cc
/gem5/src/dev/arm/flash_device.cc
/gem5/src/dev/arm/ufs_device.cc
/gem5/src/dev/intel_8254_timer.cc
/gem5/src/dev/mips/malta_cchip.cc
/gem5/src/dev/virtio/base.cc
/gem5/src/mem/bridge.cc
/gem5/src/mem/cache/prefetch/stride.cc
/gem5/src/mem/dram_ctrl.cc
/gem5/src/mem/physical.cc
/gem5/src/mem/port.cc
/gem5/src/mem/ruby/filters/BulkBloomFilter.cc
/gem5/src/mem/ruby/filters/H3BloomFilter.cc
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiGrainBloomFilter.cc
/gem5/src/mem/ruby/filters/NonCountingBloomFilter.cc
MessageBuffer.cc
garnet/fixed-pipeline/GarnetNetwork_d.cc
garnet/fixed-pipeline/NetworkInterface_d.cc
simple/PerfectSwitch.cc
/gem5/src/mem/ruby/profiler/AccessTraceForAddress.cc
/gem5/src/mem/ruby/slicc_interface/AbstractController.cc
/gem5/src/mem/ruby/structures/AbstractReplacementPolicy.cc
/gem5/src/mem/ruby/structures/BankedArray.cc
/gem5/src/mem/ruby/structures/CacheMemory.cc
/gem5/src/mem/ruby/structures/PseudoLRUPolicy.cc
/gem5/src/mem/ruby/structures/RubyMemoryControl.cc
/gem5/src/mem/ruby/structures/TBETable.hh
/gem5/src/mem/ruby/system/GPUCoalescer.cc
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/VIPERCoalescer.cc
/gem5/src/mem/ruby/system/WeightedLRUPolicy.cc
/gem5/src/mem/serial_link.cc
/gem5/src/mem/stack_dist_calc.cc
/gem5/src/python/swig/pyobject.cc
/gem5/src/sim/backtrace_glibc.cc
/gem5/src/sim/dvfs_handler.cc
/gem5/src/sim/serialize.hh
/gem5/src/sim/syscall_emul.hh
/gem5/tests/test-progs/gpu-hello/src/gpu-hello-kernel.cl
/gem5/tests/test-progs/gpu-hello/src/gpu-hello.cpp
/gem5/tests/test-progs/mwait/mwait.c
/gem5/util/statetrace/arch/amd64/tracechild.cc
/gem5/util/statetrace/arch/arm/tracechild.cc
/gem5/util/statetrace/arch/sparc/tracechild.cc
/gem5/util/tlm/main.cc
/gem5/util/tlm/sc_mm.cc
/gem5/util/tlm/sc_port.cc
/gem5/util/tlm/sc_target.cc
11320:42ecb523c64a 06-Feb-2016 Steve Reinhardt <steve.reinhardt@amd.com>

style: remove trailing whitespace

Result of running 'hg m5style --skip-all --fix-white -a'.


/gem5/configs/common/CacheConfig.py
/gem5/configs/common/Simulation.py
/gem5/configs/example/ruby_mem_test.py
/gem5/src/arch/alpha/isa/decoder.isa
/gem5/src/arch/alpha/linux/linux.hh
/gem5/src/arch/alpha/process.cc
/gem5/src/arch/alpha/tlb.cc
/gem5/src/arch/arm/SConscript
/gem5/src/arch/arm/interrupts.cc
/gem5/src/arch/arm/isa/bitfields.isa
/gem5/src/arch/arm/isa/formats/pred.isa
/gem5/src/arch/arm/linux/linux.hh
/gem5/src/arch/arm/stacktrace.cc
/gem5/src/arch/mips/isa/decoder.isa
/gem5/src/arch/mips/linux/linux.hh
/gem5/src/arch/mips/linux/process.cc
/gem5/src/arch/mips/pagetable.hh
/gem5/src/arch/power/SConscript
/gem5/src/arch/sparc/interrupts.cc
/gem5/src/arch/sparc/linux/linux.hh
/gem5/src/arch/sparc/pagetable.hh
/gem5/src/arch/x86/cpuid.cc
/gem5/src/arch/x86/faults.cc
/gem5/src/arch/x86/insts/micromediaop.hh
/gem5/src/arch/x86/isa/insts/general_purpose/system_calls.py
/gem5/src/arch/x86/isa/insts/romutil.py
/gem5/src/arch/x86/isa/insts/simd64/integer/data_transfer/move.py
/gem5/src/arch/x86/isa/microops/base.isa
/gem5/src/arch/x86/isa/microops/mediaop.isa
/gem5/src/arch/x86/isa/microops/regop.isa
/gem5/src/arch/x86/process.cc
/gem5/src/arch/x86/process.hh
/gem5/src/base/cp_annotate.cc
/gem5/src/base/cp_annotate.hh
/gem5/src/base/cprintf.hh
/gem5/src/base/flags.hh
/gem5/src/base/inet.cc
/gem5/src/base/inet.hh
/gem5/src/base/loader/ecoff_object.cc
/gem5/src/base/loader/elf_object.cc
/gem5/src/base/statistics.cc
/gem5/src/cpu/o3/decode_impl.hh
/gem5/src/cpu/simple/timing.cc
/gem5/src/cpu/testers/directedtest/DirectedGenerator.cc
/gem5/src/cpu/testers/directedtest/DirectedGenerator.hh
/gem5/src/cpu/testers/directedtest/InvalidateGenerator.cc
/gem5/src/cpu/testers/directedtest/InvalidateGenerator.hh
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.cc
/gem5/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
/gem5/src/cpu/testers/directedtest/SeriesRequestGenerator.hh
/gem5/src/cpu/testers/networktest/networktest.cc
/gem5/src/cpu/timebuf.hh
/gem5/src/dev/mc146818.cc
/gem5/src/dev/net/i8254xGBe.cc
/gem5/src/dev/net/i8254xGBe.hh
/gem5/src/dev/net/i8254xGBe_defs.hh
/gem5/src/dev/x86/i8042.cc
/gem5/src/dev/x86/i8254.hh
/gem5/src/dev/x86/intdev.hh
/gem5/src/mem/mport.hh
Topology.cc
Topology.hh
fault_model/FaultModel.cc
fault_model/FaultModel.hh
fault_model/FaultModel.py
fault_model/SConscript
garnet/fixed-pipeline/GarnetLink_d.py
garnet/fixed-pipeline/Router_d.hh
garnet/flexible-pipeline/GarnetLink.py
garnet/flexible-pipeline/GarnetNetwork.hh
garnet/flexible-pipeline/Router.hh
simple/SimpleLink.cc
/gem5/src/mem/slicc/ast/StallAndWaitStatementAST.py
/gem5/src/mem/slicc/ast/TypeFieldEnumAST.py
/gem5/src/mem/slicc/ast/TypeFieldStateAST.py
/gem5/src/python/m5/util/__init__.py
/gem5/src/python/swig/event.i
/gem5/src/sim/Root.py
/gem5/src/sim/eventq.cc
/gem5/src/sim/eventq.hh
/gem5/src/sim/insttracer.hh
/gem5/src/sim/pseudo_inst.cc
/gem5/src/unittest/cprintftest.cc
/gem5/system/alpha/console/console.c
/gem5/tests/configs/memtest-ruby.py
/gem5/util/checkpoint-tester.py
/gem5/util/compile
/gem5/util/m5/m5.c
/gem5/util/qdo
/gem5/util/statetrace/SConstruct
11189:4237221d3e31 06-Nov-2015 Andreas Hansson <andreas.hansson@arm.com>

misc: Appease clang static analyzer

A few minor fixes to issues identified by the clang static analyzer.

11171:60d4dfa3241a 14-Oct-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: remove unused functionalRead() function.

Not required since functional reads cannot rely on messages that are inflight.

11170:1151cfea92e3 14-Oct-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: garnet: flexible: refactor flit

11169:44b5c183c3cd 12-Oct-2015 Andreas Hansson <andreas.hansson@arm.com>

misc: Add explicit overrides and fix other clang >= 3.5 issues

This patch adds explicit overrides as this is now required when using
"-Wall" with clang >= 3.5, the latter now part of the most recent
XCode. The patch consequently removes "virtual" for those methods
where "override" is added. The latter should be enough of an
indication.

As part of this patch, a few minor issues that clang >= 3.5 complains
about are also resolved (unused methods and variables).


/gem5/src/arch/alpha/process.hh
/gem5/src/arch/alpha/system.hh
/gem5/src/arch/alpha/tlb.hh
/gem5/src/arch/arm/table_walker.hh
/gem5/src/arch/arm/tlb.hh
/gem5/src/arch/generic/tlb.hh
/gem5/src/cpu/base.hh
/gem5/src/cpu/checker/cpu.hh
/gem5/src/cpu/minor/cpu.hh
/gem5/src/cpu/minor/func_unit.cc
/gem5/src/cpu/minor/pipeline.hh
/gem5/src/cpu/o3/cpu.hh
/gem5/src/cpu/pred/bpred_unit.hh
/gem5/src/cpu/simple/atomic.hh
/gem5/src/cpu/simple/base.hh
/gem5/src/cpu/simple/timing.hh
/gem5/src/cpu/testers/traffic_gen/traffic_gen.hh
/gem5/src/dev/alpha/backdoor.hh
/gem5/src/dev/alpha/tsunami.hh
/gem5/src/dev/alpha/tsunami_cchip.hh
/gem5/src/dev/alpha/tsunami_io.hh
/gem5/src/dev/alpha/tsunami_pchip.hh
/gem5/src/dev/copy_engine.hh
/gem5/src/dev/disk_image.hh
/gem5/src/dev/dma_device.hh
/gem5/src/dev/etherlink.hh
/gem5/src/dev/ethertap.hh
/gem5/src/dev/i2cbus.hh
/gem5/src/dev/i8254xGBe.hh
/gem5/src/dev/ide_ctrl.hh
/gem5/src/dev/ide_disk.hh
/gem5/src/dev/ns_gige.hh
/gem5/src/dev/pcidev.hh
/gem5/src/dev/sinic.hh
/gem5/src/dev/uart8250.hh
/gem5/src/dev/virtio/fs9p.hh
/gem5/src/mem/abstract_mem.hh
/gem5/src/mem/cache/cache.hh
/gem5/src/mem/cache/tags/base_set_assoc.hh
/gem5/src/mem/cache/tags/fa_lru.hh
/gem5/src/mem/dram_ctrl.hh
/gem5/src/mem/dramsim2.hh
/gem5/src/mem/page_table.hh
garnet/fixed-pipeline/GarnetLink_d.py
garnet/fixed-pipeline/NetworkLink_d.cc
garnet/fixed-pipeline/NetworkLink_d.hh
/gem5/src/mem/ruby/structures/RubyMemoryControl.hh
/gem5/src/mem/ruby/system/DMASequencer.hh
/gem5/src/mem/ruby/system/RubyPort.hh
/gem5/src/mem/ruby/system/RubySystem.hh
/gem5/src/mem/simple_mem.hh
/gem5/src/sim/clock_domain.hh
/gem5/src/sim/process.hh
/gem5/src/sim/root.hh
/gem5/src/sim/sim_events.hh
/gem5/src/sim/system.hh
/gem5/src/sim/ticked_object.hh
/gem5/src/sim/voltage_domain.hh
11124:5d38dc2f7d66 24-Sep-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: simple network: refactor code

Drops an unused variable and marks three variables as const.

11123:a8980f67b3fc 23-Sep-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: garnet: refactor code in network links

11119:3be6083fd774 18-Sep-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: garnet: mark some variables as const

11118:75c1e564a725 18-Sep-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: print addresses in hex
Changeset 4872dbdea907 replaced Address by Addr, but did not make changes to
print statements. So the addresses which were being printed in hex earlier
along with their line address, were now being printed in decimals. This patch
adds a function printAddress(Addr) that can be used to print the address in hex
along with the lines address. This function has been put to use in some of the
places. At other places, change has been made to print just the address in
hex.

11113:5a2e1b1b5c43 16-Sep-2015 Joe Gross <joe.gross@amd.com>

ruby: fix message buffer init order

The recent changes to make MessageBuffers SimObjects required them to be
initialized in a particular order, which could break some protocols. Fix this
by calling initNetQueues on the external nodes of each external link in the
constructor of Network.

This patch also refactors the duplicated code for checking network allocation
and setting net queues (which are called by initNetQueues) from the simple and
garnet networks to be in Network.

11111:6da33e720481 16-Sep-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: message buffer, timer table: significant changes

This patch changes MessageBuffer and TimerTable, two structures used for
buffering messages by components in ruby. These structures would no longer
maintain pointers to clock objects. Functions in these structures have been
changed to take as input current time in Tick. Similarly, these structures
will not operate on Cycle valued latencies for different operations. The
corresponding functions would need to be provided with these latencies by
components invoking the relevant functions. These latencies should also be
in Ticks.

I felt the need for these changes while trying to speed up ruby. The ultimate
aim is to eliminate Consumer class and replace it with an EventManager object in
the MessageBuffer and TimerTable classes. This object would be used for
scheduling events. The event itself would contain information on the object and
function to be invoked.

In hindsight, it seems I should have done this while I was moving away from use
of a single global clock in the memory system. That change led to introduction
of clock objects that replaced the global clock object. It never crossed my
mind that having clock object pointers is not a good design. And now I really
don't like the fact that we have separate consumer, receiver and sender
pointers in message buffers.


/gem5/src/mem/protocol/MESI_Three_Level-L0cache.sm
/gem5/src/mem/protocol/MESI_Three_Level-L1cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-L1cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-L2cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-dir.sm
/gem5/src/mem/protocol/MESI_Two_Level-dma.sm
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MI_example-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dma.sm
/gem5/src/mem/protocol/MOESI_hammer-cache.sm
/gem5/src/mem/protocol/MOESI_hammer-dir.sm
/gem5/src/mem/protocol/MOESI_hammer-dma.sm
/gem5/src/mem/protocol/Network_test-cache.sm
/gem5/src/mem/protocol/Network_test-dir.sm
/gem5/src/mem/protocol/RubySlicc_Defines.sm
/gem5/src/mem/protocol/RubySlicc_Exports.sm
/gem5/src/mem/protocol/RubySlicc_Types.sm
MessageBuffer.cc
MessageBuffer.hh
MessageBuffer.py
garnet/fixed-pipeline/NetworkInterface_d.cc
garnet/flexible-pipeline/NetworkInterface.cc
simple/PerfectSwitch.cc
simple/SimpleNetwork.py
simple/Switch.cc
simple/Throttle.cc
/gem5/src/mem/ruby/slicc_interface/AbstractController.cc
/gem5/src/mem/ruby/structures/TBETable.hh
/gem5/src/mem/ruby/structures/TimerTable.cc
/gem5/src/mem/ruby/structures/TimerTable.hh
/gem5/src/mem/ruby/system/DMASequencer.cc
/gem5/src/mem/ruby/system/RubyPort.cc
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/slicc/ast/EnqueueStatementAST.py
/gem5/src/mem/slicc/ast/ObjDeclAST.py
/gem5/src/mem/slicc/ast/PeekStatementAST.py
/gem5/src/mem/slicc/ast/StallAndWaitStatementAST.py
/gem5/src/mem/slicc/symbols/StateMachine.py
11108:6342ddf6d733 16-Sep-2015 David Hashe <david.hashe@amd.com>

ruby: rename System.{hh,cc} to RubySystem.{hh,cc}

The eventual aim of this change is to pass RubySystem pointers through to
objects generated from the SLICC protocol code.

Because some of these objects need to dereference their RubySystem pointers,
they need access to the System.hh header file.

In src/mem/ruby/SConscript, the MakeInclude function creates single-line header
files in the build directory that do nothing except include the corresponding
header file from the source tree.

However, SLICC also generates a list of header files from its symbol table, and
writes it to mem/protocol/Types.hh in the build directory. This code assumes
that the header file name is the same as the class name.

The end result of this is the many of the generated slicc files try to include
RubySystem.hh, when the file they really need is System.hh. The path of least
resistence is just to rename System.hh to RubySystem.hh.


/gem5/src/mem/ruby/common/Address.cc
/gem5/src/mem/ruby/common/DataBlock.cc
/gem5/src/mem/ruby/filters/BlockBloomFilter.cc
/gem5/src/mem/ruby/filters/BulkBloomFilter.cc
/gem5/src/mem/ruby/filters/LSB_CountingBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiGrainBloomFilter.cc
/gem5/src/mem/ruby/filters/NonCountingBloomFilter.cc
MessageBuffer.cc
Network.cc
garnet/fixed-pipeline/GarnetNetwork_d.cc
garnet/fixed-pipeline/OutVcState_d.cc
garnet/flexible-pipeline/GarnetNetwork.cc
simple/SimpleNetwork.cc
simple/Throttle.cc
simple/Throttle.hh
/gem5/src/mem/ruby/slicc_interface/AbstractController.cc
/gem5/src/mem/ruby/structures/BankedArray.cc
/gem5/src/mem/ruby/structures/BankedArray.hh
/gem5/src/mem/ruby/structures/CacheMemory.cc
/gem5/src/mem/ruby/structures/DirectoryMemory.cc
/gem5/src/mem/ruby/structures/Prefetcher.cc
/gem5/src/mem/ruby/structures/Prefetcher.hh
/gem5/src/mem/ruby/structures/RubyMemoryControl.cc
/gem5/src/mem/ruby/structures/RubyMemoryControl.hh
/gem5/src/mem/ruby/structures/TimerTable.cc
/gem5/src/mem/ruby/structures/WireBuffer.cc
/gem5/src/mem/ruby/system/CacheRecorder.cc
/gem5/src/mem/ruby/system/DMASequencer.cc
/gem5/src/mem/ruby/system/DMASequencer.hh
/gem5/src/mem/ruby/system/RubyPort.hh
/gem5/src/mem/ruby/system/RubySystem.cc
/gem5/src/mem/ruby/system/RubySystem.hh
/gem5/src/mem/ruby/system/RubySystem.py
/gem5/src/mem/ruby/system/SConscript
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/ruby/system/System.hh
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/mem/slicc/symbols/Type.py
11096:efaacec43726 14-Sep-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: topology: refactor code.

11093:8049ffff6d68 12-Sep-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: perfect switch: refactor code
Refactored the code in operateVnet(), moved partly to a new function
operateMessageBuffer(). This is required since a later patch moves to having a
wakeup event per MessageBuffer instead of one event for the entire Switch.

11092:a51ef09e3a78 12-Sep-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: simple network: store Switch* in PerfectSwitch and Throttle
There are two reasons for doing so:

a. provide a source of clock to PerfectSwitch. A follow on patch removes sender
and receiver pointers from MessageBuffer means that the object owning the
buffer should have some way of providing timing info.

b. schedule events. A follow on patch removes the consumer class. So the
PerfectSwitch needs some EventManager object to schedule events on its own.

11065:37e19af67f62 30-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: specify number of vnets for each protocol
The default value for number of virtual networks is being removed. Each protocol
should now specify the value it needs.

11064:386a5200e298 30-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: network: drop member m_in_use

This member indicates whether or not a particular virtual network is in use.
Instead of having a default big value for the number of virtual networks and
then checking whether a virtual network is in use, the next patch removes the
default value and the protocol configuration file would now specify the
number of virtual networks it requires.

Additionally, the patch also refactors some of the code used for computing the
virtual channel next in the round robin order.

11063:b254723105b5 30-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: garnet: mark few functions const in BaseGarnetNetwork.hh

11061:25b53a7195f7 29-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: eliminate type uint64 and int64
These types are being replaced with uint64_t and int64_t.

11049:dfb0aa3f0649 19-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: reverts to changeset: bf82f1f7b040


/gem5/configs/ruby/Ruby.py
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.hh
/gem5/src/cpu/testers/rubytest/RubyTester.hh
/gem5/src/mem/protocol/MESI_Three_Level-L0cache.sm
/gem5/src/mem/protocol/MESI_Three_Level-L1cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-L1cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-L2cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-dir.sm
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_hammer-cache.sm
/gem5/src/mem/protocol/MOESI_hammer-dir.sm
/gem5/src/mem/protocol/RubySlicc_Types.sm
/gem5/src/mem/ruby/common/DataBlock.hh
/gem5/src/mem/ruby/common/Histogram.cc
/gem5/src/mem/ruby/common/Histogram.hh
/gem5/src/mem/ruby/common/SubBlock.cc
/gem5/src/mem/ruby/common/SubBlock.hh
/gem5/src/mem/ruby/common/TypeDefines.hh
/gem5/src/mem/ruby/filters/H3BloomFilter.cc
/gem5/src/mem/ruby/filters/H3BloomFilter.hh
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.hh
MessageBuffer.cc
MessageBuffer.hh
garnet/flexible-pipeline/NetworkInterface.cc
garnet/flexible-pipeline/flit.cc
garnet/flexible-pipeline/flit.hh
simple/PerfectSwitch.cc
simple/PerfectSwitch.hh
simple/SimpleNetwork.cc
simple/SimpleNetwork.hh
simple/Switch.cc
simple/Throttle.cc
simple/Throttle.hh
/gem5/src/mem/ruby/profiler/AccessTraceForAddress.hh
/gem5/src/mem/ruby/profiler/AddressProfiler.cc
/gem5/src/mem/ruby/profiler/AddressProfiler.hh
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/profiler/StoreTrace.cc
/gem5/src/mem/ruby/profiler/StoreTrace.hh
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/structures/AbstractReplacementPolicy.cc
/gem5/src/mem/ruby/structures/AbstractReplacementPolicy.hh
/gem5/src/mem/ruby/structures/BankedArray.cc
/gem5/src/mem/ruby/structures/BankedArray.hh
/gem5/src/mem/ruby/structures/CacheMemory.cc
/gem5/src/mem/ruby/structures/CacheMemory.hh
/gem5/src/mem/ruby/structures/DirectoryMemory.cc
/gem5/src/mem/ruby/structures/DirectoryMemory.hh
/gem5/src/mem/ruby/structures/LRUPolicy.cc
/gem5/src/mem/ruby/structures/LRUPolicy.hh
/gem5/src/mem/ruby/structures/PseudoLRUPolicy.cc
/gem5/src/mem/ruby/structures/PseudoLRUPolicy.hh
/gem5/src/mem/ruby/structures/RubyMemoryControl.cc
/gem5/src/mem/ruby/structures/RubyMemoryControl.hh
/gem5/src/mem/ruby/system/CacheRecorder.cc
/gem5/src/mem/ruby/system/CacheRecorder.hh
/gem5/src/mem/ruby/system/RubySystem.py
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/ruby/system/System.hh
/gem5/src/mem/slicc/ast/EnumDeclAST.py
/gem5/src/mem/slicc/ast/FormalParamAST.py
/gem5/src/mem/slicc/ast/FuncCallExprAST.py
/gem5/src/mem/slicc/ast/FuncDeclAST.py
/gem5/src/mem/slicc/ast/InPortDeclAST.py
/gem5/src/mem/slicc/ast/MethodCallExprAST.py
/gem5/src/mem/slicc/ast/StateDeclAST.py
/gem5/src/mem/slicc/parser.py
/gem5/src/mem/slicc/symbols/Func.py
/gem5/src/mem/slicc/symbols/StateMachine.py
11047:dcf729f0bbfa 14-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: simple network: refactor code

Drops an unused variable and marks three variables as const.

11043:d22f7d7dfd5c 14-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: garnet: flexible: refactor flit

11037:91d6a2d95cf8 14-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: simple network: store Switch* in PerfectSwitch and Throttle

11036:3de670f298b1 14-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: remove unused functionalRead() function.

11035:690ecdba9324 14-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: perfect switch: refactor code

Refactored the code in operateVnet(), moved partly to a new function
operateMessageBuffer().

11031:3815437cb231 14-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: eliminate type uint64 and int64

These types are being replaced with uint64_t and int64_t.

11025:4872dbdea907 14-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: replace Address by Addr
This patch eliminates the type Address defined by the ruby memory system.
This memory system would now use the type Addr that is in use by the
rest of the system.


/gem5/src/cpu/testers/rubytest/Check.cc
/gem5/src/cpu/testers/rubytest/Check.hh
/gem5/src/cpu/testers/rubytest/CheckTable.cc
/gem5/src/cpu/testers/rubytest/CheckTable.hh
/gem5/src/cpu/testers/rubytest/RubyTester.hh
/gem5/src/mem/protocol/MESI_Three_Level-L0cache.sm
/gem5/src/mem/protocol/MESI_Three_Level-L1cache.sm
/gem5/src/mem/protocol/MESI_Three_Level-msg.sm
/gem5/src/mem/protocol/MESI_Two_Level-L1cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-L2cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-dir.sm
/gem5/src/mem/protocol/MESI_Two_Level-dma.sm
/gem5/src/mem/protocol/MESI_Two_Level-msg.sm
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MI_example-dma.sm
/gem5/src/mem/protocol/MI_example-msg.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-msg.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_token-msg.sm
/gem5/src/mem/protocol/MOESI_hammer-cache.sm
/gem5/src/mem/protocol/MOESI_hammer-dir.sm
/gem5/src/mem/protocol/MOESI_hammer-dma.sm
/gem5/src/mem/protocol/MOESI_hammer-msg.sm
/gem5/src/mem/protocol/Network_test-cache.sm
/gem5/src/mem/protocol/Network_test-dir.sm
/gem5/src/mem/protocol/Network_test-msg.sm
/gem5/src/mem/protocol/RubySlicc_ComponentMapping.sm
/gem5/src/mem/protocol/RubySlicc_Defines.sm
/gem5/src/mem/protocol/RubySlicc_Exports.sm
/gem5/src/mem/protocol/RubySlicc_MemControl.sm
/gem5/src/mem/protocol/RubySlicc_Types.sm
/gem5/src/mem/protocol/RubySlicc_Util.sm
/gem5/src/mem/ruby/common/Address.cc
/gem5/src/mem/ruby/common/Address.hh
/gem5/src/mem/ruby/common/SubBlock.cc
/gem5/src/mem/ruby/common/SubBlock.hh
/gem5/src/mem/ruby/common/TypeDefines.hh
/gem5/src/mem/ruby/filters/AbstractBloomFilter.hh
/gem5/src/mem/ruby/filters/BlockBloomFilter.cc
/gem5/src/mem/ruby/filters/BlockBloomFilter.hh
/gem5/src/mem/ruby/filters/BulkBloomFilter.cc
/gem5/src/mem/ruby/filters/BulkBloomFilter.hh
/gem5/src/mem/ruby/filters/GenericBloomFilter.cc
/gem5/src/mem/ruby/filters/GenericBloomFilter.hh
/gem5/src/mem/ruby/filters/H3BloomFilter.cc
/gem5/src/mem/ruby/filters/H3BloomFilter.hh
/gem5/src/mem/ruby/filters/LSB_CountingBloomFilter.cc
/gem5/src/mem/ruby/filters/LSB_CountingBloomFilter.hh
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.hh
/gem5/src/mem/ruby/filters/MultiGrainBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiGrainBloomFilter.hh
/gem5/src/mem/ruby/filters/NonCountingBloomFilter.cc
/gem5/src/mem/ruby/filters/NonCountingBloomFilter.hh
MessageBuffer.cc
MessageBuffer.hh
/gem5/src/mem/ruby/profiler/AccessTraceForAddress.hh
/gem5/src/mem/ruby/profiler/AddressProfiler.cc
/gem5/src/mem/ruby/profiler/AddressProfiler.hh
/gem5/src/mem/ruby/profiler/StoreTrace.cc
/gem5/src/mem/ruby/profiler/StoreTrace.hh
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
/gem5/src/mem/ruby/slicc_interface/AbstractController.cc
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/slicc_interface/RubyRequest.cc
/gem5/src/mem/ruby/slicc_interface/RubyRequest.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
/gem5/src/mem/ruby/structures/CacheMemory.cc
/gem5/src/mem/ruby/structures/CacheMemory.hh
/gem5/src/mem/ruby/structures/DirectoryMemory.cc
/gem5/src/mem/ruby/structures/DirectoryMemory.hh
/gem5/src/mem/ruby/structures/MemoryNode.hh
/gem5/src/mem/ruby/structures/PerfectCacheMemory.hh
/gem5/src/mem/ruby/structures/PersistentTable.cc
/gem5/src/mem/ruby/structures/PersistentTable.hh
/gem5/src/mem/ruby/structures/Prefetcher.cc
/gem5/src/mem/ruby/structures/Prefetcher.hh
/gem5/src/mem/ruby/structures/RubyMemoryControl.cc
/gem5/src/mem/ruby/structures/RubyMemoryControl.hh
/gem5/src/mem/ruby/structures/TBETable.hh
/gem5/src/mem/ruby/structures/TimerTable.cc
/gem5/src/mem/ruby/structures/TimerTable.hh
/gem5/src/mem/ruby/system/CacheRecorder.cc
/gem5/src/mem/ruby/system/CacheRecorder.hh
/gem5/src/mem/ruby/system/DMASequencer.cc
/gem5/src/mem/ruby/system/DMASequencer.hh
/gem5/src/mem/ruby/system/RubyPort.cc
/gem5/src/mem/ruby/system/RubyPort.hh
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/Sequencer.hh
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/slicc/ast/ActionDeclAST.py
/gem5/src/mem/slicc/ast/InPortDeclAST.py
/gem5/src/mem/slicc/ast/StallAndWaitStatementAST.py
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/mem/slicc/symbols/Type.py
11021:e8a6637afa4c 14-Aug-2015 Joel Hestness <jthestness@gmail.com>

ruby: Expose MessageBuffers as SimObjects

Expose MessageBuffers from SLICC controllers as SimObjects that can be
manipulated in Python. This patch has numerous benefits:
1) First and foremost, it exposes MessageBuffers as SimObjects that can be
manipulated in Python code. This allows parameters to be set and checked in
Python code to avoid obfuscating parameters within protocol files. Further, now
as SimObjects, MessageBuffer parameters are printed to config output files as a
way to track parameters across simulations (e.g. buffer sizes)

2) Cleans up special-case code for responseFromMemory buffers, and aligns their
instantiation and use with mandatoryQueue buffers. These two special buffers
are the only MessageBuffers that are exposed to components outside of SLICC
controllers, and they're both slave ends of these buffers. They should be
exposed outside of SLICC in the same way, and this patch does it.

3) Distinguishes buffer-specific parameters from buffer-to-network parameters.
Specifically, buffer size, randomization, ordering, recycle latency, and ports
are all specific to a MessageBuffer, while the virtual network ID and type are
intrinsics of how the buffer is connected to network ports. The former are
specified in the Python object, while the latter are specified in the
controller *.sm files. Unlike buffer-specific parameters, which may need to
change depending on the simulated system structure, buffer-to-network
parameters can be specified statically for most or all different simulated
systems.

10986:4fbe4b0adb4d 20-Jul-2015 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: improved stall and wait debugging

Added dprintfs and asserts for identifying stall and wait bugs.

10983:6036e4555eda 20-Jul-2015 David Hashe <david.hashe@amd.com>

ruby: change router pipeline stages to 2

This patch changes the router pipeline stages from 4 to 2. The
canonical 4-stage router is conservative while a lower-latency router
with look ahead routing and speculative allocation is well acknowledged.

10982:a47c4db94389 20-Jul-2015 David Hashe <david.hashe@amd.com>

ruby: change advance_stage for flit_d

Sets m_stage.second to the second parameter of the function.
Then, for every place where advance_stage is called, adds
a cycle to the argument being passed.

10979:3c11859e4a81 20-Jul-2015 David Hashe <david.hashe@amd.com>

ruby: adds size and empty apis to the msg buffer stallmap

10977:9b3b9be42dd9 20-Jul-2015 David Hashe <david.hashe@amd.com>

ruby: Fix for stallAndWait bug

It was previously possible for a stalled message to be reordered after an
incomming message. This patch ensures that any stalled message stays in its
original request order.

10927:9689ead7b479 22-Jul-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: network: NetworkLink inherits from Consumer now.

10920:58fbfddff18d 10-Jul-2015 Brandon Potter <brandon.potter@amd.com>

ruby: replace global g_abs_controls with per-RubySystem var

This is another step in the process of removing global variables
from Ruby to enable multiple RubySystem instances in a single simulation.

The list of abstract controllers is per-RubySystem and should be
represented that way, rather than as a global.

Since this is the last remaining Ruby global variable, the
src/mem/ruby/Common/Global.* files are also removed.

10919:80069a602c83 10-Jul-2015 Brandon Potter <brandon.potter@amd.com>

ruby: replace global g_system_ptr with per-object pointers

This is another step in the process of removing global variables
from Ruby to enable multiple RubySystem instances in a single simulation.

With possibly multiple RubySystem objects, we can no longer use a global
variable to find "the" RubySystem object. Instead, each Ruby component
has to carry a pointer to the RubySystem object to which it belongs.

10918:dd3ab1f109ad 10-Jul-2015 Brandon Potter <brandon.potter@amd.com>

ruby: replace g_ruby_start with per-RubySystem m_start_cycle

This patch begins the process of removing global variables from the Ruby
source with the goal of eventually allowing users to create multiple Ruby
instances in a single simulation. Currently, users cannot do so because
several global variables and static members are referenced by the RubySystem
object in a way that assumes that there will only ever be a single RubySystem.
These need to be replaced with per-RubySystem equivalents.

This specific patch replaces the global var g_ruby_start, which is used
to calculate throughput statistics for Throttles in simple networks and
links in Garnet networks, with a RubySystem instance var m_start_cycle.

10917:c38f28fad4c3 10-Jul-2015 Brandon Potter <brandon.potter@amd.com>

ruby: remove extra whitespace and correct misspelled words

10895:287285860dd6 04-Jul-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: drop NetworkMessage class

This patch drops the NetworkMessage class. The relevant data members and functions
have been moved to the Message class, which was the parent of NetworkMessage.

10893:f567e80c0714 04-Jul-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: remove message buffer node

This structure's only purpose was to provide a comparison function for
ordering messages in the MessageBuffer. The comparison function is now
being moved to the Message class itself. So we no longer require this
structure.

10837:ecbab2522757 19-May-2015 Joel Hestness <jthestness@gmail.com>

ruby: Fix RubySystem warm-up and cool-down scope

The processes of warming up and cooling down Ruby caches are simulation-wide
processes, not just RubySystem instance-specific processes. Thus, the warm-up
and cool-down variables should be globally visible to any Ruby components
participating in either process. Make these variables static members and track
the warm-up and cool-down processes as appropriate.

This patch also has two side benefits:
1) It removes references to the RubySystem g_system_ptr, which are problematic
for allowing multiple RubySystem instances in a single simulation. Warmup and
cooldown variables being static (global) reduces the need for instance-specific
dereferences through the RubySystem.
2) From the AbstractController, it removes local RubySystem pointers, which are
used inconsistently with other uses of the RubySystem: 11 other uses reference
the RubySystem with the g_system_ptr. Only sequencers have local pointers.

10534:50bbc64efbb8 12-Nov-2014 Mitch Hayenga <mitch.hayenga@arm.com>

mem: Delete unused variable in Garnet NetworkLink

With recent changes OSX clang compilation fails due to an unused variable.

10524:fff17530cef6 06-Nov-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: interface with classic memory controller
This patch is the final in the series. The whole series and this patch in
particular were written with the aim of interfacing ruby's directory controller
with the memory controller in the classic memory system. This is being done
since ruby's memory controller has not being kept up to date with the changes
going on in DRAMs. Classic's memory controller is more up to date and
supports multiple different types of DRAM. This also brings classic and
ruby ever more close. The patch also changes ruby's memory controller to
expose the same interface.


/gem5/configs/common/MemConfig.py
/gem5/configs/example/fs.py
/gem5/configs/example/ruby_direct_test.py
/gem5/configs/example/ruby_mem_test.py
/gem5/configs/example/ruby_random_test.py
/gem5/configs/example/se.py
/gem5/configs/ruby/MESI_Three_Level.py
/gem5/configs/ruby/MESI_Two_Level.py
/gem5/configs/ruby/MI_example.py
/gem5/configs/ruby/MOESI_CMP_directory.py
/gem5/configs/ruby/MOESI_CMP_token.py
/gem5/configs/ruby/MOESI_hammer.py
/gem5/configs/ruby/Ruby.py
/gem5/src/mem/protocol/MESI_Two_Level-dir.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_hammer-dir.sm
/gem5/src/mem/protocol/RubySlicc_Defines.sm
/gem5/src/mem/protocol/RubySlicc_Types.sm
/gem5/src/mem/ruby/SConscript
MessageBuffer.cc
/gem5/src/mem/ruby/slicc_interface/AbstractController.cc
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/slicc_interface/Controller.py
/gem5/src/mem/ruby/structures/Cache.py
/gem5/src/mem/ruby/structures/DirectoryMemory.py
/gem5/src/mem/ruby/structures/MemoryControl.cc
/gem5/src/mem/ruby/structures/MemoryControl.hh
/gem5/src/mem/ruby/structures/MemoryControl.py
/gem5/src/mem/ruby/structures/MemoryNode.cc
/gem5/src/mem/ruby/structures/MemoryNode.hh
/gem5/src/mem/ruby/structures/MemoryVector.hh
/gem5/src/mem/ruby/structures/RubyMemoryControl.cc
/gem5/src/mem/ruby/structures/RubyMemoryControl.hh
/gem5/src/mem/ruby/structures/RubyMemoryControl.py
/gem5/src/mem/ruby/structures/SConscript
/gem5/src/mem/ruby/system/RubySystem.py
/gem5/src/mem/ruby/system/Sequencer.py
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/ruby/system/System.hh
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/python/swig/pyobject.cc
/gem5/tests/configs/memtest-ruby.py
/gem5/tests/configs/pc-simple-timing-ruby.py
/gem5/tests/configs/rubytest-ruby.py
/gem5/tests/configs/simple-timing-mp-ruby.py
/gem5/tests/configs/simple-timing-ruby.py
10446:bb00790bc85c 11-Oct-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: network: garnet: add statistics for different activities
This patch adds some statistics to garnet that record the activity
of certain structures in the on-chip network. These statistics, in a later
patch, will be used for computing the energy consumed by the on-chip network.

10445:e9fe0dc3cda3 11-Oct-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: network: garnet: remove functions for computing power

10444:bbe7f8bd41ae 11-Oct-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: drop Orion network power model

Orion is being dropped from ruby. It would be replaced with DSENT
which has better models. Note that the power / energy numbers reported
after this patch has been applied are not for use.


garnet/fixed-pipeline/InputUnit_d.hh
garnet/fixed-pipeline/NetworkLink_d.hh
garnet/fixed-pipeline/OutputUnit_d.hh
garnet/fixed-pipeline/Router_d.hh
orion/Allocator/Arbiter.cc
orion/Allocator/Arbiter.hh
orion/Allocator/MatrixArbiter.cc
orion/Allocator/MatrixArbiter.hh
orion/Allocator/RRArbiter.cc
orion/Allocator/RRArbiter.hh
orion/Allocator/SConscript
orion/Allocator/SWAllocator.cc
orion/Allocator/SWAllocator.hh
orion/Allocator/VCAllocator.cc
orion/Allocator/VCAllocator.hh
orion/Buffer/AmpUnit.cc
orion/Buffer/AmpUnit.hh
orion/Buffer/BitlineUnit.cc
orion/Buffer/BitlineUnit.hh
orion/Buffer/Buffer.cc
orion/Buffer/Buffer.hh
orion/Buffer/DecoderUnit.cc
orion/Buffer/DecoderUnit.hh
orion/Buffer/MemUnit.cc
orion/Buffer/MemUnit.hh
orion/Buffer/OutdrvUnit.cc
orion/Buffer/OutdrvUnit.hh
orion/Buffer/PrechargeUnit.cc
orion/Buffer/PrechargeUnit.hh
orion/Buffer/Register.cc
orion/Buffer/Register.hh
orion/Buffer/SConscript
orion/Buffer/SRAM.cc
orion/Buffer/SRAM.hh
orion/Buffer/WordlineUnit.cc
orion/Buffer/WordlineUnit.hh
orion/Clock.cc
orion/Clock.hh
orion/ConfigFile.cc
orion/ConfigFile.hh
orion/Crossbar/Crossbar.cc
orion/Crossbar/Crossbar.hh
orion/Crossbar/MatrixCrossbar.cc
orion/Crossbar/MatrixCrossbar.hh
orion/Crossbar/MultreeCrossbar.cc
orion/Crossbar/MultreeCrossbar.hh
orion/Crossbar/SConscript
orion/FlipFlop.cc
orion/FlipFlop.hh
orion/NetworkPower.cc
orion/NetworkPower.hh
orion/OrionConfig.cc
orion/OrionConfig.hh
orion/OrionLink.cc
orion/OrionLink.hh
orion/OrionRouter.cc
orion/OrionRouter.hh
orion/SConscript
orion/TechParameter.cc
orion/TechParameter.hh
orion/Type.hh
orion/Wire.cc
orion/Wire.hh
orion/orion.hh
orion/router.cfg
10370:4466307b8a2a 15-Sep-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: network: revert some of the changes from ad9c042dce54
The changeset ad9c042dce54 made changes to the structures under the network
directory to use a map of buffers instead of vector of buffers.
The reasoning was that not all vnets that are created are used and we
needlessly allocate more buffers than required and then iterate over them
while processing network messages. But the move to map resulted in a slow
down which was pointed out by Andreas Hansson. This patch moves things
back to using vector of message buffers.

10348:c91b23c72d5e 03-Sep-2014 Andreas Hansson <andreas.hansson@arm.com>

base: Use the global Mersenne twister throughout

This patch tidies up random number generation to ensure that it is
done consistently throughout the code base. In essence this involves a
clean-up of Ruby, and some code simplifications in the traffic
generator.

As part of this patch a bunch of skewed distributions (off-by-one etc)
have been fixed.

Note that a single global random number generator is used, and that
the object instantiation order will impact the behaviour (the sequence
of numbers will be unaffected, but if module A calles random before
module B then they would obviously see a different outcome). The
dependency on the instantiation order is true in any case due to the
execution-model of gem5, so we leave it as is. Also note that the
global ranom generator is not thread safe at this point.

Regressions using the memtest, TrafficGen or any Ruby tester are
affected and will be updated accordingly.

10312:08f4deeb5b48 01-Sep-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: PerfectSwitch: moves code to a per vnet helper function
This patch moves code from the wakeup() function to a operateVnet().
The aim is to improve the readiblity of the code.

10311:ad9c042dce54 01-Sep-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: message buffers: significant changes

This patch is the final patch in a series of patches. The aim of the series
is to make ruby more configurable than it was. More specifically, the
connections between controllers are not at all possible (unless one is ready
to make significant changes to the coherence protocol). Moreover the buffers
themselves are magically connected to the network inside the slicc code.
These connections are not part of the configuration file.

This patch makes changes so that these connections will now be made in the
python configuration files associated with the protocols. This requires
each state machine to expose the message buffers it uses for input and output.
So, the patch makes these buffers configurable members of the machines.

The patch drops the slicc code that usd to connect these buffers to the
network. Now these buffers are exposed to the python configuration system
as Master and Slave ports. In the configuration files, any master port
can be connected any slave port. The file pyobject.cc has been modified to
take care of allocating the actual message buffer. This is inline with how
other port connections work.


/gem5/configs/ruby/MESI_Three_Level.py
/gem5/configs/ruby/MESI_Two_Level.py
/gem5/configs/ruby/MI_example.py
/gem5/configs/ruby/MOESI_CMP_directory.py
/gem5/configs/ruby/MOESI_CMP_token.py
/gem5/configs/ruby/MOESI_hammer.py
/gem5/configs/ruby/Network_test.py
/gem5/configs/ruby/Ruby.py
/gem5/src/mem/protocol/MESI_Three_Level-L0cache.sm
/gem5/src/mem/protocol/MESI_Three_Level-L1cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-L1cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-L2cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-dir.sm
/gem5/src/mem/protocol/MESI_Two_Level-dma.sm
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MI_example-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dma.sm
/gem5/src/mem/protocol/MOESI_hammer-cache.sm
/gem5/src/mem/protocol/MOESI_hammer-dir.sm
/gem5/src/mem/protocol/MOESI_hammer-dma.sm
/gem5/src/mem/protocol/Network_test-cache.sm
/gem5/src/mem/protocol/Network_test-dir.sm
Network.cc
Network.hh
Network.py
garnet/BaseGarnetNetwork.cc
garnet/BaseGarnetNetwork.hh
garnet/fixed-pipeline/NetworkInterface_d.cc
garnet/fixed-pipeline/NetworkInterface_d.hh
garnet/flexible-pipeline/NetworkInterface.cc
garnet/flexible-pipeline/NetworkInterface.hh
garnet/flexible-pipeline/Router.cc
garnet/flexible-pipeline/flitBuffer.cc
garnet/flexible-pipeline/flitBuffer.hh
simple/PerfectSwitch.cc
simple/PerfectSwitch.hh
simple/SimpleNetwork.cc
simple/SimpleNetwork.hh
simple/Switch.cc
simple/Switch.hh
simple/Throttle.cc
simple/Throttle.hh
/gem5/src/mem/ruby/slicc_interface/AbstractController.cc
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/python/swig/pyobject.cc
10303:71e0934af9f1 01-Sep-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: network: move getNumNodes() to base class
All the implementations were doing the same things.

10302:0e9e99e6369a 01-Sep-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: eliminate type Time
There is another type Time in src/base class which results in a conflict.

10301:44839e8febbd 01-Sep-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: move files from ruby/system to ruby/structures

The directory ruby/system is crowded and unorganized. Hence, the files the
hold actual physical structures, are being moved to the directory
ruby/structures. This includes Cache Memory, Directory Memory,
Memory Controller, Wire Buffer, TBE Table, Perfect Cache Memory, Timer Table,
Bank Array.

The directory ruby/systems has the glue code that holds these structures
together.


/gem5/src/mem/ruby/SConscript
/gem5/src/mem/ruby/buffers/MessageBuffer.cc
/gem5/src/mem/ruby/buffers/MessageBuffer.hh
/gem5/src/mem/ruby/buffers/MessageBufferNode.cc
/gem5/src/mem/ruby/buffers/MessageBufferNode.hh
/gem5/src/mem/ruby/buffers/SConscript
/gem5/src/mem/ruby/common/MachineID.hh
/gem5/src/mem/ruby/common/NetDest.hh
MessageBuffer.cc
MessageBuffer.hh
MessageBufferNode.cc
MessageBufferNode.hh
SConscript
garnet/BaseGarnetNetwork.cc
garnet/fixed-pipeline/NetworkInterface_d.cc
garnet/flexible-pipeline/NetworkInterface.cc
simple/PerfectSwitch.cc
simple/SimpleNetwork.cc
simple/Switch.cc
simple/Throttle.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/recorder/CacheRecorder.cc
/gem5/src/mem/ruby/recorder/CacheRecorder.hh
/gem5/src/mem/ruby/recorder/SConscript
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
/gem5/src/mem/ruby/structures/AbstractReplacementPolicy.hh
/gem5/src/mem/ruby/structures/BankedArray.cc
/gem5/src/mem/ruby/structures/BankedArray.hh
/gem5/src/mem/ruby/structures/Cache.py
/gem5/src/mem/ruby/structures/CacheMemory.cc
/gem5/src/mem/ruby/structures/CacheMemory.hh
/gem5/src/mem/ruby/structures/DirectoryMemory.cc
/gem5/src/mem/ruby/structures/DirectoryMemory.hh
/gem5/src/mem/ruby/structures/DirectoryMemory.py
/gem5/src/mem/ruby/structures/LRUPolicy.hh
/gem5/src/mem/ruby/structures/MemoryControl.cc
/gem5/src/mem/ruby/structures/MemoryControl.hh
/gem5/src/mem/ruby/structures/MemoryControl.py
/gem5/src/mem/ruby/structures/MemoryNode.cc
/gem5/src/mem/ruby/structures/MemoryNode.hh
/gem5/src/mem/ruby/structures/MemoryVector.hh
/gem5/src/mem/ruby/structures/PerfectCacheMemory.hh
/gem5/src/mem/ruby/structures/PersistentTable.cc
/gem5/src/mem/ruby/structures/PersistentTable.hh
/gem5/src/mem/ruby/structures/Prefetcher.hh
/gem5/src/mem/ruby/structures/PseudoLRUPolicy.hh
/gem5/src/mem/ruby/structures/RubyMemoryControl.cc
/gem5/src/mem/ruby/structures/RubyMemoryControl.hh
/gem5/src/mem/ruby/structures/RubyMemoryControl.py
/gem5/src/mem/ruby/structures/SConscript
/gem5/src/mem/ruby/structures/SparseMemory.cc
/gem5/src/mem/ruby/structures/SparseMemory.hh
/gem5/src/mem/ruby/structures/TBETable.hh
/gem5/src/mem/ruby/structures/TimerTable.cc
/gem5/src/mem/ruby/structures/TimerTable.hh
/gem5/src/mem/ruby/structures/WireBuffer.cc
/gem5/src/mem/ruby/structures/WireBuffer.hh
/gem5/src/mem/ruby/structures/WireBuffer.py
/gem5/src/mem/ruby/system/AbstractReplacementPolicy.hh
/gem5/src/mem/ruby/system/BankedArray.cc
/gem5/src/mem/ruby/system/BankedArray.hh
/gem5/src/mem/ruby/system/Cache.py
/gem5/src/mem/ruby/system/CacheMemory.cc
/gem5/src/mem/ruby/system/CacheMemory.hh
/gem5/src/mem/ruby/system/CacheRecorder.cc
/gem5/src/mem/ruby/system/CacheRecorder.hh
/gem5/src/mem/ruby/system/DirectoryMemory.cc
/gem5/src/mem/ruby/system/DirectoryMemory.hh
/gem5/src/mem/ruby/system/DirectoryMemory.py
/gem5/src/mem/ruby/system/LRUPolicy.hh
/gem5/src/mem/ruby/system/MachineID.hh
/gem5/src/mem/ruby/system/MemoryControl.cc
/gem5/src/mem/ruby/system/MemoryControl.hh
/gem5/src/mem/ruby/system/MemoryControl.py
/gem5/src/mem/ruby/system/MemoryNode.cc
/gem5/src/mem/ruby/system/MemoryNode.hh
/gem5/src/mem/ruby/system/MemoryVector.hh
/gem5/src/mem/ruby/system/PerfectCacheMemory.hh
/gem5/src/mem/ruby/system/PersistentTable.cc
/gem5/src/mem/ruby/system/PersistentTable.hh
/gem5/src/mem/ruby/system/PseudoLRUPolicy.hh
/gem5/src/mem/ruby/system/RubyMemoryControl.cc
/gem5/src/mem/ruby/system/RubyMemoryControl.hh
/gem5/src/mem/ruby/system/RubyMemoryControl.py
/gem5/src/mem/ruby/system/RubyPort.hh
/gem5/src/mem/ruby/system/SConscript
/gem5/src/mem/ruby/system/Sequencer.hh
/gem5/src/mem/ruby/system/SparseMemory.cc
/gem5/src/mem/ruby/system/SparseMemory.hh
/gem5/src/mem/ruby/system/System.hh
/gem5/src/mem/ruby/system/TBETable.hh
/gem5/src/mem/ruby/system/TimerTable.cc
/gem5/src/mem/ruby/system/TimerTable.hh
/gem5/src/mem/ruby/system/WireBuffer.cc
/gem5/src/mem/ruby/system/WireBuffer.hh
/gem5/src/mem/ruby/system/WireBuffer.py
/gem5/src/mem/slicc/symbols/Type.py
10226:056363356d15 23-May-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: message buffer: drop dequeue_getDelayCycles()
The functionality of updating and returning the delay cycles would now be
performed by the dequeue() function itself.

10122:1268f1fd2714 20-Mar-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: garnet: convert network interfaces into clocked objects
This helps in configuring the network interfaces from the python script and
these objects no longer rely on the network object for the timing information.

10086:bd1089db3a88 23-Feb-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: remove few not required #includes

10082:70f350b13ec0 21-Feb-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: network: move message buffers to base network class.

10081:26670ac8244e 21-Feb-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: network: garnet: fixed: removes net_ptr from links

10079:fb7859dc2273 20-Feb-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: network: garnet: fixed: removes next cycle functions
At several places, there are functions that take a cycle value as input
and performs some computation. Along with each such function, another
function was being defined that simply added one more cycle to input and
computed the same function. This patch removes this second copy of the
function. Places where these functions were being called have been updated
to use the original function with argument being current cycle + 1.

10078:9400a90ec5d1 20-Feb-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: controller: slight code refactoring

10076:f81d94b53661 20-Feb-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: network: removes unused code.

10074:0e013fa647ac 20-Feb-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: message buffer: removes some unecessary functions.

10005:8c2b0dc16ccd 04-Jan-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: add support for clusters

A cluster over here means a set of controllers that can be accessed only by a
certain set of cores. For example, consider a two level hierarchy. Assume
there are 4 L1 controllers (private) and 2 L2 controllers. We can have two
different hierarchies here:

a. the address space is partitioned between the two L2 controllers. Each L1
controller accesses both the L2 controllers. In this case, each L1 controller
is a cluster initself.

b. both the L2 controllers can cache any address. An L1 controller has access
to only one of the L2 controllers. In this case, each L2 controller
along with the L1 controllers that access it, form a cluster.

This patch allows for each controller to have a cluster ID, which is 0 by
default. By setting the cluster ID properly, one can instantiate hierarchies
with clusters. Note that the coherence protocol might have to be changed as
well.

9946:ebd44da818d5 30-Oct-2013 Emilio Castillo <castilloe@unican.es>

ruby: Fixed a deadlock when restoring a checkpoint with garnet
This patch fixes a problem where in Garnet, the enqueue time in the
VCallocator and the SWallocator which is of type Cycles was being stored
inside a variable with int type.

This lead to a known problem restoring checkpoints with garnet & the fixed
pipeline enabled. That value was really big and didn't fit in the variable
overflowing it, therefore some conditions on the VC allocation stage & the
SW allocation stage were not met and the packets didn't advance through the
network, leading to a deadlock panic right after the checkpoint was restored.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>

9869:a204694db4f9 11-Sep-2013 Joel Hestness <jthestness@gmail.com>

ruby: Fix Topology throttle connections

The Topology source sets up input and output buffers for each of the external
nodes of a topology by indexing on Ruby's generated controller unique IDs.
These unique IDs are found by adding the MachineType_base_number to the version
number of each controller (see any generated *_Controller.cc - init() calls
getToNetQueue and getFromNetQueue using m_version + base). However, the
Topology object used the cntrl_id - which is required to be unique across all
controllers - to index the controllers list as they are being connected to
their input and output buffers. If the cntrl_ids did not match the Ruby unique
ID, the throttles end up connected to incorrectly indexed nodes in the network,
resulting in packets traversing incorrect network paths. This patch fixes the
Topology indexing scheme by using the Ruby unique ID to match that of the
SimpleNetwork buffer vectors.

9866:94dac7d7bb88 11-Sep-2013 Joel Hestness <jthestness@gmail.com>

ruby: Statically allocate stats in SimpleNetwork, Switch, Throttle

The previous changeset (9863:9483739f83ee) used STL vector containers to
dynamically allocate stats in the Ruby SimpleNetwork, Switch and Throttle. For
gcc versions before at least 4.6.3, this causes the standard vector allocator
to call Stats copy constructors (a no-no, since stats should be allocated in
the body of each SimObject instance). Since the size of these stats arrays is
known at compile time (NOTE: after code generation), this patch changes their
allocation to be static rather than using an STL vector.

9863:9483739f83ee 06-Sep-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: network: convert to gem5 style stats

9860:7248fa3e6e0f 06-Sep-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: remove undefined message size type
This message size type does not work well with one of the statistical
variables. It also seems unnecessary.

9859:1bd310386038 06-Sep-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: network: removes reset functionality

9858:f2417ecf5cc9 06-Sep-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: network: shorten variable names

9799:5aed42e54180 28-Jun-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: network: remove reconfiguration code
This code seems not to be of any use now. There is no path in the simulator
that allows for reconfiguring the network. A better approach would be to
take a checkpoint and start the simulation from the checkpoint with the new
configuration.

9670:fa4eedccce17 23-Apr-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: patch checkpoint restore with garnet
Due to recent changes to clocking system in Ruby and the way Ruby restores
state from a checkpoint, garnet was failing to run from a checkpointed state.
The problem is that Ruby resets the time to zero while warming up the caches.
If any component records a local copy of the time (read calls curCycle())
before the simulation has started, then that component will not operate until
that time is reached. In the context of this particular patch, the Garnet
Network class calls curCycle() at multiple places. Any non-operational
component can block in requests in the memory system, which the system
interprets as a deadlock. This patch makes changes so that Garnet can
successfully run from checkpointed state.

It adds a globally visible time at which the actual execution started. This
time is initialized in RubySystem::startup() function. This variable is only
meant for components with in Ruby. This replaces the private variable that
was maintained within Garnet since it is not possible to figure out the
correct time when the value of this variable can be set.

The patch also does away with all cases where curCycle() is called with in
some Ruby component before the system has actually started executing. This
is required due to the quirky manner in which ruby restores from a checkpoint.

9600:34df8f24be7e 22-Mar-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: consumer: avoid using receiver side clock
A set of patches was recently committed to allow multiple clock domains
in ruby. In those patches, I had inadvertently made an incorrect use of
the clocks. Suppose object A needs to schedule an event on object B. It
was possible that A accesses B's clock to schedule the event. This is not
possible in actual system. Hence, changes are being to the Consumer class
so as to avoid such happenings. Note that in a multi eventq simulation,
this can possibly lead to an incorrect simulation.

There are two functions in the Consumer class that are used for scheduling
events. The first function takes in the relative delay over the current time
as the argument and adds the current time to it for scheduling the event.
The second function takes in the absolute time (in ticks) for scheduling the
event. The first function is now being moved to protected section of the
class so that only objects of the derived classes can use it. All other
objects will have to specify absolute time while scheduling an event
for some consumer.

9594:219ad5fe8c04 22-Mar-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: convert Topology to regular class
The Topology class in Ruby does not need to inherit from SimObject class.
This patch turns it into a regular class. The topology object is now created
in the constructor of the Network class. All the parameters for the topology
class have been moved to the network class.

9593:9441ca79f3c8 22-Mar-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: network: move routers from topology to network

9580:d1e6329cd367 07-Mar-2013 Andreas Hansson <andreas.hansson@arm.com>

ruby: Fix gcc 4.8 maybe-uninitialized compilation error

This patch fixes the one-and-only gcc 4.8 compilation error, being a
warning about "maybe uninitialized" in Orion.

9576:2c094ad4dc70 06-Mar-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: garnet: fixed: implement functional access

9560:322472967603 19-Feb-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: remove unused variable m_print_config in class Topology

9557:8666e81607a6 19-Feb-2013 Andreas Hansson <andreas.hansson@arm.com>

scons: Fix warnings issued by clang 3.2svn (XCode 4.6)

This patch fixes the warnings that clang3.2svn emit due to the "-Wall"
flag. There is one case of an uninitialised value in the ARM neon ISA
description, and then a whole range of unused private fields that are
pruned.

9554:406fbcf60223 19-Feb-2013 Andreas Hansson <andreas.hansson@arm.com>

scons: Add warning for missing declarations

This patch enables warnings for missing declarations. To avoid issues
with SWIG-generated code, the warning is only applied to non-SWIG
code.

9550:e0e2c8f83d08 19-Feb-2013 Andreas Hansson <andreas.hansson@arm.com>

scons: Fix up numerous warnings about name shadowing

This patch address the most important name shadowing warnings (as
produced when using gcc/clang with -Wshadow). There are many
locations where constructor parameters and function parameters shadow
local variables, but these are left unchanged.

9508:dde110931867 10-Feb-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: enable multiple clock domains
This patch allows ruby to have multiple clock domains. As I understand
with this patch, controllers can have different frequencies. The entire
network needs to run at a single frequency.

The idea is that with in an object, time is treated in terms of cycles.
But the messages that are passed from one entity to another should contain
the time in Ticks. As of now, this is only true for the message buffers,
but not for the links in the network. As I understand the code, all the
entities in different networks (simple, garnet-fixed, garnet-flexible) should
be clocked at the same frequency.

Another problem is that the directory controller has to operate at the same
frequency as the ruby system. This is because the memory controller does
not make use of the Message Buffer, and instead implements a buffer of its
own. So, it has no idea of the frequency at which the directory controller
is operating and uses ruby system's frequency for scheduling events.

9506:f5335ac67f41 10-Feb-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: replace Time with Cycles in garnet fixed and flexible

9500:9c3e3d1c7a87 10-Feb-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: replace Time with Cycles in Message class
Concomitant changes are being committed as well, including the io operator<<
for the Cycles class.

9499:b03b556a8fbb 10-Feb-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: replaces Time with Cycles in many places
The patch started of with replacing Time with Cycles in the Consumer class.
But to get ruby to compile, the rest of the changes had to be carried out.
Subsequent patches will further this process, till we completely replace
Time with Cycles.


/gem5/src/mem/protocol/MESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MESI_CMP_directory-dma.sm
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MI_example-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dma.sm
/gem5/src/mem/protocol/MOESI_hammer-cache.sm
/gem5/src/mem/protocol/MOESI_hammer-dir.sm
/gem5/src/mem/protocol/MOESI_hammer-dma.sm
/gem5/src/mem/protocol/Network_test-cache.sm
/gem5/src/mem/protocol/RubySlicc_Exports.sm
/gem5/src/mem/protocol/RubySlicc_Types.sm
/gem5/src/mem/protocol/RubySlicc_Util.sm
/gem5/src/mem/ruby/buffers/MessageBuffer.cc
/gem5/src/mem/ruby/buffers/MessageBuffer.hh
/gem5/src/mem/ruby/buffers/MessageBufferNode.hh
/gem5/src/mem/ruby/common/Consumer.cc
/gem5/src/mem/ruby/common/Consumer.hh
BasicLink.hh
BasicLink.py
garnet/fixed-pipeline/GarnetLink_d.py
garnet/fixed-pipeline/InputUnit_d.hh
garnet/fixed-pipeline/NetworkInterface_d.cc
garnet/fixed-pipeline/NetworkLink_d.hh
garnet/fixed-pipeline/OutputUnit_d.hh
garnet/fixed-pipeline/Router_d.cc
garnet/fixed-pipeline/SWallocator_d.cc
garnet/fixed-pipeline/Switch_d.cc
garnet/fixed-pipeline/VCallocator_d.cc
garnet/flexible-pipeline/GarnetLink.py
garnet/flexible-pipeline/NetworkInterface.cc
garnet/flexible-pipeline/NetworkLink.hh
garnet/flexible-pipeline/Router.cc
garnet/flexible-pipeline/Router.hh
simple/PerfectSwitch.cc
simple/Switch.cc
simple/Switch.hh
simple/Throttle.cc
simple/Throttle.hh
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/slicc_interface/Controller.py
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
/gem5/src/mem/ruby/system/Cache.py
/gem5/src/mem/ruby/system/CacheMemory.hh
/gem5/src/mem/ruby/system/RubyMemoryControl.cc
/gem5/src/mem/ruby/system/RubyMemoryControl.hh
/gem5/src/mem/ruby/system/RubyMemoryControl.py
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/TimerTable.cc
/gem5/src/mem/ruby/system/TimerTable.hh
/gem5/src/mem/ruby/system/WireBuffer.cc
/gem5/src/mem/ruby/system/WireBuffer.hh
/gem5/src/mem/slicc/ast/EnqueueStatementAST.py
/gem5/src/mem/slicc/ast/FuncCallExprAST.py
/gem5/src/mem/slicc/ast/InfixOperatorExprAST.py
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/mem/slicc/symbols/Type.py
9497:2759161b9d7f 10-Feb-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: modifies histogram add() function
This patch modifies the Histogram class' add() function so that it can add
linear histograms as well. The function assumes that the left end point of
the ranges of the two histograms are the same. It also assumes that when
the ranges of the two histogram are changed to accomodate an element not in
the range, the factor used in changing the range is same for both the
histograms.

This function is then used in removing one of the calls to the global
profiler*. The histograms for recording the delays incurred in processing
different requests are now maintained by the controllers. The profiler
adds these histograms when it needs to print the stats.

9496:28d88a0fda74 10-Feb-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: record fully busy cycle with in the controller
This patch does several things. First, the counter for fully busy cycles for a
controller is now kept with in the controller, instead of being part of the profiler.
Second, the topology class no longer keeps an array of controllers which was only
used for printing stats. Instead, ruby system will now ask each controller to print
the stats. Thirdly, the statistical variable for recording how many different types
were created is being moved in to the controller from the profiler. Note that for
printing, the profiler will collate results from different controllers.

9475:736909f5c13b 17-Jan-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: remove calls to g_system_ptr->getTime()
This patch further removes calls to g_system_ptr->getTime() where ever other
clocked objects are available for providing current time.

9466:23e13ad7091f 14-Jan-2013 Nilay Vaish <nilay@cs.wisc.edu>

Ruby: remove reference to g_system_ptr from class Message
This patch was initiated so as to remove reference to g_system_ptr,
the pointer to Ruby System that is used for getting the current time.
That simple change actual requires changing a lot many things in slicc and
garnet. All these changes are related to how time is handled.

In most of the places, g_system_ptr has been replaced by another clock
object. The changes have been done under the assumption that all the
components in the memory system are on the same clock frequency, but the
actual clocks might be distributed.


/gem5/src/mem/ruby/common/Global.hh
garnet/BaseGarnetNetwork.cc
garnet/fixed-pipeline/GarnetNetwork_d.cc
garnet/fixed-pipeline/InputUnit_d.cc
garnet/fixed-pipeline/InputUnit_d.hh
garnet/fixed-pipeline/NetworkInterface_d.cc
garnet/fixed-pipeline/NetworkLink_d.cc
garnet/fixed-pipeline/NetworkLink_d.hh
garnet/fixed-pipeline/OutputUnit_d.cc
garnet/fixed-pipeline/OutputUnit_d.hh
garnet/fixed-pipeline/RoutingUnit_d.cc
garnet/fixed-pipeline/SWallocator_d.cc
garnet/fixed-pipeline/Switch_d.cc
garnet/fixed-pipeline/VCallocator_d.cc
garnet/fixed-pipeline/VirtualChannel_d.cc
garnet/fixed-pipeline/VirtualChannel_d.hh
garnet/fixed-pipeline/flitBuffer_d.cc
garnet/fixed-pipeline/flitBuffer_d.hh
garnet/fixed-pipeline/flit_d.cc
garnet/fixed-pipeline/flit_d.hh
garnet/flexible-pipeline/GarnetNetwork.cc
garnet/flexible-pipeline/NetworkInterface.cc
garnet/flexible-pipeline/NetworkLink.cc
garnet/flexible-pipeline/Router.cc
garnet/flexible-pipeline/flit.cc
garnet/flexible-pipeline/flit.hh
garnet/flexible-pipeline/flitBuffer.cc
garnet/flexible-pipeline/flitBuffer.hh
orion/NetworkPower.cc
/gem5/src/mem/ruby/slicc_interface/Message.hh
/gem5/src/mem/ruby/slicc_interface/NetworkMessage.hh
/gem5/src/mem/ruby/slicc_interface/RubyRequest.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
/gem5/src/mem/ruby/structures/Prefetcher.hh
/gem5/src/mem/ruby/system/DMASequencer.cc
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/WireBuffer.cc
/gem5/src/mem/slicc/ast/EnqueueStatementAST.py
/gem5/src/mem/slicc/symbols/Type.py
9465:4ae4f3f4b870 14-Jan-2013 Nilay Vaish <nilay@cs.wisc.edu>

Ruby: use ClockedObject in Consumer class
Many Ruby structures inherit from the Consumer, which is used for scheduling
events. The Consumer used to relay on an Event Manager for scheduling events
and on g_system_ptr for time. With this patch, the Consumer will now use a
ClockedObject to schedule events and to query for current time. This resulted
in several structures being converted from SimObjects to ClockedObjects. Also,
the MessageBuffer class now requires a pointer to a ClockedObject so as to
query for time.

9389:8f8c911ab5a7 07-Jan-2013 Andreas Hansson <andreas.hansson@arm.com>

ruby: Fix missing cxx_header in Switch

This patch addresses a warning related to the swig interface
generation for the Switch class. The cxx_header is now specified
correctly, and the header in question has got a few includes added to
make it all compile.

9356:b279bad40aa3 16-Nov-2012 Nilay Vaish <nilay@cs.wisc.edu>

sim: have a curTick per eventq
This patch adds a _curTick variable to an eventq. This variable is updated
whenever an event is serviced in function serviceOne(), or all events upto
a particular time are processed in function serviceEvents(). This change
helps when there are eventqs that do not make use of curTick for scheduling
events.

9354:7691ec6b173b 10-Nov-2012 Nilay Vaish <nilay@cs.wisc.edu>

ruby: support functional accesses in garnet flexible network

9338:97b4a2be1e5b 02-Nov-2012 Andreas Sandberg <Andreas.Sandberg@arm.com>

sim: Include object header files in SWIG interfaces

When casting objects in the generated SWIG interfaces, SWIG uses
classical C-style casts ( (Foo *)bar; ). In some cases, this can
degenerate into the equivalent of a reinterpret_cast (mainly if only a
forward declaration of the type is available). This usually works for
most compilers, but it is known to break if multiple inheritance is
used anywhere in the object hierarchy.

This patch introduces the cxx_header attribute to Python SimObject
definitions, which should be used to specify a header to include in
the SWIG interface. The header should include the declaration of the
wrapped object. We currently don't enforce header the use of the
header attribute, but a warning will be generated for objects that do
not use it.


/gem5/src/SConscript
/gem5/src/arch/alpha/AlphaInterrupts.py
/gem5/src/arch/alpha/AlphaSystem.py
/gem5/src/arch/alpha/AlphaTLB.py
/gem5/src/arch/arm/ArmInterrupts.py
/gem5/src/arch/arm/ArmNativeTrace.py
/gem5/src/arch/arm/ArmSystem.py
/gem5/src/arch/arm/ArmTLB.py
/gem5/src/arch/mips/MipsInterrupts.py
/gem5/src/arch/mips/MipsSystem.py
/gem5/src/arch/mips/MipsTLB.py
/gem5/src/arch/power/PowerInterrupts.py
/gem5/src/arch/power/PowerTLB.py
/gem5/src/arch/sparc/SparcInterrupts.py
/gem5/src/arch/sparc/SparcNativeTrace.py
/gem5/src/arch/sparc/SparcSystem.py
/gem5/src/arch/sparc/SparcTLB.py
/gem5/src/arch/x86/X86LocalApic.py
/gem5/src/arch/x86/X86NativeTrace.py
/gem5/src/arch/x86/X86System.py
/gem5/src/arch/x86/X86TLB.py
/gem5/src/arch/x86/bios/ACPI.py
/gem5/src/arch/x86/bios/E820.py
/gem5/src/arch/x86/bios/IntelMP.py
/gem5/src/arch/x86/bios/SMBios.py
/gem5/src/base/CPA.py
/gem5/src/base/vnc/Vnc.py
/gem5/src/cpu/BaseCPU.py
/gem5/src/cpu/CheckerCPU.py
/gem5/src/cpu/ExeTracer.py
/gem5/src/cpu/FuncUnit.py
/gem5/src/cpu/IntelTrace.py
/gem5/src/cpu/IntrControl.py
/gem5/src/cpu/LegionTrace.py
/gem5/src/cpu/NativeTrace.py
/gem5/src/cpu/inorder/InOrderCPU.py
/gem5/src/cpu/inorder/InOrderTrace.py
/gem5/src/cpu/inteltrace.hh
/gem5/src/cpu/o3/FUPool.py
/gem5/src/cpu/simple/AtomicSimpleCPU.py
/gem5/src/cpu/simple/BaseSimpleCPU.py
/gem5/src/cpu/simple/TimingSimpleCPU.py
/gem5/src/cpu/static_inst.hh
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.py
/gem5/src/cpu/testers/memtest/MemTest.py
/gem5/src/cpu/testers/networktest/NetworkTest.py
/gem5/src/cpu/testers/rubytest/RubyTester.py
/gem5/src/cpu/testers/traffic_gen/TrafficGen.py
/gem5/src/dev/BadDevice.py
/gem5/src/dev/CopyEngine.py
/gem5/src/dev/Device.py
/gem5/src/dev/DiskImage.py
/gem5/src/dev/Ethernet.py
/gem5/src/dev/Ide.py
/gem5/src/dev/Pci.py
/gem5/src/dev/Platform.py
/gem5/src/dev/SimpleDisk.py
/gem5/src/dev/Terminal.py
/gem5/src/dev/Uart.py
/gem5/src/dev/alpha/AlphaBackdoor.py
/gem5/src/dev/alpha/Tsunami.py
/gem5/src/dev/alpha/tsunami_io.hh
/gem5/src/dev/arm/RealView.py
/gem5/src/dev/arm/pl011.hh
/gem5/src/dev/arm/realview.hh
/gem5/src/dev/arm/timer_cpulocal.hh
/gem5/src/dev/copy_engine.hh
/gem5/src/dev/mips/Malta.py
/gem5/src/dev/mips/malta_io.hh
/gem5/src/dev/sparc/T1000.py
/gem5/src/dev/x86/Cmos.py
/gem5/src/dev/x86/I8042.py
/gem5/src/dev/x86/I82094AA.py
/gem5/src/dev/x86/I8237.py
/gem5/src/dev/x86/I8254.py
/gem5/src/dev/x86/I8259.py
/gem5/src/dev/x86/Pc.py
/gem5/src/dev/x86/PcSpeaker.py
/gem5/src/dev/x86/SouthBridge.py
/gem5/src/dev/x86/X86IntPin.py
/gem5/src/dev/x86/speaker.hh
/gem5/src/mem/AbstractMemory.py
/gem5/src/mem/AddrMapper.py
/gem5/src/mem/Bridge.py
/gem5/src/mem/Bus.py
/gem5/src/mem/CommMonitor.py
/gem5/src/mem/MemObject.py
/gem5/src/mem/SimpleDRAM.py
/gem5/src/mem/SimpleMemory.py
/gem5/src/mem/cache/BaseCache.py
/gem5/src/mem/cache/prefetch/Prefetcher.py
/gem5/src/mem/cache/tags/iic_repl/Repl.py
BasicLink.py
BasicRouter.py
Network.py
fault_model/FaultModel.py
garnet/BaseGarnetNetwork.py
garnet/fixed-pipeline/GarnetLink_d.py
garnet/fixed-pipeline/GarnetNetwork_d.py
garnet/fixed-pipeline/GarnetRouter_d.py
garnet/flexible-pipeline/GarnetLink.py
garnet/flexible-pipeline/GarnetNetwork.py
garnet/flexible-pipeline/GarnetRouter.py
simple/SimpleLink.py
simple/SimpleNetwork.py
/gem5/src/mem/ruby/profiler/Profiler.py
/gem5/src/mem/ruby/slicc_interface/Controller.py
/gem5/src/mem/ruby/system/Cache.py
/gem5/src/mem/ruby/system/DirectoryMemory.py
/gem5/src/mem/ruby/system/MemoryControl.py
/gem5/src/mem/ruby/system/RubyMemoryControl.py
/gem5/src/mem/ruby/system/RubySystem.py
/gem5/src/mem/ruby/system/Sequencer.py
/gem5/src/mem/ruby/system/WireBuffer.py
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/python/m5/SimObject.py
/gem5/src/sim/BaseTLB.py
/gem5/src/sim/ClockedObject.py
/gem5/src/sim/InstTracer.py
/gem5/src/sim/Process.py
/gem5/src/sim/Root.py
/gem5/src/sim/System.py
9302:c2e70a9bc340 15-Oct-2012 Nilay Vaish <nilay@cs.wisc.edu>

ruby: improved support for functional accesses
This patch adds support to different entities in the ruby memory system
for more reliable functional read/write accesses. Only the simple network
has been augmented as of now. Later on Garnet will also support functional
accesses.
The patch adds functional access code to all the different types of messages
that protocols can send around. These messages are functionally accessed
by going through the buffers maintained by the network entities.
The patch also rectifies some of the bugs found in coherence protocols while
testing the patch.

With this patch applied, functional writes always succeed. But functional
reads can still fail.


/gem5/configs/example/ruby_mem_test.py
/gem5/src/mem/protocol/MESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MESI_CMP_directory-msg.sm
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MI_example-msg.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-msg.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_token-msg.sm
/gem5/src/mem/protocol/MOESI_hammer-cache.sm
/gem5/src/mem/protocol/MOESI_hammer-dir.sm
/gem5/src/mem/protocol/MOESI_hammer-msg.sm
/gem5/src/mem/protocol/Network_test-msg.sm
/gem5/src/mem/protocol/RubySlicc_Exports.sm
/gem5/src/mem/protocol/RubySlicc_MemControl.sm
/gem5/src/mem/ruby/buffers/MessageBuffer.cc
/gem5/src/mem/ruby/buffers/MessageBuffer.hh
/gem5/src/mem/ruby/buffers/MessageBufferNode.hh
Network.hh
simple/PerfectSwitch.cc
simple/SimpleNetwork.cc
simple/SimpleNetwork.hh
simple/Switch.cc
simple/Switch.hh
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/slicc_interface/Message.hh
/gem5/src/mem/ruby/slicc_interface/NetworkMessage.hh
/gem5/src/mem/ruby/slicc_interface/RubyRequest.cc
/gem5/src/mem/ruby/slicc_interface/RubyRequest.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
/gem5/src/mem/ruby/system/MemoryControl.cc
/gem5/src/mem/ruby/system/MemoryControl.hh
/gem5/src/mem/ruby/system/RubyMemoryControl.cc
/gem5/src/mem/ruby/system/RubyMemoryControl.hh
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/slicc/ast/TypeDeclAST.py
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/mem/slicc/symbols/SymbolTable.py
/gem5/src/mem/slicc/symbols/Type.py
9275:ef43e69c837a 02-Oct-2012 Nilay Vaish <nilay@cs.wisc.edu>

ruby: makes some members non-static
This patch makes some of the members (profiler, network, memory vector)
of ruby system non-static.

9274:ba635023d4bb 02-Oct-2012 Nilay Vaish <nilay@cs.wisc.edu>

ruby: changes to simple network
This patch makes the Switch structure inherit from BasicRouter, as is
done in two other networks.

9230:33eb3c8a98b9 18-Sep-2012 Nilay Vaish <nilay@cs.wisc.edu>

ruby: avoid using g_system_ptr for event scheduling
This patch removes the use of g_system_ptr for event scheduling. Each consumer
object now needs to specify upfront an EventManager object it would use for
scheduling events. This makes the ruby memory system more amenable for a
multi-threaded simulation.

9171:ae88ecf37145 27-Aug-2012 Nilay Vaish <nilay@cs.wisc.edu>

Ruby: Remove RubyEventQueue
This patch removes RubyEventQueue. Consumer objects now rely on RubySystem
or themselves for scheduling events.


/gem5/src/cpu/testers/directedtest/RubyDirectedTester.cc
/gem5/src/cpu/testers/rubytest/Check.cc
/gem5/src/cpu/testers/rubytest/RubyTester.cc
/gem5/src/mem/ruby/buffers/MessageBuffer.cc
/gem5/src/mem/ruby/buffers/MessageBuffer.hh
/gem5/src/mem/ruby/common/Consumer.cc
/gem5/src/mem/ruby/common/Consumer.hh
/gem5/src/mem/ruby/common/Global.cc
/gem5/src/mem/ruby/common/Global.hh
/gem5/src/mem/ruby/common/SConscript
/gem5/src/mem/ruby/common/TypeDefines.hh
/gem5/src/mem/ruby/eventqueue/RubyEventQueue.cc
/gem5/src/mem/ruby/eventqueue/RubyEventQueue.hh
/gem5/src/mem/ruby/eventqueue/RubyEventQueueNode.cc
/gem5/src/mem/ruby/eventqueue/RubyEventQueueNode.hh
/gem5/src/mem/ruby/eventqueue/SConscript
garnet/BaseGarnetNetwork.cc
garnet/fixed-pipeline/GarnetNetwork_d.cc
garnet/fixed-pipeline/InputUnit_d.cc
garnet/fixed-pipeline/InputUnit_d.hh
garnet/fixed-pipeline/NetworkInterface_d.cc
garnet/fixed-pipeline/NetworkLink_d.cc
garnet/fixed-pipeline/OutVcState_d.cc
garnet/fixed-pipeline/OutputUnit_d.cc
garnet/fixed-pipeline/OutputUnit_d.hh
garnet/fixed-pipeline/Router_d.cc
garnet/fixed-pipeline/SWallocator_d.cc
garnet/fixed-pipeline/Switch_d.cc
garnet/fixed-pipeline/VCallocator_d.cc
garnet/fixed-pipeline/VirtualChannel_d.cc
garnet/fixed-pipeline/VirtualChannel_d.hh
garnet/fixed-pipeline/flitBuffer_d.cc
garnet/fixed-pipeline/flit_d.cc
garnet/fixed-pipeline/flit_d.hh
garnet/flexible-pipeline/GarnetNetwork.cc
garnet/flexible-pipeline/NetworkInterface.cc
garnet/flexible-pipeline/NetworkLink.cc
garnet/flexible-pipeline/Router.cc
garnet/flexible-pipeline/flit.cc
garnet/flexible-pipeline/flitBuffer.cc
orion/NetworkPower.cc
simple/PerfectSwitch.cc
simple/Throttle.cc
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/profiler/StoreTrace.cc
/gem5/src/mem/ruby/profiler/StoreTrace.hh
/gem5/src/mem/ruby/slicc_interface/Message.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
/gem5/src/mem/ruby/system/CacheMemory.cc
/gem5/src/mem/ruby/system/CacheMemory.hh
/gem5/src/mem/ruby/system/RubyMemoryControl.cc
/gem5/src/mem/ruby/system/RubyPort.cc
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/Sequencer.hh
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/ruby/system/System.hh
/gem5/src/mem/ruby/system/TimerTable.cc
/gem5/src/mem/ruby/system/TimerTable.hh
/gem5/src/mem/ruby/system/WireBuffer.cc
/gem5/src/mem/ruby/system/WireBuffer.hh
/gem5/src/mem/slicc/ast/AST.py
/gem5/src/mem/slicc/ast/FuncCallExprAST.py
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/mem/slicc/symbols/Type.py
9148:a7a72f42919e 10-Aug-2012 Jason Power <powerjg@cs.wisc.edu>

Ruby: Clean up topology changes
This patch moves instantiateTopology into Ruby.py and removes the
mem/ruby/network/topologies directory. It also adds some extra inheritance to
the topologies to clean up some issues in the existing topologies.

9117:49116b947194 12-Jul-2012 Nilay Vaish <nilay@cs.wisc.edu>

Ruby: remove config information from ruby.stats
This patch removes printConfig() functions from all structures in Ruby.
Most of the information is already part of config.ini, and where ever it
is not, it would become in due course.


/gem5/src/mem/ruby/buffers/MessageBuffer.hh
/gem5/src/mem/ruby/filters/GenericBloomFilter.hh
Network.hh
Topology.cc
Topology.hh
garnet/fixed-pipeline/GarnetNetwork_d.cc
garnet/fixed-pipeline/GarnetNetwork_d.hh
garnet/fixed-pipeline/InputUnit_d.cc
garnet/fixed-pipeline/InputUnit_d.hh
garnet/fixed-pipeline/NetworkInterface_d.cc
garnet/fixed-pipeline/NetworkInterface_d.hh
garnet/fixed-pipeline/OutputUnit_d.cc
garnet/fixed-pipeline/OutputUnit_d.hh
garnet/fixed-pipeline/Router_d.cc
garnet/fixed-pipeline/Router_d.hh
garnet/flexible-pipeline/GarnetNetwork.cc
garnet/flexible-pipeline/GarnetNetwork.hh
garnet/flexible-pipeline/NetworkInterface.cc
garnet/flexible-pipeline/NetworkInterface.hh
garnet/flexible-pipeline/Router.cc
garnet/flexible-pipeline/Router.hh
simple/PerfectSwitch.cc
simple/PerfectSwitch.hh
simple/SimpleNetwork.cc
simple/SimpleNetwork.hh
simple/Switch.cc
simple/Switch.hh
simple/Throttle.cc
simple/Throttle.hh
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/system/AbstractMemOrCache.hh
/gem5/src/mem/ruby/system/CacheMemory.cc
/gem5/src/mem/ruby/system/CacheMemory.hh
/gem5/src/mem/ruby/system/DMASequencer.cc
/gem5/src/mem/ruby/system/DMASequencer.hh
/gem5/src/mem/ruby/system/DirectoryMemory.cc
/gem5/src/mem/ruby/system/DirectoryMemory.hh
/gem5/src/mem/ruby/system/MemoryControl.cc
/gem5/src/mem/ruby/system/MemoryControl.hh
/gem5/src/mem/ruby/system/PerfectCacheMemory.hh
/gem5/src/mem/ruby/system/PersistentTable.hh
/gem5/src/mem/ruby/system/RubyMemoryControl.cc
/gem5/src/mem/ruby/system/RubyMemoryControl.hh
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/Sequencer.hh
/gem5/src/mem/ruby/system/SparseMemory.hh
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/ruby/system/System.hh
/gem5/src/mem/ruby/system/TBETable.hh
/gem5/src/mem/ruby/system/TimerTable.hh
/gem5/src/mem/ruby/system/WireBuffer.cc
/gem5/src/mem/ruby/system/WireBuffer.hh
9116:9171e26543fa 12-Jul-2012 Nilay Vaish <nilay@cs.wisc.edu>

Ruby: remove some unused stuff from SLICC files

9109:6bce09259194 11-Jul-2012 Brad Beckmann <Brad.Beckmann@amd.com>

# User Brad Beckmann <Brad.Beckmann@amd.com>
ruby: fixed fatal print statement

9100:3caf131d7a95 11-Jul-2012 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: changes how Topologies are created

Instead of just passing a list of controllers to the makeTopology function
in src/mem/ruby/network/topologies/<Topo>.py we pass in a function pointer
which knows how to make the topology, possibly with some extra state set
in the configs/ruby/<protocol>.py file. Thus, we can move all of the files
from network/topologies to configs/topologies. A new class BaseTopology
is added which all topologies in configs/topologies must inheirit from and
follow its API.

8970:1fc1256d5798 28-Apr-2012 Nilay Vaish <nilay@cs.wisc.edu>

Garnet: Correct computation of link utilization
The computation for link utilization was incorrect for the flexible network.
The utilization was being divided twice by the total time.

8946:fb6c89334b86 14-Apr-2012 Andreas Hansson <andreas.hansson@arm.com>

clang/gcc: Fix compilation issues with clang 3.0 and gcc 4.6

This patch addresses a number of minor issues that cause problems when
compiling with clang >= 3.0 and gcc >= 4.6. Most importantly, it
avoids using the deprecated ext/hash_map and instead uses
unordered_map (and similarly so for the hash_set). To make use of the
new STL containers, g++ and clang has to be invoked with "-std=c++0x",
and this is now added for all gcc versions >= 4.6, and for clang >=
3.0. For gcc >= 4.3 and <= 4.5 and clang <= 3.0 we use the tr1
unordered_map to avoid the deprecation warning.

The addition of c++0x in turn causes a few problems, as the
compiler is more stringent and adds a number of new warnings. Below,
the most important issues are enumerated:

1) the use of namespaces is more strict, e.g. for isnan, and all
headers opening the entire namespace std are now fixed.

2) another other issue caused by the more stringent compiler is the
narrowing of the embedded python, which used to be a char array,
and is now unsigned char since there were values larger than 128.

3) a particularly odd issue that arose with the new c++0x behaviour is
found in range.hh, where the operator< causes gcc to complain about
the template type parsing (the "<" is interpreted as the beginning
of a template argument), and the problem seems to be related to the
begin/end members introduced for the range-type iteration, which is
a new feature in c++11.

As a minor update, this patch also fixes the build flags for the clang
debug target that used to be shared with gcc and incorrectly use
"-ggdb".

8913:8b223e308b08 22-Mar-2012 Andreas Hansson <andreas.hansson@arm.com>

Scons: Remove Werror=False in SConscript files

This patch removes the overriding of "-Werror" in a handful of
cases. The code compiles with gcc 4.6.3 and clang 3.0 without any
warnings, and thus without any errors. There are no functional changes
introduced by this patch. In the future, rather than ypassing
"-Werror", address the warnings.

8903:c739a3a829f5 19-Mar-2012 Tushar Krishna <tushar@csail.mit.edu>

Garnet: Stats at vnet granularity + code cleanup

This patch
(1) Moves redundant code from fixed and flexible networks to BaseGarnetNetwork.
(2) Prints network stats at vnet granularity.

8737:770ccf3af571 31-Jan-2012 Koan-Sin Tan <koansin.tan@gmail.com>

clang: Enable compiling gem5 using clang 2.9 and 3.0

This patch adds the necessary flags to the SConstruct and SConscript
files for compiling using clang 2.9 and later (on Ubuntu et al and OSX
XCode 4.2), and also cleans up a bunch of compiler warnings found by
clang. Most of the warnings are related to hidden virtual functions,
comparisons with unsigneds >= 0, and if-statements with empty
bodies. A number of mismatches between struct and class are also
fixed. clang 2.8 is not working as it has problems with class names
that occur in multiple namespaces (e.g. Statistics in
kernel_stats.hh).

clang has a bug (http://llvm.org/bugs/show_bug.cgi?id=7247) which
causes confusion between the container std::set and the function
Packet::set, and this is currently addressed by not including the
entire namespace std, but rather selecting e.g. "using std::vector" in
the appropriate places.


/gem5/SConstruct
/gem5/ext/libelf/SConscript
/gem5/src/SConscript
/gem5/src/arch/alpha/tlb.cc
/gem5/src/arch/alpha/tlb.hh
/gem5/src/arch/arm/insts/static_inst.hh
/gem5/src/arch/arm/insts/vfp.hh
/gem5/src/arch/arm/isa/templates/basic.isa
/gem5/src/arch/arm/miscregs.cc
/gem5/src/arch/generic/memhelpers.hh
/gem5/src/arch/mips/faults.cc
/gem5/src/arch/mips/faults.hh
/gem5/src/arch/x86/bios/acpi.hh
/gem5/src/arch/x86/bios/intelmp.cc
/gem5/src/arch/x86/bios/intelmp.hh
/gem5/src/arch/x86/bios/smbios.hh
/gem5/src/base/fast_alloc.cc
/gem5/src/base/range_map.hh
/gem5/src/base/remote_gdb.hh
/gem5/src/base/stl_helpers.hh
/gem5/src/cpu/base.cc
/gem5/src/cpu/base.hh
/gem5/src/cpu/func_unit.hh
/gem5/src/cpu/inorder/cpu.cc
/gem5/src/cpu/inorder/cpu.hh
/gem5/src/cpu/inorder/resource.cc
/gem5/src/cpu/inorder/resource.hh
/gem5/src/cpu/inorder/resource_pool.cc
/gem5/src/cpu/inorder/resource_pool.hh
/gem5/src/cpu/inorder/resources/cache_unit.hh
/gem5/src/cpu/inorder/thread_context.cc
/gem5/src/cpu/nativetrace.hh
/gem5/src/cpu/o3/bpred_unit.hh
/gem5/src/cpu/o3/commit.hh
/gem5/src/cpu/o3/cpu.cc
/gem5/src/cpu/o3/cpu.hh
/gem5/src/cpu/o3/decode.hh
/gem5/src/cpu/o3/decode_impl.hh
/gem5/src/cpu/o3/fetch.hh
/gem5/src/cpu/o3/fu_pool.cc
/gem5/src/cpu/o3/fu_pool.hh
/gem5/src/cpu/o3/iew.hh
/gem5/src/cpu/o3/iew_impl.hh
/gem5/src/cpu/o3/inst_queue.hh
/gem5/src/cpu/o3/inst_queue_impl.hh
/gem5/src/cpu/o3/lsq.hh
/gem5/src/cpu/o3/lsq_unit.hh
/gem5/src/cpu/o3/mem_dep_unit.cc
/gem5/src/cpu/o3/mem_dep_unit.hh
/gem5/src/cpu/o3/rename.hh
/gem5/src/cpu/o3/sat_counter.hh
/gem5/src/cpu/quiesce_event.hh
/gem5/src/cpu/sched_list.hh
/gem5/src/cpu/simple/atomic.cc
/gem5/src/cpu/simple/atomic.hh
/gem5/src/cpu/simple/base.cc
/gem5/src/cpu/simple/base.hh
/gem5/src/cpu/simple/timing.cc
/gem5/src/cpu/simple/timing.hh
/gem5/src/cpu/static_inst.hh
/gem5/src/dev/alpha/tsunami_cchip.cc
/gem5/src/dev/alpha/tsunami_io.cc
/gem5/src/dev/arm/pl111.cc
/gem5/src/dev/arm/pl111.hh
/gem5/src/dev/copy_engine.cc
/gem5/src/dev/disk_image.cc
/gem5/src/dev/disk_image.hh
/gem5/src/dev/ide_ctrl.cc
/gem5/src/dev/ns_gige.cc
/gem5/src/dev/pciconfigall.cc
/gem5/src/dev/pcidev.cc
/gem5/src/mem/cache/base.hh
/gem5/src/mem/cache/tags/iic.cc
/gem5/src/mem/cache/tags/iic_repl/gen.cc
/gem5/src/mem/cache/tags/iic_repl/gen.hh
/gem5/src/mem/cache/tags/iic_repl/repl.hh
/gem5/src/mem/packet.hh
garnet/fixed-pipeline/GarnetNetwork_d.cc
/gem5/src/mem/ruby/system/Sequencer.hh
/gem5/src/python/m5/SimObject.py
/gem5/src/sim/core.hh
/gem5/src/sim/process.cc
/gem5/src/sim/process.hh
/gem5/src/sim/process_impl.hh
/gem5/src/sim/serialize.cc
/gem5/src/sim/sim_object.cc
/gem5/src/sim/sim_object.hh
/gem5/src/sim/syscall_emul.hh
8645:89929730804b 31-Dec-2011 Nilay Vaish<nilay@cs.wisc.edu>

Ruby: Shuffle some of the included files
This patch adds and removes included files from some of the files so as to
organize remove some false dependencies and include some files directly
instead of transitively.

8619:2f1875b5f107 23-Nov-2011 Tushar Krishna <tushar@csail.mit.edu>

Topology: bug fix in external link initialization

8612:df3b7a1e883f 04-Nov-2011 Tushar Krishna <tushar@csail.mit.edu>

GARNET: adding a fault model for resilient on-chip network research.

This patch adds a fault model, which provides the probability of a number of
architectural faults in the interconnection network (e.g., data corruption,
misrouting). These probabilities can be used to realistically inject faults
in GARNET and faithfully evaluate the effectiveness of novel resilient NoC
architectures.

8608:02d7ac5fb855 03-Nov-2011 Nilay Vaish<nilay@cs.wisc.edu>

Ruby: Remove some unused typedefs
This patch removes some of the unused typedefs. It also moves
some of the typedefs from Global.hh to TypeDefines.hh. The patch
also eliminates the file NodeID.hh.

8607:5fb918115c07 31-Oct-2011 Gabe Black <gblack@eecs.umich.edu>

GCC: Get everything working with gcc 4.6.1.

And by "everything" I mean all the quick regressions.

8530:3aaa99208a84 29-Aug-2011 Nilay Vaish<nilay@cs.wisc.edu>

Ruby: Remove some unused code

8492:1ad244a20877 08-Aug-2011 Nilay Vaish<nilay@cs.wisc.edu>

BuildEnv: Eliminate RUBY as build environment variable
This patch replaces RUBY with PROTOCOL in all the SConscript files as
the environment variable that decides whether or not certain components
of the simulator are compiled.

8485:7a9a7f2a3d46 03-Aug-2011 Nilay Vaish<nilay@cs.wisc.edu>

Ruby: Remove files and includes not in use

8436:5648986156db 30-Jun-2011 Brad Beckmann <Brad.Beckmann@amd.com>, Nilay Vaish <nilay@cs.wisc.edu>

Ruby: Add support for functional accesses
This patch rpovides functional access support in Ruby. Currently only
the M5Port of RubyPort supports functional accesses. The support for
functional through the PioPort will be added as a separate patch.


/gem5/configs/example/ruby_direct_test.py
/gem5/configs/example/ruby_fs.py
/gem5/configs/example/ruby_mem_test.py
/gem5/configs/example/ruby_network_test.py
/gem5/configs/example/ruby_random_test.py
/gem5/configs/example/se.py
/gem5/configs/ruby/MESI_CMP_directory.py
/gem5/configs/ruby/MI_example.py
/gem5/configs/ruby/MOESI_CMP_directory.py
/gem5/configs/ruby/MOESI_CMP_token.py
/gem5/configs/ruby/MOESI_hammer.py
/gem5/configs/ruby/Ruby.py
/gem5/src/cpu/testers/memtest/MemTest.py
/gem5/src/cpu/testers/memtest/memtest.cc
/gem5/src/cpu/testers/memtest/memtest.hh
/gem5/src/mem/packet.cc
/gem5/src/mem/packet.hh
/gem5/src/mem/protocol/MESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MESI_CMP_directory-dma.sm
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MI_example-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dma.sm
/gem5/src/mem/protocol/MOESI_hammer-cache.sm
/gem5/src/mem/protocol/MOESI_hammer-dir.sm
/gem5/src/mem/protocol/MOESI_hammer-dma.sm
/gem5/src/mem/protocol/RubySlicc_Exports.sm
Network.cc
Network.py
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.py
/gem5/src/mem/ruby/recorder/Tracer.cc
/gem5/src/mem/ruby/recorder/Tracer.py
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/slicc_interface/Controller.py
/gem5/src/mem/ruby/slicc_interface/SConscript
/gem5/src/mem/ruby/system/Cache.py
/gem5/src/mem/ruby/system/DirectoryMemory.cc
/gem5/src/mem/ruby/system/DirectoryMemory.py
/gem5/src/mem/ruby/system/RubyPort.cc
/gem5/src/mem/ruby/system/RubyPort.hh
/gem5/src/mem/ruby/system/RubySystem.py
/gem5/src/mem/ruby/system/SConscript
/gem5/src/mem/ruby/system/Sequencer.py
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/ruby/system/System.hh
/gem5/src/mem/slicc/ast/MemberExprAST.py
/gem5/tests/configs/memtest-ruby.py
/gem5/tests/configs/rubytest-ruby.py
/gem5/tests/configs/simple-timing-mp-ruby.py
/gem5/tests/configs/simple-timing-ruby.py
8332:23711432221f 02-Jun-2011 Nathan Binkert <nate@binkert.org>

copyright: clean up copyright blocks


/gem5/src/arch/alpha/kgdb.h
/gem5/src/arch/alpha/remote_gdb.cc
/gem5/src/arch/arm/remote_gdb.cc
/gem5/src/arch/generic/debugfaults.hh
/gem5/src/arch/sparc/remote_gdb.cc
/gem5/src/arch/x86/insts/badmicroop.cc
/gem5/src/arch/x86/insts/badmicroop.hh
/gem5/src/arch/x86/isa/formats/nop.isa
/gem5/src/base/random_mt.cc
/gem5/src/base/remote_gdb.cc
/gem5/src/dev/ide_wdcreg.h
/gem5/src/dev/sparc/dtod.hh
orion/Allocator/Arbiter.cc
orion/Allocator/Arbiter.hh
orion/Allocator/MatrixArbiter.cc
orion/Allocator/MatrixArbiter.hh
orion/Allocator/RRArbiter.cc
orion/Allocator/RRArbiter.hh
orion/Allocator/SWAllocator.cc
orion/Allocator/SWAllocator.hh
orion/Allocator/VCAllocator.cc
orion/Allocator/VCAllocator.hh
orion/Buffer/AmpUnit.cc
orion/Buffer/AmpUnit.hh
orion/Buffer/BitlineUnit.cc
orion/Buffer/BitlineUnit.hh
orion/Buffer/Buffer.cc
orion/Buffer/Buffer.hh
orion/Buffer/DecoderUnit.cc
orion/Buffer/DecoderUnit.hh
orion/Buffer/MemUnit.cc
orion/Buffer/MemUnit.hh
orion/Buffer/OutdrvUnit.cc
orion/Buffer/OutdrvUnit.hh
orion/Buffer/PrechargeUnit.cc
orion/Buffer/PrechargeUnit.hh
orion/Buffer/Register.cc
orion/Buffer/Register.hh
orion/Buffer/SRAM.cc
orion/Buffer/SRAM.hh
orion/Buffer/WordlineUnit.cc
orion/Buffer/WordlineUnit.hh
orion/Clock.cc
orion/Clock.hh
orion/Crossbar/Crossbar.cc
orion/Crossbar/Crossbar.hh
orion/Crossbar/MatrixCrossbar.cc
orion/Crossbar/MatrixCrossbar.hh
orion/Crossbar/MultreeCrossbar.cc
orion/Crossbar/MultreeCrossbar.hh
orion/FlipFlop.cc
orion/FlipFlop.hh
orion/OrionLink.cc
orion/OrionLink.hh
orion/OrionRouter.cc
orion/OrionRouter.hh
orion/TechParameter.cc
orion/TechParameter.hh
orion/Type.hh
orion/Wire.cc
orion/Wire.hh
/gem5/src/sim/fault_fwd.hh
/gem5/src/sim/root.cc
/gem5/src/sim/root.hh
/gem5/src/unittest/unittest.cc
/gem5/src/unittest/unittest.hh
8330:681497e0356b 31-May-2011 Tushar Krishna <tushar@csail.mit.edu>

orion: bug fix in link power, and some reorg

8329:24a00a6d5992 31-May-2011 Tushar Krishna <tushar@csail.mit.edu>

garnet: added network ptr to links to be used by orion

8322:19949c6de823 23-May-2011 Steve Reinhardt <steve.reinhardt@amd.com>

config: tweak ruby configs to clean up hierarchy

Re-enabling implicit parenting (see previous patch) causes current
Ruby config scripts to create some strange hierarchies and generate
several warnings. This patch makes three general changes to address
these issues.

1. The order of object creation in the ruby config files makes the L1
caches children of the sequencer rather than the controller; these
config ciles are rewritten to assign the L1 caches to the
controller first.

2. The assignment of the sequencer list to system.ruby.cpu_ruby_ports
causes the sequencers to be children of system.ruby, generating
warnings because they are already parented to their respective
controllers. Changing this attribute to _cpu_ruby_ports fixes this
because the leading underscore means this is now treated as a plain
Python attribute rather than a child assignment. As a result, the
configuration hierarchy changes such that, e.g.,
system.ruby.cpu_ruby_ports0 becomes system.l1_cntrl0.sequencer.

3. In the topology classes, the routers become children of some random
internal link node rather than direct children of the topology.
The topology classes are rewritten to assign the routers to the
topology object first.

8313:1eaa1fbd2212 21-May-2011 Tushar Krishna <tushar@csail.mit.edu>

garnet: use vnet_type from protocol to decide buffer depths

The virtual channels within "response" vnets are made buffers_per_data_vc
deep (default=4), while virtual channels within other vnets are made
buffers_per_ctrl_vc deep (default = 1). This is for accurate power estimates.

8308:79cf09f5a234 18-May-2011 Tushar Krishna <tushar@csail.mit.edu>

slicc: added vnet_type field to identify response vnets from others

Identifying response vnets versus other vnets will allow garnet to
determine which vnets will carry data packets, and which will carry
ctrl packets, and use appropriate buffer sizes (since data packets are larger
than ctrl packets). This in turn allows the orion power model to accurately
estimate buffer power.

8307:76f7c2858c5c 18-May-2011 Tushar Krishna <tushar@csail.mit.edu>

garnet: rename and rearrange config parameters.

Renamed (message) class to vnet for consistency with rest of ruby.
Moved some parameters specific to fixed/flexible garnet networks into their
corresponding py files.

8292:0990d8c19b64 07-May-2011 Tushar Krishna <tushar@csail.mit.edu>

network: added Torus and Pt2Pt topologies

8266:66a3187a6714 02-May-2011 Korey Sewell <ksewell@umich.edu>

ruby: dbg: use system ticks instead of cycles

8263:8743998edfd3 28-Apr-2011 Brad Beckmann <Brad.Beckmann@amd.com>

network: set the ExtLink bw to 16 bytes

Therefore all links by default are 16 bytes wide and thus work with Garnet's
uniform link bandwidth assumption.

8262:89d0e7c17d1e 28-Apr-2011 Brad Beckmann <Brad.Beckmann@amd.com>

garnet: removed flit_width from Routers

8261:39e42ccddd63 28-Apr-2011 Brad Beckmann <Brad.Beckmann@amd.com>

network: adjusted default endpoint bandwidth

The simple network's endpoint bandwidth value is used to adjust the overall
bandwidth of the network. Specifically, the ration between endpoint bandwidth
and the MESSAGE_SIZE_MULTIPLIER determines the increase. By setting the value
to 1000, that means the bandwdith factor specified in the links translates to
the link bandwidth in bytes. Previously, it was increasing that value by 10.

This patch will likely require a reset of the ruby regression tester stats.

8260:f113f73dd494 28-Apr-2011 Brad Beckmann <Brad.Beckmann@amd.com>

network: removed the unused network-wide latency param

8259:36987780169e 28-Apr-2011 Brad Beckmann <Brad.Beckmann@amd.com>

network: moved network config params

Moved the buffer_size, endpoint_bandwidth, and adaptive_routing params out of
the top-level parent network object and to only those networks that actually
use those parameters.

8258:7c377f5162f8 28-Apr-2011 Brad Beckmann <Brad.Beckmann@amd.com>

network: basic link bw for garnet and simple networks

This patch ensures that both Garnet and the simple networks use the bw value
specified in the topology. To do so, the patch generalizes the specification
of bw for basic links. This value is then translated to the specific value
used by the simple and Garnet networks. Since Garent does not support
non-uniformed link bandwidth, the patch also adds a check to ensure all bws are
equal.

8257:7226aebb77b4 28-Apr-2011 Brad Beckmann <Brad.Beckmann@amd.com>

network: convert links & switches to first class C++ SimObjects

This patch converts links and switches from second class simobjects that were
virtually ignored by the networks (both simple and Garnet) to first class
simobjects that directly correspond to c++ ojbects manipulated by the
topology and network classes. This is especially true for Garnet, where the
links and switches directly correspond to specific C++ objects.

By making this change, many aspects of the Topology class were simplified.


/gem5/configs/ruby/MESI_CMP_directory.py
/gem5/configs/ruby/MI_example.py
/gem5/configs/ruby/MOESI_CMP_directory.py
/gem5/configs/ruby/MOESI_CMP_token.py
/gem5/configs/ruby/MOESI_hammer.py
/gem5/configs/ruby/Network_test.py
/gem5/configs/ruby/Ruby.py
/gem5/src/mem/protocol/RubySlicc_Exports.sm
BasicLink.cc
BasicLink.hh
BasicLink.py
BasicRouter.cc
BasicRouter.hh
BasicRouter.py
Network.hh
Network.py
SConscript
Topology.cc
Topology.hh
garnet/fixed-pipeline/CreditLink_d.hh
garnet/fixed-pipeline/GarnetLink_d.cc
garnet/fixed-pipeline/GarnetLink_d.hh
garnet/fixed-pipeline/GarnetLink_d.py
garnet/fixed-pipeline/GarnetNetwork_d.cc
garnet/fixed-pipeline/GarnetNetwork_d.hh
garnet/fixed-pipeline/GarnetRouter_d.py
garnet/fixed-pipeline/NetworkLink_d.cc
garnet/fixed-pipeline/NetworkLink_d.hh
garnet/fixed-pipeline/Router_d.cc
garnet/fixed-pipeline/Router_d.hh
garnet/fixed-pipeline/SConscript
garnet/flexible-pipeline/GarnetLink.cc
garnet/flexible-pipeline/GarnetLink.hh
garnet/flexible-pipeline/GarnetLink.py
garnet/flexible-pipeline/GarnetNetwork.cc
garnet/flexible-pipeline/GarnetNetwork.hh
garnet/flexible-pipeline/GarnetRouter.py
garnet/flexible-pipeline/NetworkLink.cc
garnet/flexible-pipeline/NetworkLink.hh
garnet/flexible-pipeline/Router.cc
garnet/flexible-pipeline/Router.hh
garnet/flexible-pipeline/SConscript
orion/NetworkPower.cc
simple/SimpleNetwork.cc
simple/SimpleNetwork.hh
topologies/Crossbar.py
topologies/Mesh.py
topologies/MeshDirCorners.py
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/slicc_interface/Controller.py
8256:2284cec55ef4 28-Apr-2011 Brad Beckmann <Brad.Beckmann@amd.com>

garnet: cleaned up flexible network header file

8255:73089f793a0a 28-Apr-2011 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: moved topology to the top network directory

Moved the Topology class to the top network directory because it is shared by
both the simple and Garnet networks.

8254:779d775abc11 28-Apr-2011 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: removed dated comment in SimpleNetwork

8232:b28d06a175be 15-Apr-2011 Nathan Binkert <nate@binkert.org>

trace: reimplement the DTRACE function so it doesn't use a vector
At the same time, rename the trace flags to debug flags since they
have broader usage than simply tracing. This means that
--trace-flags is now --debug-flags and --trace-help is now --debug-help


/gem5/src/SConscript
/gem5/src/arch/alpha/interrupts.hh
/gem5/src/arch/alpha/kernel_stats.cc
/gem5/src/arch/alpha/linux/process.cc
/gem5/src/arch/alpha/linux/system.cc
/gem5/src/arch/alpha/process.cc
/gem5/src/arch/alpha/remote_gdb.cc
/gem5/src/arch/alpha/stacktrace.hh
/gem5/src/arch/alpha/system.cc
/gem5/src/arch/alpha/tlb.cc
/gem5/src/arch/alpha/vtophys.cc
/gem5/src/arch/arm/faults.cc
/gem5/src/arch/arm/isa.cc
/gem5/src/arch/arm/isa.hh
/gem5/src/arch/arm/isa/includes.isa
/gem5/src/arch/arm/nativetrace.cc
/gem5/src/arch/arm/predecoder.cc
/gem5/src/arch/arm/process.cc
/gem5/src/arch/arm/remote_gdb.cc
/gem5/src/arch/arm/stacktrace.hh
/gem5/src/arch/arm/tlb.cc
/gem5/src/arch/arm/types.hh
/gem5/src/arch/mips/faults.cc
/gem5/src/arch/mips/isa.cc
/gem5/src/arch/mips/isa/includes.isa
/gem5/src/arch/mips/linux/process.cc
/gem5/src/arch/mips/locked_mem.hh
/gem5/src/arch/mips/process.cc
/gem5/src/arch/mips/stacktrace.hh
/gem5/src/arch/mips/tlb.cc
/gem5/src/arch/power/process.cc
/gem5/src/arch/power/stacktrace.hh
/gem5/src/arch/power/tlb.cc
/gem5/src/arch/sparc/interrupts.hh
/gem5/src/arch/sparc/isa.cc
/gem5/src/arch/sparc/isa/includes.isa
/gem5/src/arch/sparc/process.cc
/gem5/src/arch/sparc/remote_gdb.cc
/gem5/src/arch/sparc/stacktrace.hh
/gem5/src/arch/sparc/tlb.cc
/gem5/src/arch/sparc/ua2005.cc
/gem5/src/arch/sparc/vtophys.cc
/gem5/src/arch/x86/faults.cc
/gem5/src/arch/x86/insts/microregop.cc
/gem5/src/arch/x86/insts/static_inst.hh
/gem5/src/arch/x86/interrupts.cc
/gem5/src/arch/x86/isa/includes.isa
/gem5/src/arch/x86/nativetrace.cc
/gem5/src/arch/x86/pagetable_walker.cc
/gem5/src/arch/x86/predecoder.cc
/gem5/src/arch/x86/predecoder.hh
/gem5/src/arch/x86/process.cc
/gem5/src/arch/x86/stacktrace.hh
/gem5/src/arch/x86/tlb.cc
/gem5/src/arch/x86/vtophys.cc
/gem5/src/base/debug.cc
/gem5/src/base/debug.hh
/gem5/src/base/loader/aout_object.cc
/gem5/src/base/loader/ecoff_object.cc
/gem5/src/base/loader/elf_object.cc
/gem5/src/base/loader/raw_object.cc
/gem5/src/base/mysql.cc
/gem5/src/base/remote_gdb.cc
/gem5/src/base/trace.cc
/gem5/src/base/trace.hh
/gem5/src/base/vnc/vncserver.cc
/gem5/src/cpu/SConscript
/gem5/src/cpu/activity.cc
/gem5/src/cpu/base.cc
/gem5/src/cpu/base_dyn_inst_impl.hh
/gem5/src/cpu/exetrace.cc
/gem5/src/cpu/exetrace.hh
/gem5/src/cpu/inorder/cpu.cc
/gem5/src/cpu/inorder/first_stage.cc
/gem5/src/cpu/inorder/inorder_dyn_inst.cc
/gem5/src/cpu/inorder/inorder_dyn_inst.hh
/gem5/src/cpu/inorder/inorder_trace.cc
/gem5/src/cpu/inorder/pipeline_stage.cc
/gem5/src/cpu/inorder/reg_dep_map.cc
/gem5/src/cpu/inorder/resource.cc
/gem5/src/cpu/inorder/resource_pool.cc
/gem5/src/cpu/inorder/resource_sked.cc
/gem5/src/cpu/inorder/resources/agen_unit.cc
/gem5/src/cpu/inorder/resources/bpred_unit.cc
/gem5/src/cpu/inorder/resources/branch_predictor.cc
/gem5/src/cpu/inorder/resources/cache_unit.cc
/gem5/src/cpu/inorder/resources/decode_unit.cc
/gem5/src/cpu/inorder/resources/execution_unit.cc
/gem5/src/cpu/inorder/resources/fetch_seq_unit.cc
/gem5/src/cpu/inorder/resources/fetch_unit.cc
/gem5/src/cpu/inorder/resources/graduation_unit.cc
/gem5/src/cpu/inorder/resources/inst_buffer.cc
/gem5/src/cpu/inorder/resources/mult_div_unit.cc
/gem5/src/cpu/inorder/resources/use_def.cc
/gem5/src/cpu/inorder/thread_context.cc
/gem5/src/cpu/inteltrace.hh
/gem5/src/cpu/intr_control.cc
/gem5/src/cpu/nativetrace.cc
/gem5/src/cpu/o3/bpred_unit_impl.hh
/gem5/src/cpu/o3/commit_impl.hh
/gem5/src/cpu/o3/cpu.cc
/gem5/src/cpu/o3/decode_impl.hh
/gem5/src/cpu/o3/fetch_impl.hh
/gem5/src/cpu/o3/free_list.cc
/gem5/src/cpu/o3/free_list.hh
/gem5/src/cpu/o3/iew.hh
/gem5/src/cpu/o3/iew_impl.hh
/gem5/src/cpu/o3/inst_queue_impl.hh
/gem5/src/cpu/o3/lsq_impl.hh
/gem5/src/cpu/o3/lsq_unit.hh
/gem5/src/cpu/o3/lsq_unit_impl.hh
/gem5/src/cpu/o3/mem_dep_unit.hh
/gem5/src/cpu/o3/mem_dep_unit_impl.hh
/gem5/src/cpu/o3/regfile.hh
/gem5/src/cpu/o3/rename_impl.hh
/gem5/src/cpu/o3/rename_map.cc
/gem5/src/cpu/o3/rob_impl.hh
/gem5/src/cpu/o3/scoreboard.cc
/gem5/src/cpu/o3/scoreboard.hh
/gem5/src/cpu/o3/store_set.cc
/gem5/src/cpu/o3/thread_context_impl.hh
/gem5/src/cpu/pc_event.cc
/gem5/src/cpu/pred/2bit_local.cc
/gem5/src/cpu/pred/btb.cc
/gem5/src/cpu/quiesce_event.cc
/gem5/src/cpu/simple/atomic.cc
/gem5/src/cpu/simple/base.cc
/gem5/src/cpu/simple/timing.cc
/gem5/src/cpu/simple_thread.hh
/gem5/src/cpu/testers/directedtest/InvalidateGenerator.cc
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.cc
/gem5/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
/gem5/src/cpu/testers/memtest/memtest.cc
/gem5/src/cpu/testers/networktest/networktest.cc
/gem5/src/cpu/testers/rubytest/Check.cc
/gem5/src/cpu/testers/rubytest/CheckTable.cc
/gem5/src/cpu/testers/rubytest/RubyTester.cc
/gem5/src/cpu/thread_context.cc
/gem5/src/dev/alpha/backdoor.cc
/gem5/src/dev/alpha/tsunami_cchip.cc
/gem5/src/dev/alpha/tsunami_io.cc
/gem5/src/dev/alpha/tsunami_pchip.cc
/gem5/src/dev/copy_engine.cc
/gem5/src/dev/disk_image.cc
/gem5/src/dev/etherbus.cc
/gem5/src/dev/etherlink.cc
/gem5/src/dev/ethertap.cc
/gem5/src/dev/i8254xGBe.cc
/gem5/src/dev/i8254xGBe.hh
/gem5/src/dev/ide_ctrl.cc
/gem5/src/dev/ide_disk.cc
/gem5/src/dev/intel_8254_timer.cc
/gem5/src/dev/intel_8254_timer.hh
/gem5/src/dev/io_device.cc
/gem5/src/dev/isa_fake.cc
/gem5/src/dev/mc146818.cc
/gem5/src/dev/ns_gige.cc
/gem5/src/dev/pciconfigall.cc
/gem5/src/dev/pcidev.cc
/gem5/src/dev/simple_disk.cc
/gem5/src/dev/sinic.cc
/gem5/src/dev/sparc/iob.cc
/gem5/src/dev/sparc/mm_disk.cc
/gem5/src/dev/terminal.cc
/gem5/src/dev/uart8250.cc
/gem5/src/dev/x86/cmos.cc
/gem5/src/dev/x86/i8042.cc
/gem5/src/dev/x86/i82094aa.cc
/gem5/src/dev/x86/i8254.cc
/gem5/src/dev/x86/i8259.cc
/gem5/src/dev/x86/speaker.cc
/gem5/src/kern/linux/events.cc
/gem5/src/kern/linux/linux.cc
/gem5/src/kern/system_events.cc
/gem5/src/kern/tru64/tru64.hh
/gem5/src/kern/tru64/tru64_events.cc
/gem5/src/mem/bridge.cc
/gem5/src/mem/bus.cc
/gem5/src/mem/cache/base.cc
/gem5/src/mem/cache/base.hh
/gem5/src/mem/cache/cache_impl.hh
/gem5/src/mem/cache/mshr.cc
/gem5/src/mem/cache/prefetch/base.cc
/gem5/src/mem/cache/prefetch/ghb.cc
/gem5/src/mem/cache/prefetch/stride.cc
/gem5/src/mem/cache/tags/iic.cc
/gem5/src/mem/cache/tags/lru.cc
/gem5/src/mem/page_table.cc
/gem5/src/mem/physical.cc
/gem5/src/mem/port.cc
/gem5/src/mem/ruby/buffers/MessageBuffer.cc
/gem5/src/mem/ruby/common/NetDest.hh
garnet/fixed-pipeline/NetworkInterface_d.cc
garnet/fixed-pipeline/Switch_d.cc
garnet/flexible-pipeline/NetworkInterface.cc
garnet/flexible-pipeline/Router.cc
simple/PerfectSwitch.cc
simple/Throttle.cc
simple/Topology.cc
/gem5/src/mem/ruby/system/CacheMemory.cc
/gem5/src/mem/ruby/system/DMASequencer.cc
/gem5/src/mem/ruby/system/DirectoryMemory.cc
/gem5/src/mem/ruby/system/RubyPort.cc
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/SparseMemory.cc
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/mem/tport.cc
/gem5/src/python/m5/debug.py
/gem5/src/python/m5/main.py
/gem5/src/python/m5/trace.py
/gem5/src/python/swig/debug.i
/gem5/src/python/swig/trace.i
/gem5/src/sim/eventq.cc
/gem5/src/sim/eventq.hh
/gem5/src/sim/faults.cc
/gem5/src/sim/pseudo_inst.cc
/gem5/src/sim/root.cc
/gem5/src/sim/sim_object.cc
/gem5/src/sim/syscall_emul.cc
/gem5/src/sim/syscall_emul.hh
/gem5/src/sim/system.cc
8229:78bf55f23338 15-Apr-2011 Nathan Binkert <nate@binkert.org>

includes: sort all includes


/gem5/src/arch/alpha/faults.cc
/gem5/src/arch/alpha/isa.hh
/gem5/src/arch/alpha/isa/main.isa
/gem5/src/arch/alpha/linux/system.cc
/gem5/src/arch/alpha/mt.hh
/gem5/src/arch/alpha/process.cc
/gem5/src/arch/alpha/remote_gdb.cc
/gem5/src/arch/alpha/remote_gdb.hh
/gem5/src/arch/alpha/tlb.cc
/gem5/src/arch/alpha/tru64/process.cc
/gem5/src/arch/alpha/types.hh
/gem5/src/arch/alpha/utility.hh
/gem5/src/arch/arm/faults.cc
/gem5/src/arch/arm/faults.hh
/gem5/src/arch/arm/insts/macromem.cc
/gem5/src/arch/arm/insts/static_inst.cc
/gem5/src/arch/arm/insts/vfp.hh
/gem5/src/arch/arm/intregs.hh
/gem5/src/arch/arm/isa/includes.isa
/gem5/src/arch/arm/linux/atag.hh
/gem5/src/arch/arm/linux/linux.cc
/gem5/src/arch/arm/linux/process.cc
/gem5/src/arch/arm/linux/process.hh
/gem5/src/arch/arm/linux/system.cc
/gem5/src/arch/arm/locked_mem.hh
/gem5/src/arch/arm/pagetable.hh
/gem5/src/arch/arm/predecoder.hh
/gem5/src/arch/arm/process.hh
/gem5/src/arch/arm/registers.hh
/gem5/src/arch/arm/remote_gdb.cc
/gem5/src/arch/arm/system.cc
/gem5/src/arch/arm/system.hh
/gem5/src/arch/arm/table_walker.cc
/gem5/src/arch/arm/table_walker.hh
/gem5/src/arch/arm/tlb.hh
/gem5/src/arch/arm/vtophys.hh
/gem5/src/arch/generic/debugfaults.hh
/gem5/src/arch/generic/types.hh
/gem5/src/arch/mips/dsp.cc
/gem5/src/arch/mips/dsp.hh
/gem5/src/arch/mips/isa.cc
/gem5/src/arch/mips/isa.hh
/gem5/src/arch/mips/isa/includes.isa
/gem5/src/arch/mips/isa_traits.hh
/gem5/src/arch/mips/linux/linux.cc
/gem5/src/arch/mips/linux/process.cc
/gem5/src/arch/mips/linux/process.hh
/gem5/src/arch/mips/linux/system.cc
/gem5/src/arch/mips/mt.hh
/gem5/src/arch/mips/process.cc
/gem5/src/arch/mips/process.hh
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/gem5/src/arch/x86/bios/acpi.cc
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/gem5/src/cpu/activity.cc
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/gem5/src/cpu/base.cc
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/gem5/src/cpu/inorder/pipeline_traits.5stage.cc
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/gem5/src/cpu/inorder/pipeline_traits.9stage.smt2.cc
/gem5/src/cpu/inorder/pipeline_traits.9stage.smt2.hh
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/gem5/src/cpu/inorder/reg_dep_map.cc
/gem5/src/cpu/inorder/resource.cc
/gem5/src/cpu/inorder/resource.hh
/gem5/src/cpu/inorder/resource_pool.9stage.cc
/gem5/src/cpu/inorder/resource_pool.cc
/gem5/src/cpu/inorder/resource_pool.hh
/gem5/src/cpu/inorder/resource_sked.cc
/gem5/src/cpu/inorder/resource_sked.hh
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/gem5/src/cpu/inorder/resources/bpred_unit.hh
/gem5/src/cpu/inorder/resources/branch_predictor.hh
/gem5/src/cpu/inorder/resources/cache_unit.cc
/gem5/src/cpu/inorder/resources/cache_unit.hh
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/gem5/src/cpu/inorder/resources/execution_unit.cc
/gem5/src/cpu/inorder/resources/execution_unit.hh
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/gem5/src/cpu/inorder/resources/fetch_unit.hh
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/gem5/src/cpu/inorder/resources/inst_buffer.hh
/gem5/src/cpu/inorder/resources/mem_dep_unit.hh
/gem5/src/cpu/inorder/resources/mult_div_unit.cc
/gem5/src/cpu/inorder/resources/mult_div_unit.hh
/gem5/src/cpu/inorder/resources/resource_list.hh
/gem5/src/cpu/inorder/resources/tlb_unit.cc
/gem5/src/cpu/inorder/resources/tlb_unit.hh
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/gem5/src/cpu/intr_control.cc
/gem5/src/cpu/intr_control.hh
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/gem5/src/cpu/o3/bpred_unit.hh
/gem5/src/cpu/o3/bpred_unit_impl.hh
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/gem5/src/cpu/o3/cpu.cc
/gem5/src/cpu/o3/cpu.hh
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/gem5/src/cpu/o3/inst_queue.cc
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/gem5/src/cpu/o3/mem_dep_unit.cc
/gem5/src/cpu/o3/rename.hh
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/gem5/src/cpu/o3/thread_context.cc
/gem5/src/cpu/o3/thread_context.hh
/gem5/src/cpu/ozone/back_end.hh
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/gem5/src/cpu/ozone/base_dyn_inst.cc
/gem5/src/cpu/ozone/checker_builder.cc
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/gem5/src/cpu/ozone/ea_list.cc
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/gem5/src/cpu/ozone/rename_table.cc
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/gem5/src/cpu/ozone/simple_cpu_builder.cc
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/gem5/src/cpu/pc_event.cc
/gem5/src/cpu/profile.cc
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/gem5/src/cpu/quiesce_event.cc
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/gem5/src/cpu/static_inst.cc
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/gem5/src/cpu/testers/directedtest/InvalidateGenerator.cc
/gem5/src/cpu/testers/directedtest/InvalidateGenerator.hh
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/gem5/src/cpu/testers/memtest/memtest.cc
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/gem5/src/cpu/testers/rubytest/CheckTable.cc
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/gem5/src/cpu/trace/trace_cpu.cc
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/gem5/src/dev/arm/kmi.cc
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/gem5/src/dev/etherint.cc
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/gem5/src/dev/io_device.cc
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/gem5/src/dev/mips/malta.cc
/gem5/src/dev/mips/malta_cchip.hh
/gem5/src/dev/mips/malta_io.cc
/gem5/src/dev/mips/malta_pchip.cc
/gem5/src/dev/mips/malta_pchip.hh
/gem5/src/dev/pciconfigall.hh
/gem5/src/dev/platform.hh
/gem5/src/dev/ps2.cc
/gem5/src/dev/simple_disk.hh
/gem5/src/dev/sparc/iob.cc
/gem5/src/dev/sparc/iob.hh
/gem5/src/dev/sparc/mm_disk.cc
/gem5/src/dev/sparc/mm_disk.hh
/gem5/src/dev/terminal.cc
/gem5/src/dev/terminal.hh
/gem5/src/dev/x86/i8042.hh
/gem5/src/dev/x86/i82094aa.hh
/gem5/src/dev/x86/i8259.hh
/gem5/src/dev/x86/intdev.hh
/gem5/src/dev/x86/pc.cc
/gem5/src/dev/x86/south_bridge.hh
/gem5/src/kern/kernel_stats.cc
/gem5/src/kern/kernel_stats.hh
/gem5/src/kern/linux/events.cc
/gem5/src/kern/linux/printk.cc
/gem5/src/kern/operatingsystem.cc
/gem5/src/kern/tru64/dump_mbuf.cc
/gem5/src/kern/tru64/printf.cc
/gem5/src/kern/tru64/tru64.hh
/gem5/src/kern/tru64/tru64_events.cc
/gem5/src/mem/bridge.hh
/gem5/src/mem/bus.hh
/gem5/src/mem/cache/base.hh
/gem5/src/mem/cache/blk.hh
/gem5/src/mem/cache/builder.cc
/gem5/src/mem/cache/cache.hh
/gem5/src/mem/cache/cache_impl.hh
/gem5/src/mem/cache/mshr_queue.hh
/gem5/src/mem/cache/prefetch/base.cc
/gem5/src/mem/cache/prefetch/stride.hh
/gem5/src/mem/cache/tags/base.cc
/gem5/src/mem/cache/tags/base.hh
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/gem5/src/mem/cache/tags/iic.cc
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/gem5/src/mem/cache/tags/iic_repl/gen.cc
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/gem5/src/mem/cache/tags/lru.cc
/gem5/src/mem/cache/tags/lru.hh
/gem5/src/mem/packet.cc
/gem5/src/mem/packet.hh
/gem5/src/mem/page_table.cc
/gem5/src/mem/physical.cc
/gem5/src/mem/ruby/buffers/MessageBuffer.hh
/gem5/src/mem/ruby/common/NetDest.cc
/gem5/src/mem/ruby/common/Set.hh
/gem5/src/mem/ruby/filters/GenericBloomFilter.hh
Network.cc
garnet/BaseGarnetNetwork.hh
garnet/fixed-pipeline/GarnetNetwork_d.cc
garnet/fixed-pipeline/GarnetNetwork_d.hh
garnet/fixed-pipeline/InputUnit_d.hh
garnet/fixed-pipeline/NetworkInterface_d.cc
garnet/fixed-pipeline/NetworkInterface_d.hh
garnet/fixed-pipeline/NetworkLink_d.cc
garnet/fixed-pipeline/NetworkLink_d.hh
garnet/fixed-pipeline/OutVcState_d.cc
garnet/fixed-pipeline/OutVcState_d.hh
garnet/fixed-pipeline/OutputUnit_d.hh
garnet/fixed-pipeline/Router_d.cc
garnet/fixed-pipeline/Router_d.hh
garnet/fixed-pipeline/RoutingUnit_d.cc
garnet/fixed-pipeline/RoutingUnit_d.hh
garnet/fixed-pipeline/SWallocator_d.cc
garnet/fixed-pipeline/SWallocator_d.hh
garnet/fixed-pipeline/Switch_d.cc
garnet/fixed-pipeline/Switch_d.hh
garnet/fixed-pipeline/VCallocator_d.cc
garnet/fixed-pipeline/VCallocator_d.hh
garnet/fixed-pipeline/VirtualChannel_d.hh
garnet/fixed-pipeline/flitBuffer_d.hh
garnet/flexible-pipeline/FlexibleConsumer.hh
garnet/flexible-pipeline/GarnetNetwork.cc
garnet/flexible-pipeline/GarnetNetwork.hh
garnet/flexible-pipeline/NetworkInterface.cc
garnet/flexible-pipeline/NetworkInterface.hh
garnet/flexible-pipeline/NetworkLink.cc
garnet/flexible-pipeline/NetworkLink.hh
garnet/flexible-pipeline/Router.cc
garnet/flexible-pipeline/Router.hh
garnet/flexible-pipeline/VCarbiter.cc
garnet/flexible-pipeline/VCarbiter.hh
garnet/flexible-pipeline/flitBuffer.hh
orion/Allocator/Arbiter.cc
orion/Allocator/MatrixArbiter.hh
orion/Allocator/RRArbiter.cc
orion/Allocator/RRArbiter.hh
orion/Allocator/SWAllocator.cc
orion/Allocator/VCAllocator.cc
orion/Buffer/Buffer.cc
orion/Buffer/DecoderUnit.hh
orion/Buffer/OutdrvUnit.cc
orion/Buffer/PrechargeUnit.cc
orion/Buffer/Register.cc
orion/Buffer/SRAM.cc
orion/Buffer/SRAM.hh
orion/Buffer/WordlineUnit.cc
orion/Clock.cc
orion/ConfigFile.hh
orion/Crossbar/Crossbar.cc
orion/Crossbar/MatrixCrossbar.cc
orion/Crossbar/MatrixCrossbar.hh
orion/Crossbar/MultreeCrossbar.cc
orion/Crossbar/MultreeCrossbar.hh
orion/FlipFlop.cc
orion/NetworkPower.cc
orion/NetworkPower.hh
orion/OrionConfig.cc
orion/OrionConfig.hh
orion/OrionLink.cc
orion/OrionRouter.cc
orion/TechParameter.cc
orion/Wire.cc
orion/orion.hh
simple/PerfectSwitch.hh
simple/Switch.cc
simple/Throttle.cc
simple/Throttle.hh
simple/Topology.cc
/gem5/src/mem/ruby/profiler/CacheProfiler.hh
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/recorder/CacheRecorder.cc
/gem5/src/mem/ruby/recorder/CacheRecorder.hh
/gem5/src/mem/ruby/recorder/Tracer.hh
/gem5/src/mem/ruby/slicc_interface/AbstractEntry.hh
/gem5/src/mem/ruby/slicc_interface/RubyRequest.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.cc
/gem5/src/mem/ruby/slicc_interface/RubySlicc_includes.hh
/gem5/src/mem/ruby/system/CacheMemory.hh
/gem5/src/mem/ruby/system/RubyPort.cc
/gem5/src/mem/ruby/system/RubyPort.hh
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/Sequencer.hh
/gem5/src/mem/ruby/system/WireBuffer.hh
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/mem/tport.hh
/gem5/src/mem/translating_port.cc
/gem5/src/mem/vport.hh
/gem5/src/python/swig/core.i
/gem5/src/python/swig/event.i
/gem5/src/python/swig/inet.i
/gem5/src/python/swig/pyobject.cc
/gem5/src/python/swig/sim_object.i
/gem5/src/python/swig/stats.i
/gem5/src/python/swig/system.i
/gem5/src/sim/faults.cc
/gem5/src/sim/faults.hh
/gem5/src/sim/init.cc
/gem5/src/sim/process.cc
/gem5/src/sim/process_impl.hh
/gem5/src/sim/pseudo_inst.cc
/gem5/src/sim/serialize.cc
/gem5/src/sim/serialize.hh
/gem5/src/sim/stat_control.cc
/gem5/src/sim/syscall_emul.cc
/gem5/src/sim/syscall_emul.hh
/gem5/src/sim/system.cc
/gem5/src/sim/tlb.cc
/gem5/src/sim/vptr.hh
/gem5/src/unittest/cprintftest.cc
/gem5/src/unittest/cprintftime.cc
/gem5/src/unittest/initest.cc
/gem5/src/unittest/rangemaptest.cc
/gem5/src/unittest/stattest.cc
/gem5/src/unittest/symtest.cc
/gem5/util/ccdrv/devtime.c
/gem5/util/m5/m5.c
/gem5/util/statetrace/arch/amd64/tracechild.cc
/gem5/util/statetrace/arch/amd64/tracechild.hh
/gem5/util/statetrace/arch/arm/tracechild.cc
/gem5/util/statetrace/arch/arm/tracechild.hh
/gem5/util/statetrace/arch/i686/tracechild.cc
/gem5/util/statetrace/arch/i686/tracechild.hh
/gem5/util/statetrace/arch/sparc/tracechild.cc
/gem5/util/statetrace/arch/sparc/tracechild.hh
/gem5/util/statetrace/base/regstate.hh
/gem5/util/statetrace/base/statetrace.cc
/gem5/util/statetrace/base/tracechild.cc
/gem5/util/tap/tap.cc
/gem5/util/term/term.c
8173:2c47dc111abd 21-Mar-2011 Tushar Krishna <tushar@csail.mit.edu>

This patch makes garnet use the info about active and inactive vnets during allocation and power estimations etc

8172:bdb039c42553 21-Mar-2011 Tushar Krishna <tushar@csail.mit.edu>

fix garnet fleible pipeline

8171:19444b1f092c 21-Mar-2011 Tushar Krishna <tushar@csail.mit.edu>

This patch adds the network tester for simple and garnet networks.
The tester code is in testers/networktest.
The tester can be invoked by configs/example/ruby_network_test.py.
A dummy coherence protocol called Network_test is also addded for network-only simulations and testing. The protocol takes in messages from the tester and just pushes them into the network in the appropriate vnet, without storing any state.

8101:2e1ee8ec6266 01-Mar-2011 Nilay Vaish<nilay@cs.wisc.edu>

Ruby: Fix DPRINTF bugs in PerfectSwitch and MessageBuffer
At a couple of places in PerfectSwitch.cc and MessageBuffer.cc, DPRINTF()
has not been provided with correct number of arguments. The patch fixes these
bugs.

8054:9138d38eccd7 23-Feb-2011 Korey Sewell <ksewell@umich.edu>

ruby: cleaning up RubyQueue and RubyNetwork dprintfs
Overall, continue to progress Ruby debug messages to more of the normal M5
debug message style
- add a name() to the Ruby Throttle & PerfectSwitch objects so that the debug output
isn't littered w/"global:" everywhere.
- clean up messages that print over multiple lines when possible
- clean up duplicate prints in the message buffer

7973:e5550966464a 14-Feb-2011 Nilay Vaish<nilay@cs.wisc.edu>

Ruby: Improve Change PerfectSwitch's wakeup function
Currently the wakeup function for the PerfectSwitch contains three loops -

loop on number of virtual networks
loop on number of incoming links
loop till all messages for this (link, network) have been routed

With an 8 processor mesh network and Hammer protocol, about 11-12% of the
was observed to have been spent in this function, which is the highest
amongst all the functions. It was found that the innermost loop is executed
about 45 times per invocation of the wakeup function, when each invocation
of the wakeup function processes just about one message.

The patch tries to do away with the redundant executions of the innermost
loop. Counters have been added for each virtual network that record the
number of messages that need to be routed for that virtual network. The
inner loops are only executed when the number of messages for that particular
virtual network > 0. This does away with almost 80% of the executions of the
innermost loop. The function now consumes about 5-6% of the total execution
time.

7929:68f37178b408 07-Feb-2011 Nilay Vaish<nilay@cs.wisc.edu>

Orion: Replace printf() with fatal()
The code for Orion 2.0 makes use of printf() at several places where there as
an error in configuration of the model. These have been replaced with fatal().

7928:5f2a2deb377d 07-Feb-2011 Korey Sewell <ksewell@umich.edu>

ruby: add stdio header in SRAM.hh
missing header file caused RUBY_FS to not compile

7919:3a02353d6e43 07-Feb-2011 Joel Hestness <hestness@cs.utexas.edu>

garnet: Split network power in ruby.stats

Split out dynamic and static power numbers for printing to ruby.stats

7904:6f5299ff8260 07-Feb-2011 Brad Beckmann <Brad.Beckmann@amd.com>

MOESI_hammer: Added full-bit directory support

7896:46e9b3bf447f 07-Feb-2011 Tushar Krishna <tushar@csail.mit.edu>

garnet: added orion2.0 for network power calculation


garnet/fixed-pipeline/InputUnit_d.cc
garnet/fixed-pipeline/InputUnit_d.hh
garnet/fixed-pipeline/NetworkLink_d.hh
garnet/fixed-pipeline/Router_d.cc
garnet/fixed-pipeline/Router_d.hh
garnet/fixed-pipeline/VCallocator_d.cc
garnet/fixed-pipeline/VCallocator_d.hh
orion/Allocator/Arbiter.cc
orion/Allocator/Arbiter.hh
orion/Allocator/MatrixArbiter.cc
orion/Allocator/MatrixArbiter.hh
orion/Allocator/RRArbiter.cc
orion/Allocator/RRArbiter.hh
orion/Allocator/SConscript
orion/Allocator/SWAllocator.cc
orion/Allocator/SWAllocator.hh
orion/Allocator/VCAllocator.cc
orion/Allocator/VCAllocator.hh
orion/Buffer/AmpUnit.cc
orion/Buffer/AmpUnit.hh
orion/Buffer/BitlineUnit.cc
orion/Buffer/BitlineUnit.hh
orion/Buffer/Buffer.cc
orion/Buffer/Buffer.hh
orion/Buffer/DecoderUnit.cc
orion/Buffer/DecoderUnit.hh
orion/Buffer/MemUnit.cc
orion/Buffer/MemUnit.hh
orion/Buffer/OutdrvUnit.cc
orion/Buffer/OutdrvUnit.hh
orion/Buffer/PrechargeUnit.cc
orion/Buffer/PrechargeUnit.hh
orion/Buffer/Register.cc
orion/Buffer/Register.hh
orion/Buffer/SConscript
orion/Buffer/SRAM.cc
orion/Buffer/SRAM.hh
orion/Buffer/WordlineUnit.cc
orion/Buffer/WordlineUnit.hh
orion/Clock.cc
orion/Clock.hh
orion/ConfigFile.cc
orion/ConfigFile.hh
orion/Crossbar/Crossbar.cc
orion/Crossbar/Crossbar.hh
orion/Crossbar/MatrixCrossbar.cc
orion/Crossbar/MatrixCrossbar.hh
orion/Crossbar/MultreeCrossbar.cc
orion/Crossbar/MultreeCrossbar.hh
orion/Crossbar/SConscript
orion/FlipFlop.cc
orion/FlipFlop.hh
orion/NetworkPower.cc
orion/NetworkPower.hh
orion/OrionConfig.cc
orion/OrionConfig.hh
orion/OrionLink.cc
orion/OrionLink.hh
orion/OrionRouter.cc
orion/OrionRouter.hh
orion/SConscript
orion/SIM_port.hh
orion/SIM_power.hh
orion/SIM_power_test.hh
orion/TechParameter.cc
orion/TechParameter.hh
orion/Type.hh
orion/Wire.cc
orion/Wire.hh
orion/orion.hh
orion/parm_technology.hh
orion/power_arbiter.cc
orion/power_arbiter.hh
orion/power_array.cc
orion/power_array.hh
orion/power_bus.cc
orion/power_bus.hh
orion/power_crossbar.cc
orion/power_crossbar.hh
orion/power_ll.cc
orion/power_ll.hh
orion/power_router_init.cc
orion/power_router_init.hh
orion/power_static.cc
orion/power_static.hh
orion/power_utils.cc
orion/power_utils.hh
orion/router.cfg
7895:8439266ec9e5 07-Feb-2011 Tushar Krishna <tushar@csail.mit.edu>

garnet: separate data and ctrl VCs

Separate data VCs and ctrl VCs in garnet, as ctrl VCs have 1 buffer per VC,
while data VCs have > 1 buffers per VC. This is for correct power estimations.

7832:de7601e6e19d 10-Jan-2011 Nathan Binkert <nate@binkert.org>

ruby: get rid of ruby's Debug.hh

Get rid of the Debug class
Get rid of ASSERT and use assert
Use DPRINTFR for ProtocolTrace

7805:f249937228b5 23-Dec-2010 Nilay Vaish<nilay@cs.wisc.edu>

This patch removes the WARN_* and ERROR_* from src/mem/ruby/common/Debug.hh file. These statements have been replaced with warn(), panic() and fatal() defined in src/base/misc.hh

7780:42da07116e12 01-Dec-2010 Nilay Vaish <nilay@cs.wisc.edu>

ruby: Converted old ruby debug calls to M5 debug calls

This patch developed by Nilay Vaish converts all the old GEMS-style ruby
debug calls to the appropriate M5 debug calls.


/gem5/src/cpu/testers/rubytest/CheckTable.cc
/gem5/src/mem/SConscript
/gem5/src/mem/protocol/MESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-perfectDir.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_hammer-cache.sm
/gem5/src/mem/protocol/MOESI_hammer-dir.sm
/gem5/src/mem/ruby/SConsopts
/gem5/src/mem/ruby/buffers/MessageBuffer.cc
/gem5/src/mem/ruby/common/Debug.cc
/gem5/src/mem/ruby/common/Debug.hh
/gem5/src/mem/ruby/common/NetDest.hh
garnet/fixed-pipeline/NetworkInterface_d.cc
garnet/fixed-pipeline/Switch_d.cc
garnet/flexible-pipeline/NetworkInterface.cc
garnet/flexible-pipeline/Router.cc
simple/PerfectSwitch.cc
simple/Throttle.cc
simple/Topology.cc
/gem5/src/mem/ruby/storebuffer/storebuffer.cc
/gem5/src/mem/ruby/system/CacheMemory.cc
/gem5/src/mem/ruby/system/DirectoryMemory.cc
/gem5/src/mem/ruby/system/SConscript
/gem5/src/mem/ruby/system/SparseMemory.cc
/gem5/src/mem/ruby/tester/RaceyPseudoThread.cc
/gem5/src/mem/slicc/ast/FuncCallExprAST.py
/gem5/src/mem/slicc/symbols/StateMachine.py
7548:764a7401e217 20-Aug-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Added bcast msg profiling to hammer and token

7547:a5ddcb2abfa1 20-Aug-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Added consolidated network msg stats

7540:86c3bf056a0d 20-Aug-2010 Brad Beckmann <Brad.Beckmann@amd.com>

config: Added the topology description to m5 config.ini

7496:10510cc7bb9f 08-Jul-2010 Brad Beckmann <Brad.Beckmann@amd.com>

garnet: Added topology print function to Garnet printStats

7486:3006bde825fd 22-Jun-2010 Tushar Krishna <Tushar.Krishna@amd.com>

style: updated garnet to match M5 coding style


garnet/BaseGarnetNetwork.cc
garnet/BaseGarnetNetwork.hh
garnet/NetworkHeader.hh
garnet/fixed-pipeline/CreditLink_d.hh
garnet/fixed-pipeline/GarnetNetwork_d.cc
garnet/fixed-pipeline/GarnetNetwork_d.hh
garnet/fixed-pipeline/InputUnit_d.cc
garnet/fixed-pipeline/InputUnit_d.hh
garnet/fixed-pipeline/NetworkInterface_d.cc
garnet/fixed-pipeline/NetworkInterface_d.hh
garnet/fixed-pipeline/NetworkLink_d.cc
garnet/fixed-pipeline/NetworkLink_d.hh
garnet/fixed-pipeline/OutVcState_d.cc
garnet/fixed-pipeline/OutVcState_d.hh
garnet/fixed-pipeline/OutputUnit_d.cc
garnet/fixed-pipeline/OutputUnit_d.hh
garnet/fixed-pipeline/Router_d.cc
garnet/fixed-pipeline/Router_d.hh
garnet/fixed-pipeline/RoutingUnit_d.cc
garnet/fixed-pipeline/RoutingUnit_d.hh
garnet/fixed-pipeline/SWallocator_d.cc
garnet/fixed-pipeline/SWallocator_d.hh
garnet/fixed-pipeline/Switch_d.cc
garnet/fixed-pipeline/Switch_d.hh
garnet/fixed-pipeline/VCallocator_d.cc
garnet/fixed-pipeline/VCallocator_d.hh
garnet/fixed-pipeline/VirtualChannel_d.cc
garnet/fixed-pipeline/VirtualChannel_d.hh
garnet/fixed-pipeline/flitBuffer_d.cc
garnet/fixed-pipeline/flitBuffer_d.hh
garnet/fixed-pipeline/flit_d.cc
garnet/fixed-pipeline/flit_d.hh
garnet/flexible-pipeline/FlexibleConsumer.hh
garnet/flexible-pipeline/GarnetNetwork.cc
garnet/flexible-pipeline/GarnetNetwork.hh
garnet/flexible-pipeline/InVcState.cc
garnet/flexible-pipeline/InVcState.hh
garnet/flexible-pipeline/NetworkInterface.cc
garnet/flexible-pipeline/NetworkInterface.hh
garnet/flexible-pipeline/NetworkLink.cc
garnet/flexible-pipeline/NetworkLink.hh
garnet/flexible-pipeline/OutVcState.cc
garnet/flexible-pipeline/OutVcState.hh
garnet/flexible-pipeline/Router.cc
garnet/flexible-pipeline/Router.hh
garnet/flexible-pipeline/VCarbiter.cc
garnet/flexible-pipeline/VCarbiter.hh
garnet/flexible-pipeline/flit.cc
garnet/flexible-pipeline/flit.hh
garnet/flexible-pipeline/flitBuffer.cc
garnet/flexible-pipeline/flitBuffer.hh
garnet/flexible-pipeline/netconfig.defaults
7456:8b9be6e12c9b 11-Jun-2010 Nathan Binkert <nate@binkert.org>

ruby: get rid of PrioHeap and use STL

One big difference is that PrioHeap puts the smallest element at the
top of the heap, whereas stl puts the largest element on top, so I
changed all comparisons so they did the right thing.

Some usage of PrioHeap was simply changed to a std::vector, using sort
at the right time, other usage had me just use the various heap functions
in the stl.

7455:586f99bf0dc4 11-Jun-2010 Nathan Binkert <nate@binkert.org>

ruby: get rid of the Map class

7454:3a3e8e8cce1b 11-Jun-2010 Nathan Binkert <nate@binkert.org>

ruby: get rid of Vector and use STL
add a couple of helper functions to base for deleteing all pointers in
a container and outputting containers to a stream


/gem5/src/base/stl_helpers.hh
/gem5/src/cpu/rubytest/CheckTable.cc
/gem5/src/cpu/rubytest/CheckTable.hh
/gem5/src/cpu/rubytest/RubyTester.cc
/gem5/src/cpu/rubytest/RubyTester.hh
/gem5/src/mem/gems_common/Map.hh
/gem5/src/mem/gems_common/PrioHeap.hh
/gem5/src/mem/gems_common/Vector.hh
/gem5/src/mem/ruby/buffers/MessageBuffer.hh
/gem5/src/mem/ruby/common/DataBlock.hh
/gem5/src/mem/ruby/common/Histogram.cc
/gem5/src/mem/ruby/common/Histogram.hh
/gem5/src/mem/ruby/common/NetDest.cc
/gem5/src/mem/ruby/common/NetDest.hh
/gem5/src/mem/ruby/common/SubBlock.cc
/gem5/src/mem/ruby/common/SubBlock.hh
/gem5/src/mem/ruby/eventqueue/RubyEventQueue.hh
/gem5/src/mem/ruby/filters/BlockBloomFilter.cc
/gem5/src/mem/ruby/filters/BlockBloomFilter.hh
/gem5/src/mem/ruby/filters/BulkBloomFilter.cc
/gem5/src/mem/ruby/filters/BulkBloomFilter.hh
/gem5/src/mem/ruby/filters/H3BloomFilter.cc
/gem5/src/mem/ruby/filters/H3BloomFilter.hh
/gem5/src/mem/ruby/filters/LSB_CountingBloomFilter.cc
/gem5/src/mem/ruby/filters/LSB_CountingBloomFilter.hh
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.hh
/gem5/src/mem/ruby/filters/MultiGrainBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiGrainBloomFilter.hh
/gem5/src/mem/ruby/filters/NonCountingBloomFilter.cc
/gem5/src/mem/ruby/filters/NonCountingBloomFilter.hh
Network.cc
Network.hh
garnet/fixed-pipeline/GarnetNetwork_d.cc
garnet/fixed-pipeline/GarnetNetwork_d.hh
garnet/fixed-pipeline/InputUnit_d.cc
garnet/fixed-pipeline/InputUnit_d.hh
garnet/fixed-pipeline/NetworkInterface_d.cc
garnet/fixed-pipeline/NetworkInterface_d.hh
garnet/fixed-pipeline/NetworkLink_d.cc
garnet/fixed-pipeline/NetworkLink_d.hh
garnet/fixed-pipeline/OutputUnit_d.cc
garnet/fixed-pipeline/OutputUnit_d.hh
garnet/fixed-pipeline/Router_d.cc
garnet/fixed-pipeline/Router_d.hh
garnet/fixed-pipeline/RoutingUnit_d.cc
garnet/fixed-pipeline/RoutingUnit_d.hh
garnet/fixed-pipeline/SWallocator_d.cc
garnet/fixed-pipeline/SWallocator_d.hh
garnet/fixed-pipeline/Switch_d.cc
garnet/fixed-pipeline/Switch_d.hh
garnet/fixed-pipeline/VCallocator_d.cc
garnet/fixed-pipeline/VCallocator_d.hh
garnet/flexible-pipeline/GarnetNetwork.cc
garnet/flexible-pipeline/GarnetNetwork.hh
garnet/flexible-pipeline/NetworkInterface.cc
garnet/flexible-pipeline/NetworkInterface.hh
garnet/flexible-pipeline/NetworkLink.cc
garnet/flexible-pipeline/NetworkLink.hh
garnet/flexible-pipeline/Router.cc
garnet/flexible-pipeline/Router.hh
simple/PerfectSwitch.cc
simple/PerfectSwitch.hh
simple/SimpleNetwork.cc
simple/SimpleNetwork.hh
simple/Switch.cc
simple/Switch.hh
simple/Throttle.cc
simple/Throttle.hh
simple/Topology.cc
simple/Topology.hh
/gem5/src/mem/ruby/profiler/AddressProfiler.cc
/gem5/src/mem/ruby/profiler/CacheProfiler.cc
/gem5/src/mem/ruby/profiler/CacheProfiler.hh
/gem5/src/mem/ruby/profiler/MemCntrlProfiler.cc
/gem5/src/mem/ruby/profiler/MemCntrlProfiler.hh
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/system/CacheMemory.cc
/gem5/src/mem/ruby/system/CacheMemory.hh
/gem5/src/mem/ruby/system/MemoryVector.hh
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/ruby/system/System.hh
/gem5/src/mem/ruby/system/TimerTable.cc
/gem5/src/mem/ruby/tester/DeterministicDriver.cc
/gem5/src/mem/ruby/tester/DeterministicDriver.hh
/gem5/src/mem/ruby/tester/RaceyDriver.cc
/gem5/src/mem/ruby/tester/RaceyDriver.hh
/gem5/src/mem/slicc/symbols/StateMachine.py
7453:1a5db3dd0f62 11-Jun-2010 Nathan Binkert <nate@binkert.org>

ruby: get rid of RefCnt and Allocator stuff use base/refcnt.hh

This was somewhat tricky because the RefCnt API was somewhat odd. The
biggest confusion was that the the RefCnt object's constructor that
took a TYPE& cloned the object. I created an explicit virtual clone()
function for things that took advantage of this version of the
constructor. I was conservative and used clone() when I was in doubt
of whether or not it was necessary. I still think that there are
probably too many instances of clone(), but hopefully not too many.

I converted several instances of const MsgPtr & to a simple MsgPtr.
If the function wants to avoid the overhead of creating another
reference, then it should just use a regular pointer instead of a ref
counting ptr.

There were a couple of instances where refcounted objects were created
on the stack. This seems pretty dangerous since if you ever
accidentally make a reference to that object with a ref counting
pointer, bad things are bound to happen.

7056:b66b558578bd 02-Apr-2010 Nathan Binkert <nate@binkert.org>

ruby: get rid of gems_common/util.hh and .cc and use stuff in src/base

7055:4e24742201d7 02-Apr-2010 Nathan Binkert <nate@binkert.org>

ruby: get "using namespace" out of headers
In addition to obvious changes, this required a slight change to the slicc
grammar to allow types with :: in them. Otherwise slicc barfs on std::string
which we need for the headers that slicc generates.


/gem5/src/cpu/rubytest/Check.cc
/gem5/src/cpu/rubytest/Check.hh
/gem5/src/cpu/rubytest/CheckTable.cc
/gem5/src/cpu/rubytest/RubyTester.cc
/gem5/src/cpu/rubytest/RubyTester.hh
/gem5/src/mem/gems_common/Vector.hh
/gem5/src/mem/protocol/MESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MESI_SCMP_bankdirectory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L2cache.sm
/gem5/src/mem/protocol/MSI_MOSI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MSI_MOSI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MSI_MOSI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MSI_MOSI_CMP_directory-msg.sm
/gem5/src/mem/protocol/RubySlicc_Exports.sm
/gem5/src/mem/protocol/RubySlicc_Profiler.sm
/gem5/src/mem/protocol/RubySlicc_Util.sm
/gem5/src/mem/ruby/buffers/MessageBuffer.cc
/gem5/src/mem/ruby/common/Address.cc
/gem5/src/mem/ruby/common/Address.hh
/gem5/src/mem/ruby/common/Driver.hh
/gem5/src/mem/ruby/common/NetDest.cc
/gem5/src/mem/ruby/common/NetDest.hh
/gem5/src/mem/ruby/common/Set.cc
/gem5/src/mem/ruby/common/Set.hh
/gem5/src/mem/ruby/common/SubBlock.cc
/gem5/src/mem/ruby/common/SubBlock.hh
/gem5/src/mem/ruby/eventqueue/RubyEventQueue.cc
/gem5/src/mem/ruby/filters/AbstractBloomFilter.hh
/gem5/src/mem/ruby/filters/BlockBloomFilter.cc
/gem5/src/mem/ruby/filters/BlockBloomFilter.hh
/gem5/src/mem/ruby/filters/BulkBloomFilter.cc
/gem5/src/mem/ruby/filters/BulkBloomFilter.hh
/gem5/src/mem/ruby/filters/GenericBloomFilter.cc
/gem5/src/mem/ruby/filters/GenericBloomFilter.hh
/gem5/src/mem/ruby/filters/H3BloomFilter.cc
/gem5/src/mem/ruby/filters/H3BloomFilter.hh
/gem5/src/mem/ruby/filters/LSB_CountingBloomFilter.cc
/gem5/src/mem/ruby/filters/LSB_CountingBloomFilter.hh
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.hh
/gem5/src/mem/ruby/filters/MultiGrainBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiGrainBloomFilter.hh
/gem5/src/mem/ruby/filters/NonCountingBloomFilter.cc
/gem5/src/mem/ruby/filters/NonCountingBloomFilter.hh
/gem5/src/mem/ruby/libruby.cc
Network.hh
garnet/NetworkHeader.hh
garnet/fixed-pipeline/GarnetNetwork_d.cc
garnet/fixed-pipeline/GarnetNetwork_d.hh
garnet/fixed-pipeline/InputUnit_d.cc
garnet/fixed-pipeline/InputUnit_d.hh
garnet/fixed-pipeline/NetworkInterface_d.cc
garnet/fixed-pipeline/NetworkInterface_d.hh
garnet/fixed-pipeline/NetworkLink_d.hh
garnet/fixed-pipeline/OutputUnit_d.cc
garnet/fixed-pipeline/OutputUnit_d.hh
garnet/fixed-pipeline/Router_d.cc
garnet/fixed-pipeline/Router_d.hh
garnet/fixed-pipeline/SWallocator_d.hh
garnet/fixed-pipeline/Switch_d.hh
garnet/fixed-pipeline/VCallocator_d.hh
garnet/fixed-pipeline/VirtualChannel_d.hh
garnet/fixed-pipeline/flitBuffer_d.cc
garnet/fixed-pipeline/flitBuffer_d.hh
garnet/fixed-pipeline/flit_d.cc
garnet/fixed-pipeline/flit_d.hh
garnet/flexible-pipeline/GarnetNetwork.cc
garnet/flexible-pipeline/GarnetNetwork.hh
garnet/flexible-pipeline/NetworkInterface.cc
garnet/flexible-pipeline/NetworkInterface.hh
garnet/flexible-pipeline/NetworkLink.hh
garnet/flexible-pipeline/Router.cc
garnet/flexible-pipeline/Router.hh
garnet/flexible-pipeline/VCarbiter.hh
garnet/flexible-pipeline/flit.cc
garnet/flexible-pipeline/flit.hh
garnet/flexible-pipeline/flitBuffer.cc
garnet/flexible-pipeline/flitBuffer.hh
simple/PerfectSwitch.cc
simple/SimpleNetwork.cc
simple/SimpleNetwork.hh
simple/Switch.cc
simple/Throttle.cc
simple/Throttle.hh
simple/Topology.cc
/gem5/src/mem/ruby/profiler/AccessTraceForAddress.cc
/gem5/src/mem/ruby/profiler/AccessTraceForAddress.hh
/gem5/src/mem/ruby/profiler/AddressProfiler.cc
/gem5/src/mem/ruby/profiler/AddressProfiler.hh
/gem5/src/mem/ruby/profiler/CacheProfiler.cc
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/profiler/StoreTrace.cc
/gem5/src/mem/ruby/profiler/StoreTrace.hh
/gem5/src/mem/ruby/recorder/CacheRecorder.cc
/gem5/src/mem/ruby/recorder/TraceRecord.cc
/gem5/src/mem/ruby/recorder/TraceRecord.hh
/gem5/src/mem/ruby/recorder/Tracer.cc
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/slicc_interface/AbstractEntry.hh
/gem5/src/mem/ruby/slicc_interface/NetworkMessage.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.cc
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.hh
/gem5/src/mem/ruby/system/CacheMemory.cc
/gem5/src/mem/ruby/system/CacheMemory.hh
/gem5/src/mem/ruby/system/DMASequencer.cc
/gem5/src/mem/ruby/system/DirectoryMemory.cc
/gem5/src/mem/ruby/system/DirectoryMemory.hh
/gem5/src/mem/ruby/system/MemoryControl.cc
/gem5/src/mem/ruby/system/MemoryControl.hh
/gem5/src/mem/ruby/system/PerfectCacheMemory.hh
/gem5/src/mem/ruby/system/PersistentTable.cc
/gem5/src/mem/ruby/system/PersistentTable.hh
/gem5/src/mem/ruby/system/RubyPort.hh
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/Sequencer.hh
/gem5/src/mem/ruby/system/SparseMemory.cc
/gem5/src/mem/ruby/system/SparseMemory.hh
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/ruby/system/System.hh
/gem5/src/mem/ruby/system/TBETable.hh
/gem5/src/mem/ruby/system/TimerTable.cc
/gem5/src/mem/ruby/system/TimerTable.hh
/gem5/src/mem/slicc/ast/EnumDeclAST.py
/gem5/src/mem/slicc/ast/LiteralExprAST.py
/gem5/src/mem/slicc/parser.py
/gem5/src/mem/slicc/symbols/Func.py
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/mem/slicc/symbols/Type.py
7054:7d6862b80049 31-Mar-2010 Nathan Binkert <nate@binkert.org>

style: another ruby style pass


/gem5/src/mem/ruby/SConsopts
/gem5/src/mem/ruby/common/Address.hh
/gem5/src/mem/ruby/eventqueue/RubyEventQueueNode.hh
/gem5/src/mem/ruby/libruby.hh
Network.cc
Network.hh
simple/HierarchicalSwitchTopology.cc
simple/HierarchicalSwitchTopology.hh
simple/PerfectSwitch.cc
simple/PerfectSwitch.hh
simple/PtToPtTopology.hh
simple/SimpleNetwork.cc
simple/SimpleNetwork.hh
simple/Switch.cc
simple/Switch.hh
simple/Throttle.cc
simple/Throttle.hh
simple/Topology.cc
simple/Topology.hh
simple/Torus2DTopology.cc
simple/Torus2DTopology.hh
topologies/Crossbar.py
topologies/Mesh.py
topologies/MeshDirCorners.py
topologies/SConscript
/gem5/src/mem/ruby/profiler/AddressProfiler.cc
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/recorder/CacheRecorder.cc
/gem5/src/mem/ruby/recorder/CacheRecorder.hh
/gem5/src/mem/ruby/recorder/TraceRecord.cc
/gem5/src/mem/ruby/recorder/TraceRecord.hh
/gem5/src/mem/ruby/recorder/Tracer.cc
/gem5/src/mem/ruby/recorder/Tracer.hh
/gem5/src/mem/ruby/storebuffer/hfa.hh
/gem5/src/mem/ruby/storebuffer/hfatypes.hh
/gem5/src/mem/ruby/storebuffer/interface.cc
/gem5/src/mem/ruby/storebuffer/interface.hh
/gem5/src/mem/ruby/storebuffer/stb_interface.cc
/gem5/src/mem/ruby/storebuffer/stb_interface.hh
/gem5/src/mem/ruby/storebuffer/storebuffer.cc
/gem5/src/mem/ruby/storebuffer/storebuffer.hh
/gem5/src/mem/ruby/system/DirectoryMemory.cc
/gem5/src/mem/ruby/system/PersistentTable.cc
/gem5/src/mem/ruby/system/PersistentTable.hh
/gem5/src/mem/ruby/system/SparseMemory.cc
/gem5/src/mem/ruby/system/SparseMemory.hh
7032:9f938aea1942 22-Mar-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Reorganized Ruby topology and protocol files

7030:a200627c3d42 22-Mar-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Disable adaptive routing by for faster simulation perf.

7024:30883414ad10 22-Mar-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Finally removed bash code cira. 2001ish!

7020:34a5bdcce1e6 22-Mar-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Removed the obsolete file specified network files


simple/Network_Files/GarnetFileMaker.py
simple/Network_Files/NUCA_Procs-16_ProcsPerChip-16_L2Banks-16_Memories-16.txt
simple/Network_Files/NUCA_Procs-16_ProcsPerChip-16_L2Banks-16_Memories-4.txt
simple/Network_Files/NUCA_Procs-16_ProcsPerChip-16_L2Banks-16_Memories-8.txt
simple/Network_Files/NUCA_Procs-16_ProcsPerChip-1_L2Banks-16_Memories-16.txt
simple/Network_Files/NUCA_Procs-16_ProcsPerChip-4_L2Banks-16_Memories-16.txt
simple/Network_Files/NUCA_Procs-16_ProcsPerChip-4_L2Banks-16_Memories-4.txt
simple/Network_Files/NUCA_Procs-16_ProcsPerChip-4_L2Banks-32_Memories-4.txt
simple/Network_Files/NUCA_Procs-16_ProcsPerChip-4_L2Banks-4_Memories-16.txt
simple/Network_Files/NUCA_Procs-16_ProcsPerChip-4_L2Banks-4_Memories-4.txt
simple/Network_Files/NUCA_Procs-1_ProcsPerChip-1_L2Banks-1_Memories-1.txt
simple/Network_Files/NUCA_Procs-1_ProcsPerChip-1_L2Banks-256_Memories-1.txt
simple/Network_Files/NUCA_Procs-1_ProcsPerChip-1_L2Banks-32_Memories-1.txt
simple/Network_Files/NUCA_Procs-1_ProcsPerChip-1_L2Banks-64_Memories-1.txt
simple/Network_Files/NUCA_Procs-2_ProcsPerChip-1_L2Banks-2_Memories-2.txt
simple/Network_Files/NUCA_Procs-2_ProcsPerChip-2_L2Banks-2_Memories-2.txt
simple/Network_Files/NUCA_Procs-32_ProcsPerChip-32_L2Banks-32_Memories-16.txt
simple/Network_Files/NUCA_Procs-32_ProcsPerChip-32_L2Banks-32_Memories-4.txt
simple/Network_Files/NUCA_Procs-4_ProcsPerChip-1_L2Banks-4_Memories-4.txt
simple/Network_Files/NUCA_Procs-4_ProcsPerChip-4_L2Banks-4_Memories-4.txt
simple/Network_Files/NUCA_Procs-7_ProcsPerChip-7_L2Banks-7_Memories-7.txt
simple/Network_Files/NUCA_Procs-8_ProcsPerChip-1_L2Banks-8_Memories-8.txt
simple/Network_Files/NUCA_Procs-8_ProcsPerChip-4_L2Banks-8_Memories-8.txt
simple/Network_Files/NUCA_Procs-8_ProcsPerChip-8_L2Banks-256_Memories-8.txt
simple/Network_Files/NUCA_Procs-8_ProcsPerChip-8_L2Banks-8_Memories-8.txt
simple/Network_Files/NetworkFileMaker.py
simple/Network_Files/TLC_Procs-8_ProcsPerChip-8_L2Banks-256_Memories-8.txt
simple/Network_Files/TOKEN_CMP_Procs-16_ProcsPerChip-16_L2Banks-16_Memories-16.txt
simple/Network_Files/TOKEN_CMP_Procs-16_ProcsPerChip-4_L2Banks-16_Memories-16.txt
7019:a49fd5febdce 22-Mar-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Added copyright to many Ruby *.py files

7009:44ed5e0c7228 16-Mar-2010 Nathan Binkert <nate@binkert.org>

orion: Make declarations match definition

7002:48a19d52d939 10-Mar-2010 Nathan Binkert <nate@binkert.org>

ruby: get rid of std-includes.hh
Do not use "using namespace std;" in headers
Include header files as needed


/gem5/src/cpu/rubytest/CheckTable.hh
/gem5/src/mem/gems_common/Map.hh
/gem5/src/mem/gems_common/PrioHeap.hh
/gem5/src/mem/gems_common/RefCnt.hh
/gem5/src/mem/gems_common/Vector.hh
/gem5/src/mem/gems_common/std-includes.hh
/gem5/src/mem/gems_common/util.cc
/gem5/src/mem/gems_common/util.hh
/gem5/src/mem/ruby/buffers/MessageBuffer.hh
/gem5/src/mem/ruby/buffers/MessageBufferNode.cc
/gem5/src/mem/ruby/buffers/MessageBufferNode.hh
/gem5/src/mem/ruby/common/Address.hh
/gem5/src/mem/ruby/common/Consumer.hh
/gem5/src/mem/ruby/common/DataBlock.hh
/gem5/src/mem/ruby/common/Debug.cc
/gem5/src/mem/ruby/common/Debug.hh
/gem5/src/mem/ruby/common/Global.hh
/gem5/src/mem/ruby/common/Histogram.cc
/gem5/src/mem/ruby/common/Histogram.hh
/gem5/src/mem/ruby/eventqueue/RubyEventQueue.hh
/gem5/src/mem/ruby/eventqueue/RubyEventQueueNode.cc
/gem5/src/mem/ruby/eventqueue/RubyEventQueueNode.hh
garnet/fixed-pipeline/NetworkInterface_d.cc
garnet/flexible-pipeline/NetworkInterface.cc
simple/PerfectSwitch.cc
simple/PerfectSwitch.hh
simple/Switch.cc
simple/Switch.hh
simple/Topology.cc
simple/Topology.hh
/gem5/src/mem/ruby/profiler/CacheProfiler.hh
/gem5/src/mem/ruby/profiler/MemCntrlProfiler.cc
/gem5/src/mem/ruby/profiler/MemCntrlProfiler.hh
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/recorder/CacheRecorder.hh
/gem5/src/mem/ruby/recorder/Tracer.cc
/gem5/src/mem/ruby/recorder/Tracer.hh
/gem5/src/mem/ruby/slicc_interface/Message.hh
/gem5/src/mem/ruby/system/MachineID.hh
/gem5/src/mem/ruby/system/MemoryNode.cc
/gem5/src/mem/ruby/system/MemoryNode.hh
/gem5/src/mem/ruby/system/NodeID.hh
/gem5/src/mem/ruby/system/PseudoLRUPolicy.hh
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/mem/slicc/symbols/Type.py
6968:33d2b758697b 01-Feb-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Added FS support to the simple mesh topology

Added full-system support to the simple mesh toplogy by allowing dma contrllers
to be attached to router zero in the network.

6920:e031f09a7dcc 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Re-enabled orion power models

Removed the dummy power function implementations so that Orion can implement
them correctly. Since Orion lacks modular design, this patch simply enables
scons to compile it. There are no python configuration changes in this patch.

6918:9b57f0108bc8 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Converted Garnet to M5 configuration

6917:341a71fd2600 29-Jan-2010 Steve Reinhardt <steve.reinhardt@amd.com>

Garnet: reorganize directory tree.
Rename the ruby/network/garnet-foo directories to garnet/foo.
Move the common NetworkHeader.hh file from garnet-fixed-pipeline
up to the common garnet directory.
Fix up include paths.


garnet-fixed-pipeline/CreditLink_d.hh
garnet-fixed-pipeline/GarnetNetwork_d.cc
garnet-fixed-pipeline/GarnetNetwork_d.hh
garnet-fixed-pipeline/InputUnit_d.cc
garnet-fixed-pipeline/InputUnit_d.hh
garnet-fixed-pipeline/NetworkHeader.hh
garnet-fixed-pipeline/NetworkInterface_d.cc
garnet-fixed-pipeline/NetworkInterface_d.hh
garnet-fixed-pipeline/NetworkLink_d.cc
garnet-fixed-pipeline/NetworkLink_d.hh
garnet-fixed-pipeline/OutVcState_d.cc
garnet-fixed-pipeline/OutVcState_d.hh
garnet-fixed-pipeline/OutputUnit_d.cc
garnet-fixed-pipeline/OutputUnit_d.hh
garnet-fixed-pipeline/Router_d.cc
garnet-fixed-pipeline/Router_d.hh
garnet-fixed-pipeline/RoutingUnit_d.cc
garnet-fixed-pipeline/RoutingUnit_d.hh
garnet-fixed-pipeline/SConscript
garnet-fixed-pipeline/SWallocator_d.cc
garnet-fixed-pipeline/SWallocator_d.hh
garnet-fixed-pipeline/Switch_d.cc
garnet-fixed-pipeline/Switch_d.hh
garnet-fixed-pipeline/VCallocator_d.cc
garnet-fixed-pipeline/VCallocator_d.hh
garnet-fixed-pipeline/VirtualChannel_d.cc
garnet-fixed-pipeline/VirtualChannel_d.hh
garnet-fixed-pipeline/flitBuffer_d.cc
garnet-fixed-pipeline/flitBuffer_d.hh
garnet-fixed-pipeline/flit_d.cc
garnet-fixed-pipeline/flit_d.hh
garnet-flexible-pipeline/FlexibleConsumer.hh
garnet-flexible-pipeline/GarnetNetwork.cc
garnet-flexible-pipeline/GarnetNetwork.hh
garnet-flexible-pipeline/InVcState.cc
garnet-flexible-pipeline/InVcState.hh
garnet-flexible-pipeline/NetworkConfig.hh
garnet-flexible-pipeline/NetworkInterface.cc
garnet-flexible-pipeline/NetworkInterface.hh
garnet-flexible-pipeline/NetworkLink.cc
garnet-flexible-pipeline/NetworkLink.hh
garnet-flexible-pipeline/OutVcState.cc
garnet-flexible-pipeline/OutVcState.hh
garnet-flexible-pipeline/Router.cc
garnet-flexible-pipeline/Router.hh
garnet-flexible-pipeline/SConscript
garnet-flexible-pipeline/VCarbiter.cc
garnet-flexible-pipeline/VCarbiter.hh
garnet-flexible-pipeline/flit.cc
garnet-flexible-pipeline/flit.hh
garnet-flexible-pipeline/flitBuffer.cc
garnet-flexible-pipeline/flitBuffer.hh
garnet-flexible-pipeline/netconfig.defaults
garnet/NetworkHeader.hh
garnet/fixed-pipeline/CreditLink_d.hh
garnet/fixed-pipeline/GarnetNetwork_d.cc
garnet/fixed-pipeline/GarnetNetwork_d.hh
garnet/fixed-pipeline/InputUnit_d.cc
garnet/fixed-pipeline/InputUnit_d.hh
garnet/fixed-pipeline/NetworkInterface_d.cc
garnet/fixed-pipeline/NetworkInterface_d.hh
garnet/fixed-pipeline/NetworkLink_d.cc
garnet/fixed-pipeline/NetworkLink_d.hh
garnet/fixed-pipeline/OutVcState_d.cc
garnet/fixed-pipeline/OutVcState_d.hh
garnet/fixed-pipeline/OutputUnit_d.cc
garnet/fixed-pipeline/OutputUnit_d.hh
garnet/fixed-pipeline/Router_d.cc
garnet/fixed-pipeline/Router_d.hh
garnet/fixed-pipeline/RoutingUnit_d.cc
garnet/fixed-pipeline/RoutingUnit_d.hh
garnet/fixed-pipeline/SConscript
garnet/fixed-pipeline/SWallocator_d.cc
garnet/fixed-pipeline/SWallocator_d.hh
garnet/fixed-pipeline/Switch_d.cc
garnet/fixed-pipeline/Switch_d.hh
garnet/fixed-pipeline/VCallocator_d.cc
garnet/fixed-pipeline/VCallocator_d.hh
garnet/fixed-pipeline/VirtualChannel_d.cc
garnet/fixed-pipeline/VirtualChannel_d.hh
garnet/fixed-pipeline/flitBuffer_d.cc
garnet/fixed-pipeline/flitBuffer_d.hh
garnet/fixed-pipeline/flit_d.cc
garnet/fixed-pipeline/flit_d.hh
garnet/flexible-pipeline/FlexibleConsumer.hh
garnet/flexible-pipeline/GarnetNetwork.cc
garnet/flexible-pipeline/GarnetNetwork.hh
garnet/flexible-pipeline/InVcState.cc
garnet/flexible-pipeline/InVcState.hh
garnet/flexible-pipeline/NetworkConfig.hh
garnet/flexible-pipeline/NetworkInterface.cc
garnet/flexible-pipeline/NetworkInterface.hh
garnet/flexible-pipeline/NetworkLink.cc
garnet/flexible-pipeline/NetworkLink.hh
garnet/flexible-pipeline/OutVcState.cc
garnet/flexible-pipeline/OutVcState.hh
garnet/flexible-pipeline/Router.cc
garnet/flexible-pipeline/Router.hh
garnet/flexible-pipeline/SConscript
garnet/flexible-pipeline/VCarbiter.cc
garnet/flexible-pipeline/VCarbiter.hh
garnet/flexible-pipeline/flit.cc
garnet/flexible-pipeline/flit.hh
garnet/flexible-pipeline/flitBuffer.cc
garnet/flexible-pipeline/flitBuffer.hh
garnet/flexible-pipeline/netconfig.defaults
6916:a421f60f0e87 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Added a mesh topology

6895:5f3d2d3f977e 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: added ruby stats print
Moved the previous rubymem stats print feature to ruby System so that ruby
stats are printed on simulation exit.

6891:77451885bb00 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Removed out_link_vec from Consumer
Removed the out_line_vec data structure from the Consumer. I'm not sure
what this did before, but currently it has no usefulness.

6881:5a61a8a9009a 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: connects sm queues to the network

6879:c07cf29b5a33 29-Jan-2010 Steve Reinhardt <steve.reinhardt@amd.com>

ruby: Add support for generating topologies in Python.

6876:a658c315512c 29-Jan-2010 Steve Reinhardt <steve.reinhardt@amd.com>

ruby: Convert most Ruby objects to M5 SimObjects.
The necessary companion conversion of Ruby objects generated by SLICC
are converted to M5 SimObjects in the following patch, so this patch
alone does not compile.
Conversion of Garnet network models is also handled in a separate
patch; that code is temporarily disabled from compiling to allow
testing of interim code.


/gem5/configs/example/memtest-ruby.py
/gem5/src/mem/SConscript
/gem5/src/mem/ruby/SConscript
/gem5/src/mem/ruby/common/Debug.cc
/gem5/src/mem/ruby/common/Debug.hh
/gem5/src/mem/ruby/common/Debug.py
/gem5/src/mem/ruby/common/SConscript
/gem5/src/mem/ruby/config/MESI_CMP_directory.rb
/gem5/src/mem/ruby/config/MI_example-homogeneous.rb
/gem5/src/mem/ruby/config/MI_example.rb
/gem5/src/mem/ruby/config/MOESI_CMP_directory.rb
/gem5/src/mem/ruby/config/MOESI_CMP_token.rb
/gem5/src/mem/ruby/config/MOESI_hammer-homogeneous.rb
/gem5/src/mem/ruby/config/MOESI_hammer.rb
/gem5/src/mem/ruby/config/SConscript
/gem5/src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb
/gem5/src/mem/ruby/config/assert.rb
/gem5/src/mem/ruby/config/cfg.rb
/gem5/src/mem/ruby/config/defaults.rb
/gem5/src/mem/ruby/config/libruby_cfg_test.cc
/gem5/src/mem/ruby/config/print_cfg.rb
/gem5/src/mem/ruby/config/util.rb
/gem5/src/mem/ruby/eventqueue/RubyEventQueue.cc
/gem5/src/mem/ruby/libruby.cc
Network.cc
Network.hh
Network.py
SConscript
garnet-fixed-pipeline/GarnetNetwork_d.cc
garnet-fixed-pipeline/GarnetNetwork_d.hh
garnet-fixed-pipeline/SConscript
garnet-flexible-pipeline/GarnetNetwork.cc
garnet-flexible-pipeline/GarnetNetwork.hh
garnet-flexible-pipeline/NetworkConfig.hh
garnet-flexible-pipeline/SConscript
orion/SConscript
simple/HierarchicalSwitchTopology.hh
simple/PtToPtTopology.hh
simple/SConscript
simple/SimpleNetwork.cc
simple/SimpleNetwork.hh
simple/SimpleNetwork.py
simple/Topology.cc
simple/Topology.hh
simple/Torus2DTopology.hh
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/profiler/Profiler.py
/gem5/src/mem/ruby/profiler/SConscript
/gem5/src/mem/ruby/recorder/SConscript
/gem5/src/mem/ruby/recorder/Tracer.cc
/gem5/src/mem/ruby/recorder/Tracer.hh
/gem5/src/mem/ruby/recorder/Tracer.py
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/slicc_interface/Controller.py
/gem5/src/mem/ruby/slicc_interface/SConscript
/gem5/src/mem/ruby/system/Cache.py
/gem5/src/mem/ruby/system/CacheMemory.cc
/gem5/src/mem/ruby/system/CacheMemory.hh
/gem5/src/mem/ruby/system/DMASequencer.cc
/gem5/src/mem/ruby/system/DMASequencer.hh
/gem5/src/mem/ruby/system/DirectoryMemory.cc
/gem5/src/mem/ruby/system/DirectoryMemory.hh
/gem5/src/mem/ruby/system/DirectoryMemory.py
/gem5/src/mem/ruby/system/MemoryControl.cc
/gem5/src/mem/ruby/system/MemoryControl.hh
/gem5/src/mem/ruby/system/MemoryControl.py
/gem5/src/mem/ruby/system/RubyPort.cc
/gem5/src/mem/ruby/system/RubyPort.hh
/gem5/src/mem/ruby/system/RubySystem.py
/gem5/src/mem/ruby/system/SConscript
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/Sequencer.hh
/gem5/src/mem/ruby/system/Sequencer.py
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/ruby/system/System.hh
6875:5eb6e323b595 29-Jan-2010 Steve Reinhardt <steve.reinhardt@amd.com>

ruby: get rid of obsolete, unused CustomTopology class.

6846:60e0df8086f0 17-Sep-2009 Polina Dudnik <pdudnik@cs.wisc.edu>

Functionality migrated to sequencer.

6838:829892ec644c 14-Sep-2009 Derek Hower <drh5@cs.wisc.edu>

ruby: removed stray printf

6795:394bc95d417b 18-Nov-2009 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: removed the chip pointer from MessageBuffer
The Chip object no longer exists and thus is removed from the MessageBuffer
constructor.

6781:8da9d36fc14a 18-Nov-2009 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Added default names to message buffers
Added default names to message buffers created by the simple network.

6762:a22a47e60c21 18-Nov-2009 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Ruby destruction fix.

6712:b95abe00dd9d 04-Nov-2009 Nathan Binkert <nate@binkert.org>

build: fix compile problems pointed out by gcc 4.4

6700:deb871e1fc27 28-Oct-2009 Nathan Binkert <nate@binkert.org>

license: Fix license on network model code

This mostly was a matter of changing the license owner to Princeton
which is as it should have been. The code was originally licensed
under the GPL but was relicensed as BSD by Li-Shiuan Peh on July 27,
2009. This relicensing was in an explicit e-mail to Nathan Binkert,
Brad Beckmann, Mark Hill, David Wood, and Steve Reinhardt.


Network.cc
garnet-fixed-pipeline/CreditLink_d.hh
garnet-fixed-pipeline/GarnetNetwork_d.cc
garnet-fixed-pipeline/GarnetNetwork_d.hh
garnet-fixed-pipeline/InputUnit_d.cc
garnet-fixed-pipeline/InputUnit_d.hh
garnet-fixed-pipeline/NetworkHeader.hh
garnet-fixed-pipeline/NetworkInterface_d.cc
garnet-fixed-pipeline/NetworkInterface_d.hh
garnet-fixed-pipeline/NetworkLink_d.cc
garnet-fixed-pipeline/NetworkLink_d.hh
garnet-fixed-pipeline/OutVcState_d.cc
garnet-fixed-pipeline/OutVcState_d.hh
garnet-fixed-pipeline/OutputUnit_d.cc
garnet-fixed-pipeline/OutputUnit_d.hh
garnet-fixed-pipeline/Router_d.cc
garnet-fixed-pipeline/Router_d.hh
garnet-fixed-pipeline/RoutingUnit_d.cc
garnet-fixed-pipeline/RoutingUnit_d.hh
garnet-fixed-pipeline/SWallocator_d.cc
garnet-fixed-pipeline/SWallocator_d.hh
garnet-fixed-pipeline/Switch_d.cc
garnet-fixed-pipeline/Switch_d.hh
garnet-fixed-pipeline/VCallocator_d.cc
garnet-fixed-pipeline/VCallocator_d.hh
garnet-fixed-pipeline/VirtualChannel_d.cc
garnet-fixed-pipeline/VirtualChannel_d.hh
garnet-fixed-pipeline/flitBuffer_d.cc
garnet-fixed-pipeline/flitBuffer_d.hh
garnet-fixed-pipeline/flit_d.cc
garnet-fixed-pipeline/flit_d.hh
garnet-flexible-pipeline/FlexibleConsumer.hh
garnet-flexible-pipeline/GarnetNetwork.cc
garnet-flexible-pipeline/GarnetNetwork.hh
garnet-flexible-pipeline/InVcState.cc
garnet-flexible-pipeline/InVcState.hh
garnet-flexible-pipeline/NetworkConfig.hh
garnet-flexible-pipeline/NetworkInterface.cc
garnet-flexible-pipeline/NetworkInterface.hh
garnet-flexible-pipeline/NetworkLink.cc
garnet-flexible-pipeline/NetworkLink.hh
garnet-flexible-pipeline/OutVcState.cc
garnet-flexible-pipeline/OutVcState.hh
garnet-flexible-pipeline/Router.cc
garnet-flexible-pipeline/Router.hh
garnet-flexible-pipeline/VCarbiter.cc
garnet-flexible-pipeline/VCarbiter.hh
garnet-flexible-pipeline/flit.cc
garnet-flexible-pipeline/flit.hh
garnet-flexible-pipeline/flitBuffer.cc
garnet-flexible-pipeline/flitBuffer.hh
6493:1fa51760a963 07-Aug-2009 Tushar Krishna <Tushar.Krishna@amd.com>

bug fix for data_msg_size in network/Network.cc

6372:f1a41ea3bbab 18-Jul-2009 Derek Hower <drh5@cs.wisc.edu>

ruby: removed all refs to old RubyConfig


/gem5/src/mem/ruby/buffers/MessageBuffer.cc
/gem5/src/mem/ruby/common/Address.hh
/gem5/src/mem/ruby/common/NetDest.cc
/gem5/src/mem/ruby/common/NetDest.hh
/gem5/src/mem/ruby/common/Set.cc
/gem5/src/mem/ruby/common/Set.hh
/gem5/src/mem/ruby/common/SubBlock.hh
/gem5/src/mem/ruby/config/RubyConfig.cc
/gem5/src/mem/ruby/config/RubyConfig.hh
/gem5/src/mem/ruby/eventqueue/RubyEventQueue.cc
/gem5/src/mem/ruby/filters/AbstractBloomFilter.hh
/gem5/src/mem/ruby/filters/BlockBloomFilter.hh
/gem5/src/mem/ruby/filters/BulkBloomFilter.hh
/gem5/src/mem/ruby/filters/GenericBloomFilter.cc
/gem5/src/mem/ruby/filters/GenericBloomFilter.hh
/gem5/src/mem/ruby/filters/H3BloomFilter.hh
/gem5/src/mem/ruby/filters/LSB_CountingBloomFilter.hh
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.hh
/gem5/src/mem/ruby/filters/MultiGrainBloomFilter.hh
/gem5/src/mem/ruby/filters/NonCountingBloomFilter.hh
Network.hh
garnet-flexible-pipeline/NetworkConfig.hh
simple/PerfectSwitch.cc
simple/SimpleNetwork.cc
simple/Throttle.cc
simple/Topology.cc
/gem5/src/mem/ruby/profiler/AccessTraceForAddress.hh
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/profiler/StoreTrace.hh
/gem5/src/mem/ruby/recorder/Tracer.cc
/gem5/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
/gem5/src/mem/ruby/system/AbstractMemOrCache.hh
/gem5/src/mem/ruby/system/CacheMemory.hh
/gem5/src/mem/ruby/system/DirectoryMemory.cc
/gem5/src/mem/ruby/system/PerfectCacheMemory.hh
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/Sequencer.hh
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/ruby/system/System.hh
/gem5/src/mem/ruby/tester/RaceyPseudoThread.cc
/gem5/src/mem/slicc/ast/EnqueueStatementAST.cc
/gem5/src/mem/slicc/symbols/StateMachine.cc
/gem5/src/mem/slicc/symbols/Type.cc
6371:a1768b396928 18-Jul-2009 Derek Hower <drh5@cs.wisc.edu>

ruby: removed dead files

6294:b42cea5e1625 08-Jul-2009 Derek Hower <drh5@cs.wisc.edu>

removed stray debug print

6288:083a6806dd96 06-Jul-2009 Nathan Binkert <nate@binkert.org>

ruby: apply some fixes that were overwritten by the recent ruby import.

6286:40b142645016 06-Jul-2009 Nathan Binkert <nate@binkert.org>

scons: update SCons files for changes in ruby.

6285:ce086eca1ede 06-Jul-2009 Nathan Binkert <nate@binkert.org>

ruby: Import the latest ruby changes from gems.
This was done with an automated process, so there could be things that were
done in this tree in the past that didn't make it. One known regression
is that atomic memory operations do not seem to work properly anymore.


/gem5/src/mem/gems_common/std-includes.hh
/gem5/src/mem/gems_common/util.cc
/gem5/src/mem/gems_common/util.hh
/gem5/src/mem/protocol/MESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-mem.sm
/gem5/src/mem/protocol/MESI_CMP_directory-msg.sm
/gem5/src/mem/protocol/MESI_CMP_directory.slicc
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MI_example-dma.sm
/gem5/src/mem/protocol/MI_example-msg.sm
/gem5/src/mem/protocol/MI_example.slicc
/gem5/src/mem/protocol/RubySlicc_ComponentMapping.sm
/gem5/src/mem/protocol/RubySlicc_Exports.sm
/gem5/src/mem/protocol/RubySlicc_Types.sm
/gem5/src/mem/protocol/standard_1level_CMP-protocol.sm
/gem5/src/mem/ruby/buffers/MessageBuffer.cc
/gem5/src/mem/ruby/buffers/MessageBuffer.hh
/gem5/src/mem/ruby/common/Address.hh
/gem5/src/mem/ruby/common/Consumer.hh
/gem5/src/mem/ruby/common/DataBlock.cc
/gem5/src/mem/ruby/common/DataBlock.hh
/gem5/src/mem/ruby/common/Debug.cc
/gem5/src/mem/ruby/common/Debug.hh
/gem5/src/mem/ruby/common/Driver.hh
/gem5/src/mem/ruby/common/Global.hh
/gem5/src/mem/ruby/common/Set.cc
/gem5/src/mem/ruby/common/SubBlock.cc
/gem5/src/mem/ruby/common/SubBlock.hh
/gem5/src/mem/ruby/common/TypeDefines.hh
/gem5/src/mem/ruby/config/MI_example-homogeneous.rb
/gem5/src/mem/ruby/config/RubyConfig.cc
/gem5/src/mem/ruby/config/RubyConfig.hh
/gem5/src/mem/ruby/config/cfg.rb
/gem5/src/mem/ruby/config/config.hh
/gem5/src/mem/ruby/config/defaults.rb
/gem5/src/mem/ruby/config/libruby_cfg_test.cc
/gem5/src/mem/ruby/config/print_cfg.rb
/gem5/src/mem/ruby/config/rubyconfig.defaults
/gem5/src/mem/ruby/config/tester.defaults
/gem5/src/mem/ruby/eventqueue/RubyEventQueue.cc
/gem5/src/mem/ruby/filters/AbstractBloomFilter.hh
/gem5/src/mem/ruby/filters/BlockBloomFilter.cc
/gem5/src/mem/ruby/filters/BlockBloomFilter.hh
/gem5/src/mem/ruby/filters/BulkBloomFilter.cc
/gem5/src/mem/ruby/filters/BulkBloomFilter.hh
/gem5/src/mem/ruby/filters/GenericBloomFilter.cc
/gem5/src/mem/ruby/filters/GenericBloomFilter.hh
/gem5/src/mem/ruby/filters/H3BloomFilter.cc
/gem5/src/mem/ruby/filters/H3BloomFilter.hh
/gem5/src/mem/ruby/filters/LSB_CountingBloomFilter.cc
/gem5/src/mem/ruby/filters/LSB_CountingBloomFilter.hh
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.hh
/gem5/src/mem/ruby/filters/MultiGrainBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiGrainBloomFilter.hh
/gem5/src/mem/ruby/filters/NonCountingBloomFilter.cc
/gem5/src/mem/ruby/filters/NonCountingBloomFilter.hh
/gem5/src/mem/ruby/init.cc
/gem5/src/mem/ruby/init.hh
/gem5/src/mem/ruby/libruby.cc
/gem5/src/mem/ruby/libruby.hh
/gem5/src/mem/ruby/libruby_internal.hh
Network.cc
Network.hh
garnet-fixed-pipeline/CreditLink_d.hh
garnet-fixed-pipeline/GarnetNetwork_d.cc
garnet-fixed-pipeline/GarnetNetwork_d.hh
garnet-fixed-pipeline/NetworkInterface_d.cc
garnet-fixed-pipeline/NetworkLink_d.cc
garnet-fixed-pipeline/NetworkLink_d.hh
garnet-fixed-pipeline/OutVcState_d.cc
garnet-fixed-pipeline/OutVcState_d.hh
garnet-fixed-pipeline/OutputUnit_d.cc
garnet-fixed-pipeline/Router_d.cc
garnet-fixed-pipeline/SWallocator_d.cc
garnet-fixed-pipeline/VCallocator_d.cc
garnet-flexible-pipeline/GarnetNetwork.cc
garnet-flexible-pipeline/GarnetNetwork.hh
garnet-flexible-pipeline/NetworkConfig.hh
garnet-flexible-pipeline/NetworkInterface.cc
garnet-flexible-pipeline/NetworkLink.cc
garnet-flexible-pipeline/Router.cc
simple/CustomTopology.cc
simple/CustomTopology.hh
simple/HierarchicalSwitchTopology.cc
simple/HierarchicalSwitchTopology.hh
simple/PerfectSwitch.cc
simple/PtToPtTopology.cc
simple/PtToPtTopology.hh
simple/SimpleNetwork.cc
simple/SimpleNetwork.hh
simple/Switch.cc
simple/Switch.hh
simple/Throttle.cc
simple/Throttle.hh
simple/Topology.cc
simple/Topology.hh
simple/Torus2DTopology.cc
simple/Torus2DTopology.hh
/gem5/src/mem/ruby/profiler/AddressProfiler.cc
/gem5/src/mem/ruby/profiler/AddressProfiler.hh
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/recorder/CacheRecorder.cc
/gem5/src/mem/ruby/recorder/CacheRecorder.hh
/gem5/src/mem/ruby/recorder/TraceRecord.cc
/gem5/src/mem/ruby/recorder/TraceRecord.hh
/gem5/src/mem/ruby/recorder/Tracer.cc
/gem5/src/mem/ruby/recorder/Tracer.hh
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
/gem5/src/mem/ruby/slicc_interface/AbstractChip.cc
/gem5/src/mem/ruby/slicc_interface/AbstractChip.hh
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.cc
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
/gem5/src/mem/ruby/storebuffer/hfa.hh
/gem5/src/mem/ruby/storebuffer/hfatypes.hh
/gem5/src/mem/ruby/storebuffer/interface.cc
/gem5/src/mem/ruby/storebuffer/interface.hh
/gem5/src/mem/ruby/storebuffer/stb_interface.cc
/gem5/src/mem/ruby/storebuffer/stb_interface.hh
/gem5/src/mem/ruby/storebuffer/storebuffer.cc
/gem5/src/mem/ruby/storebuffer/storebuffer.hh
/gem5/src/mem/ruby/system/AbstractMemOrCache.hh
/gem5/src/mem/ruby/system/CacheMemory.hh
/gem5/src/mem/ruby/system/DMASequencer.cc
/gem5/src/mem/ruby/system/DMASequencer.hh
/gem5/src/mem/ruby/system/DirectoryMemory.cc
/gem5/src/mem/ruby/system/DirectoryMemory.hh
/gem5/src/mem/ruby/system/MemoryControl.cc
/gem5/src/mem/ruby/system/MemoryControl.hh
/gem5/src/mem/ruby/system/MemoryVector.hh
/gem5/src/mem/ruby/system/NodePersistentTable.cc
/gem5/src/mem/ruby/system/NodePersistentTable.hh
/gem5/src/mem/ruby/system/PersistentArbiter.cc
/gem5/src/mem/ruby/system/PersistentArbiter.hh
/gem5/src/mem/ruby/system/PersistentTable.cc
/gem5/src/mem/ruby/system/PersistentTable.hh
/gem5/src/mem/ruby/system/ProcessorInterface.hh
/gem5/src/mem/ruby/system/RubyPort.cc
/gem5/src/mem/ruby/system/RubyPort.hh
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/Sequencer.hh
/gem5/src/mem/ruby/system/StoreBuffer.cc
/gem5/src/mem/ruby/system/StoreBuffer.hh
/gem5/src/mem/ruby/system/StoreCache.cc
/gem5/src/mem/ruby/system/StoreCache.hh
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/ruby/system/System.hh
/gem5/src/mem/ruby/system/TBETable.hh
/gem5/src/mem/ruby/tester/BarrierGenerator.cc
/gem5/src/mem/ruby/tester/BarrierGenerator.hh
/gem5/src/mem/ruby/tester/Check.cc
/gem5/src/mem/ruby/tester/Check.hh
/gem5/src/mem/ruby/tester/CheckTable.cc
/gem5/src/mem/ruby/tester/CheckTable.hh
/gem5/src/mem/ruby/tester/DetermGETXGenerator.cc
/gem5/src/mem/ruby/tester/DetermGETXGenerator.hh
/gem5/src/mem/ruby/tester/DetermInvGenerator.cc
/gem5/src/mem/ruby/tester/DetermInvGenerator.hh
/gem5/src/mem/ruby/tester/DetermSeriesGETSGenerator.cc
/gem5/src/mem/ruby/tester/DetermSeriesGETSGenerator.hh
/gem5/src/mem/ruby/tester/DeterministicDriver.cc
/gem5/src/mem/ruby/tester/DeterministicDriver.hh
/gem5/src/mem/ruby/tester/Driver_Tester.cc
/gem5/src/mem/ruby/tester/Driver_Tester.hh
/gem5/src/mem/ruby/tester/EventQueue_Tester.hh
/gem5/src/mem/ruby/tester/Global_Tester.hh
/gem5/src/mem/ruby/tester/Instruction.cc
/gem5/src/mem/ruby/tester/Instruction.hh
/gem5/src/mem/ruby/tester/RaceyDriver.cc
/gem5/src/mem/ruby/tester/RaceyDriver.hh
/gem5/src/mem/ruby/tester/RaceyPseudoThread.cc
/gem5/src/mem/ruby/tester/RaceyPseudoThread.hh
/gem5/src/mem/ruby/tester/RequestGenerator.cc
/gem5/src/mem/ruby/tester/RequestGenerator.hh
/gem5/src/mem/ruby/tester/SpecifiedGenerator.cc
/gem5/src/mem/ruby/tester/SpecifiedGenerator.hh
/gem5/src/mem/ruby/tester/SyntheticDriver.cc
/gem5/src/mem/ruby/tester/SyntheticDriver.hh
/gem5/src/mem/ruby/tester/Tester.cc
/gem5/src/mem/ruby/tester/Tester.hh
/gem5/src/mem/ruby/tester/main.cc
/gem5/src/mem/ruby/tester/main.hh
/gem5/src/mem/ruby/tester/test_framework.cc
/gem5/src/mem/ruby/tester/test_framework.hh
/gem5/src/mem/slicc/ast/ASTs.hh
/gem5/src/mem/slicc/ast/EnqueueStatementAST.cc
/gem5/src/mem/slicc/ast/MachineAST.cc
/gem5/src/mem/slicc/ast/MachineAST.hh
/gem5/src/mem/slicc/ast/MethodCallExprAST.cc
/gem5/src/mem/slicc/ast/NewExprAST.cc
/gem5/src/mem/slicc/ast/NewExprAST.hh
/gem5/src/mem/slicc/ast/ObjDeclAST.cc
/gem5/src/mem/slicc/parser/lexer.ll
/gem5/src/mem/slicc/parser/parser.yy
/gem5/src/mem/slicc/symbols/Func.cc
/gem5/src/mem/slicc/symbols/Func.hh
/gem5/src/mem/slicc/symbols/StateMachine.cc
/gem5/src/mem/slicc/symbols/StateMachine.hh
/gem5/src/mem/slicc/symbols/Symbol.hh
/gem5/src/mem/slicc/symbols/SymbolTable.cc
/gem5/src/mem/slicc/symbols/SymbolTable.hh
/gem5/src/mem/slicc/symbols/Type.cc
/gem5/src/mem/slicc/symbols/Type.hh
/gem5/src/mem/slicc/symbols/Var.hh
6284:a63d1dc4c820 06-Jul-2009 Nathan Binkert <nate@binkert.org>

ruby: replace strings that were missed in original ruby import.


/gem5/src/mem/gems_common/ioutil/attrlex.ll
/gem5/src/mem/gems_common/ioutil/attrparse.yy
/gem5/src/mem/ruby/common/Global.hh
/gem5/src/mem/ruby/common/NetDest.cc
/gem5/src/mem/ruby/common/NetDest.hh
/gem5/src/mem/ruby/common/Set.cc
/gem5/src/mem/ruby/common/Set.hh
/gem5/src/mem/ruby/config/RubyConfig.cc
/gem5/src/mem/ruby/config/RubyConfig.hh
/gem5/src/mem/ruby/eventqueue/RubyEventQueue.hh
/gem5/src/mem/ruby/init.cc
/gem5/src/mem/ruby/init.hh
Network.hh
garnet-fixed-pipeline/CreditLink_d.hh
garnet-fixed-pipeline/GarnetNetwork_d.cc
garnet-fixed-pipeline/GarnetNetwork_d.hh
garnet-fixed-pipeline/InputUnit_d.hh
garnet-fixed-pipeline/NetworkHeader.hh
garnet-fixed-pipeline/NetworkInterface_d.cc
garnet-fixed-pipeline/NetworkInterface_d.hh
garnet-fixed-pipeline/NetworkLink_d.cc
garnet-fixed-pipeline/NetworkLink_d.hh
garnet-fixed-pipeline/OutVcState_d.hh
garnet-fixed-pipeline/OutputUnit_d.hh
garnet-fixed-pipeline/Router_d.cc
garnet-fixed-pipeline/Router_d.hh
garnet-fixed-pipeline/RoutingUnit_d.hh
garnet-fixed-pipeline/SWallocator_d.cc
garnet-fixed-pipeline/SWallocator_d.hh
garnet-fixed-pipeline/Switch_d.hh
garnet-fixed-pipeline/VCallocator_d.cc
garnet-fixed-pipeline/VCallocator_d.hh
garnet-fixed-pipeline/VirtualChannel_d.hh
garnet-fixed-pipeline/flitBuffer_d.hh
garnet-fixed-pipeline/flit_d.hh
garnet-flexible-pipeline/FlexibleConsumer.hh
garnet-flexible-pipeline/GarnetNetwork.cc
garnet-flexible-pipeline/GarnetNetwork.hh
garnet-flexible-pipeline/InVcState.hh
garnet-flexible-pipeline/NetworkConfig.hh
garnet-flexible-pipeline/NetworkInterface.hh
garnet-flexible-pipeline/NetworkLink.cc
garnet-flexible-pipeline/NetworkLink.hh
garnet-flexible-pipeline/OutVcState.hh
garnet-flexible-pipeline/Router.cc
garnet-flexible-pipeline/Router.hh
garnet-flexible-pipeline/VCarbiter.hh
garnet-flexible-pipeline/flit.hh
garnet-flexible-pipeline/flitBuffer.hh
simple/PerfectSwitch.cc
simple/SimpleNetwork.cc
simple/SimpleNetwork.hh
simple/Switch.cc
simple/Throttle.cc
simple/Topology.cc
simple/Topology.hh
/gem5/src/mem/ruby/profiler/AddressProfiler.cc
/gem5/src/mem/ruby/profiler/AddressProfiler.hh
/gem5/src/mem/ruby/profiler/CacheProfiler.cc
/gem5/src/mem/ruby/profiler/CacheProfiler.hh
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc
/gem5/src/mem/ruby/slicc_interface/AbstractChip.cc
/gem5/src/mem/ruby/slicc_interface/NetworkMessage.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.cc
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
/gem5/src/mem/ruby/system/AbstractMemOrCache.hh
/gem5/src/mem/ruby/system/CacheMemory.hh
/gem5/src/mem/ruby/system/DirectoryMemory.cc
/gem5/src/mem/ruby/system/DirectoryMemory.hh
/gem5/src/mem/ruby/system/MachineID.hh
/gem5/src/mem/ruby/system/MemoryControl.cc
/gem5/src/mem/ruby/system/MemoryControl.hh
/gem5/src/mem/ruby/system/NodeID.hh
/gem5/src/mem/ruby/system/NodePersistentTable.hh
/gem5/src/mem/ruby/system/PerfectCacheMemory.hh
/gem5/src/mem/ruby/system/PersistentArbiter.hh
/gem5/src/mem/ruby/system/Sequencer.hh
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/ruby/system/System.hh
/gem5/src/mem/ruby/system/TBETable.hh
/gem5/src/mem/ruby/system/TimerTable.hh
/gem5/src/mem/ruby/tester/Instruction.hh
/gem5/src/mem/ruby/tester/SpecifiedGenerator.cc
/gem5/src/mem/ruby/tester/SpecifiedGenerator.hh
/gem5/src/mem/slicc/ast/AST.cc
/gem5/src/mem/slicc/ast/AST.hh
/gem5/src/mem/slicc/ast/ActionDeclAST.cc
/gem5/src/mem/slicc/ast/ActionDeclAST.hh
/gem5/src/mem/slicc/ast/AssignStatementAST.cc
/gem5/src/mem/slicc/ast/AssignStatementAST.hh
/gem5/src/mem/slicc/ast/ChipComponentAccessAST.cc
/gem5/src/mem/slicc/ast/ChipComponentAccessAST.hh
/gem5/src/mem/slicc/ast/DeclAST.cc
/gem5/src/mem/slicc/ast/DeclAST.hh
/gem5/src/mem/slicc/ast/DeclListAST.cc
/gem5/src/mem/slicc/ast/DeclListAST.hh
/gem5/src/mem/slicc/ast/EnqueueStatementAST.hh
/gem5/src/mem/slicc/ast/EnumDeclAST.cc
/gem5/src/mem/slicc/ast/EnumDeclAST.hh
/gem5/src/mem/slicc/ast/EnumExprAST.cc
/gem5/src/mem/slicc/ast/EnumExprAST.hh
/gem5/src/mem/slicc/ast/ExprAST.cc
/gem5/src/mem/slicc/ast/ExprAST.hh
/gem5/src/mem/slicc/ast/ExprStatementAST.cc
/gem5/src/mem/slicc/ast/ExprStatementAST.hh
/gem5/src/mem/slicc/ast/FormalParamAST.cc
/gem5/src/mem/slicc/ast/FormalParamAST.hh
/gem5/src/mem/slicc/ast/FuncCallExprAST.cc
/gem5/src/mem/slicc/ast/FuncCallExprAST.hh
/gem5/src/mem/slicc/ast/FuncDeclAST.cc
/gem5/src/mem/slicc/ast/FuncDeclAST.hh
/gem5/src/mem/slicc/ast/IfStatementAST.cc
/gem5/src/mem/slicc/ast/IfStatementAST.hh
/gem5/src/mem/slicc/ast/InPortDeclAST.cc
/gem5/src/mem/slicc/ast/InPortDeclAST.hh
/gem5/src/mem/slicc/ast/InfixOperatorExprAST.cc
/gem5/src/mem/slicc/ast/InfixOperatorExprAST.hh
/gem5/src/mem/slicc/ast/LiteralExprAST.cc
/gem5/src/mem/slicc/ast/LiteralExprAST.hh
/gem5/src/mem/slicc/ast/Location.cc
/gem5/src/mem/slicc/ast/Location.hh
/gem5/src/mem/slicc/ast/MachineAST.cc
/gem5/src/mem/slicc/ast/MachineAST.hh
/gem5/src/mem/slicc/ast/MemberExprAST.cc
/gem5/src/mem/slicc/ast/MemberExprAST.hh
/gem5/src/mem/slicc/ast/MethodCallExprAST.cc
/gem5/src/mem/slicc/ast/MethodCallExprAST.hh
/gem5/src/mem/slicc/ast/ObjDeclAST.cc
/gem5/src/mem/slicc/ast/ObjDeclAST.hh
/gem5/src/mem/slicc/ast/OutPortDeclAST.cc
/gem5/src/mem/slicc/ast/OutPortDeclAST.hh
/gem5/src/mem/slicc/ast/PairAST.cc
/gem5/src/mem/slicc/ast/PairAST.hh
/gem5/src/mem/slicc/ast/PairListAST.cc
/gem5/src/mem/slicc/ast/PairListAST.hh
/gem5/src/mem/slicc/ast/PeekStatementAST.cc
/gem5/src/mem/slicc/ast/PeekStatementAST.hh
/gem5/src/mem/slicc/ast/ReturnStatementAST.cc
/gem5/src/mem/slicc/ast/ReturnStatementAST.hh
/gem5/src/mem/slicc/ast/StatementAST.cc
/gem5/src/mem/slicc/ast/StatementAST.hh
/gem5/src/mem/slicc/ast/StatementListAST.cc
/gem5/src/mem/slicc/ast/StatementListAST.hh
/gem5/src/mem/slicc/ast/TransitionDeclAST.cc
/gem5/src/mem/slicc/ast/TransitionDeclAST.hh
/gem5/src/mem/slicc/ast/TypeAST.cc
/gem5/src/mem/slicc/ast/TypeAST.hh
/gem5/src/mem/slicc/ast/TypeDeclAST.cc
/gem5/src/mem/slicc/ast/TypeDeclAST.hh
/gem5/src/mem/slicc/ast/TypeFieldAST.cc
/gem5/src/mem/slicc/ast/TypeFieldAST.hh
/gem5/src/mem/slicc/ast/TypeFieldEnumAST.cc
/gem5/src/mem/slicc/ast/TypeFieldEnumAST.hh
/gem5/src/mem/slicc/ast/TypeFieldMemberAST.cc
/gem5/src/mem/slicc/ast/TypeFieldMemberAST.hh
/gem5/src/mem/slicc/ast/TypeFieldMethodAST.cc
/gem5/src/mem/slicc/ast/TypeFieldMethodAST.hh
/gem5/src/mem/slicc/ast/VarExprAST.cc
/gem5/src/mem/slicc/ast/VarExprAST.hh
/gem5/src/mem/slicc/generator/fileio.cc
/gem5/src/mem/slicc/generator/fileio.hh
/gem5/src/mem/slicc/generator/html_gen.cc
/gem5/src/mem/slicc/generator/html_gen.hh
/gem5/src/mem/slicc/generator/mif_gen.hh
/gem5/src/mem/slicc/main.hh
/gem5/src/mem/slicc/symbols/Func.cc
/gem5/src/mem/slicc/symbols/Func.hh
/gem5/src/mem/slicc/symbols/SymbolTable.hh
/gem5/src/mem/slicc/symbols/Transition.hh
/gem5/src/mem/slicc/symbols/Type.cc
/gem5/src/mem/slicc/symbols/Type.hh
/gem5/src/mem/slicc/symbols/Var.hh
6216:2f4020838149 17-May-2009 Nathan Binkert <nate@binkert.org>

includes: sort includes again


/gem5/src/arch/alpha/isa_traits.hh
/gem5/src/arch/alpha/predecoder.hh
/gem5/src/arch/arm/utility.hh
/gem5/src/arch/mips/dsp.hh
/gem5/src/arch/mips/isa_traits.hh
/gem5/src/arch/mips/utility.hh
/gem5/src/arch/sparc/isa_traits.hh
/gem5/src/arch/sparc/predecoder.hh
/gem5/src/arch/sparc/regfile.hh
/gem5/src/arch/x86/bios/acpi.hh
/gem5/src/arch/x86/bios/e820.hh
/gem5/src/arch/x86/bios/intelmp.cc
/gem5/src/arch/x86/bios/smbios.cc
/gem5/src/arch/x86/bios/smbios.hh
/gem5/src/arch/x86/intmessage.hh
/gem5/src/arch/x86/miscregfile.hh
/gem5/src/arch/x86/pagetable.hh
/gem5/src/arch/x86/pagetable_walker.hh
/gem5/src/arch/x86/predecoder.cc
/gem5/src/arch/x86/regfile.hh
/gem5/src/arch/x86/utility.hh
/gem5/src/arch/x86/x86_traits.hh
/gem5/src/base/cp_annotate.hh
/gem5/src/base/crc.cc
/gem5/src/base/inet.cc
/gem5/src/base/inet.hh
/gem5/src/base/intmath.hh
/gem5/src/base/misc.cc
/gem5/src/base/pollevent.cc
/gem5/src/base/res_list.hh
/gem5/src/base/statistics.hh
/gem5/src/base/stats/mysql.cc
/gem5/src/base/stats/output.cc
/gem5/src/cpu/exetrace.hh
/gem5/src/cpu/inorder/comm.hh
/gem5/src/cpu/inorder/inorder_trace.hh
/gem5/src/cpu/inteltrace.hh
/gem5/src/cpu/legiontrace.hh
/gem5/src/cpu/nativetrace.hh
/gem5/src/cpu/o3/2bit_local_pred.hh
/gem5/src/cpu/o3/bpred_unit.hh
/gem5/src/cpu/o3/comm.hh
/gem5/src/cpu/o3/fetch_impl.hh
/gem5/src/cpu/o3/inst_queue.hh
/gem5/src/cpu/o3/ras.hh
/gem5/src/cpu/o3/store_set.hh
/gem5/src/cpu/o3/tournament_pred.hh
/gem5/src/cpu/ozone/ea_list.hh
/gem5/src/cpu/ozone/inst_queue.hh
/gem5/src/cpu/ozone/null_predictor.hh
/gem5/src/cpu/simple/base.cc
/gem5/src/cpu/simple_thread.hh
/gem5/src/cpu/static_inst.hh
/gem5/src/cpu/thread_context.hh
/gem5/src/dev/alpha/backdoor.hh
/gem5/src/dev/etherlink.hh
/gem5/src/dev/etherpkt.hh
/gem5/src/dev/intel_8254_timer.hh
/gem5/src/dev/mips/backdoor.hh
/gem5/src/dev/ns_gige.cc
/gem5/src/dev/sinic.cc
/gem5/src/dev/x86/intdev.hh
/gem5/src/dev/x86/south_bridge.cc
/gem5/src/kern/tru64/dump_mbuf.cc
/gem5/src/kern/tru64/mbuf.hh
/gem5/src/mem/bus.hh
/gem5/src/mem/cache/cache_impl.hh
/gem5/src/mem/cache/mshr.cc
/gem5/src/mem/cache/tags/fa_lru.cc
/gem5/src/mem/cache/tags/fa_lru.hh
/gem5/src/mem/cache/tags/iic_repl/gen.cc
/gem5/src/mem/cache/tags/iic_repl/repl.hh
/gem5/src/mem/cache/tags/lru.hh
/gem5/src/mem/gems_common/util.cc
/gem5/src/mem/packet.hh
/gem5/src/mem/page_table.hh
/gem5/src/mem/physical.cc
/gem5/src/mem/ruby/common/Debug.hh
/gem5/src/mem/ruby/common/Global.hh
orion/power_ll.cc
orion/power_utils.cc
/gem5/src/mem/rubymem.cc
/gem5/src/mem/slicc/slicc_global.hh
/gem5/src/python/swig/core.i
/gem5/src/python/swig/event.i
/gem5/src/python/swig/pyobject.hh
/gem5/src/python/swig/sim_object.i
/gem5/src/sim/arguments.hh
/gem5/src/sim/eventq.hh
/gem5/src/sim/init.cc
/gem5/src/sim/insttracer.hh
/gem5/src/sim/sim_object.cc
/gem5/src/sim/simulate.cc
/gem5/src/sim/syscall_emul.hh
/gem5/src/unittest/rangemaptest.cc
/gem5/src/unittest/rangemultimaptest.cc
/gem5/util/statetrace/arch/tracechild_amd64.hh
/gem5/util/statetrace/arch/tracechild_i386.hh
/gem5/util/statetrace/arch/tracechild_sparc.hh
6168:ba6fe02228db 11-May-2009 Nathan Binkert <nate@binkert.org>

ruby: add RUBY sticky option that must be set to add ruby to the build
Default is false

6157:eaf2fd8f54c0 11-May-2009 Nathan Binkert <nate@binkert.org>

ruby: Migrate all of ruby and slicc to SCons.
Add the PROTOCOL sticky option sets the coherence protocol that slicc
will parse and therefore ruby will use. This whole process was made
difficult by the fact that the set of files that are output by slicc
are not easily known ahead of time. The easiest thing wound up being
to write a parser for slicc that would tell me. Incidentally this
means we now have a slicc grammar written in python.

6156:76de2027b8ad 11-May-2009 Nathan Binkert <nate@binkert.org>

ruby: clean up a few warnings

6154:6bb54dcb940e 11-May-2009 Nathan Binkert <nate@binkert.org>

ruby: Make ruby #includes use full paths to the files they're including.
This basically means changing all #include statements and changing
autogenerated code so that it generates the correct paths. Because
slicc generates #includes, I had to hard code the include paths to
mem/protocol.


/gem5/src/mem/gems_common/Allocator.hh
/gem5/src/mem/gems_common/Map.hh
/gem5/src/mem/gems_common/PrioHeap.hh
/gem5/src/mem/gems_common/RefCnt_tester.cc
/gem5/src/mem/gems_common/RefCountable.hh
/gem5/src/mem/gems_common/Vector.hh
/gem5/src/mem/gems_common/ioutil/attrlex.ll
/gem5/src/mem/gems_common/ioutil/attrparse.yy
/gem5/src/mem/gems_common/ioutil/confio.cc
/gem5/src/mem/gems_common/ioutil/confio.hh
/gem5/src/mem/gems_common/ioutil/initvar.cc
/gem5/src/mem/gems_common/ioutil/vardecl.hh
/gem5/src/mem/gems_common/util.cc
/gem5/src/mem/gems_common/util.hh
/gem5/src/mem/ruby/buffers/MessageBuffer.cc
/gem5/src/mem/ruby/buffers/MessageBuffer.hh
/gem5/src/mem/ruby/buffers/MessageBufferNode.cc
/gem5/src/mem/ruby/buffers/MessageBufferNode.hh
/gem5/src/mem/ruby/common/Address.cc
/gem5/src/mem/ruby/common/Address.hh
/gem5/src/mem/ruby/common/BigSet.cc
/gem5/src/mem/ruby/common/BigSet.hh
/gem5/src/mem/ruby/common/Consumer.hh
/gem5/src/mem/ruby/common/DataBlock.cc
/gem5/src/mem/ruby/common/DataBlock.hh
/gem5/src/mem/ruby/common/Debug.cc
/gem5/src/mem/ruby/common/Driver.cc
/gem5/src/mem/ruby/common/Driver.hh
/gem5/src/mem/ruby/common/Global.cc
/gem5/src/mem/ruby/common/Global.hh
/gem5/src/mem/ruby/common/Histogram.cc
/gem5/src/mem/ruby/common/Histogram.hh
/gem5/src/mem/ruby/common/Message.cc
/gem5/src/mem/ruby/common/NetDest.cc
/gem5/src/mem/ruby/common/NetDest.hh
/gem5/src/mem/ruby/common/OptBigSet.cc
/gem5/src/mem/ruby/common/OptBigSet.hh
/gem5/src/mem/ruby/common/Set.cc
/gem5/src/mem/ruby/common/Set.hh
/gem5/src/mem/ruby/common/SubBlock.cc
/gem5/src/mem/ruby/common/SubBlock.hh
/gem5/src/mem/ruby/config/RubyConfig.cc
/gem5/src/mem/ruby/config/RubyConfig.hh
/gem5/src/mem/ruby/eventqueue/RubyEventQueue.cc
/gem5/src/mem/ruby/eventqueue/RubyEventQueue.hh
/gem5/src/mem/ruby/eventqueue/RubyEventQueueNode.cc
/gem5/src/mem/ruby/eventqueue/RubyEventQueueNode.hh
/gem5/src/mem/ruby/init.cc
Network.hh
garnet-fixed-pipeline/CreditLink_d.hh
garnet-fixed-pipeline/GarnetNetwork_d.cc
garnet-fixed-pipeline/GarnetNetwork_d.hh
garnet-fixed-pipeline/InputUnit_d.cc
garnet-fixed-pipeline/InputUnit_d.hh
garnet-fixed-pipeline/NetworkHeader.hh
garnet-fixed-pipeline/NetworkInterface_d.cc
garnet-fixed-pipeline/NetworkInterface_d.hh
garnet-fixed-pipeline/NetworkLink_d.cc
garnet-fixed-pipeline/NetworkLink_d.hh
garnet-fixed-pipeline/OutVcState_d.cc
garnet-fixed-pipeline/OutVcState_d.hh
garnet-fixed-pipeline/OutputUnit_d.cc
garnet-fixed-pipeline/OutputUnit_d.hh
garnet-fixed-pipeline/Router_d.cc
garnet-fixed-pipeline/Router_d.hh
garnet-fixed-pipeline/RoutingUnit_d.cc
garnet-fixed-pipeline/RoutingUnit_d.hh
garnet-fixed-pipeline/SWallocator_d.cc
garnet-fixed-pipeline/SWallocator_d.hh
garnet-fixed-pipeline/Switch_d.cc
garnet-fixed-pipeline/Switch_d.hh
garnet-fixed-pipeline/VCallocator_d.cc
garnet-fixed-pipeline/VCallocator_d.hh
garnet-fixed-pipeline/VirtualChannel_d.cc
garnet-fixed-pipeline/VirtualChannel_d.hh
garnet-fixed-pipeline/flitBuffer_d.cc
garnet-fixed-pipeline/flitBuffer_d.hh
garnet-fixed-pipeline/flit_d.cc
garnet-fixed-pipeline/flit_d.hh
garnet-flexible-pipeline/FlexibleConsumer.hh
garnet-flexible-pipeline/GarnetNetwork.cc
garnet-flexible-pipeline/GarnetNetwork.hh
garnet-flexible-pipeline/InVcState.cc
garnet-flexible-pipeline/InVcState.hh
garnet-flexible-pipeline/NetworkConfig.hh
garnet-flexible-pipeline/NetworkInterface.cc
garnet-flexible-pipeline/NetworkInterface.hh
garnet-flexible-pipeline/NetworkLink.cc
garnet-flexible-pipeline/NetworkLink.hh
garnet-flexible-pipeline/OutVcState.cc
garnet-flexible-pipeline/OutVcState.hh
garnet-flexible-pipeline/Router.cc
garnet-flexible-pipeline/Router.hh
garnet-flexible-pipeline/VCarbiter.cc
garnet-flexible-pipeline/VCarbiter.hh
garnet-flexible-pipeline/flit.cc
garnet-flexible-pipeline/flit.hh
garnet-flexible-pipeline/flitBuffer.cc
garnet-flexible-pipeline/flitBuffer.hh
orion/NetworkPower.cc
orion/SIM_power.hh
orion/power_arbiter.cc
orion/power_arbiter.hh
orion/power_array.cc
orion/power_bus.cc
orion/power_crossbar.cc
orion/power_ll.cc
orion/power_router_init.cc
orion/power_router_init.hh
orion/power_static.cc
orion/power_static.hh
orion/power_utils.cc
simple/PerfectSwitch.cc
simple/PerfectSwitch.hh
simple/SimpleNetwork.cc
simple/SimpleNetwork.hh
simple/Switch.cc
simple/Switch.hh
simple/Throttle.cc
simple/Throttle.hh
simple/Topology.cc
simple/Topology.hh
/gem5/src/mem/ruby/profiler/AccessTraceForAddress.cc
/gem5/src/mem/ruby/profiler/AccessTraceForAddress.hh
/gem5/src/mem/ruby/profiler/AddressProfiler.cc
/gem5/src/mem/ruby/profiler/AddressProfiler.hh
/gem5/src/mem/ruby/profiler/CacheProfiler.cc
/gem5/src/mem/ruby/profiler/CacheProfiler.hh
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/profiler/StoreTrace.cc
/gem5/src/mem/ruby/profiler/StoreTrace.hh
/gem5/src/mem/ruby/profiler/XactProfiler.cc
/gem5/src/mem/ruby/profiler/XactProfiler.hh
/gem5/src/mem/ruby/recorder/CacheRecorder.cc
/gem5/src/mem/ruby/recorder/CacheRecorder.hh
/gem5/src/mem/ruby/recorder/TraceRecord.cc
/gem5/src/mem/ruby/recorder/TraceRecord.hh
/gem5/src/mem/ruby/recorder/Tracer.cc
/gem5/src/mem/ruby/recorder/Tracer.hh
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
/gem5/src/mem/ruby/slicc_interface/AbstractChip.cc
/gem5/src/mem/ruby/slicc_interface/AbstractChip.hh
/gem5/src/mem/ruby/slicc_interface/Message.hh
/gem5/src/mem/ruby/slicc_interface/NetworkMessage.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.cc
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_includes.hh
/gem5/src/mem/ruby/system/AbstractBloomFilter.hh
/gem5/src/mem/ruby/system/AbstractMemOrCache.hh
/gem5/src/mem/ruby/system/AbstractReplacementPolicy.hh
/gem5/src/mem/ruby/system/BlockBloomFilter.cc
/gem5/src/mem/ruby/system/BlockBloomFilter.hh
/gem5/src/mem/ruby/system/BulkBloomFilter.cc
/gem5/src/mem/ruby/system/BulkBloomFilter.hh
/gem5/src/mem/ruby/system/CacheMemory.hh
/gem5/src/mem/ruby/system/DirectoryMemory.cc
/gem5/src/mem/ruby/system/DirectoryMemory.hh
/gem5/src/mem/ruby/system/GenericBloomFilter.cc
/gem5/src/mem/ruby/system/GenericBloomFilter.hh
/gem5/src/mem/ruby/system/H3BloomFilter.cc
/gem5/src/mem/ruby/system/H3BloomFilter.hh
/gem5/src/mem/ruby/system/LRUPolicy.hh
/gem5/src/mem/ruby/system/LSB_CountingBloomFilter.cc
/gem5/src/mem/ruby/system/LSB_CountingBloomFilter.hh
/gem5/src/mem/ruby/system/MachineID.hh
/gem5/src/mem/ruby/system/MemoryControl.cc
/gem5/src/mem/ruby/system/MemoryControl.hh
/gem5/src/mem/ruby/system/MemoryNode.cc
/gem5/src/mem/ruby/system/MemoryNode.hh
/gem5/src/mem/ruby/system/MultiBitSelBloomFilter.cc
/gem5/src/mem/ruby/system/MultiBitSelBloomFilter.hh
/gem5/src/mem/ruby/system/MultiGrainBloomFilter.cc
/gem5/src/mem/ruby/system/MultiGrainBloomFilter.hh
/gem5/src/mem/ruby/system/NodeID.hh
/gem5/src/mem/ruby/system/NodePersistentTable.cc
/gem5/src/mem/ruby/system/NodePersistentTable.hh
/gem5/src/mem/ruby/system/NonCountingBloomFilter.cc
/gem5/src/mem/ruby/system/NonCountingBloomFilter.hh
/gem5/src/mem/ruby/system/PerfectCacheMemory.hh
/gem5/src/mem/ruby/system/PersistentArbiter.cc
/gem5/src/mem/ruby/system/PersistentArbiter.hh
/gem5/src/mem/ruby/system/PersistentTable.cc
/gem5/src/mem/ruby/system/PersistentTable.hh
/gem5/src/mem/ruby/system/PseudoLRUPolicy.hh
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/Sequencer.hh
/gem5/src/mem/ruby/system/StoreBuffer.cc
/gem5/src/mem/ruby/system/StoreBuffer.hh
/gem5/src/mem/ruby/system/StoreCache.cc
/gem5/src/mem/ruby/system/StoreCache.hh
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/ruby/system/System.hh
/gem5/src/mem/ruby/system/TBETable.hh
/gem5/src/mem/ruby/system/TimerTable.cc
/gem5/src/mem/ruby/system/TimerTable.hh
/gem5/src/mem/ruby/tester/BarrierGenerator.cc
/gem5/src/mem/ruby/tester/BarrierGenerator.hh
/gem5/src/mem/ruby/tester/Check.cc
/gem5/src/mem/ruby/tester/Check.hh
/gem5/src/mem/ruby/tester/CheckTable.cc
/gem5/src/mem/ruby/tester/CheckTable.hh
/gem5/src/mem/ruby/tester/DetermGETXGenerator.cc
/gem5/src/mem/ruby/tester/DetermGETXGenerator.hh
/gem5/src/mem/ruby/tester/DetermInvGenerator.cc
/gem5/src/mem/ruby/tester/DetermInvGenerator.hh
/gem5/src/mem/ruby/tester/DetermSeriesGETSGenerator.cc
/gem5/src/mem/ruby/tester/DetermSeriesGETSGenerator.hh
/gem5/src/mem/ruby/tester/DeterministicDriver.cc
/gem5/src/mem/ruby/tester/DeterministicDriver.hh
/gem5/src/mem/ruby/tester/Instruction.cc
/gem5/src/mem/ruby/tester/Instruction.hh
/gem5/src/mem/ruby/tester/RaceyDriver.cc
/gem5/src/mem/ruby/tester/RaceyDriver.hh
/gem5/src/mem/ruby/tester/RequestGenerator.cc
/gem5/src/mem/ruby/tester/RequestGenerator.hh
/gem5/src/mem/ruby/tester/SpecifiedGenerator.cc
/gem5/src/mem/ruby/tester/SpecifiedGenerator.hh
/gem5/src/mem/ruby/tester/SyntheticDriver.cc
/gem5/src/mem/ruby/tester/SyntheticDriver.hh
/gem5/src/mem/ruby/tester/Tester.cc
/gem5/src/mem/ruby/tester/Tester.hh
/gem5/src/mem/ruby/tester/XactAbortRequestGenerator.cc
/gem5/src/mem/ruby/tester/XactAbortRequestGenerator.hh
/gem5/src/mem/ruby/tester/XactRequestGenerator.cc
/gem5/src/mem/ruby/tester/XactRequestGenerator.hh
/gem5/src/mem/ruby/tester/main.cc
/gem5/src/mem/ruby/tester/main.hh
/gem5/src/mem/ruby/tester/test_framework.cc
/gem5/src/mem/ruby/tester/test_framework.hh
/gem5/src/mem/slicc/ast/AST.cc
/gem5/src/mem/slicc/ast/AST.hh
/gem5/src/mem/slicc/ast/ASTs.hh
/gem5/src/mem/slicc/ast/ActionDeclAST.cc
/gem5/src/mem/slicc/ast/ActionDeclAST.hh
/gem5/src/mem/slicc/ast/AssignStatementAST.cc
/gem5/src/mem/slicc/ast/AssignStatementAST.hh
/gem5/src/mem/slicc/ast/CheckAllocateStatementAST.cc
/gem5/src/mem/slicc/ast/CheckAllocateStatementAST.hh
/gem5/src/mem/slicc/ast/CheckStopSlotsStatementAST.cc
/gem5/src/mem/slicc/ast/CheckStopSlotsStatementAST.hh
/gem5/src/mem/slicc/ast/ChipComponentAccessAST.cc
/gem5/src/mem/slicc/ast/ChipComponentAccessAST.hh
/gem5/src/mem/slicc/ast/CopyHeadStatementAST.cc
/gem5/src/mem/slicc/ast/CopyHeadStatementAST.hh
/gem5/src/mem/slicc/ast/DeclAST.cc
/gem5/src/mem/slicc/ast/DeclAST.hh
/gem5/src/mem/slicc/ast/DeclListAST.cc
/gem5/src/mem/slicc/ast/DeclListAST.hh
/gem5/src/mem/slicc/ast/EnqueueStatementAST.cc
/gem5/src/mem/slicc/ast/EnqueueStatementAST.hh
/gem5/src/mem/slicc/ast/EnumDeclAST.cc
/gem5/src/mem/slicc/ast/EnumDeclAST.hh
/gem5/src/mem/slicc/ast/EnumExprAST.cc
/gem5/src/mem/slicc/ast/EnumExprAST.hh
/gem5/src/mem/slicc/ast/ExprAST.cc
/gem5/src/mem/slicc/ast/ExprAST.hh
/gem5/src/mem/slicc/ast/ExprStatementAST.cc
/gem5/src/mem/slicc/ast/ExprStatementAST.hh
/gem5/src/mem/slicc/ast/FormalParamAST.cc
/gem5/src/mem/slicc/ast/FormalParamAST.hh
/gem5/src/mem/slicc/ast/FuncCallExprAST.cc
/gem5/src/mem/slicc/ast/FuncCallExprAST.hh
/gem5/src/mem/slicc/ast/FuncDeclAST.cc
/gem5/src/mem/slicc/ast/FuncDeclAST.hh
/gem5/src/mem/slicc/ast/IfStatementAST.cc
/gem5/src/mem/slicc/ast/IfStatementAST.hh
/gem5/src/mem/slicc/ast/InPortDeclAST.cc
/gem5/src/mem/slicc/ast/InPortDeclAST.hh
/gem5/src/mem/slicc/ast/InfixOperatorExprAST.cc
/gem5/src/mem/slicc/ast/InfixOperatorExprAST.hh
/gem5/src/mem/slicc/ast/LiteralExprAST.cc
/gem5/src/mem/slicc/ast/LiteralExprAST.hh
/gem5/src/mem/slicc/ast/Location.cc
/gem5/src/mem/slicc/ast/Location.hh
/gem5/src/mem/slicc/ast/MachineAST.cc
/gem5/src/mem/slicc/ast/MachineAST.hh
/gem5/src/mem/slicc/ast/MemberExprAST.cc
/gem5/src/mem/slicc/ast/MemberExprAST.hh
/gem5/src/mem/slicc/ast/MethodCallExprAST.cc
/gem5/src/mem/slicc/ast/MethodCallExprAST.hh
/gem5/src/mem/slicc/ast/ObjDeclAST.cc
/gem5/src/mem/slicc/ast/ObjDeclAST.hh
/gem5/src/mem/slicc/ast/OutPortDeclAST.cc
/gem5/src/mem/slicc/ast/OutPortDeclAST.hh
/gem5/src/mem/slicc/ast/PairAST.cc
/gem5/src/mem/slicc/ast/PairAST.hh
/gem5/src/mem/slicc/ast/PairListAST.cc
/gem5/src/mem/slicc/ast/PairListAST.hh
/gem5/src/mem/slicc/ast/PeekStatementAST.cc
/gem5/src/mem/slicc/ast/PeekStatementAST.hh
/gem5/src/mem/slicc/ast/ReturnStatementAST.cc
/gem5/src/mem/slicc/ast/ReturnStatementAST.hh
/gem5/src/mem/slicc/ast/StatementAST.cc
/gem5/src/mem/slicc/ast/StatementAST.hh
/gem5/src/mem/slicc/ast/StatementListAST.cc
/gem5/src/mem/slicc/ast/StatementListAST.hh
/gem5/src/mem/slicc/ast/TransitionDeclAST.cc
/gem5/src/mem/slicc/ast/TransitionDeclAST.hh
/gem5/src/mem/slicc/ast/TypeAST.cc
/gem5/src/mem/slicc/ast/TypeAST.hh
/gem5/src/mem/slicc/ast/TypeDeclAST.cc
/gem5/src/mem/slicc/ast/TypeDeclAST.hh
/gem5/src/mem/slicc/ast/TypeFieldAST.cc
/gem5/src/mem/slicc/ast/TypeFieldAST.hh
/gem5/src/mem/slicc/ast/TypeFieldEnumAST.cc
/gem5/src/mem/slicc/ast/TypeFieldEnumAST.hh
/gem5/src/mem/slicc/ast/TypeFieldMemberAST.cc
/gem5/src/mem/slicc/ast/TypeFieldMemberAST.hh
/gem5/src/mem/slicc/ast/TypeFieldMethodAST.cc
/gem5/src/mem/slicc/ast/TypeFieldMethodAST.hh
/gem5/src/mem/slicc/ast/VarExprAST.cc
/gem5/src/mem/slicc/ast/VarExprAST.hh
/gem5/src/mem/slicc/generator/fileio.cc
/gem5/src/mem/slicc/generator/fileio.hh
/gem5/src/mem/slicc/generator/html_gen.cc
/gem5/src/mem/slicc/generator/html_gen.hh
/gem5/src/mem/slicc/generator/mif_gen.cc
/gem5/src/mem/slicc/generator/mif_gen.hh
/gem5/src/mem/slicc/main.cc
/gem5/src/mem/slicc/main.hh
/gem5/src/mem/slicc/parser/lexer.ll
/gem5/src/mem/slicc/parser/parser.yy
/gem5/src/mem/slicc/slicc_global.hh
/gem5/src/mem/slicc/symbols/Action.hh
/gem5/src/mem/slicc/symbols/Event.hh
/gem5/src/mem/slicc/symbols/Func.cc
/gem5/src/mem/slicc/symbols/Func.hh
/gem5/src/mem/slicc/symbols/State.hh
/gem5/src/mem/slicc/symbols/StateMachine.cc
/gem5/src/mem/slicc/symbols/StateMachine.hh
/gem5/src/mem/slicc/symbols/Symbol.cc
/gem5/src/mem/slicc/symbols/Symbol.hh
/gem5/src/mem/slicc/symbols/SymbolTable.cc
/gem5/src/mem/slicc/symbols/SymbolTable.hh
/gem5/src/mem/slicc/symbols/Transition.cc
/gem5/src/mem/slicc/symbols/Transition.hh
/gem5/src/mem/slicc/symbols/Type.cc
/gem5/src/mem/slicc/symbols/Type.hh
/gem5/src/mem/slicc/symbols/Var.cc
/gem5/src/mem/slicc/symbols/Var.hh
6153:0011560d49b0 11-May-2009 Dan Gibson <gibson@cs.wisc.edu>

ruby: remove unnecessary code.

1) Removing files from the ruby build left some unresovled
symbols. Those have been fixed.

2) Most of the dependencies on Simics data types and the simics
interface files have been removed.

3) Almost all mention of opal is gone.

4) Huge chunks of LogTM are now gone.

5) Handling 1-4 left ~hundreds of unresolved references, which were
fixed, yielding a snowball effect (and the massive size of this
delta).


/gem5/src/mem/gems_common/ioutil/FakeSimicsDataTypes.hh
/gem5/src/mem/gems_common/ioutil/confio.cc
/gem5/src/mem/gems_common/ioutil/initvar.cc
/gem5/src/mem/gems_common/ioutil/initvar.hh
/gem5/src/mem/protocol/LogTM.sm
/gem5/src/mem/protocol/MESI_CMP_filter_directory-L1cache.sm
/gem5/src/mem/protocol/MESI_CMP_filter_directory-L2cache.sm
/gem5/src/mem/protocol/MESI_CMP_filter_directory-mem.sm
/gem5/src/mem/protocol/MESI_CMP_filter_directory-msg.sm
/gem5/src/mem/protocol/MESI_CMP_filter_directory.slicc
/gem5/src/mem/protocol/MESI_CMP_filter_directory_m-mem.sm
/gem5/src/mem/protocol/MESI_CMP_filter_directory_m.slicc
/gem5/src/mem/ruby/FakeSimicsDataTypes.hh
/gem5/src/mem/ruby/config/RubyConfig.cc
/gem5/src/mem/ruby/config/config.hh
/gem5/src/mem/ruby/config/rubyconfig.defaults
/gem5/src/mem/ruby/config/tester.defaults
/gem5/src/mem/ruby/init.cc
/gem5/src/mem/ruby/init.hh
/gem5/src/mem/ruby/interfaces/OpalInterface.cc
/gem5/src/mem/ruby/interfaces/OpalInterface.hh
garnet-flexible-pipeline/NetworkConfig.hh
simple/Topology.cc
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/recorder/CacheRecorder.cc
/gem5/src/mem/ruby/simics/commands.cc
/gem5/src/mem/ruby/simics/commands.hh
/gem5/src/mem/ruby/simics/interface.cc
/gem5/src/mem/ruby/simics/interface.hh
/gem5/src/mem/ruby/simics/simics_api_dummy.c
/gem5/src/mem/ruby/system/DirectoryMemory.cc
/gem5/src/mem/ruby/system/PerfectCacheMemory.hh
/gem5/src/mem/ruby/system/PersistentArbiter.hh
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/ruby/system/System.hh
/gem5/src/mem/ruby/tester/DeterministicDriver.cc
/gem5/src/mem/ruby/tester/RaceyDriver.cc
/gem5/src/mem/ruby/tester/SyntheticDriver.cc
/gem5/src/mem/ruby/tester/Tester.cc
/gem5/src/mem/ruby/tester/main.cc
/gem5/src/mem/ruby/tester/test_framework.cc
6149:ff34514cbf37 11-May-2009 Derek Hower <drh5@cs.wisc.edu>

ruby: Renamed Ruby's EventQueue to RubyEventQueue

6145:15cca6ab723a 11-May-2009 Nathan Binkert <nate@binkert.org>

ruby: Import ruby and slicc from GEMS

We eventually plan to replace the m5 cache hierarchy with the GEMS
hierarchy, but for now we will make both live alongside eachother.


/gem5/src/mem/gems_common/Allocator.hh
/gem5/src/mem/gems_common/Map.hh
/gem5/src/mem/gems_common/PrioHeap.hh
/gem5/src/mem/gems_common/RefCnt.hh
/gem5/src/mem/gems_common/RefCnt_tester.cc
/gem5/src/mem/gems_common/RefCountable.hh
/gem5/src/mem/gems_common/Vector.hh
/gem5/src/mem/gems_common/calc_host.sh
/gem5/src/mem/gems_common/ioutil/attrlex.ll
/gem5/src/mem/gems_common/ioutil/attrparse.yy
/gem5/src/mem/gems_common/ioutil/confio.cc
/gem5/src/mem/gems_common/ioutil/confio.hh
/gem5/src/mem/gems_common/ioutil/embedtext.py
/gem5/src/mem/gems_common/ioutil/initvar.cc
/gem5/src/mem/gems_common/ioutil/initvar.hh
/gem5/src/mem/gems_common/ioutil/vardecl.hh
/gem5/src/mem/gems_common/std-includes.hh
/gem5/src/mem/gems_common/util.cc
/gem5/src/mem/gems_common/util.hh
/gem5/src/mem/protocol/LogTM.sm
/gem5/src/mem/protocol/MESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-mem.sm
/gem5/src/mem/protocol/MESI_CMP_directory-msg.sm
/gem5/src/mem/protocol/MESI_CMP_directory.slicc
/gem5/src/mem/protocol/MESI_CMP_filter_directory-L1cache.sm
/gem5/src/mem/protocol/MESI_CMP_filter_directory-L2cache.sm
/gem5/src/mem/protocol/MESI_CMP_filter_directory-mem.sm
/gem5/src/mem/protocol/MESI_CMP_filter_directory-msg.sm
/gem5/src/mem/protocol/MESI_CMP_filter_directory.slicc
/gem5/src/mem/protocol/MESI_CMP_filter_directory_m-mem.sm
/gem5/src/mem/protocol/MESI_CMP_filter_directory_m.slicc
/gem5/src/mem/protocol/MESI_SCMP_bankdirectory-L1cache.sm
/gem5/src/mem/protocol/MESI_SCMP_bankdirectory-L2cache.sm
/gem5/src/mem/protocol/MESI_SCMP_bankdirectory-mem.sm
/gem5/src/mem/protocol/MESI_SCMP_bankdirectory-msg.sm
/gem5/src/mem/protocol/MESI_SCMP_bankdirectory.slicc
/gem5/src/mem/protocol/MESI_SCMP_bankdirectory_m-mem.sm
/gem5/src/mem/protocol/MESI_SCMP_bankdirectory_m.slicc
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MI_example-msg.sm
/gem5/src/mem/protocol/MI_example.slicc
/gem5/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-msg.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-perfectDir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory.slicc
/gem5/src/mem/protocol/MOESI_CMP_directory_m-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory_m.slicc
/gem5/src/mem/protocol/MOESI_CMP_token-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_token-msg.sm
/gem5/src/mem/protocol/MOESI_CMP_token.slicc
/gem5/src/mem/protocol/MOESI_SMP_directory-cache.sm
/gem5/src/mem/protocol/MOESI_SMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_SMP_directory-msg.sm
/gem5/src/mem/protocol/MOESI_SMP_directory.slicc
/gem5/src/mem/protocol/MOESI_SMP_token-cache.sm
/gem5/src/mem/protocol/MOESI_SMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_SMP_token-msg.sm
/gem5/src/mem/protocol/MOESI_SMP_token.slicc
/gem5/src/mem/protocol/MOSI_SMP_bcast-cache.sm
/gem5/src/mem/protocol/MOSI_SMP_bcast-dir.sm
/gem5/src/mem/protocol/MOSI_SMP_bcast-msg.sm
/gem5/src/mem/protocol/MOSI_SMP_bcast.slicc
/gem5/src/mem/protocol/MOSI_SMP_bcast_1level-cache.sm
/gem5/src/mem/protocol/MOSI_SMP_bcast_1level.slicc
/gem5/src/mem/protocol/MOSI_SMP_bcast_m-dir.sm
/gem5/src/mem/protocol/MOSI_SMP_bcast_m.slicc
/gem5/src/mem/protocol/MOSI_SMP_directory_1level-cache.sm
/gem5/src/mem/protocol/MOSI_SMP_directory_1level-dir.sm
/gem5/src/mem/protocol/MOSI_SMP_directory_1level-msg.sm
/gem5/src/mem/protocol/MOSI_SMP_directory_1level.slicc
/gem5/src/mem/protocol/MSI_MOSI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MSI_MOSI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MSI_MOSI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MSI_MOSI_CMP_directory-msg.sm
/gem5/src/mem/protocol/MSI_MOSI_CMP_directory.slicc
/gem5/src/mem/protocol/RubySlicc_ComponentMapping.sm
/gem5/src/mem/protocol/RubySlicc_Defines.sm
/gem5/src/mem/protocol/RubySlicc_Exports.sm
/gem5/src/mem/protocol/RubySlicc_MemControl.sm
/gem5/src/mem/protocol/RubySlicc_Profiler.sm
/gem5/src/mem/protocol/RubySlicc_Types.sm
/gem5/src/mem/protocol/RubySlicc_Util.sm
/gem5/src/mem/protocol/RubySlicc_interfaces.slicc
/gem5/src/mem/protocol/doc/MSI_MOSI_CMP_directory_2level-protocol-description.txt
/gem5/src/mem/protocol/doc/MSI_dir_L1_MOSI_dir_L2_SNUCA_CMP-protocol-description.txt
/gem5/src/mem/protocol/standard_1level_SMP-protocol.sm
/gem5/src/mem/protocol/standard_CMP-protocol.sm
/gem5/src/mem/protocol/standard_SMP-protocol.sm
/gem5/src/mem/ruby/Decomissioning_note
/gem5/src/mem/ruby/FakeSimicsDataTypes.hh
/gem5/src/mem/ruby/README.debugging
/gem5/src/mem/ruby/buffers/MessageBuffer.cc
/gem5/src/mem/ruby/buffers/MessageBuffer.hh
/gem5/src/mem/ruby/buffers/MessageBufferNode.cc
/gem5/src/mem/ruby/buffers/MessageBufferNode.hh
/gem5/src/mem/ruby/common/Address.cc
/gem5/src/mem/ruby/common/Address.hh
/gem5/src/mem/ruby/common/BigSet.cc
/gem5/src/mem/ruby/common/BigSet.hh
/gem5/src/mem/ruby/common/Consumer.hh
/gem5/src/mem/ruby/common/DataBlock.cc
/gem5/src/mem/ruby/common/DataBlock.hh
/gem5/src/mem/ruby/common/Debug.cc
/gem5/src/mem/ruby/common/Debug.def
/gem5/src/mem/ruby/common/Debug.hh
/gem5/src/mem/ruby/common/Driver.cc
/gem5/src/mem/ruby/common/Driver.hh
/gem5/src/mem/ruby/common/Global.cc
/gem5/src/mem/ruby/common/Global.hh
/gem5/src/mem/ruby/common/Histogram.cc
/gem5/src/mem/ruby/common/Histogram.hh
/gem5/src/mem/ruby/common/Message.cc
/gem5/src/mem/ruby/common/NetDest.cc
/gem5/src/mem/ruby/common/NetDest.hh
/gem5/src/mem/ruby/common/OptBigSet.cc
/gem5/src/mem/ruby/common/OptBigSet.hh
/gem5/src/mem/ruby/common/Set.cc
/gem5/src/mem/ruby/common/Set.hh
/gem5/src/mem/ruby/common/SubBlock.cc
/gem5/src/mem/ruby/common/SubBlock.hh
/gem5/src/mem/ruby/config/RubyConfig.cc
/gem5/src/mem/ruby/config/RubyConfig.hh
/gem5/src/mem/ruby/config/config.include
/gem5/src/mem/ruby/config/rubyconfig.defaults
/gem5/src/mem/ruby/config/tester.defaults
/gem5/src/mem/ruby/eventqueue/EventQueue.cc
/gem5/src/mem/ruby/eventqueue/EventQueue.hh
/gem5/src/mem/ruby/eventqueue/EventQueueNode.cc
/gem5/src/mem/ruby/eventqueue/EventQueueNode.hh
/gem5/src/mem/ruby/eventqueue/EventQueue_tester.cc
/gem5/src/mem/ruby/init.cc
/gem5/src/mem/ruby/init.hh
/gem5/src/mem/ruby/interfaces/OpalInterface.cc
/gem5/src/mem/ruby/interfaces/OpalInterface.hh
/gem5/src/mem/ruby/interfaces/mf_api.hh
Network.hh
garnet-fixed-pipeline/CreditLink_d.hh
garnet-fixed-pipeline/GarnetNetwork_d.cc
garnet-fixed-pipeline/GarnetNetwork_d.hh
garnet-fixed-pipeline/InputUnit_d.cc
garnet-fixed-pipeline/InputUnit_d.hh
garnet-fixed-pipeline/NetworkHeader.hh
garnet-fixed-pipeline/NetworkInterface_d.cc
garnet-fixed-pipeline/NetworkInterface_d.hh
garnet-fixed-pipeline/NetworkLink_d.cc
garnet-fixed-pipeline/NetworkLink_d.hh
garnet-fixed-pipeline/OutVcState_d.cc
garnet-fixed-pipeline/OutVcState_d.hh
garnet-fixed-pipeline/OutputUnit_d.cc
garnet-fixed-pipeline/OutputUnit_d.hh
garnet-fixed-pipeline/Router_d.cc
garnet-fixed-pipeline/Router_d.hh
garnet-fixed-pipeline/RoutingUnit_d.cc
garnet-fixed-pipeline/RoutingUnit_d.hh
garnet-fixed-pipeline/SWallocator_d.cc
garnet-fixed-pipeline/SWallocator_d.hh
garnet-fixed-pipeline/Switch_d.cc
garnet-fixed-pipeline/Switch_d.hh
garnet-fixed-pipeline/VCallocator_d.cc
garnet-fixed-pipeline/VCallocator_d.hh
garnet-fixed-pipeline/VirtualChannel_d.cc
garnet-fixed-pipeline/VirtualChannel_d.hh
garnet-fixed-pipeline/flitBuffer_d.cc
garnet-fixed-pipeline/flitBuffer_d.hh
garnet-fixed-pipeline/flit_d.cc
garnet-fixed-pipeline/flit_d.hh
garnet-flexible-pipeline/FlexibleConsumer.hh
garnet-flexible-pipeline/GarnetNetwork.cc
garnet-flexible-pipeline/GarnetNetwork.hh
garnet-flexible-pipeline/InVcState.cc
garnet-flexible-pipeline/InVcState.hh
garnet-flexible-pipeline/NetworkConfig.hh
garnet-flexible-pipeline/NetworkInterface.cc
garnet-flexible-pipeline/NetworkInterface.hh
garnet-flexible-pipeline/NetworkLink.cc
garnet-flexible-pipeline/NetworkLink.hh
garnet-flexible-pipeline/OutVcState.cc
garnet-flexible-pipeline/OutVcState.hh
garnet-flexible-pipeline/Router.cc
garnet-flexible-pipeline/Router.hh
garnet-flexible-pipeline/VCarbiter.cc
garnet-flexible-pipeline/VCarbiter.hh
garnet-flexible-pipeline/flit.cc
garnet-flexible-pipeline/flit.hh
garnet-flexible-pipeline/flitBuffer.cc
garnet-flexible-pipeline/flitBuffer.hh
garnet-flexible-pipeline/netconfig.defaults
orion/NetworkPower.cc
orion/NetworkPower.hh
orion/SIM_port.hh
orion/SIM_power.hh
orion/SIM_power_test.hh
orion/parm_technology.hh
orion/power_arbiter.cc
orion/power_arbiter.hh
orion/power_array.cc
orion/power_array.hh
orion/power_bus.cc
orion/power_bus.hh
orion/power_crossbar.cc
orion/power_crossbar.hh
orion/power_ll.cc
orion/power_ll.hh
orion/power_router_init.cc
orion/power_router_init.hh
orion/power_static.cc
orion/power_static.hh
orion/power_utils.cc
orion/power_utils.hh
simple/Network_Files/GarnetFileMaker.py
simple/Network_Files/NUCA_Procs-16_ProcsPerChip-16_L2Banks-16_Memories-16.txt
simple/Network_Files/NUCA_Procs-16_ProcsPerChip-16_L2Banks-16_Memories-4.txt
simple/Network_Files/NUCA_Procs-16_ProcsPerChip-16_L2Banks-16_Memories-8.txt
simple/Network_Files/NUCA_Procs-16_ProcsPerChip-1_L2Banks-16_Memories-16.txt
simple/Network_Files/NUCA_Procs-16_ProcsPerChip-4_L2Banks-16_Memories-16.txt
simple/Network_Files/NUCA_Procs-16_ProcsPerChip-4_L2Banks-16_Memories-4.txt
simple/Network_Files/NUCA_Procs-16_ProcsPerChip-4_L2Banks-32_Memories-4.txt
simple/Network_Files/NUCA_Procs-16_ProcsPerChip-4_L2Banks-4_Memories-16.txt
simple/Network_Files/NUCA_Procs-16_ProcsPerChip-4_L2Banks-4_Memories-4.txt
simple/Network_Files/NUCA_Procs-1_ProcsPerChip-1_L2Banks-1_Memories-1.txt
simple/Network_Files/NUCA_Procs-1_ProcsPerChip-1_L2Banks-256_Memories-1.txt
simple/Network_Files/NUCA_Procs-1_ProcsPerChip-1_L2Banks-32_Memories-1.txt
simple/Network_Files/NUCA_Procs-1_ProcsPerChip-1_L2Banks-64_Memories-1.txt
simple/Network_Files/NUCA_Procs-2_ProcsPerChip-1_L2Banks-2_Memories-2.txt
simple/Network_Files/NUCA_Procs-2_ProcsPerChip-2_L2Banks-2_Memories-2.txt
simple/Network_Files/NUCA_Procs-32_ProcsPerChip-32_L2Banks-32_Memories-16.txt
simple/Network_Files/NUCA_Procs-32_ProcsPerChip-32_L2Banks-32_Memories-4.txt
simple/Network_Files/NUCA_Procs-4_ProcsPerChip-1_L2Banks-4_Memories-4.txt
simple/Network_Files/NUCA_Procs-4_ProcsPerChip-4_L2Banks-4_Memories-4.txt
simple/Network_Files/NUCA_Procs-7_ProcsPerChip-7_L2Banks-7_Memories-7.txt
simple/Network_Files/NUCA_Procs-8_ProcsPerChip-1_L2Banks-8_Memories-8.txt
simple/Network_Files/NUCA_Procs-8_ProcsPerChip-4_L2Banks-8_Memories-8.txt
simple/Network_Files/NUCA_Procs-8_ProcsPerChip-8_L2Banks-256_Memories-8.txt
simple/Network_Files/NUCA_Procs-8_ProcsPerChip-8_L2Banks-8_Memories-8.txt
simple/Network_Files/NetworkFileMaker.py
simple/Network_Files/TLC_Procs-8_ProcsPerChip-8_L2Banks-256_Memories-8.txt
simple/Network_Files/TOKEN_CMP_Procs-16_ProcsPerChip-16_L2Banks-16_Memories-16.txt
simple/Network_Files/TOKEN_CMP_Procs-16_ProcsPerChip-4_L2Banks-16_Memories-16.txt
simple/PerfectSwitch.cc
simple/PerfectSwitch.hh
simple/SimpleNetwork.cc
simple/SimpleNetwork.hh
simple/Switch.cc
simple/Switch.hh
simple/Throttle.cc
simple/Throttle.hh
simple/Topology.cc
simple/Topology.hh
/gem5/src/mem/ruby/profiler/AccessTraceForAddress.cc
/gem5/src/mem/ruby/profiler/AccessTraceForAddress.hh
/gem5/src/mem/ruby/profiler/AddressProfiler.cc
/gem5/src/mem/ruby/profiler/AddressProfiler.hh
/gem5/src/mem/ruby/profiler/CacheProfiler.cc
/gem5/src/mem/ruby/profiler/CacheProfiler.hh
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/profiler/StoreTrace.cc
/gem5/src/mem/ruby/profiler/StoreTrace.hh
/gem5/src/mem/ruby/profiler/XactProfiler.cc
/gem5/src/mem/ruby/profiler/XactProfiler.hh
/gem5/src/mem/ruby/recorder/CacheRecorder.cc
/gem5/src/mem/ruby/recorder/CacheRecorder.hh
/gem5/src/mem/ruby/recorder/TraceRecord.cc
/gem5/src/mem/ruby/recorder/TraceRecord.hh
/gem5/src/mem/ruby/recorder/Tracer.cc
/gem5/src/mem/ruby/recorder/Tracer.hh
/gem5/src/mem/ruby/simics/commands.cc
/gem5/src/mem/ruby/simics/commands.hh
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