History log of /gem5/src/mem/ruby/
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14300:22183ae13998 19-Sep-2019 Jing Qu <jqu32@wisc.edu>

mem-ruby: prevent cacheProbe being called multiple times

The cacheProbe() function will return the victim entry, and it gets
called for multiple times in trigger function in a single miss. This
will cause a problem when we try to add a new replacement policy to
the Ruby system. Certain policy, like RRIP, will modify the block
information every time the getVictim() function gets called. To
prevent future problems, we need to store the victim entry, so that
we only call it once in one miss.

Change-Id: Ic5ca05f789d9bbfb963b8e993ef707020f243702
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21099
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

14262:991410960fdb 11-May-2019 Daniel R. Carvalho <odanrc@yahoo.com.br>

mem-ruby: Move Bloom Filters to base

All Bloom Filters are completely independent of Ruby, and
therefore can be used everywhere.

As a side effect, Ruby was not using the filters, so
their dependency was removed.

Change-Id: Ic5f430610c33c0791fb81c79101ebe737189497e
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18875
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

14217:68c3d00f780a 26-Aug-2019 Srikant Bharadwaj <srikant.bharadwaj@amd.com>

ruby: Fix the way stall map size is checked for availability

To ensure that enqueuer observes the practical availability. We
check the message buffer queue size at the start of the cycle.
We also add the size of the stall queue to consider the total
queue size. However, messages can be moved from regular queue
to stall map. This leads to messages being considered twice leading
to false flow control. This patch fixes it by storing the stall map
size at the beginning of the cycle and considering it for checking
availability.

Change-Id: I6ea94f34fe5279b91f74e106d43263e55ec4bf06
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20389
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

14204:c1bc1320aa86 11-May-2019 Daniel R. Carvalho <odanrc@yahoo.com.br>

mem-ruby: Define BloomFilter namespace

Define a BloomFilter namespace and put all BloomFilter related
code in it.

As a side effect the BloomFilter classes have been renamed to
remove the "BloomFilter" suffix.

Change-Id: I3ee8cc225bf3b820e561c3e25a6bf38e0012e3a8
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18874
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

14203:186d80c1a87f 11-May-2019 Daniel R. Carvalho <odanrc@yahoo.com.br>

mem-ruby: Make H3 inherit from MultiBitSelBloomFilter

Make MultiBitSelBloomFilter a generic BloomFilter that maps
multiple entries to an address, and therefore uses multiple
hash functions. This allows the common functionality of both
filters to be merged into one, since they only differ in the
hash functions being used.

Change-Id: I0984067b710a208715f5f2727b8c4312feb6529b
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18873
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

14202:64f03da8df1e 10-May-2019 Daniel R. Carvalho <odanrc@yahoo.com.br>

mem-ruby: Finish implementing BloomFilter merge

Not all Bloom Filters had their union functionality implemented.
This change adds them.

Change-Id: I86af18d3c5eabd0da8280b57a88789b3af803c04
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18872
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

14201:ecd0511edbc3 09-May-2019 Daniel R. Carvalho <odanrc@yahoo.com.br>

mem-ruby: Remove NonCountingBloomFilter

Make BlockBloomFilter accept having a single bitfield, in which
case it behaves exactly as the NonCountingBloomFilter, and thus
the latter can be removed.

Change-Id: I56d96a89290c933293ce434bbe0e8bcd4bbcaa42
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18871
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

14200:e30d3fc98da7 10-May-2019 Daniel R. Carvalho <odanrc@yahoo.com.br>

mem-ruby: Make MultiGrainBloomFilter generic

Allow combining any number of Bloom Filters in the MultiGrain.

Change-Id: I73ae33063e1feed731af6f625d2f64245f21df18
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18869
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

14199:89b4c53db683 09-May-2019 Daniel R. Carvalho <odanrc@yahoo.com.br>

mem-ruby: Parameterize xor bits in BlockBloomFilter

Parameterize bitfield ranges in BlockBloomFilter such that the
hash is applied between masked bitfields of an address.

Change-Id: I008bd873458e9815e98530e308491adb65bb34cb
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18870
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

14184:11ac1337c5e2 16-Aug-2019 Gabe Black <gabeblack@google.com>

mem: Move ruby protocols into a directory called ruby_protocol.

Now that the gem5 protocols are split out, it would be nice to put them
in their own protocol directory. It's also confusing to have files
called *_protocol which are not in the protocol directory.

Change-Id: I7475ee111630050a2421816dfd290921baab9f71
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20230
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>


/gem5/src/cpu/testers/directedtest/InvalidateGenerator.hh
/gem5/src/cpu/testers/directedtest/SeriesRequestGenerator.hh
/gem5/src/cpu/testers/rubytest/Check.hh
/gem5/src/learning_gem5/part3/MSI-cache.sm
/gem5/src/learning_gem5/part3/SConsopts
/gem5/src/mem/protocol/GPU_RfO-SQC.sm
/gem5/src/mem/protocol/GPU_RfO-TCC.sm
/gem5/src/mem/protocol/GPU_RfO-TCCdir.sm
/gem5/src/mem/protocol/GPU_RfO-TCP.sm
/gem5/src/mem/protocol/GPU_RfO.slicc
/gem5/src/mem/protocol/GPU_VIPER-SQC.sm
/gem5/src/mem/protocol/GPU_VIPER-TCC.sm
/gem5/src/mem/protocol/GPU_VIPER-TCP.sm
/gem5/src/mem/protocol/GPU_VIPER.slicc
/gem5/src/mem/protocol/GPU_VIPER_Baseline.slicc
/gem5/src/mem/protocol/GPU_VIPER_Region-TCC.sm
/gem5/src/mem/protocol/GPU_VIPER_Region.slicc
/gem5/src/mem/protocol/Garnet_standalone-cache.sm
/gem5/src/mem/protocol/Garnet_standalone-dir.sm
/gem5/src/mem/protocol/Garnet_standalone-msg.sm
/gem5/src/mem/protocol/Garnet_standalone.slicc
/gem5/src/mem/protocol/MESI_Three_Level-L0cache.sm
/gem5/src/mem/protocol/MESI_Three_Level-L1cache.sm
/gem5/src/mem/protocol/MESI_Three_Level-msg.sm
/gem5/src/mem/protocol/MESI_Three_Level.slicc
/gem5/src/mem/protocol/MESI_Two_Level-L1cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-L2cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-dir.sm
/gem5/src/mem/protocol/MESI_Two_Level-dma.sm
/gem5/src/mem/protocol/MESI_Two_Level-msg.sm
/gem5/src/mem/protocol/MESI_Two_Level.slicc
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MI_example-dma.sm
/gem5/src/mem/protocol/MI_example-msg.sm
/gem5/src/mem/protocol/MI_example.slicc
/gem5/src/mem/protocol/MOESI_AMD_Base-CorePair.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-L3cache.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-Region-CorePair.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-Region-dir.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-Region-msg.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-RegionBuffer.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-RegionDir.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-dir.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-msg.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-probeFilter.sm
/gem5/src/mem/protocol/MOESI_AMD_Base.slicc
/gem5/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-msg.sm
/gem5/src/mem/protocol/MOESI_CMP_directory.slicc
/gem5/src/mem/protocol/MOESI_CMP_token-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_token-msg.sm
/gem5/src/mem/protocol/MOESI_CMP_token.slicc
/gem5/src/mem/protocol/MOESI_hammer-cache.sm
/gem5/src/mem/protocol/MOESI_hammer-dir.sm
/gem5/src/mem/protocol/MOESI_hammer-dma.sm
/gem5/src/mem/protocol/MOESI_hammer-msg.sm
/gem5/src/mem/protocol/MOESI_hammer.slicc
/gem5/src/mem/protocol/RubySlicc_ComponentMapping.sm
/gem5/src/mem/protocol/RubySlicc_Defines.sm
/gem5/src/mem/protocol/RubySlicc_Exports.sm
/gem5/src/mem/protocol/RubySlicc_MemControl.sm
/gem5/src/mem/protocol/RubySlicc_Types.sm
/gem5/src/mem/protocol/RubySlicc_Util.sm
/gem5/src/mem/protocol/RubySlicc_interfaces.slicc
/gem5/src/mem/protocol/SConscript
/gem5/src/mem/protocol/SConsopts
SConscript
common/MachineID.hh
network/Network.hh
network/Topology.hh
network/simple/Switch.hh
profiler/AccessTraceForAddress.hh
profiler/AddressProfiler.cc
profiler/AddressProfiler.hh
profiler/Profiler.cc
profiler/Profiler.hh
protocol/GPU_RfO-SQC.sm
protocol/GPU_RfO-TCC.sm
protocol/GPU_RfO-TCCdir.sm
protocol/GPU_RfO-TCP.sm
protocol/GPU_RfO.slicc
protocol/GPU_VIPER-SQC.sm
protocol/GPU_VIPER-TCC.sm
protocol/GPU_VIPER-TCP.sm
protocol/GPU_VIPER.slicc
protocol/GPU_VIPER_Baseline.slicc
protocol/GPU_VIPER_Region-TCC.sm
protocol/GPU_VIPER_Region.slicc
protocol/Garnet_standalone-cache.sm
protocol/Garnet_standalone-dir.sm
protocol/Garnet_standalone-msg.sm
protocol/Garnet_standalone.slicc
protocol/MESI_Three_Level-L0cache.sm
protocol/MESI_Three_Level-L1cache.sm
protocol/MESI_Three_Level-msg.sm
protocol/MESI_Three_Level.slicc
protocol/MESI_Two_Level-L1cache.sm
protocol/MESI_Two_Level-L2cache.sm
protocol/MESI_Two_Level-dir.sm
protocol/MESI_Two_Level-dma.sm
protocol/MESI_Two_Level-msg.sm
protocol/MESI_Two_Level.slicc
protocol/MI_example-cache.sm
protocol/MI_example-dir.sm
protocol/MI_example-dma.sm
protocol/MI_example-msg.sm
protocol/MI_example.slicc
protocol/MOESI_AMD_Base-CorePair.sm
protocol/MOESI_AMD_Base-L3cache.sm
protocol/MOESI_AMD_Base-Region-CorePair.sm
protocol/MOESI_AMD_Base-Region-dir.sm
protocol/MOESI_AMD_Base-Region-msg.sm
protocol/MOESI_AMD_Base-RegionBuffer.sm
protocol/MOESI_AMD_Base-RegionDir.sm
protocol/MOESI_AMD_Base-dir.sm
protocol/MOESI_AMD_Base-msg.sm
protocol/MOESI_AMD_Base-probeFilter.sm
protocol/MOESI_AMD_Base.slicc
protocol/MOESI_CMP_directory-L1cache.sm
protocol/MOESI_CMP_directory-L2cache.sm
protocol/MOESI_CMP_directory-dir.sm
protocol/MOESI_CMP_directory-dma.sm
protocol/MOESI_CMP_directory-msg.sm
protocol/MOESI_CMP_directory.slicc
protocol/MOESI_CMP_token-L1cache.sm
protocol/MOESI_CMP_token-L2cache.sm
protocol/MOESI_CMP_token-dir.sm
protocol/MOESI_CMP_token-dma.sm
protocol/MOESI_CMP_token-msg.sm
protocol/MOESI_CMP_token.slicc
protocol/MOESI_hammer-cache.sm
protocol/MOESI_hammer-dir.sm
protocol/MOESI_hammer-dma.sm
protocol/MOESI_hammer-msg.sm
protocol/MOESI_hammer.slicc
protocol/RubySlicc_ComponentMapping.sm
protocol/RubySlicc_Defines.sm
protocol/RubySlicc_Exports.sm
protocol/RubySlicc_MemControl.sm
protocol/RubySlicc_Types.sm
protocol/RubySlicc_Util.sm
protocol/RubySlicc_interfaces.slicc
protocol/SConscript
protocol/SConsopts
slicc_interface/AbstractCacheEntry.hh
slicc_interface/AbstractController.cc
slicc_interface/AbstractController.hh
slicc_interface/AbstractEntry.hh
slicc_interface/Message.hh
slicc_interface/RubyRequest.hh
slicc_interface/RubySlicc_ComponentMapping.hh
structures/CacheMemory.cc
structures/CacheMemory.hh
structures/DirectoryMemory.hh
structures/PerfectCacheMemory.hh
structures/PersistentTable.hh
system/CacheRecorder.hh
system/DMASequencer.cc
system/DMASequencer.hh
system/GPUCoalescer.hh
system/RubyPort.cc
system/RubyPort.hh
system/Sequencer.cc
system/Sequencer.hh
system/VIPERCoalescer.hh
/gem5/src/mem/slicc/main.py
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/mem/slicc/symbols/SymbolTable.py
/gem5/src/mem/slicc/symbols/Type.py
14166:bcebed5b33ad 06-Jun-2019 Pablo Prieto <pablo.prieto@unican.es>

mem-ruby, arch-hsail: Removed hit latency from VIPERCoalescer

Removed the dcache hit latency from VIPERCoalescer so HSAIL_X86
compiles after commit 496d5ed3e1f7dad42b0c2ebe0050d84621be8f99

Change-Id: I050a58d90f0f6356824c3c3bcb3f0b3c76d145e0
Signed-off-by: Pablo Prieto <pablo.prieto@unican.es>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19148
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

14125:89db448f81e6 30-Jul-2019 Pouya Fotouhi <Pouya.Fotouhi@amd.com>

mem-ruby: Remove assertion with incorrect assumption

Current code assumes that only one cacheline would either be in
RW. This is not true for GPU protocols, and may not be true
for some CPU-only protocols with state violations.

Change-Id: I70db4fbb4e80663551e8635307bb937a4db8dc63
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19708
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

14079:0d35b63510ed 08-May-2019 Daniel R. Carvalho <odanrc@yahoo.com.br>

mem-ruby: Fix MultiGrainBloomFilter accessing

When accessing the page filter the page hash should be used
instead of the hash of the base filter.

Change-Id: I17b7c64f2a0d654c7d9a77a7bfb435385d81032c
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18739
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

14078:90e52798b6ce 07-May-2019 Daniel R. Carvalho <odanrc@yahoo.com.br>

mem-ruby: Remove Bloom Filters' ruby dependency

Substitute the common ruby header by base's bitfield to
eliminate all ruby dependency in Bloom Filters.

As a side note, BulkBloomFilter now assumes addresses are
64 bit long.

Change-Id: Ibdb1f926ddcc06c848851c1e6a34863541808360
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18738
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

14077:47938885514e 07-May-2019 Daniel R. Carvalho <odanrc@yahoo.com.br>

mem-ruby: Parameterize block size in Bloom Filters

Substitute all occurrences of Ruby's block size by a
Python configurable offset.

Change-Id: If4913e842921447deda943b0482fb0c78a44c275
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18737
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

14076:271aa7778eb0 06-May-2019 Daniel R. Carvalho <odanrc@yahoo.com.br>

mem-ruby: Make Bloom Filters SimObjects

Make all bloom filters SimObjects.

Change-Id: I586293cdfb559361cb868b3198368e8b9b193356
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18736
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

14075:0bfb08f318dd 05-May-2019 Daniel R. Carvalho <odanrc@yahoo.com.br>

mem-ruby: Generalize use of bloom filters' isSet

In general the corresponding entries of an address are considered
to be set when the sum of all of them reach their maximum value
(i.e., they are all set), so generalize that into the base class.

Change-Id: If50b8c56065ad339b4ff2322ddc3c077a3bfc518
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18735
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

14074:45ed745858cc 05-May-2019 Daniel R. Carvalho <odanrc@yahoo.com.br>

mem-ruby: Cleanup filters

Renamed member variables to comply with general naming
conventional outside of the ruby folder so that the
filters can be moved out.

Moved code to base to reduce code duplication.

Renamed the private get_index functions to hash, to make their
functionality explicit.

Change-Id: Ic6519cfc5e09ea95bc502a29b27f750f04eda754
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18734
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

14073:4a435d5c63f2 08-May-2019 Daniel R. Carvalho <odanrc@yahoo.com.br>

mem-ruby: Fix MultiGrainBloomFilter total count calculation

Previous value was always 0, and was never incrementing. The
total count should take into account the value stored in the
entry.

Change-Id: I93813e3f388198967b30cf11848a8a8c3a7b91f4
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18733
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

14072:aede6dbe889e 05-May-2019 Daniel R. Carvalho <odanrc@yahoo.com.br>

mem-ruby: Remove index based functions in bloom filters

Most of the index based functions were not implemented, and a
user is more likely to be interested in checking the filter
contents based on an address than an index.

As a side effect, the Bulk's hash function became unused, and
according to the paper permute() was doing more than just
permuting, so it was renamed.

Change-Id: I6423a2565a082fee2e7f11fa489a11f253064d99
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18732
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

14071:054392802955 07-May-2019 Daniel R. Carvalho <odanrc@yahoo.com.br>

mem-ruby: Remove Bloom Filter's print()

Print was unused. As a side effect 'using namespace std' is no
longer needed.

Change-Id: Ief10cba1a11dfdd4edb7464eb9291fc83d6668cd
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18731
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

14070:104aec37a31f 08-May-2019 Daniel R. Carvalho <odanrc@yahoo.com.br>

mem-ruby: Standardize Bloom Filter deletion support

Standard Bloom Filters do not support element deletion by default,
however some variants do. Allow calling the unset function with
all filters, and do nothing by default.

Change-Id: Icf4b0f8b997c4c70fa714b2576474810275db78b
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18730
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

14069:bdafa68f3cce 06-May-2019 Daniel R. Carvalho <odanrc@yahoo.com.br>

mem-ruby: Bloom filters - Remove in/decrement

Increment and decrement were functions created to supply the
different naming convention used by the counting bloom filter.
They were removed, and the set and unset functions were used
in their place instead, as in the other filters.

Change-Id: I45732bdfa3083add0a975f374a0f3560003e9d09
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18729
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

14037:a1e12c851596 20-Apr-2017 John Alsop <johnathan.alsop@amd.com>

mem-ruby: Enable set size increase

Add NUMBER_BITS_PER_SET environment variable to control
the size of the bitmask in Set.hh (default=64).
Necessary for configs which require >64 instances of a given
machine type. This can be set in the build_opts file, e.g.
by adding the following line:
NUMBER_BITS_PER_SET = <number>

Change-Id: I314a3cadca8ce975fcf4a60d9022494751688e88
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18968
Reviewed-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

13981:577196ddd040 02-May-2019 Gabe Black <gabeblack@google.com>

arch, base, cpu, dev, mem, sim: Remove #if 0-ed out code.

This code will be preserved through version control, but otherwise
creates clutter and will rot in place since it's never compiled.

Change-Id: Id265f6deac445116843956ea5cf1210d8127274e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18608
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

13974:af47a3ae0f6b 19-Feb-2019 Tiago Muck <tiago.muck@arm.com>

mem-ruby: Hit latencies defined by the controllers

Removed the icache/dcache hit latency parameters from the Sequencer.
They were replaced by the mandatory queue enqueue latency that is now
defined by the top-level cache controller. By default, the latency is
defined by the mandatory_queue_latency parameter. When the latency
depends on specific protocol states or on the request type, the protocol
may override the mandatoryQueueLatency function.

Change-Id: I72e57a7ea49501ef81dc7f591bef14134274647c
Signed-off-by: Tiago Muck <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18413
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

13973:2f953d25716b 25-Feb-2019 Tiago Muck <tiago.muck@arm.com>

mem-ruby: Do not change blocked msg enqueue info

Updating the message counter and enqueue times when adding blocked
messages back to the queue does not make a lot of sense since these
messages are not new arrivals.
More importantly, this may lead to starvation. See the scenario below:

1) Request A for a blocked line X arrives
2) A is handled; X is blocked so A is stalled
3) Request B for X arrives; Reponse for X arrives
4) Response is handled; X unblocked; A added back to the request queue
5) B is handled ahead of A (since A's arrival was updated);
X may become blocked again

If new requests keep comming for X, A may will be stalled forever.

Change-Id: Icad79f3f716a870e91cb3455437b8b3c35f130ac
Signed-off-by: Tiago Muck <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18412
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

13956:0a8aa25fb57e 06-May-2019 Daniel R. Carvalho <odanrc@yahoo.com.br>

mem-ruby: Replace string parameter in MultiBitSelBloomFilter

Replace string parameter from MultiBitSelBloomFilter's constructor
by their tokenized counterparts.

Change-Id: I2e3db109dc4814fa0e9c13259f1136a6c4083092
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18728
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

13892:0182a0601f66 22-Apr-2019 Gabe Black <gabeblack@google.com>

mem: Minimize the use of MemObject.

MemObject doesn't provide anything beyond its base ClockedObject any
more, so this change removes it from most inheritance hierarchies.
Occasionally MemObject is replaced with SimObject when I was fairly
confident that the extra functionality of ClockedObject wasn't needed.

Change-Id: Ic014ab61e56402e62548e8c831eb16e26523fdce
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18289
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>


/gem5/src/arch/arm/ArmTLB.py
/gem5/src/arch/arm/table_walker.cc
/gem5/src/arch/arm/table_walker.hh
/gem5/src/arch/generic/BaseTLB.py
/gem5/src/arch/generic/tlb.hh
/gem5/src/arch/x86/X86TLB.py
/gem5/src/arch/x86/pagetable_walker.cc
/gem5/src/arch/x86/pagetable_walker.hh
/gem5/src/cpu/BaseCPU.py
/gem5/src/cpu/base.cc
/gem5/src/cpu/base.hh
/gem5/src/cpu/o3/checker.cc
/gem5/src/cpu/o3/cpu.hh
/gem5/src/cpu/simple/base.cc
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.cc
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.hh
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.py
/gem5/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc
/gem5/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh
/gem5/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.py
/gem5/src/cpu/testers/memtest/MemTest.py
/gem5/src/cpu/testers/memtest/memtest.cc
/gem5/src/cpu/testers/memtest/memtest.hh
/gem5/src/cpu/testers/rubytest/RubyTester.cc
/gem5/src/cpu/testers/rubytest/RubyTester.hh
/gem5/src/cpu/testers/rubytest/RubyTester.py
/gem5/src/cpu/testers/traffic_gen/BaseTrafficGen.py
/gem5/src/cpu/testers/traffic_gen/base.cc
/gem5/src/cpu/testers/traffic_gen/base.hh
/gem5/src/cpu/thread_state.hh
/gem5/src/dev/Device.py
/gem5/src/dev/dma_device.cc
/gem5/src/dev/dma_device.hh
/gem5/src/dev/io_device.cc
/gem5/src/dev/io_device.hh
/gem5/src/dev/x86/intdev.hh
/gem5/src/doc/memory_system.doxygen
/gem5/src/gpu-compute/GPU.py
/gem5/src/gpu-compute/LdsState.py
/gem5/src/gpu-compute/X86GPUTLB.py
/gem5/src/gpu-compute/compute_unit.cc
/gem5/src/gpu-compute/compute_unit.hh
/gem5/src/gpu-compute/gpu_tlb.cc
/gem5/src/gpu-compute/gpu_tlb.hh
/gem5/src/gpu-compute/lds_state.cc
/gem5/src/gpu-compute/lds_state.hh
/gem5/src/gpu-compute/tlb_coalescer.cc
/gem5/src/gpu-compute/tlb_coalescer.hh
/gem5/src/mem/AbstractMemory.py
/gem5/src/mem/AddrMapper.py
/gem5/src/mem/Bridge.py
/gem5/src/mem/CommMonitor.py
/gem5/src/mem/ExternalMaster.py
/gem5/src/mem/ExternalSlave.py
/gem5/src/mem/MemChecker.py
/gem5/src/mem/MemDelay.py
/gem5/src/mem/SerialLink.py
/gem5/src/mem/XBar.py
/gem5/src/mem/abstract_mem.cc
/gem5/src/mem/abstract_mem.hh
/gem5/src/mem/addr_mapper.cc
/gem5/src/mem/addr_mapper.hh
/gem5/src/mem/bridge.cc
/gem5/src/mem/bridge.hh
/gem5/src/mem/cache/Cache.py
/gem5/src/mem/cache/base.cc
/gem5/src/mem/cache/base.hh
/gem5/src/mem/comm_monitor.cc
/gem5/src/mem/comm_monitor.hh
/gem5/src/mem/dram_ctrl.cc
/gem5/src/mem/dramsim2.cc
/gem5/src/mem/external_master.cc
/gem5/src/mem/external_master.hh
/gem5/src/mem/external_slave.cc
/gem5/src/mem/external_slave.hh
/gem5/src/mem/mem_checker_monitor.cc
/gem5/src/mem/mem_checker_monitor.hh
/gem5/src/mem/mem_delay.cc
/gem5/src/mem/mem_delay.hh
/gem5/src/mem/mport.hh
/gem5/src/mem/packet.hh
/gem5/src/mem/port.cc
/gem5/src/mem/port.hh
/gem5/src/mem/qos/mem_sink.cc
/gem5/src/mem/qport.hh
network/dummy_port.hh
slicc_interface/AbstractController.cc
slicc_interface/AbstractController.hh
slicc_interface/Controller.py
system/RubyPort.cc
system/RubyPort.hh
system/Sequencer.py
system/WeightedLRUReplacementPolicy.py
/gem5/src/mem/serial_link.cc
/gem5/src/mem/serial_link.hh
/gem5/src/mem/simple_mem.cc
/gem5/src/mem/tport.cc
/gem5/src/mem/tport.hh
/gem5/src/mem/xbar.cc
/gem5/src/mem/xbar.hh
/gem5/src/python/m5/SimObject.py
/gem5/src/sim/System.py
/gem5/src/sim/cxx_manager.cc
/gem5/src/sim/system.cc
/gem5/src/sim/system.hh
13799:15badf7874ee 19-Mar-2019 Andrea Mondelli <Andrea.Mondelli@ucf.edu>

misc: missing override specifier

Missing specifier of overridden virtual function
declared in sim_object.hh

Removed redundant "virtual" keyword

Change-Id: I42aa3349b537c9e62607bce20cf1b3aabdb99bf2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17468
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

13784:1941dc118243 07-Mar-2019 Gabe Black <gabeblack@google.com>

arch, cpu, dev, gpu, mem, sim, python: start using getPort.

Replace the getMasterPort, getSlavePort, and getEthPort functions
with getPort, and remove extraneous mechanisms that are no longer
necessary.

Change-Id: Iab7e3c02d2f3a0cf33e7e824e18c28646b5bc318
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17040
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>


/gem5/src/arch/arm/table_walker.cc
/gem5/src/arch/arm/table_walker.hh
/gem5/src/arch/arm/tlb.cc
/gem5/src/arch/arm/tlb.hh
/gem5/src/arch/generic/tlb.hh
/gem5/src/arch/x86/interrupts.hh
/gem5/src/arch/x86/pagetable_walker.cc
/gem5/src/arch/x86/pagetable_walker.hh
/gem5/src/arch/x86/tlb.cc
/gem5/src/arch/x86/tlb.hh
/gem5/src/cpu/base.cc
/gem5/src/cpu/base.hh
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.cc
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.hh
/gem5/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc
/gem5/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh
/gem5/src/cpu/testers/memtest/memtest.cc
/gem5/src/cpu/testers/memtest/memtest.hh
/gem5/src/cpu/testers/rubytest/RubyTester.cc
/gem5/src/cpu/testers/rubytest/RubyTester.hh
/gem5/src/cpu/testers/traffic_gen/base.cc
/gem5/src/cpu/testers/traffic_gen/base.hh
/gem5/src/cpu/trace/trace_cpu.cc
/gem5/src/dev/dma_device.cc
/gem5/src/dev/dma_device.hh
/gem5/src/dev/io_device.cc
/gem5/src/dev/io_device.hh
/gem5/src/dev/net/Ethernet.py
/gem5/src/dev/net/SConscript
/gem5/src/dev/net/dist_etherlink.cc
/gem5/src/dev/net/dist_etherlink.hh
/gem5/src/dev/net/etherbus.cc
/gem5/src/dev/net/etherbus.hh
/gem5/src/dev/net/etherdevice.hh
/gem5/src/dev/net/etherlink.cc
/gem5/src/dev/net/etherlink.hh
/gem5/src/dev/net/etherobject.hh
/gem5/src/dev/net/etherswitch.cc
/gem5/src/dev/net/etherswitch.hh
/gem5/src/dev/net/ethertap.cc
/gem5/src/dev/net/ethertap.hh
/gem5/src/dev/net/i8254xGBe.cc
/gem5/src/dev/net/i8254xGBe.hh
/gem5/src/dev/net/ns_gige.cc
/gem5/src/dev/net/ns_gige.hh
/gem5/src/dev/net/python.cc
/gem5/src/dev/net/sinic.cc
/gem5/src/dev/net/sinic.hh
/gem5/src/dev/pci/copy_engine.cc
/gem5/src/dev/pci/copy_engine.hh
/gem5/src/dev/x86/i82094aa.cc
/gem5/src/dev/x86/i82094aa.hh
/gem5/src/gpu-compute/compute_unit.hh
/gem5/src/gpu-compute/dispatcher.cc
/gem5/src/gpu-compute/dispatcher.hh
/gem5/src/gpu-compute/gpu_tlb.cc
/gem5/src/gpu-compute/gpu_tlb.hh
/gem5/src/gpu-compute/lds_state.hh
/gem5/src/gpu-compute/tlb_coalescer.cc
/gem5/src/gpu-compute/tlb_coalescer.hh
/gem5/src/learning_gem5/part2/simple_cache.cc
/gem5/src/learning_gem5/part2/simple_cache.hh
/gem5/src/learning_gem5/part2/simple_memobj.cc
/gem5/src/learning_gem5/part2/simple_memobj.hh
/gem5/src/mem/addr_mapper.cc
/gem5/src/mem/addr_mapper.hh
/gem5/src/mem/bridge.cc
/gem5/src/mem/bridge.hh
/gem5/src/mem/cache/base.cc
/gem5/src/mem/cache/base.hh
/gem5/src/mem/comm_monitor.cc
/gem5/src/mem/comm_monitor.hh
/gem5/src/mem/dram_ctrl.cc
/gem5/src/mem/dram_ctrl.hh
/gem5/src/mem/dramsim2.cc
/gem5/src/mem/dramsim2.hh
/gem5/src/mem/external_master.cc
/gem5/src/mem/external_master.hh
/gem5/src/mem/external_slave.cc
/gem5/src/mem/external_slave.hh
/gem5/src/mem/mem_checker_monitor.cc
/gem5/src/mem/mem_checker_monitor.hh
/gem5/src/mem/mem_delay.cc
/gem5/src/mem/mem_delay.hh
/gem5/src/mem/mem_object.cc
/gem5/src/mem/mem_object.hh
/gem5/src/mem/qos/mem_sink.cc
/gem5/src/mem/qos/mem_sink.hh
network/MessageBuffer.hh
network/Network.hh
network/dummy_port.hh
slicc_interface/AbstractController.cc
slicc_interface/AbstractController.hh
system/RubyPort.cc
system/RubyPort.hh
/gem5/src/mem/serial_link.cc
/gem5/src/mem/serial_link.hh
/gem5/src/mem/simple_mem.cc
/gem5/src/mem/simple_mem.hh
/gem5/src/mem/xbar.cc
/gem5/src/mem/xbar.hh
/gem5/src/python/SConscript
/gem5/src/python/pybind11/pybind.hh
/gem5/src/python/pybind11/pyobject.cc
/gem5/src/sim/SConscript
/gem5/src/sim/cxx_manager.cc
/gem5/src/sim/init.cc
/gem5/src/sim/python.cc
/gem5/src/sim/system.cc
/gem5/src/sim/system.hh
13773:fc2f9a60cb2d 14-Mar-2019 Ryan Gambord <gambordr@oregonstate.edu>

mem: Removed circular include ref

If BasicLink.hh is modified, the style checker forces a reordering of
the includes, which results in build errors because it ends up including
Topology.hh before including its xxxParams.hh files, which include
forward declarations of the BasicLink family of classes, and so
Topology.hh throws errors that BasicLink etc. are not declared.

Change-Id: I664a0652e53f0cc61763c2190a980c655b85d397
Signed-off-by: Ryan Gambord <gambordr@oregonstate.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17270
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

13736:e678df1f0bf2 22-Feb-2019 Srikant Bharadwaj <srikant.bharadwaj@amd.com>

ruby: Fix garnet's round robin arbitration for vc selection

Garnet utilizes round robin policy to select a VC for
transmission ar Network Interface and Routers. The current logic
for round robin is only fair if all the virtual networks are active
at a given router. If the router or network interface is not
receiving traffic in from any vnet then the priority is always taken
up by the next vnet in numerically (or loops back to 0).

This fix changes the way we perform round robin arbitration. When
a VC is selected in a cycle, the round robin pointer is set to the VC
next to it and is iterated from there on. If any VC does not have a
flit in a given cycle, it will lose its turn until the next round.
At maximum traffic this will model round robin correctly even if
a certain VNET is not active at that unit.

Change-Id: I9bf805221054f9f25bee14b57ff521f4ce4ca980
Reviewed-on: https://gem5-review.googlesource.com/c/16688
Reviewed-by: Jieming Yin <Jieming.Yin@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

13709:dd6b7ac5801f 26-Jan-2019 Andreas Sandberg <andreas.sandberg@arm.com>

python: Make iterator handling Python 3 compatible

Many functions that used to return lists (e.g., dict.items()) now
return iterators and their iterator counterparts (e.g.,
dict.iteritems()) have been removed. Switch calls to the Python 2.7
iterator methods to use the Python 3 equivalent and add explicit list
conversions where necessary.

Change-Id: I0c18114955af8f4932d81fb689a0adb939dafaba
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15992
Reviewed-by: Juha Jäykkä <juha.jaykka@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

13665:9c7fe3811b88 25-Jan-2019 Andreas Sandberg <andreas.sandberg@arm.com>

python: Don't assume SimObjects live in the global namespace

The importer in Python 3 doesn't like the way we import SimObjects
from the global namespace. Convert the existing SimObject declarations
to import from m5.objects. As a side-effect, this makes these files
consistent with configuration files.

Change-Id: I11153502b430822130722839e1fa767b82a027aa
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15981
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>


/gem5/src/arch/alpha/AlphaSystem.py
/gem5/src/arch/alpha/AlphaTLB.py
/gem5/src/arch/arm/ArmISA.py
/gem5/src/arch/arm/ArmNativeTrace.py
/gem5/src/arch/arm/ArmPMU.py
/gem5/src/arch/arm/ArmSemihosting.py
/gem5/src/arch/arm/ArmSystem.py
/gem5/src/arch/arm/ArmTLB.py
/gem5/src/arch/arm/tracers/TarmacTrace.py
/gem5/src/arch/mips/MipsSystem.py
/gem5/src/arch/mips/MipsTLB.py
/gem5/src/arch/power/PowerTLB.py
/gem5/src/arch/riscv/RiscvSystem.py
/gem5/src/arch/riscv/RiscvTLB.py
/gem5/src/arch/sparc/SparcNativeTrace.py
/gem5/src/arch/sparc/SparcSystem.py
/gem5/src/arch/sparc/SparcTLB.py
/gem5/src/arch/x86/X86LocalApic.py
/gem5/src/arch/x86/X86NativeTrace.py
/gem5/src/arch/x86/X86System.py
/gem5/src/arch/x86/X86TLB.py
/gem5/src/base/vnc/Vnc.py
/gem5/src/cpu/BaseCPU.py
/gem5/src/cpu/CPUTracers.py
/gem5/src/cpu/CheckerCPU.py
/gem5/src/cpu/DummyChecker.py
/gem5/src/cpu/InstPBTrace.py
/gem5/src/cpu/kvm/BaseKvmCPU.py
/gem5/src/cpu/kvm/X86KvmCPU.py
/gem5/src/cpu/minor/MinorCPU.py
/gem5/src/cpu/o3/FUPool.py
/gem5/src/cpu/o3/FuncUnitConfig.py
/gem5/src/cpu/o3/O3CPU.py
/gem5/src/cpu/o3/O3Checker.py
/gem5/src/cpu/o3/probe/ElasticTrace.py
/gem5/src/cpu/o3/probe/SimpleTrace.py
/gem5/src/cpu/simple/AtomicSimpleCPU.py
/gem5/src/cpu/simple/BaseSimpleCPU.py
/gem5/src/cpu/simple/NonCachingSimpleCPU.py
/gem5/src/cpu/simple/TimingSimpleCPU.py
/gem5/src/cpu/simple/probes/SimPoint.py
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.py
/gem5/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.py
/gem5/src/cpu/testers/memtest/MemTest.py
/gem5/src/cpu/testers/rubytest/RubyTester.py
/gem5/src/cpu/testers/traffic_gen/BaseTrafficGen.py
/gem5/src/cpu/testers/traffic_gen/PyTrafficGen.py
/gem5/src/cpu/testers/traffic_gen/TrafficGen.py
/gem5/src/cpu/trace/TraceCPU.py
/gem5/src/dev/BadDevice.py
/gem5/src/dev/Device.py
/gem5/src/dev/Platform.py
/gem5/src/dev/alpha/AlphaBackdoor.py
/gem5/src/dev/alpha/Tsunami.py
/gem5/src/dev/arm/EnergyCtrl.py
/gem5/src/dev/arm/FlashDevice.py
/gem5/src/dev/arm/Gic.py
/gem5/src/dev/arm/NoMali.py
/gem5/src/dev/arm/RealView.py
/gem5/src/dev/arm/UFSHostDevice.py
/gem5/src/dev/arm/VirtIOMMIO.py
/gem5/src/dev/i2c/I2C.py
/gem5/src/dev/mips/Malta.py
/gem5/src/dev/net/Ethernet.py
/gem5/src/dev/pci/CopyEngine.py
/gem5/src/dev/pci/PciDevice.py
/gem5/src/dev/pci/PciHost.py
/gem5/src/dev/serial/Terminal.py
/gem5/src/dev/serial/Uart.py
/gem5/src/dev/sparc/T1000.py
/gem5/src/dev/storage/Ide.py
/gem5/src/dev/virtio/VirtIO.py
/gem5/src/dev/virtio/VirtIO9P.py
/gem5/src/dev/virtio/VirtIOBlock.py
/gem5/src/dev/virtio/VirtIOConsole.py
/gem5/src/dev/x86/Cmos.py
/gem5/src/dev/x86/I8042.py
/gem5/src/dev/x86/I82094AA.py
/gem5/src/dev/x86/I8237.py
/gem5/src/dev/x86/I8254.py
/gem5/src/dev/x86/I8259.py
/gem5/src/dev/x86/Pc.py
/gem5/src/dev/x86/PcSpeaker.py
/gem5/src/dev/x86/SouthBridge.py
/gem5/src/gpu-compute/GPU.py
/gem5/src/gpu-compute/LdsState.py
/gem5/src/learning_gem5/part2/SimpleCache.py
/gem5/src/learning_gem5/part2/SimpleMemobj.py
/gem5/src/mem/AbstractMemory.py
/gem5/src/mem/AddrMapper.py
/gem5/src/mem/Bridge.py
/gem5/src/mem/CommMonitor.py
/gem5/src/mem/DRAMCtrl.py
/gem5/src/mem/ExternalMaster.py
/gem5/src/mem/ExternalSlave.py
/gem5/src/mem/HMCController.py
/gem5/src/mem/MemChecker.py
/gem5/src/mem/MemDelay.py
/gem5/src/mem/MemObject.py
/gem5/src/mem/SerialLink.py
/gem5/src/mem/SimpleMemory.py
/gem5/src/mem/XBar.py
/gem5/src/mem/cache/Cache.py
/gem5/src/mem/cache/prefetch/Prefetcher.py
/gem5/src/mem/cache/tags/Tags.py
/gem5/src/mem/probes/MemFootprintProbe.py
/gem5/src/mem/probes/MemTraceProbe.py
/gem5/src/mem/probes/StackDistProbe.py
/gem5/src/mem/qos/QoSMemCtrl.py
/gem5/src/mem/qos/QoSMemSinkCtrl.py
network/BasicRouter.py
network/Network.py
network/garnet2.0/GarnetLink.py
network/garnet2.0/GarnetNetwork.py
network/simple/SimpleLink.py
network/simple/SimpleNetwork.py
slicc_interface/Controller.py
structures/LRUReplacementPolicy.py
structures/PseudoLRUReplacementPolicy.py
structures/RubyCache.py
structures/RubyPrefetcher.py
system/GPUCoalescer.py
system/RubySystem.py
system/Sequencer.py
system/VIPERCoalescer.py
system/WeightedLRUReplacementPolicy.py
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/sim/System.py
/gem5/src/sim/TickedObject.py
/gem5/src/sim/power/MathExprPowerModel.py
/gem5/src/sim/power/ThermalModel.py
13661:c6e84ef6a309 19-Jan-2019 Pouya Fotouhi <pfotouhi@ucdavis.edu>

mem-ruby: Fixing Topology

The constructor assumes the number of nodes (i.e. controllers) equal to
the number of external nodes.
This is a not necessarily valid for all cases (e.g MESI_Three_Level -
where L0s are directly connected to L1s).
MachineType_base_number(MachineType_NUM) provides the total number of
controllers.

Signed-off-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>
Change-Id: Id906099dc967ec70aa34dedb0b55351031ff242c
Reviewed-on: https://gem5-review.googlesource.com/c/15716
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

13564:9bbd53a77887 27-Nov-2018 Nikos Nikoleris <nikos.nikoleris@arm.com>

mem: Determine if a packet queue forces ordering at construction

A packet queue is typically used to hold on to packets that are
schedules to be sent in the future or when they need to queue behind
younger packets that have been sent out yet. Due to memory order
requirements, some MemObjects need to maintain the order for packet
(mostly responses) that reference the same cache block.

Prior to this patch the ordering requirements where determined when
the packet was scheduled to be sent. This patch moves the parameter to
the constructor.

Change-Id: Ieb4d94e86bc7514f5036b313ec23ea47dd653164
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15555
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

13449:2f7efa89c58b 26-Nov-2018 Gabe Black <gabeblack@google.com>

arch, base, cpu, gpu, mem: Replace assert(0 or false with panic.

Neither assert(0) nor assert(false) give any hint as to why control
getting to them is bad, and their more descriptive versions,
assert(0 && "description") and assert(false && "description"), jury
rig assert to add an error message when the utility function panic()
already does that directly with better formatting options.

This change replaces that flavor of call to assert with panic, except
in the actual code which processes the formatting that panic uses (to
avoid infinitely recurring error handling), and in some *.sm files
since I don't know what rules those have to follow and don't want to
accidentaly break them.

Change-Id: I8addfbfaf77eaed94ec8191f2ae4efb477cefdd0
Reviewed-on: https://gem5-review.googlesource.com/c/14636
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

13399:98f54e365584 14-Oct-2018 Daniel R. Carvalho <odanrc@yahoo.com.br>

mem-ruby: Use Packet writing functions instead of memcpy

Classes were using memcpy instead of the Packet functions
created for writing to/from the packet. This allows these
writes to be better checked and tracked.

Change-Id: Iae3fba1351330916ee1d4103809c71e151b1639e
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/13915
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

13062:6f9defe1c11e 19-Sep-2018 Xianwei Zhang <xianwei.zhang@amd.com>

mem-ruby: Fix a bug in MessageBuffer randomization

In the previous implementation, messages are randomly inserted with
delays only if both RubySystem and MessageBuffer randomization flags
are set true. However, to find race conditions and cover more slicc
transitions, ruby random testers rely on setting RubySystem flag to
turn on randomization on all message buffers.
As a fix, this patch enables a message buffer to have randomization
when either RubySystem or its own flag is set.

Change-Id: I1e076908ff07e5846ebad4f4fc1c8f28d40bbfd4
Reviewed-on: https://gem5-review.googlesource.com/12784
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

12892:796175b0e2dc 15-Feb-2018 Brandon Potter <brandon.potter@amd.com>

scons,ruby: do not generate unnecessary files

Do not generate garnet tester file or Ruby debug headers without a Ruby
protocol (i.e. PROTOCOL=None). It makes no sense to include these files
into the build when there will be no protocol to utilize them.

Change-Id: I8db4dd532f60008217a10c88a2e089f85df9d104
Reviewed-on: https://gem5-review.googlesource.com/8381
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

12890:2dcd62e80e96 19-Feb-2018 Brandon Potter <brandon.potter@amd.com>

ruby: remove unused code inside '#if 0 ... #endif'

The commented code contains bitrot. It is not clear how to fix the code
so remove it.

The code will not compile if the preprocessor defines are removed. The
llocker and uulocker variables that are used as indices into the
persistent_randomize array are undefined. It's not clear what they should
be from the current code.

5ab13e2deb shows when the lines were last modified. The functionality
contained in the comments probably have not been used since that time.
(This is an example of why one should never add commented code that
is enabled by removing defines. The code rots and sits in the source
forever.)

Change-Id: I3e0e7c9afc0b6088130e6f319075809fb6f16e5a
Reviewed-on: https://gem5-review.googlesource.com/8481
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

12823:ba630bc7a36d 19-Jul-2018 Robert Kovacsics <rmk35@cl.cam.ac.uk>

mem: Rename Packet::checkFunctional to trySatisfyFunctional

Packet::checkFunctional also wrote data to/from the packet depending
on if it was read/write, respectively, which the 'check' in the name
would suggest otherwise. This renames it to doFunctional, which is
more suggestive. It also renames any function called checkFunctional
which calls Packet::checkFunctional. These are

- Bridge::BridgeMasterPort::checkFunctional
- calls Packet::checkFunctional
- MSHR::checkFunctional
- calls Packet::checkFunctional
- MSHR::TargetList::checkFunctional
- calls Packet::checkFunctional
- Queue<>::checkFunctional
(of src/mem/cache/queue.hh, not src/cpu/minor/buffers.h)
- Instantiated with Queue<WriteQueueEntry> and Queue<MSHR>
- WriteQueueEntry
- calls Packet::checkFunctional
- WriteQueueEntry::TargetList
- calls Packet::checkFunctional
- MemDelay::checkFunctional
- calls QueuedSlavePort/QueuedMasterPort::checkFunctional
- Packet::checkFunctional
- PacketQueue::checkFunctional
- calls Packet::checkFunctional
- QueuedSlavePort::checkFunctional
- calls PacketQueue::doFunctional
- QueuedMasterPort::checkFunctional
- calls PacketQueue::doFunctional
- SerialLink::SerialLinkMasterPort::checkFunctional
- calls Packet::doFunctional

Change-Id: Ieca2579c020c329040da053ba8e25820801b62c5
Reviewed-on: https://gem5-review.googlesource.com/11810
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

12750:1dde69fad30f 05-Jun-2018 Daniel R. Carvalho <odanrc@yahoo.com.br>

ruby: Fix initial weight in weighted LRU

Initial weight was using the timestamp instead of the weight.

Change-Id: I61d3c8424f85fd6856957087c477afda111f8ca7
Reviewed-on: https://gem5-review.googlesource.com/10801
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

12749:223c83ed9979 04-Jun-2018 Giacomo Travaglini <giacomo.travaglini@arm.com>

misc: Using smart pointers for memory Requests

This patch is changing the underlying type for RequestPtr from Request*
to shared_ptr<Request>. Having memory requests being managed by smart
pointers will simplify the code; it will also prevent memory leakage and
dangling pointers.

Change-Id: I7749af38a11ac8eb4d53d8df1252951e0890fde3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10996
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>


/gem5/ext/sst/ExtMaster.cc
/gem5/ext/sst/ExtSlave.cc
/gem5/src/arch/alpha/locked_mem.hh
/gem5/src/arch/alpha/tlb.cc
/gem5/src/arch/alpha/tlb.hh
/gem5/src/arch/arm/isa.cc
/gem5/src/arch/arm/locked_mem.hh
/gem5/src/arch/arm/stage2_lookup.cc
/gem5/src/arch/arm/stage2_lookup.hh
/gem5/src/arch/arm/stage2_mmu.cc
/gem5/src/arch/arm/stage2_mmu.hh
/gem5/src/arch/arm/table_walker.cc
/gem5/src/arch/arm/table_walker.hh
/gem5/src/arch/arm/tlb.cc
/gem5/src/arch/arm/tlb.hh
/gem5/src/arch/arm/tracers/tarmac_parser.cc
/gem5/src/arch/arm/tracers/tarmac_parser.hh
/gem5/src/arch/arm/vtophys.cc
/gem5/src/arch/generic/locked_mem.hh
/gem5/src/arch/generic/tlb.cc
/gem5/src/arch/generic/tlb.hh
/gem5/src/arch/hsail/insts/mem.hh
/gem5/src/arch/mips/locked_mem.hh
/gem5/src/arch/mips/tlb.cc
/gem5/src/arch/mips/tlb.hh
/gem5/src/arch/power/tlb.cc
/gem5/src/arch/power/tlb.hh
/gem5/src/arch/riscv/locked_mem.hh
/gem5/src/arch/riscv/tlb.cc
/gem5/src/arch/riscv/tlb.hh
/gem5/src/arch/sparc/tlb.cc
/gem5/src/arch/sparc/tlb.hh
/gem5/src/arch/x86/intmessage.hh
/gem5/src/arch/x86/pagetable_walker.cc
/gem5/src/arch/x86/pagetable_walker.hh
/gem5/src/arch/x86/tlb.cc
/gem5/src/arch/x86/tlb.hh
/gem5/src/cpu/base.cc
/gem5/src/cpu/base_dyn_inst.hh
/gem5/src/cpu/base_dyn_inst_impl.hh
/gem5/src/cpu/checker/cpu.cc
/gem5/src/cpu/checker/cpu.hh
/gem5/src/cpu/checker/cpu_impl.hh
/gem5/src/cpu/kvm/base.cc
/gem5/src/cpu/kvm/x86_cpu.cc
/gem5/src/cpu/minor/fetch1.cc
/gem5/src/cpu/minor/fetch1.hh
/gem5/src/cpu/minor/lsq.cc
/gem5/src/cpu/minor/lsq.hh
/gem5/src/cpu/o3/cpu.hh
/gem5/src/cpu/o3/fetch.hh
/gem5/src/cpu/o3/fetch_impl.hh
/gem5/src/cpu/o3/lsq.hh
/gem5/src/cpu/o3/lsq_impl.hh
/gem5/src/cpu/o3/lsq_unit.hh
/gem5/src/cpu/o3/lsq_unit_impl.hh
/gem5/src/cpu/simple/atomic.cc
/gem5/src/cpu/simple/atomic.hh
/gem5/src/cpu/simple/base.cc
/gem5/src/cpu/simple/base.hh
/gem5/src/cpu/simple/timing.cc
/gem5/src/cpu/simple/timing.hh
/gem5/src/cpu/testers/directedtest/InvalidateGenerator.cc
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.cc
/gem5/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
/gem5/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc
/gem5/src/cpu/testers/memtest/memtest.cc
/gem5/src/cpu/testers/rubytest/Check.cc
/gem5/src/cpu/testers/rubytest/RubyTester.cc
/gem5/src/cpu/testers/traffic_gen/base_gen.cc
/gem5/src/cpu/testers/traffic_gen/traffic_gen.cc
/gem5/src/cpu/trace/trace_cpu.cc
/gem5/src/cpu/translation.hh
/gem5/src/dev/dma_device.cc
/gem5/src/dev/x86/i82094aa.cc
/gem5/src/gpu-compute/compute_unit.cc
/gem5/src/gpu-compute/fetch_unit.cc
/gem5/src/gpu-compute/gpu_tlb.cc
/gem5/src/gpu-compute/gpu_tlb.hh
/gem5/src/gpu-compute/shader.cc
/gem5/src/gpu-compute/shader.hh
/gem5/src/learning_gem5/part2/simple_cache.cc
/gem5/src/mem/abstract_mem.cc
/gem5/src/mem/abstract_mem.hh
/gem5/src/mem/cache/base.cc
/gem5/src/mem/cache/blk.hh
/gem5/src/mem/cache/cache.cc
/gem5/src/mem/cache/mshr.cc
/gem5/src/mem/cache/noncoherent_cache.cc
/gem5/src/mem/cache/prefetch/queued.cc
/gem5/src/mem/packet.hh
/gem5/src/mem/page_table.cc
/gem5/src/mem/page_table.hh
/gem5/src/mem/port.cc
/gem5/src/mem/port_proxy.cc
/gem5/src/mem/request.hh
slicc_interface/AbstractController.cc
system/CacheRecorder.cc
system/GPUCoalescer.cc
system/GPUCoalescer.hh
system/RubyPort.cc
system/Sequencer.cc
/gem5/util/tlm/src/sc_master_port.cc
12697:cd71b966be1e 27-Apr-2018 Tony Gutierrez <anthony.gutierrez@amd.com>

style: fix amd license and style issues

Change-Id: I26136fb49f743c4a597f8021cfd27f78897267b5
Reviewed-on: https://gem5-review.googlesource.com/10463
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>


/gem5/configs/example/apu_se.py
/gem5/configs/ruby/MOESI_AMD_Base.py
/gem5/src/gpu-compute/LdsState.py
/gem5/src/gpu-compute/SConscript
/gem5/src/gpu-compute/X86GPUTLB.py
/gem5/src/gpu-compute/compute_unit.cc
/gem5/src/gpu-compute/compute_unit.hh
/gem5/src/gpu-compute/dispatcher.cc
/gem5/src/gpu-compute/dispatcher.hh
/gem5/src/gpu-compute/exec_stage.cc
/gem5/src/gpu-compute/exec_stage.hh
/gem5/src/gpu-compute/fetch_stage.cc
/gem5/src/gpu-compute/fetch_stage.hh
/gem5/src/gpu-compute/fetch_unit.cc
/gem5/src/gpu-compute/fetch_unit.hh
/gem5/src/gpu-compute/global_memory_pipeline.cc
/gem5/src/gpu-compute/global_memory_pipeline.hh
/gem5/src/gpu-compute/gpu_dyn_inst.cc
/gem5/src/gpu-compute/gpu_dyn_inst.hh
/gem5/src/gpu-compute/gpu_exec_context.cc
/gem5/src/gpu-compute/gpu_exec_context.hh
/gem5/src/gpu-compute/gpu_static_inst.cc
/gem5/src/gpu-compute/gpu_static_inst.hh
/gem5/src/gpu-compute/gpu_tlb.hh
/gem5/src/gpu-compute/lds_state.cc
/gem5/src/gpu-compute/lds_state.hh
/gem5/src/gpu-compute/local_memory_pipeline.cc
/gem5/src/gpu-compute/local_memory_pipeline.hh
/gem5/src/gpu-compute/misc.hh
/gem5/src/gpu-compute/pool_manager.cc
/gem5/src/gpu-compute/pool_manager.hh
/gem5/src/gpu-compute/schedule_stage.cc
/gem5/src/gpu-compute/schedule_stage.hh
/gem5/src/gpu-compute/scoreboard_check_stage.cc
/gem5/src/gpu-compute/scoreboard_check_stage.hh
/gem5/src/gpu-compute/shader.cc
/gem5/src/gpu-compute/simple_pool_manager.cc
/gem5/src/gpu-compute/simple_pool_manager.hh
/gem5/src/gpu-compute/tlb_coalescer.cc
/gem5/src/gpu-compute/tlb_coalescer.hh
/gem5/src/gpu-compute/vector_register_file.cc
/gem5/src/gpu-compute/vector_register_file.hh
/gem5/src/gpu-compute/wavefront.cc
/gem5/src/gpu-compute/wavefront.hh
common/IntVec.cc
common/IntVec.hh
system/GPUCoalescer.cc
system/GPUCoalescer.hh
system/GPUCoalescer.py
system/VIPERCoalescer.cc
system/VIPERCoalescer.hh
system/VIPERCoalescer.py
system/WeightedLRUPolicy.cc
system/WeightedLRUPolicy.hh
system/WeightedLRUReplacementPolicy.py
/gem5/src/sim/aux_vector.cc
/gem5/src/sim/aux_vector.hh
/gem5/src/sim/fd_array.cc
/gem5/src/sim/fd_array.hh
/gem5/src/sim/fd_entry.cc
/gem5/src/sim/fd_entry.hh
12687:f26377b7f0c1 03-May-2018 Brad Beckmann <brad.beckmann@amd.com>

mem-ruby: Consistent dprintf formats for issue outcomes

Change-Id: I053fc42f0d5f678f8e3434b53a0f09e00fc3e345
Reviewed-on: https://gem5-review.googlesource.com/10221
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

12680:91f4d6668b4f 04-Apr-2018 Giacomo Travaglini <giacomo.travaglini@arm.com>

sim,cpu,mem,arch: Introduced MasterInfo data structure

With this patch a gem5 System will store more info about its Masters.
While it was previously keeping track of the Master name and Master ID
only, it is now adding a per-Master pointer to the SimObject related to
the Master.
This will make it possible for a client to query a System for a Master
using either the master's name or the master's pointer.

Change-Id: I8b97d328a65cd06f329e2cdd3679451c17d2b8f6
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9781
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

12563:8d59ed22ae79 06-Mar-2018 Gabe Black <gabeblack@google.com>

scons: Switch from the print statement to the print function.

Starting with version 3, scons imposes using the print function instead
of the print statement in code it processes. To get things building
again, this change moves all python code within gem5 to use the
function version. Another change by another author separately made this
same change to the site_tools and site_init.py files.

Change-Id: I2de7dc3b1be756baad6f60574c47c8b7e80ea3b0
Reviewed-on: https://gem5-review.googlesource.com/8761
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

12492:4e76959883a6 05-Feb-2018 Daniel R. Carvalho <odanrc@yahoo.com.br>

mem: Standardize mem folder header guards

Standardize all header guards in the mem directory according to the most
frequent patterns. In general they have the form:
mem: __FOLDER_TREE_FILE_NAME_HH__
ruby: __FOLDER_TREE_FILENAME_HH__

Change-Id: I983853e292deb302becf151bf0e970057dc24774
Reviewed-on: https://gem5-review.googlesource.com/7881
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

12395:322bb93e5f06 09-Nov-2017 Swapnil Haria <swapnilster@gmail.com>

mem-ruby: Support atomic_noncaching acceses in ruby

Ruby has no support for atomic_noncaching accesses, which prevents using
it with kvm-cpu. This patch fixes this by directly forwarding atomic
requests from the ruby port/sequencer to the corresponding directory
based on the destination address of the packet.

Change-Id: I0b4928bfda44fd9e5e48583c51d1ea422800da2d
Reviewed-on: https://gem5-review.googlesource.com/5601
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Bradford Beckmann <brad.beckmann@amd.com>

12357:86b87f330638 07-Oct-2017 Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-ruby: Prevent ruby from crashing on CMOs

Ruby has no support for cache maintenace operations. As a workaround,
after printing a warning, we treat them as no-ops in the memory system
and respond immediately without handling them. There should be
workarounds in the memory system already that allow execution to
proceed without the requirement for cache maintenance operations.

Change-Id: I125ee4fa37b674c636d87f2d9205bbc1a74da101
Reviewed-on: https://gem5-review.googlesource.com/5057
Reviewed-by: Jieming Yin <bjm419@gmail.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

12334:e0ab29a34764 30-Nov-2017 Gabe Black <gabeblack@google.com>

misc: Rename misc.(hh|cc) to logging.(hh|cc)

These files aren't a collection of miscellaneous stuff, they're the
definition of the Logger interface, and a few utility macros for
calling into that interface (panic, warn, etc.).

Change-Id: I84267ac3f45896a83c0ef027f8f19c5e9a5667d1
Reviewed-on: https://gem5-review.googlesource.com/6226
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>


/gem5/ext/sst/gem5.cc
/gem5/src/arch/alpha/isa.cc
/gem5/src/arch/alpha/locked_mem.hh
/gem5/src/arch/alpha/mt.hh
/gem5/src/arch/alpha/process.cc
/gem5/src/arch/alpha/pseudo_inst.hh
/gem5/src/arch/alpha/utility.hh
/gem5/src/arch/arm/faults.hh
/gem5/src/arch/arm/isa_device.cc
/gem5/src/arch/arm/miscregs.cc
/gem5/src/arch/arm/process.cc
/gem5/src/arch/arm/pseudo_inst.hh
/gem5/src/arch/arm/types.hh
/gem5/src/arch/arm/utility.hh
/gem5/src/arch/generic/debugfaults.hh
/gem5/src/arch/generic/pseudo_inst.cc
/gem5/src/arch/generic/tlb.hh
/gem5/src/arch/generic/vec_reg.hh
/gem5/src/arch/hsail/gpu_isa.hh
/gem5/src/arch/mips/decoder.hh
/gem5/src/arch/mips/dsp.cc
/gem5/src/arch/mips/dsp.hh
/gem5/src/arch/mips/interrupts.hh
/gem5/src/arch/mips/locked_mem.hh
/gem5/src/arch/mips/mt.hh
/gem5/src/arch/mips/pagetable.hh
/gem5/src/arch/mips/process.cc
/gem5/src/arch/mips/pseudo_inst.hh
/gem5/src/arch/mips/registers.hh
/gem5/src/arch/mips/utility.cc
/gem5/src/arch/mips/utility.hh
/gem5/src/arch/power/interrupts.hh
/gem5/src/arch/power/isa.hh
/gem5/src/arch/power/process.cc
/gem5/src/arch/power/pseudo_inst.hh
/gem5/src/arch/power/utility.cc
/gem5/src/arch/riscv/decoder.hh
/gem5/src/arch/riscv/interrupts.hh
/gem5/src/arch/riscv/isa.hh
/gem5/src/arch/riscv/locked_mem.hh
/gem5/src/arch/riscv/pagetable.hh
/gem5/src/arch/riscv/process.cc
/gem5/src/arch/riscv/pseudo_inst.hh
/gem5/src/arch/sparc/isa/includes.isa
/gem5/src/arch/sparc/mt.hh
/gem5/src/arch/sparc/pagetable.hh
/gem5/src/arch/sparc/process.cc
/gem5/src/arch/sparc/pseudo_inst.hh
/gem5/src/arch/sparc/tlb.hh
/gem5/src/arch/sparc/utility.hh
/gem5/src/arch/x86/bios/intelmp.cc
/gem5/src/arch/x86/decoder.cc
/gem5/src/arch/x86/decoder.hh
/gem5/src/arch/x86/emulenv.cc
/gem5/src/arch/x86/faults.hh
/gem5/src/arch/x86/isa/includes.isa
/gem5/src/arch/x86/process.cc
/gem5/src/arch/x86/regs/int.hh
/gem5/src/base/SConscript
/gem5/src/base/addr_range.hh
/gem5/src/base/bigint.hh
/gem5/src/base/bmpwriter.cc
/gem5/src/base/circlebuf.hh
/gem5/src/base/debug.cc
/gem5/src/base/hostinfo.cc
/gem5/src/base/imgwriter.cc
/gem5/src/base/intmath.hh
/gem5/src/base/loader/ecoff_object.cc
/gem5/src/base/loader/elf_object.cc
/gem5/src/base/loader/object_file.hh
/gem5/src/base/loader/symtab.cc
/gem5/src/base/logging.cc
/gem5/src/base/logging.hh
/gem5/src/base/misc.cc
/gem5/src/base/misc.hh
/gem5/src/base/output.cc
/gem5/src/base/pngwriter.cc
/gem5/src/base/pollevent.cc
/gem5/src/base/random.cc
/gem5/src/base/socket.cc
/gem5/src/base/statistics.cc
/gem5/src/base/stats/text.cc
/gem5/src/base/time.cc
/gem5/src/base/trace.cc
/gem5/src/base/trie.hh
/gem5/src/base/vnc/vncinput.cc
/gem5/src/base/vnc/vncserver.cc
/gem5/src/cpu/base.cc
/gem5/src/cpu/func_unit.cc
/gem5/src/cpu/intr_control.hh
/gem5/src/cpu/kvm/device.cc
/gem5/src/cpu/kvm/perfevent.cc
/gem5/src/cpu/kvm/timer.cc
/gem5/src/cpu/minor/buffers.hh
/gem5/src/cpu/o3/free_list.hh
/gem5/src/cpu/o3/store_set.cc
/gem5/src/cpu/pc_event.hh
/gem5/src/cpu/pred/2bit_local.cc
/gem5/src/cpu/pred/btb.hh
/gem5/src/cpu/pred/ltage.cc
/gem5/src/cpu/pred/sat_counter.hh
/gem5/src/cpu/simple/base.cc
/gem5/src/cpu/static_inst.hh
/gem5/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc
/gem5/src/cpu/testers/rubytest/RubyTester.cc
/gem5/src/cpu/thread_context.cc
/gem5/src/dev/intel_8254_timer.cc
/gem5/src/dev/mc146818.hh
/gem5/src/dev/net/dist_iface.hh
/gem5/src/dev/net/etherbus.cc
/gem5/src/dev/net/etherdump.cc
/gem5/src/dev/net/etherint.cc
/gem5/src/dev/net/etherpkt.cc
/gem5/src/dev/net/ethertap.cc
/gem5/src/dev/net/pktfifo.cc
/gem5/src/dev/net/pktfifo.hh
/gem5/src/dev/pci/device.cc
/gem5/src/dev/platform.cc
/gem5/src/dev/ps2.cc
/gem5/src/dev/serial/serial.cc
/gem5/src/dev/serial/terminal.cc
/gem5/src/dev/storage/disk_image.cc
/gem5/src/dev/storage/simple_disk.cc
/gem5/src/gpu-compute/brig_object.cc
/gem5/src/gpu-compute/gpu_tlb.hh
/gem5/src/gpu-compute/hsa_object.cc
/gem5/src/gpu-compute/misc.hh
/gem5/src/gpu-compute/of_scheduling_policy.hh
/gem5/src/gpu-compute/rr_scheduling_policy.hh
/gem5/src/gpu-compute/simple_pool_manager.cc
/gem5/src/gpu-compute/tlb_coalescer.hh
/gem5/src/gpu-compute/vector_register_file.cc
/gem5/src/gpu-compute/wavefront.hh
/gem5/src/kern/operatingsystem.cc
/gem5/src/mem/cache/base.hh
/gem5/src/mem/cache/cache.cc
/gem5/src/mem/cache/cache.hh
/gem5/src/mem/cache/mshr.cc
/gem5/src/mem/cache/tags/fa_lru.cc
/gem5/src/mem/cache/write_queue_entry.cc
/gem5/src/mem/coherent_xbar.cc
/gem5/src/mem/dramsim2_wrapper.cc
/gem5/src/mem/mem_checker.hh
/gem5/src/mem/noncoherent_xbar.cc
/gem5/src/mem/packet.cc
/gem5/src/mem/packet.hh
/gem5/src/mem/request.hh
common/Set.hh
network/MessageBuffer.cc
network/Network.cc
network/fault_model/FaultModel.cc
slicc_interface/AbstractCacheEntry.hh
structures/AbstractReplacementPolicy.cc
system/GPUCoalescer.cc
system/Sequencer.cc
system/VIPERCoalescer.cc
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/mem/slicc/symbols/Type.py
/gem5/src/mem/snoop_filter.cc
/gem5/src/mem/xbar.cc
/gem5/src/proto/protoio.cc
/gem5/src/python/pybind11/core.cc
/gem5/src/python/pybind11/event.cc
/gem5/src/sim/clocked_object.cc
/gem5/src/sim/drain.cc
/gem5/src/sim/dvfs_handler.cc
/gem5/src/sim/eventq.cc
/gem5/src/sim/faults.cc
/gem5/src/sim/fd_array.cc
/gem5/src/sim/init.cc
/gem5/src/sim/init_signals.cc
/gem5/src/sim/mathexpr.cc
/gem5/src/sim/microcode_rom.cc
/gem5/src/sim/root.cc
/gem5/src/sim/serialize.cc
/gem5/src/sim/sim_object.cc
/gem5/src/sim/simulate.cc
/gem5/src/sim/syscall_emul.hh
/gem5/src/unittest/cprintftest.cc
/gem5/src/unittest/nmtest.cc
/gem5/src/unittest/stattest.cc
/gem5/util/systemc/sc_module.cc
12246:9ffa51416f39 08-Nov-2017 Gabe Black <gabeblack@google.com>

scons: Move Transform and termcap functionality into their own files.

Change-Id: Ica08e93f3873a7eafd02fe7d44c3bdbf0ce7f6b7
Reviewed-on: https://gem5-review.googlesource.com/5565
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

12133:ca42be3276af 28-Jun-2017 Sean Wilson <spwilson2@wisc.edu>

ruby: Refactor some Event subclasses to lambdas

Change-Id: I9f47a20a869553515a759d9a29c05f6ce4b42d64
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/3930
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

12071:fd0b4bd769dd 06-Jun-2017 Javier Cano-Cano <javier.cano555@gmail.com>

mem-garnet: Fix garnet stats

This patch fix some statistics that in presence of a resetStats
instruction were not reseted. This bug makes impossible to obtain
reliable network statistics when the simulation doesn't start from tick
zero.

Change-Id: Ibec45f08d95bf0a533d94b70ec960719206ae945
Maintainer: Tushar Krishna <tushar@ece.gatech.edu>
Reviewed-on: https://gem5-review.googlesource.com/3700
Reviewed-by: Jieming Yin <bjm419@gmail.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

12065:e3e51756dfef 13-Mar-2017 Nikos Nikoleris <nikos.nikoleris@arm.com>

ruby: Add support for address ranges in the directory

Previously the directory covered a flat address range that always
started from address 0. This change adds a vector of address ranges
with interleaving and hashing that each directory keeps track of and
the necessary flexibility to support systems with non continuous
memory ranges.

Change-Id: I6ea1c629bdf4c5137b7d9c89dbaf6c826adfd977
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2903
Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>


/gem5/configs/ruby/GPU_RfO.py
/gem5/configs/ruby/Garnet_standalone.py
/gem5/configs/ruby/MESI_Three_Level.py
/gem5/configs/ruby/MESI_Two_Level.py
/gem5/configs/ruby/MI_example.py
/gem5/configs/ruby/MOESI_AMD_Base.py
/gem5/configs/ruby/MOESI_CMP_directory.py
/gem5/configs/ruby/MOESI_CMP_token.py
/gem5/configs/ruby/MOESI_hammer.py
/gem5/configs/ruby/Ruby.py
/gem5/src/base/addr_range.hh
/gem5/src/mem/protocol/GPU_RfO-TCCdir.sm
/gem5/src/mem/protocol/GPU_VIPER-TCC.sm
/gem5/src/mem/protocol/GPU_VIPER_Region-TCC.sm
/gem5/src/mem/protocol/Garnet_standalone-cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-L2cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-dma.sm
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dma.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-CorePair.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-L3cache.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-Region-CorePair.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-Region-dir.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-RegionBuffer.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-RegionDir.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-probeFilter.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dma.sm
/gem5/src/mem/protocol/MOESI_hammer-cache.sm
/gem5/src/mem/protocol/MOESI_hammer-dma.sm
/gem5/src/mem/protocol/RubySlicc_ComponentMapping.sm
network/Network.cc
network/Network.hh
slicc_interface/AbstractController.cc
slicc_interface/AbstractController.hh
slicc_interface/Controller.py
slicc_interface/RubySlicc_ComponentMapping.hh
structures/DirectoryMemory.cc
structures/DirectoryMemory.hh
structures/DirectoryMemory.py
/gem5/src/mem/slicc/symbols/Type.py
12051:4cc27e53748d 03-Mar-2017 Nikos Nikoleris <nikos.nikoleris@arm.com>

ruby: Don't set the block data when a store conditional fails

Previously the Sequencer upon a Store Conditional would
unconditionally set the data of the memory location. This change
checks and prevents a failed Store Conditional from modifying any
data.

Change-Id: Id63c9579d8f054f0e95c6d338a7e31aa48762755
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2902
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

11903:a75e4eae89c0 05-Feb-2017 Lena Olson <leolson@google.com>

ruby: fix MOESI_hammer directory to work with > 3GB memory

The MOESI_hammer directory assumes a contiguous address space, but X86
has an IO gap from 3-4GB. This patch allows the directory to work with
more than 3GB of memory on X86.

Assumptions: the physical address space (range of possible physical
addresses) is 0-XGB when X <= 3GB, and 0-(X+1)GB when X > 3GB. If there
is no IO gap this patch should still work.

Change-Id: I5453a09e953643cada2c096a91d339a3676f55ee
Reviewed-on: https://gem5-review.googlesource.com/2169
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

11900:0787df49546b 27-Feb-2017 Andreas Sandberg <andreas.sandberg@arm.com>

gpu-compute: Fix Python/C++ object hierarchy discrepancies

The GPUCoalescer and the Shader classes have different base classes in
C++ and Python. This causes subtle bugs in SWIG and compilation errors
for PyBind.

Change-Id: I1ddd2a8ea43f083470538ddfea891347b21d14d8
Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2228
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Pierre-Yves Péneau <pierre-yves.peneau@lirmm.fr>
Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com>

11831:3c38d3e74980 12-Feb-2017 Tushar Krishna <tushar@ece.gatech.edu>

ruby: fix round robin arbiter in garnet2.0
The rr arbiter pointer in garnet was getting updated on every request,
even if there is no grant. This was leading to a huge variance in wait
time at a router at high injection rates.
This patch corrects it to update upon a grant.

11800:54436a1784dc 09-Nov-2016 Brandon Potter <brandon.potter@amd.com>

style: [patch 3/22] reduce include dependencies in some headers

Used cppclean to help identify useless includes and removed them. This
involved erroneously included headers, but also cases where forward
declarations could have been used rather than a full include.


/gem5/src/arch/alpha/process.cc
/gem5/src/arch/alpha/process.hh
/gem5/src/arch/arm/process.cc
/gem5/src/arch/arm/process.hh
/gem5/src/arch/mips/process.cc
/gem5/src/arch/mips/process.hh
/gem5/src/arch/power/interrupts.hh
/gem5/src/arch/power/process.cc
/gem5/src/arch/power/process.hh
/gem5/src/arch/power/remote_gdb.cc
/gem5/src/arch/riscv/interrupts.hh
/gem5/src/arch/riscv/process.cc
/gem5/src/arch/riscv/process.hh
/gem5/src/arch/sparc/process.cc
/gem5/src/arch/sparc/process.hh
/gem5/src/arch/x86/isa_traits.hh
/gem5/src/arch/x86/pagetable.hh
/gem5/src/arch/x86/process.cc
/gem5/src/arch/x86/pseudo_inst.cc
/gem5/src/arch/x86/system.cc
/gem5/src/arch/x86/system.hh
/gem5/src/arch/x86/tlb.cc
/gem5/src/arch/x86/tlb.hh
/gem5/src/arch/x86/utility.cc
/gem5/src/arch/x86/utility.hh
/gem5/src/base/bitfield.hh
/gem5/src/base/bitunion.hh
/gem5/src/base/time.cc
/gem5/src/base/vnc/vncinput.cc
/gem5/src/cpu/minor/buffers.hh
/gem5/src/cpu/testers/directedtest/InvalidateGenerator.cc
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.cc
/gem5/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
/gem5/src/cpu/testers/memtest/memtest.cc
/gem5/src/cpu/testers/rubytest/Check.cc
/gem5/src/cpu/testers/rubytest/CheckTable.cc
/gem5/src/cpu/testers/rubytest/RubyTester.cc
/gem5/src/dev/arm/flash_device.cc
/gem5/src/dev/mc146818.hh
/gem5/src/dev/net/dist_iface.hh
/gem5/src/dev/net/etherbus.cc
/gem5/src/dev/net/etherswitch.cc
/gem5/src/gpu-compute/vector_register_file.hh
/gem5/src/kern/linux/linux.cc
/gem5/src/kern/linux/linux.hh
/gem5/src/mem/cache/prefetch/stride.cc
/gem5/src/mem/external_master.cc
/gem5/src/mem/external_slave.cc
/gem5/src/mem/mem_checker.hh
/gem5/src/mem/multi_level_page_table.hh
/gem5/src/mem/multi_level_page_table_impl.hh
/gem5/src/mem/page_table.cc
/gem5/src/mem/page_table.hh
network/MessageBuffer.hh
structures/AbstractReplacementPolicy.cc
/gem5/src/mem/se_translating_port_proxy.hh
/gem5/src/mem/simple_mem.cc
/gem5/src/python/swig/pyevent.cc
/gem5/src/sim/SConscript
/gem5/src/sim/arguments.cc
/gem5/src/sim/arguments.hh
/gem5/src/sim/byteswap.hh
/gem5/src/sim/clock_domain.cc
/gem5/src/sim/clocked_object.hh
/gem5/src/sim/cxx_config.hh
/gem5/src/sim/cxx_config_ini.cc
/gem5/src/sim/cxx_config_ini.hh
/gem5/src/sim/cxx_manager.cc
/gem5/src/sim/drain.hh
/gem5/src/sim/dvfs_handler.cc
/gem5/src/sim/dvfs_handler.hh
/gem5/src/sim/eventq.hh
/gem5/src/sim/fd_entry.hh
/gem5/src/sim/init_signals.cc
/gem5/src/sim/insttracer.hh
/gem5/src/sim/microcode_rom.cc
/gem5/src/sim/microcode_rom.hh
/gem5/src/sim/power/mathexpr_powermodel.hh
/gem5/src/sim/power/power_model.cc
/gem5/src/sim/power/power_model.hh
/gem5/src/sim/power/thermal_domain.cc
/gem5/src/sim/power/thermal_domain.hh
/gem5/src/sim/power/thermal_entity.hh
/gem5/src/sim/power/thermal_model.hh
/gem5/src/sim/probe/probe.cc
/gem5/src/sim/probe/probe.hh
/gem5/src/sim/process.cc
/gem5/src/sim/process.hh
/gem5/src/sim/process_impl.hh
/gem5/src/sim/root.cc
/gem5/src/sim/serialize.hh
/gem5/src/sim/sim_exit.hh
/gem5/src/sim/sim_object.cc
/gem5/src/sim/sim_object.hh
/gem5/src/sim/simulate.hh
/gem5/src/sim/stat_register.cc
/gem5/src/sim/stat_register.hh
/gem5/src/sim/sub_system.hh
/gem5/src/sim/syscall_emul.cc
/gem5/src/sim/syscall_emul.hh
/gem5/src/sim/syscall_return.hh
/gem5/src/sim/system.hh
/gem5/src/sim/ticked_object.cc
/gem5/src/sim/ticked_object.hh
/gem5/src/sim/voltage_domain.cc
/gem5/src/sim/vptr.hh
11798:e034a4566653 19-Jan-2017 Tony Gutierrez <anthony.gutierrez@amd.com>

ruby: guard usage of GPUCoalescer code in Profiler

the GPUCoalescer code is used in the ruby profiler regardless of
whether or not the coalescer code has been compiled, which can
lead to link/run time errors. here we add #ifdefs to guard the
usage of GPUCoalescer code. eventually we should refactor this
code to use probe points.

11797:f61fbb7ceb88 19-Jan-2017 Matthew Poremba <matthew.poremba@amd.com>

ruby: Check MessageBuffer space in garnet NetworkInterface

Garnet's NetworkInterface does not consider the size of MessageBuffers when
ejecting a Message from the network. Add a size check for the MessageBuffer
and only enqueue if space is available. If space is not available, the
message if placed in a queue and the credit is held. A callback from the
MessageBuffer is implemented to wake the NetworkInterface. If there are
messages in the stalled queue, they are processed first, in a FIFO manner
and if succesfully ejected, the credit is finally sent back upstream. The
maximum size of the stall queue is equal to the number of valid VNETs
with MessageBuffers attached.

11796:315e133f45df 19-Jan-2017 Matthew Poremba <matthew.poremba@amd.com>

ruby: Add occupancy stats to MessageBuffers

This patch is an updated version of /r/3297.

"The most important statistic for measuring memory hierarchy performance is
throughput, which is affected by independent variables, buffer sizing and
communication latency. It is difficult/impossible to debug performance issues
through series buffers without knowing which are the bottlenecks. For finite
buffers, this patch adds statistics for the average number of messages in the
buffer, the occupancy of the buffer slots, and number of message stalls."

11795:588a45268ce4 19-Jan-2017 Matthew Poremba <matthew.poremba@amd.com>

ruby: Check all VNETs for injection in garnet NetworkInterface

The NetworkInterface wakeup currently iterates over all VNETs and breaks the
loop if a VNET is unable to allocate a VC. This can cause a deadlock if a
lower numbered VNET is unable to allocate a VC while a higher numbered VNET
has idle VCs. This seems like a bug as Garnet 1.0 uses a while loop over an
if-statement, suggesting the break was intended for this while loop. This
patch removes the break statement, which allows up to one message to be
dequeued from a VNET and injected into the network.

11793:ef606668d247 09-Nov-2016 Brandon Potter <brandon.potter@amd.com>

style: [patch 1/22] use /r/3648/ to reorganize includes


/gem5/src/arch/alpha/faults.cc
/gem5/src/arch/alpha/freebsd/system.cc
/gem5/src/arch/alpha/idle_event.cc
/gem5/src/arch/alpha/ipr.cc
/gem5/src/arch/alpha/isa.cc
/gem5/src/arch/alpha/kernel_stats.cc
/gem5/src/arch/alpha/linux/process.cc
/gem5/src/arch/alpha/linux/system.cc
/gem5/src/arch/alpha/pagetable.cc
/gem5/src/arch/alpha/process.cc
/gem5/src/arch/alpha/remote_gdb.cc
/gem5/src/arch/alpha/stacktrace.cc
/gem5/src/arch/alpha/system.cc
/gem5/src/arch/alpha/utility.cc
/gem5/src/arch/alpha/vtophys.cc
/gem5/src/arch/arm/faults.cc
/gem5/src/arch/arm/insts/macromem.cc
/gem5/src/arch/arm/insts/mem.cc
/gem5/src/arch/arm/insts/mem64.cc
/gem5/src/arch/arm/insts/misc.cc
/gem5/src/arch/arm/insts/pseudo.cc
/gem5/src/arch/arm/insts/static_inst.cc
/gem5/src/arch/arm/interrupts.cc
/gem5/src/arch/arm/isa.cc
/gem5/src/arch/arm/kvm/base_cpu.cc
/gem5/src/arch/arm/linux/process.cc
/gem5/src/arch/arm/linux/system.cc
/gem5/src/arch/arm/miscregs.cc
/gem5/src/arch/arm/nativetrace.cc
/gem5/src/arch/arm/process.cc
/gem5/src/arch/arm/remote_gdb.cc
/gem5/src/arch/arm/stacktrace.cc
/gem5/src/arch/arm/stage2_lookup.cc
/gem5/src/arch/arm/system.cc
/gem5/src/arch/arm/tlb.cc
/gem5/src/arch/arm/utility.cc
/gem5/src/arch/arm/vtophys.cc
/gem5/src/arch/generic/decode_cache.cc
/gem5/src/arch/generic/mmapped_ipr.cc
/gem5/src/arch/generic/pseudo_inst.cc
/gem5/src/arch/mips/bare_iron/system.cc
/gem5/src/arch/mips/dsp.cc
/gem5/src/arch/mips/faults.cc
/gem5/src/arch/mips/idle_event.cc
/gem5/src/arch/mips/interrupts.cc
/gem5/src/arch/mips/isa.cc
/gem5/src/arch/mips/linux/process.cc
/gem5/src/arch/mips/linux/system.cc
/gem5/src/arch/mips/pagetable.cc
/gem5/src/arch/mips/process.cc
/gem5/src/arch/mips/remote_gdb.cc
/gem5/src/arch/mips/stacktrace.cc
/gem5/src/arch/mips/system.cc
/gem5/src/arch/mips/tlb.cc
/gem5/src/arch/mips/utility.cc
/gem5/src/arch/mips/vtophys.cc
/gem5/src/arch/power/insts/branch.cc
/gem5/src/arch/power/insts/mem.cc
/gem5/src/arch/power/insts/static_inst.cc
/gem5/src/arch/power/isa.cc
/gem5/src/arch/power/linux/process.cc
/gem5/src/arch/power/pagetable.cc
/gem5/src/arch/power/process.cc
/gem5/src/arch/power/stacktrace.cc
/gem5/src/arch/power/tlb.cc
/gem5/src/arch/power/utility.cc
/gem5/src/arch/sparc/faults.cc
/gem5/src/arch/sparc/isa.cc
/gem5/src/arch/sparc/linux/process.cc
/gem5/src/arch/sparc/nativetrace.cc
/gem5/src/arch/sparc/pagetable.cc
/gem5/src/arch/sparc/process.cc
/gem5/src/arch/sparc/remote_gdb.cc
/gem5/src/arch/sparc/solaris/process.cc
/gem5/src/arch/sparc/system.cc
/gem5/src/arch/sparc/tlb.cc
/gem5/src/arch/sparc/ua2005.cc
/gem5/src/arch/sparc/utility.cc
/gem5/src/arch/sparc/vtophys.cc
/gem5/src/arch/x86/bios/acpi.cc
/gem5/src/arch/x86/bios/e820.cc
/gem5/src/arch/x86/bios/intelmp.cc
/gem5/src/arch/x86/bios/smbios.cc
/gem5/src/arch/x86/cpuid.cc
/gem5/src/arch/x86/decoder.cc
/gem5/src/arch/x86/emulenv.cc
/gem5/src/arch/x86/faults.cc
/gem5/src/arch/x86/insts/badmicroop.cc
/gem5/src/arch/x86/insts/microfpop.cc
/gem5/src/arch/x86/insts/microldstop.cc
/gem5/src/arch/x86/insts/micromediaop.cc
/gem5/src/arch/x86/insts/microop.cc
/gem5/src/arch/x86/insts/microregop.cc
/gem5/src/arch/x86/insts/static_inst.cc
/gem5/src/arch/x86/interrupts.cc
/gem5/src/arch/x86/isa.cc
/gem5/src/arch/x86/linux/process.cc
/gem5/src/arch/x86/linux/system.cc
/gem5/src/arch/x86/nativetrace.cc
/gem5/src/arch/x86/pagetable.cc
/gem5/src/arch/x86/pagetable_walker.cc
/gem5/src/arch/x86/process.cc
/gem5/src/arch/x86/pseudo_inst.cc
/gem5/src/arch/x86/remote_gdb.cc
/gem5/src/arch/x86/stacktrace.cc
/gem5/src/arch/x86/system.cc
/gem5/src/arch/x86/tlb.cc
/gem5/src/arch/x86/types.cc
/gem5/src/arch/x86/utility.cc
/gem5/src/arch/x86/vtophys.cc
/gem5/src/base/atomicio.cc
/gem5/src/base/bigint.cc
/gem5/src/base/cp_annotate.cc
/gem5/src/base/cprintf.cc
/gem5/src/base/debug.cc
/gem5/src/base/hostinfo.cc
/gem5/src/base/inet.cc
/gem5/src/base/inifile.cc
/gem5/src/base/loader/aout_object.cc
/gem5/src/base/loader/dtb_object.cc
/gem5/src/base/loader/ecoff_object.cc
/gem5/src/base/loader/hex_file.cc
/gem5/src/base/loader/object_file.cc
/gem5/src/base/loader/raw_object.cc
/gem5/src/base/loader/symtab.cc
/gem5/src/base/match.cc
/gem5/src/base/misc.cc
/gem5/src/base/output.cc
/gem5/src/base/pollevent.cc
/gem5/src/base/random.cc
/gem5/src/base/remote_gdb.cc
/gem5/src/base/socket.cc
/gem5/src/base/statistics.cc
/gem5/src/base/stats/text.cc
/gem5/src/base/str.cc
/gem5/src/base/time.cc
/gem5/src/base/trace.cc
/gem5/src/base/vnc/vncinput.cc
/gem5/src/base/vnc/vncserver.cc
/gem5/src/cpu/activity.cc
/gem5/src/cpu/base.cc
/gem5/src/cpu/checker/cpu.cc
/gem5/src/cpu/dummy_checker.cc
/gem5/src/cpu/exetrace.cc
/gem5/src/cpu/func_unit.cc
/gem5/src/cpu/inteltrace.cc
/gem5/src/cpu/intr_control.cc
/gem5/src/cpu/kvm/base.cc
/gem5/src/cpu/kvm/perfevent.cc
/gem5/src/cpu/kvm/timer.cc
/gem5/src/cpu/kvm/vm.cc
/gem5/src/cpu/kvm/x86_cpu.cc
/gem5/src/cpu/minor/activity.cc
/gem5/src/cpu/minor/cpu.cc
/gem5/src/cpu/minor/decode.cc
/gem5/src/cpu/minor/dyn_inst.cc
/gem5/src/cpu/minor/execute.cc
/gem5/src/cpu/minor/fetch1.cc
/gem5/src/cpu/minor/fetch2.cc
/gem5/src/cpu/minor/func_unit.cc
/gem5/src/cpu/minor/lsq.cc
/gem5/src/cpu/minor/pipeline.cc
/gem5/src/cpu/minor/scoreboard.cc
/gem5/src/cpu/nativetrace.cc
/gem5/src/cpu/o3/base_dyn_inst.cc
/gem5/src/cpu/o3/checker.cc
/gem5/src/cpu/o3/cpu.cc
/gem5/src/cpu/o3/deriv.cc
/gem5/src/cpu/o3/free_list.cc
/gem5/src/cpu/o3/fu_pool.cc
/gem5/src/cpu/o3/probe/simple_trace.cc
/gem5/src/cpu/o3/regfile.cc
/gem5/src/cpu/o3/rename_map.cc
/gem5/src/cpu/o3/scoreboard.cc
/gem5/src/cpu/o3/store_set.cc
/gem5/src/cpu/o3/thread_context.cc
/gem5/src/cpu/pc_event.cc
/gem5/src/cpu/pred/2bit_local.cc
/gem5/src/cpu/pred/bi_mode.cc
/gem5/src/cpu/pred/btb.cc
/gem5/src/cpu/pred/tournament.cc
/gem5/src/cpu/profile.cc
/gem5/src/cpu/quiesce_event.cc
/gem5/src/cpu/simple/atomic.cc
/gem5/src/cpu/simple/base.cc
/gem5/src/cpu/simple/probes/simpoint.cc
/gem5/src/cpu/simple/timing.cc
/gem5/src/cpu/simple_thread.cc
/gem5/src/cpu/static_inst.cc
/gem5/src/cpu/testers/directedtest/DirectedGenerator.cc
/gem5/src/cpu/testers/directedtest/InvalidateGenerator.cc
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.cc
/gem5/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
/gem5/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc
/gem5/src/cpu/testers/memtest/memtest.cc
/gem5/src/cpu/testers/rubytest/Check.cc
/gem5/src/cpu/testers/rubytest/CheckTable.cc
/gem5/src/cpu/testers/rubytest/RubyTester.cc
/gem5/src/cpu/thread_context.cc
/gem5/src/cpu/thread_state.cc
/gem5/src/cpu/timing_expr.cc
/gem5/src/dev/alpha/backdoor.cc
/gem5/src/dev/alpha/tsunami.cc
/gem5/src/dev/alpha/tsunami_cchip.cc
/gem5/src/dev/alpha/tsunami_io.cc
/gem5/src/dev/arm/a9scu.cc
/gem5/src/dev/arm/amba_device.cc
/gem5/src/dev/arm/amba_fake.cc
/gem5/src/dev/arm/energy_ctrl.cc
/gem5/src/dev/arm/gic_pl390.cc
/gem5/src/dev/arm/hdlcd.cc
/gem5/src/dev/arm/kmi.cc
/gem5/src/dev/arm/pl011.cc
/gem5/src/dev/arm/pl111.cc
/gem5/src/dev/arm/realview.cc
/gem5/src/dev/arm/rtc_pl031.cc
/gem5/src/dev/arm/timer_cpulocal.cc
/gem5/src/dev/arm/timer_sp804.cc
/gem5/src/dev/arm/vgic.cc
/gem5/src/dev/baddev.cc
/gem5/src/dev/intel_8254_timer.cc
/gem5/src/dev/io_device.cc
/gem5/src/dev/isa_fake.cc
/gem5/src/dev/mc146818.cc
/gem5/src/dev/mips/malta.cc
/gem5/src/dev/mips/malta_cchip.cc
/gem5/src/dev/mips/malta_io.cc
/gem5/src/dev/pci/device.cc
/gem5/src/dev/pci/host.cc
/gem5/src/dev/platform.cc
/gem5/src/dev/ps2.cc
/gem5/src/dev/ps2.hh
/gem5/src/dev/sparc/dtod.cc
/gem5/src/dev/sparc/iob.cc
/gem5/src/dev/sparc/mm_disk.cc
/gem5/src/dev/sparc/t1000.cc
/gem5/src/dev/uart.cc
/gem5/src/dev/uart8250.cc
/gem5/src/dev/virtio/base.cc
/gem5/src/dev/virtio/block.cc
/gem5/src/dev/virtio/console.cc
/gem5/src/dev/virtio/fs9p.cc
/gem5/src/dev/virtio/pci.cc
/gem5/src/dev/x86/cmos.cc
/gem5/src/dev/x86/i8042.cc
/gem5/src/dev/x86/i82094aa.cc
/gem5/src/dev/x86/i8237.cc
/gem5/src/dev/x86/i8254.cc
/gem5/src/dev/x86/i8259.cc
/gem5/src/dev/x86/pc.cc
/gem5/src/dev/x86/south_bridge.cc
/gem5/src/dev/x86/speaker.cc
/gem5/src/kern/linux/linux.cc
/gem5/src/kern/linux/printk.cc
/gem5/src/kern/operatingsystem.cc
/gem5/src/kern/system_events.cc
/gem5/src/mem/abstract_mem.cc
/gem5/src/mem/bridge.cc
/gem5/src/mem/cache/prefetch/base.cc
/gem5/src/mem/cache/prefetch/queued.cc
/gem5/src/mem/cache/prefetch/stride.cc
/gem5/src/mem/coherent_xbar.cc
/gem5/src/mem/comm_monitor.cc
/gem5/src/mem/dram_ctrl.cc
/gem5/src/mem/drampower.cc
/gem5/src/mem/dramsim2.cc
/gem5/src/mem/dramsim2_wrapper.cc
/gem5/src/mem/external_master.cc
/gem5/src/mem/external_slave.cc
/gem5/src/mem/fs_translating_port_proxy.cc
/gem5/src/mem/hmc_controller.cc
/gem5/src/mem/mem_checker.cc
/gem5/src/mem/mem_checker_monitor.cc
/gem5/src/mem/noncoherent_xbar.cc
/gem5/src/mem/packet.cc
/gem5/src/mem/packet_queue.cc
/gem5/src/mem/page_table.cc
/gem5/src/mem/physical.cc
/gem5/src/mem/port.cc
/gem5/src/mem/port_proxy.cc
/gem5/src/mem/probes/base.cc
common/Histogram.cc
common/NetDest.cc
common/SubBlock.cc
filters/BlockBloomFilter.cc
filters/BulkBloomFilter.cc
filters/H3BloomFilter.cc
filters/LSB_CountingBloomFilter.cc
filters/MultiBitSelBloomFilter.cc
filters/MultiGrainBloomFilter.cc
filters/NonCountingBloomFilter.cc
network/MessageBuffer.cc
network/Network.cc
network/Topology.cc
network/simple/PerfectSwitch.cc
network/simple/PerfectSwitch.hh
network/simple/SimpleNetwork.cc
network/simple/Switch.cc
network/simple/Throttle.cc
profiler/AccessTraceForAddress.cc
profiler/AddressProfiler.cc
profiler/StoreTrace.cc
slicc_interface/AbstractController.cc
slicc_interface/AbstractController.hh
slicc_interface/RubyRequest.cc
structures/BankedArray.cc
structures/CacheMemory.cc
structures/DirectoryMemory.cc
structures/LRUPolicy.cc
structures/Prefetcher.cc
structures/PseudoLRUPolicy.cc
structures/WireBuffer.cc
system/CacheRecorder.cc
system/DMASequencer.cc
system/RubyPort.cc
system/Sequencer.cc
/gem5/src/mem/se_translating_port_proxy.cc
/gem5/src/mem/serial_link.cc
/gem5/src/mem/simple_mem.cc
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/mem/snoop_filter.cc
/gem5/src/mem/tport.cc
/gem5/src/mem/xbar.cc
/gem5/src/proto/protoio.cc
/gem5/src/python/swig/pyevent.cc
/gem5/src/python/swig/pyevent.hh
/gem5/src/python/swig/pyobject.cc
/gem5/src/sim/arguments.cc
/gem5/src/sim/backtrace_glibc.cc
/gem5/src/sim/clock_domain.cc
/gem5/src/sim/core.cc
/gem5/src/sim/cxx_manager.cc
/gem5/src/sim/debug.cc
/gem5/src/sim/dvfs_handler.cc
/gem5/src/sim/faults.cc
/gem5/src/sim/init.cc
/gem5/src/sim/probe/probe.cc
/gem5/src/sim/process.cc
/gem5/src/sim/pseudo_inst.cc
/gem5/src/sim/py_interact.cc
/gem5/src/sim/root.cc
/gem5/src/sim/serialize.cc
/gem5/src/sim/sim_events.cc
/gem5/src/sim/sim_object.cc
/gem5/src/sim/simulate.cc
/gem5/src/sim/stat_control.cc
/gem5/src/sim/stat_control.hh
/gem5/src/sim/sub_system.cc
/gem5/src/sim/syscall_emul.cc
/gem5/src/sim/system.cc
/gem5/src/sim/voltage_domain.cc
/gem5/src/unittest/circlebuf.cc
/gem5/src/unittest/unittest.cc
11779:25dd0fd23474 20-Dec-2016 Joel Hestness <jthestness@gmail.com>

ruby: Make MessageBuffers actually finite sized

When Ruby controllers stall messages in MessageBuffers, the buffer moves those
messages off the priority heap and into a per-address stall map. When buffers
are finite-sized, the test areNSlotsAvailable() only checks the size of the
priority heap, but ignores the stall map, so the map is allowed to grow
unbounded if the controller stalls numerous messages. This patch fixes the
problem by tracking the stall map size and testing the total number of messages
in the buffer appropriately.

11778:dccdf4e12a0b 20-Dec-2016 Tony Gutierrez <anthony.gutierrez@amd.com>

ruby: fix typo in DMASequencer::ackCallback()

11777:ca38721228f3 20-Dec-2016 Tony Gutierrez <anthony.gutierrez@amd.com>

ruby: fix issue with unused var in DMASequencer

the iterator declared in DMASequencer::ackCallback() is only used in an
assert, this causes clang to fail when building fast. here we move
the find call on the request table directly into the assert.

11762:29d401db3746 15-Dec-2016 Jieming Yin <jieming.yin@amd.com>

ruby: Detect garnet network-level deadlock.

This patch detects garnet network deadlock by monitoring
network interfaces. If a network interface continuously
fails to allocate virtual channels for a message, a
possible deadlock is detected.

11755:81db27b8869a 05-Dec-2016 Andreas Hansson <andreas.hansson@arm.com>

ruby: Remove RubyMemoryControl and associated files

This patch removes the deprecated RubyMemoryControl. The DRAMCtrl
module should be used instead.

11732:e15e445c21a6 02-Dec-2016 Matthew Poremba <matthew.poremba@amd.com>

ruby: Fix overflow reported by ASAN in MessageBuffer.

In MessageBuffer the m_not_avail_count member is incremented but not used.
This causes an overflow reported by ASAN. This patch changes from an int to
Stats::Scalar, since the count is useful in debugging finite MessageBuffers.

11715:31b2c4b52047 21-Nov-2016 Jieming Yin <jieming.yin@amd.com>

ruby: Fix potential bugs in garnet2.0

1. Delete unused variable from struct LinkEntry
2. Correct GarnetExtLink and GarnetIntLink inheritance

11712:70052ef97ce1 21-Nov-2016 Tony Gutierrez <anthony.gutierrez@amd.com>

ruby: add default ctor for MachineID type

not all uses of MachineID initialize its fields, so here we add a default
ctor.

11702:0bf388858d1e 26-Oct-2016 Michael LeBeane <michael.lebeane@amd.com>

ruby: Allow multiple outstanding DMA requests
DMA sequencers and protocols can currently only issue one DMA access at
a time. This patch implements the necessary functionality to support
multiple outstanding DMA requests in Ruby.

11689:9d19bb965564 26-Oct-2016 Tony Gutierrez <anthony.gutierrez@amd.com>

ruby: make a RequestDesc class instead of std::pair

the RequestDesc was previously implemented as a std::pair, which made
the implementation overly complex and error prone. here we encapsulate the
packet, primary, and secondary types all in a single data structure with
all members properly intialized in a ctor

11667:ebf2acd02fc5 06-Oct-2016 Tushar Krishna <tushar@ece.gatech.edu>

ruby: Add M5_VAR_USED before variables used only inside assert in garnet2.0.
This removes errors when building gem5.fast

11666:10d59d546ea2 06-Oct-2016 Tushar Krishna <tushar@ece.gatech.edu>

ruby: garnet2.0
Revamped version of garnet with more optimized single-cycle routers,
more configurability, and cleaner code.

11665:db895719c482 06-Oct-2016 Tushar Krishna <tushar@ece.gatech.edu>

ruby: remove the original garnet code.
Only garnet2.0 will be supported henceforth.


network/garnet/BaseGarnetNetwork.cc
network/garnet/BaseGarnetNetwork.hh
network/garnet/BaseGarnetNetwork.py
network/garnet/NetworkHeader.hh
network/garnet/SConscript
network/garnet/fixed-pipeline/CreditLink_d.hh
network/garnet/fixed-pipeline/GarnetLink_d.cc
network/garnet/fixed-pipeline/GarnetLink_d.hh
network/garnet/fixed-pipeline/GarnetLink_d.py
network/garnet/fixed-pipeline/GarnetNetwork_d.cc
network/garnet/fixed-pipeline/GarnetNetwork_d.hh
network/garnet/fixed-pipeline/GarnetNetwork_d.py
network/garnet/fixed-pipeline/InputUnit_d.cc
network/garnet/fixed-pipeline/InputUnit_d.hh
network/garnet/fixed-pipeline/NetworkInterface_d.cc
network/garnet/fixed-pipeline/NetworkInterface_d.hh
network/garnet/fixed-pipeline/NetworkLink_d.cc
network/garnet/fixed-pipeline/NetworkLink_d.hh
network/garnet/fixed-pipeline/OutVcState_d.cc
network/garnet/fixed-pipeline/OutVcState_d.hh
network/garnet/fixed-pipeline/OutputUnit_d.cc
network/garnet/fixed-pipeline/OutputUnit_d.hh
network/garnet/fixed-pipeline/Router_d.cc
network/garnet/fixed-pipeline/Router_d.hh
network/garnet/fixed-pipeline/RoutingUnit_d.cc
network/garnet/fixed-pipeline/RoutingUnit_d.hh
network/garnet/fixed-pipeline/SConscript
network/garnet/fixed-pipeline/SWallocator_d.cc
network/garnet/fixed-pipeline/SWallocator_d.hh
network/garnet/fixed-pipeline/Switch_d.cc
network/garnet/fixed-pipeline/Switch_d.hh
network/garnet/fixed-pipeline/VCallocator_d.cc
network/garnet/fixed-pipeline/VCallocator_d.hh
network/garnet/fixed-pipeline/VirtualChannel_d.cc
network/garnet/fixed-pipeline/VirtualChannel_d.hh
network/garnet/fixed-pipeline/flitBuffer_d.cc
network/garnet/fixed-pipeline/flitBuffer_d.hh
network/garnet/fixed-pipeline/flit_d.cc
network/garnet/fixed-pipeline/flit_d.hh
network/garnet/flexible-pipeline/FlexibleConsumer.hh
network/garnet/flexible-pipeline/GarnetLink.cc
network/garnet/flexible-pipeline/GarnetLink.hh
network/garnet/flexible-pipeline/GarnetLink.py
network/garnet/flexible-pipeline/GarnetNetwork.cc
network/garnet/flexible-pipeline/GarnetNetwork.hh
network/garnet/flexible-pipeline/GarnetNetwork.py
network/garnet/flexible-pipeline/InVcState.cc
network/garnet/flexible-pipeline/InVcState.hh
network/garnet/flexible-pipeline/NetworkInterface.cc
network/garnet/flexible-pipeline/NetworkInterface.hh
network/garnet/flexible-pipeline/NetworkLink.cc
network/garnet/flexible-pipeline/NetworkLink.hh
network/garnet/flexible-pipeline/OutVcState.cc
network/garnet/flexible-pipeline/OutVcState.hh
network/garnet/flexible-pipeline/Router.cc
network/garnet/flexible-pipeline/Router.hh
network/garnet/flexible-pipeline/SConscript
network/garnet/flexible-pipeline/VCarbiter.cc
network/garnet/flexible-pipeline/VCarbiter.hh
network/garnet/flexible-pipeline/flit.cc
network/garnet/flexible-pipeline/flit.hh
network/garnet/flexible-pipeline/flitBuffer.cc
network/garnet/flexible-pipeline/flitBuffer.hh
11664:2365e9e396f7 06-Oct-2016 Tushar Krishna <tushar@ece.gatech.edu>

config: add port directions and per-router delay in topology.
This patch adds port direction names to the links during topology
creation, which can be used for better printed names for the links
or for users to code up their own adaptive routing algorithms.
It also adds support for every router to have an independent latency
value to support heterogeneous topologies with the subsequent
garnet2.0 patch.

11663:cf870cd20cfc 06-Oct-2016 Tushar Krishna <tushar@ece.gatech.edu>

config: make internal links in network topology unidirectional.
This patch makes the internal links within the network topology
unidirectional, thus allowing any deadlock-free routing algorithms to
be specified from the topology itself using weights.
This patch also renames Mesh.py and MeshDirCorners.py to
Mesh_XY.py and MeshDirCorners_XY.py (Mesh with XY routing).
It also adds a Mesh_westfirst.py and CrossbarGarnet.py topologies.

11660:cfa97c37117a 06-Oct-2016 Tushar Krishna <tushar@ece.gatech.edu>

ruby: rename ALPHA_Network_test protocol to Garnet_standalone.
Over the past 6 years, we realized that the protocol is essentially used
to run the garnet network in a standalone manner, and feed standard synthetic
traffic patterns through it.

11654:49cbf4bb0d36 29-Sep-2016 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: correct size for partial memory writes

Fixed AbstractController::queueMemoryWritePartial to specify the
correct size for partial memory writes.

11596:329e49c419b1 10-Aug-2016 Andreas Sandberg <andreas.sandberg@arm.com>

ruby: Implement support for functional accesses to PIO ranges

There are cases where we want to put boot ROMs on the PIO bus. Ruby
currently doesn't support functional accesses to such memories since
functional accesses are always assumed to go to physical memory. Add
the required support for routing functional accesses to the PIO bus.

Change-Id: Ia5b0fcbe87b9642bfd6ff98a55f71909d1a804e3
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Brad Beckmann <brad.beckmann@amd.com>
Reviewed-by: Michael LeBeane <michael.lebeane@amd.com>

11556:7aa1142a5730 01-Jul-2016 Matthew Poremba <Matthew.Poremba@amd.com>

ruby: Fix double statistic registration in garnet

Currently garnet will not run due to double statistic registration of new
stats in ClockedObject. This occurs because a temporary array named 'cls'
is being added as a child to garnet internal and external link SimObjects.
This patch simply renames the temporary array which prevents it from
being added as a child object and avoids the assertion that a statistic
was already registered.

Committed by Jason Lowe-Power <jason@lowepower.com>

11523:81332eb10367 06-Jun-2016 David Guillen Fandos <david.guillen@arm.com>

stats: Fixing regStats function for some SimObjects

Fixing an issue with regStats not calling the parent class method
for most SimObjects in Gem5. This causes issues if one adds new
stats in the base class (since they are never initialized properly!).

Change-Id: Iebc5aa66f58816ef4295dc8e48a357558d76a77c
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

11519:bf08fb8ccf4b 03-Jun-2016 Marco Elver <marco.elver@ed.ac.uk>

ruby: Implement SwapReq support

This implements SwapReq for Ruby memory.

A SwapReq should be treated like a write, except that the response
packet contains the overwritten data.

Note that, in particular, the conditional checking for isStore/isLoad
needs to be reversed, as a SwapReq is both.

11459:e41eca4aecbb 26-Apr-2016 Matthew Poremba <matthew.poremba@amd.com>

ruby: Rename pkt to m_pkt so it may be accessed via SLICC

Allow usage of packet class in ruby for convenience purposes. This may be
used to access members of the packet/request class (e.g., via helper
functions) and/or push protocol specific information to the packets
SenderState without needing to modify SLICC types and protocols in multiple
locations.

11448:8d94df4c9da4 15-Apr-2016 Joel Hestness <jthestness@gmail.com>

ruby: Fix block_on behavior

Ruby's controller block_on behavior aimed to block MessageBuffer requests into
SLICC controllers when a Locked_RMW was in flight. Unfortunately, this
functionality only partially works: When non-Locked_RMW memory accesses are
issued to the sequencer to an address with an in-flight Locked_RMW, the
sequencer may pass those accesses through to the controller. At the controller,
a number of incorrect activities can occur depending on the protocol. In
MOESI_hammer, for example, an intermediate IFETCH will cause an L1D to L2
transfer, which cannot be serviced, because the block_on functionality blocks
the trigger queue, resulting in a deadlock. Further, if an intermediate store
arrives (e.g. from a separate SMT thread), the sequencer allows the request
through to the controller, and the atomicity of the Locked_RMW may be broken.

To avoid these problems, disallow the Sequencer from passing any memory
accesses to the controller besides Locked_RMW_Write when a Locked_RMW is in-
flight.

11443:df24b9af42c7 13-Apr-2016 Andreas Hansson <andreas.hansson@arm.com>

misc: Fix issues flagged by gcc 6

A few warnings (and thus errors) pop up after being added to -Wall:

1. -Wmisleading-indentation

In the auto-generated code there were instances of if/else blocks that
were not indented to gcc's liking. This is addressed by adding braces.

2. -Wshift-negative-value

gcc is clever enougn to consider ~0 a negative constant, and
rightfully complains. This is addressed by using mask() which
explicitly casts to unsigned before shifting.

That is all. Porting done.

11430:bd1c6789c33f 07-Apr-2016 Andreas Sandberg <andreas.sandberg@arm.com>

Revert to 74c1e6513bd0 (sim: Thermal support for Linux)

11422:4f749e00b667 18-Nov-2014 Akash Bagdia <akash.bagdia@ARM.com>

power: Add power states to ClockedObject

Add 4 power states to the ClockedObject, provides necessary access functions
to check and update the power state. Default power state is UNDEFINED, it is
responsibility of the respective simulation model to provide the startup state
and any other logic for state change.

Add number of transition stat.
Add distribution of time spent in clock gated state.
Add power state residency stat.

Add dump call back function to allow stats update of distribution and residency
stats.

11347:faf5195f6ca7 23-Feb-2016 Andreas Hansson <andreas.hansson@arm.com>

scons: Add missing override to appease clang

Make clang happy...again.

11346:64e862d3758f 18-Feb-2016 Tony Gutierrez <anthony.gutierrez@amd.com>

ruby: move range change send from RubyPort to derived classes.

11343:e777659dcff6 17-Feb-2016 Tony Gutierrez <anthony.gutierrez@amd.com>

ruby: send address ranges from RubyPort

11341:bda2c39fd9fd 15-Feb-2016 Andreas Hansson <andreas.hansson@arm.com>

misc: Add missing overrides to appease clang

Since the last round of fixes a few new issues have snuck in. We
should consider switching the regression runs to clang.

11339:c45bfadcd51b 14-Feb-2016 Michael LeBeane <Michael.Lebeane@amd.com>

ruby: make DMASequencer inherit from RubyPort

This patch essentially rolls back 10518:30e3715c9405 to make RubyPort the
parent class of DMASequencer. It removes redundant code and restores some
features which were lost when directly inheriting from MemObject. For
example,
DMASequencer can now communicate to other devices using PIO, which is useful
for memmory-mapped communication between multiple DMADevices.

11325:67cc559d513a 06-Feb-2016 Steve Reinhardt <steve.reinhardt@amd.com>

style: eliminate explicit boolean comparisons

Result of running 'hg m5style --skip-all --fix-control -a' to get
rid of '== true' comparisons, plus trivial manual edits to get
rid of '== false'/'== False' comparisons.

Left a couple of explicit comparisons in where they didn't seem
unreasonable:
invalid boolean comparison in src/arch/mips/interrupts.cc:155
>> DPRINTF(Interrupt, "Interrupts OnCpuTimerINterrupt(tc) == true\n");<<
invalid boolean comparison in src/unittest/unittest.hh:110
>> "EXPECT_FALSE(" #expr ")", (expr) == false)<<

11321:02e930db812d 06-Feb-2016 Steve Reinhardt <steve.reinhardt@amd.com>

style: fix missing spaces in control statements

Result of running 'hg m5style --skip-all --fix-control -a'.


/gem5/src/arch/alpha/process.cc
/gem5/src/arch/arm/insts/macromem.cc
/gem5/src/arch/arm/insts/vfp.hh
/gem5/src/arch/arm/kvm/arm_cpu.cc
/gem5/src/arch/arm/linux/system.cc
/gem5/src/arch/arm/tlb.cc
/gem5/src/arch/generic/tlb.cc
/gem5/src/arch/mips/isa.cc
/gem5/src/arch/x86/bios/intelmp.cc
/gem5/src/arch/x86/cpuid.cc
/gem5/src/arch/x86/decoder.cc
/gem5/src/arch/x86/insts/microldstop.cc
/gem5/src/arch/x86/insts/microregop.cc
/gem5/src/arch/x86/insts/static_inst.cc
/gem5/src/arch/x86/insts/static_inst.hh
/gem5/src/arch/x86/nativetrace.cc
/gem5/src/arch/x86/pagetable_walker.cc
/gem5/src/arch/x86/process.cc
/gem5/src/arch/x86/types.hh
/gem5/src/base/atomicio.hh
/gem5/src/base/cp_annotate.cc
/gem5/src/base/fenv.c
/gem5/src/base/loader/elf_object.cc
/gem5/src/base/statistics.cc
/gem5/src/cpu/base.cc
/gem5/src/cpu/kvm/perfevent.cc
/gem5/src/cpu/kvm/x86_cpu.cc
/gem5/src/cpu/minor/decode.cc
/gem5/src/cpu/nativetrace.cc
/gem5/src/cpu/nativetrace.hh
/gem5/src/cpu/o3/inst_queue_impl.hh
/gem5/src/cpu/o3/rename_impl.hh
/gem5/src/cpu/pred/bpred_unit.cc
/gem5/src/cpu/simple/atomic.cc
/gem5/src/cpu/simple/base.cc
/gem5/src/cpu/simple/timing.cc
/gem5/src/dev/alpha/tsunami_cchip.cc
/gem5/src/dev/arm/flash_device.cc
/gem5/src/dev/arm/ufs_device.cc
/gem5/src/dev/intel_8254_timer.cc
/gem5/src/dev/mips/malta_cchip.cc
/gem5/src/dev/virtio/base.cc
/gem5/src/mem/bridge.cc
/gem5/src/mem/cache/prefetch/stride.cc
/gem5/src/mem/dram_ctrl.cc
/gem5/src/mem/physical.cc
/gem5/src/mem/port.cc
filters/BulkBloomFilter.cc
filters/H3BloomFilter.cc
filters/MultiBitSelBloomFilter.cc
filters/MultiGrainBloomFilter.cc
filters/NonCountingBloomFilter.cc
network/MessageBuffer.cc
network/garnet/fixed-pipeline/GarnetNetwork_d.cc
network/garnet/fixed-pipeline/NetworkInterface_d.cc
network/simple/PerfectSwitch.cc
profiler/AccessTraceForAddress.cc
slicc_interface/AbstractController.cc
structures/AbstractReplacementPolicy.cc
structures/BankedArray.cc
structures/CacheMemory.cc
structures/PseudoLRUPolicy.cc
structures/RubyMemoryControl.cc
structures/TBETable.hh
system/GPUCoalescer.cc
system/Sequencer.cc
system/VIPERCoalescer.cc
system/WeightedLRUPolicy.cc
/gem5/src/mem/serial_link.cc
/gem5/src/mem/stack_dist_calc.cc
/gem5/src/python/swig/pyobject.cc
/gem5/src/sim/backtrace_glibc.cc
/gem5/src/sim/dvfs_handler.cc
/gem5/src/sim/serialize.hh
/gem5/src/sim/syscall_emul.hh
/gem5/tests/test-progs/gpu-hello/src/gpu-hello-kernel.cl
/gem5/tests/test-progs/gpu-hello/src/gpu-hello.cpp
/gem5/tests/test-progs/mwait/mwait.c
/gem5/util/statetrace/arch/amd64/tracechild.cc
/gem5/util/statetrace/arch/arm/tracechild.cc
/gem5/util/statetrace/arch/sparc/tracechild.cc
/gem5/util/tlm/main.cc
/gem5/util/tlm/sc_mm.cc
/gem5/util/tlm/sc_port.cc
/gem5/util/tlm/sc_target.cc
11320:42ecb523c64a 06-Feb-2016 Steve Reinhardt <steve.reinhardt@amd.com>

style: remove trailing whitespace

Result of running 'hg m5style --skip-all --fix-white -a'.


/gem5/configs/common/CacheConfig.py
/gem5/configs/common/Simulation.py
/gem5/configs/example/ruby_mem_test.py
/gem5/src/arch/alpha/isa/decoder.isa
/gem5/src/arch/alpha/linux/linux.hh
/gem5/src/arch/alpha/process.cc
/gem5/src/arch/alpha/tlb.cc
/gem5/src/arch/arm/SConscript
/gem5/src/arch/arm/interrupts.cc
/gem5/src/arch/arm/isa/bitfields.isa
/gem5/src/arch/arm/isa/formats/pred.isa
/gem5/src/arch/arm/linux/linux.hh
/gem5/src/arch/arm/stacktrace.cc
/gem5/src/arch/mips/isa/decoder.isa
/gem5/src/arch/mips/linux/linux.hh
/gem5/src/arch/mips/linux/process.cc
/gem5/src/arch/mips/pagetable.hh
/gem5/src/arch/power/SConscript
/gem5/src/arch/sparc/interrupts.cc
/gem5/src/arch/sparc/linux/linux.hh
/gem5/src/arch/sparc/pagetable.hh
/gem5/src/arch/x86/cpuid.cc
/gem5/src/arch/x86/faults.cc
/gem5/src/arch/x86/insts/micromediaop.hh
/gem5/src/arch/x86/isa/insts/general_purpose/system_calls.py
/gem5/src/arch/x86/isa/insts/romutil.py
/gem5/src/arch/x86/isa/insts/simd64/integer/data_transfer/move.py
/gem5/src/arch/x86/isa/microops/base.isa
/gem5/src/arch/x86/isa/microops/mediaop.isa
/gem5/src/arch/x86/isa/microops/regop.isa
/gem5/src/arch/x86/process.cc
/gem5/src/arch/x86/process.hh
/gem5/src/base/cp_annotate.cc
/gem5/src/base/cp_annotate.hh
/gem5/src/base/cprintf.hh
/gem5/src/base/flags.hh
/gem5/src/base/inet.cc
/gem5/src/base/inet.hh
/gem5/src/base/loader/ecoff_object.cc
/gem5/src/base/loader/elf_object.cc
/gem5/src/base/statistics.cc
/gem5/src/cpu/o3/decode_impl.hh
/gem5/src/cpu/simple/timing.cc
/gem5/src/cpu/testers/directedtest/DirectedGenerator.cc
/gem5/src/cpu/testers/directedtest/DirectedGenerator.hh
/gem5/src/cpu/testers/directedtest/InvalidateGenerator.cc
/gem5/src/cpu/testers/directedtest/InvalidateGenerator.hh
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.cc
/gem5/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
/gem5/src/cpu/testers/directedtest/SeriesRequestGenerator.hh
/gem5/src/cpu/testers/networktest/networktest.cc
/gem5/src/cpu/timebuf.hh
/gem5/src/dev/mc146818.cc
/gem5/src/dev/net/i8254xGBe.cc
/gem5/src/dev/net/i8254xGBe.hh
/gem5/src/dev/net/i8254xGBe_defs.hh
/gem5/src/dev/x86/i8042.cc
/gem5/src/dev/x86/i8254.hh
/gem5/src/dev/x86/intdev.hh
/gem5/src/mem/mport.hh
network/Topology.cc
network/Topology.hh
network/fault_model/FaultModel.cc
network/fault_model/FaultModel.hh
network/fault_model/FaultModel.py
network/fault_model/SConscript
network/garnet/fixed-pipeline/GarnetLink_d.py
network/garnet/fixed-pipeline/Router_d.hh
network/garnet/flexible-pipeline/GarnetLink.py
network/garnet/flexible-pipeline/GarnetNetwork.hh
network/garnet/flexible-pipeline/Router.hh
network/simple/SimpleLink.cc
/gem5/src/mem/slicc/ast/StallAndWaitStatementAST.py
/gem5/src/mem/slicc/ast/TypeFieldEnumAST.py
/gem5/src/mem/slicc/ast/TypeFieldStateAST.py
/gem5/src/python/m5/util/__init__.py
/gem5/src/python/swig/event.i
/gem5/src/sim/Root.py
/gem5/src/sim/eventq.cc
/gem5/src/sim/eventq.hh
/gem5/src/sim/insttracer.hh
/gem5/src/sim/pseudo_inst.cc
/gem5/src/unittest/cprintftest.cc
/gem5/system/alpha/console/console.c
/gem5/tests/configs/memtest-ruby.py
/gem5/util/checkpoint-tester.py
/gem5/util/compile
/gem5/util/m5/m5.c
/gem5/util/qdo
/gem5/util/statetrace/SConstruct
11309:9be8a40026df 20-Jul-2015 David Hashe <david.hashe@amd.com>

ruby: split CPU and GPU latency stats

11308:7d8836fd043d 19-Jan-2016 Tony Gutierrez <anthony.gutierrez@amd.com>

gpu-compute: AMD's baseline GPU model


/gem5/SConstruct
/gem5/build_opts/HSAIL_X86
/gem5/build_opts/X86_MOESI_AMD_Base
/gem5/configs/common/GPUTLBConfig.py
/gem5/configs/common/GPUTLBOptions.py
/gem5/configs/example/apu_se.py
/gem5/configs/example/ruby_gpu_random_test.py
/gem5/configs/ruby/AMD_Base_Constructor.py
/gem5/configs/ruby/GPU_RfO.py
/gem5/configs/ruby/GPU_VIPER.py
/gem5/configs/ruby/GPU_VIPER_Baseline.py
/gem5/configs/ruby/GPU_VIPER_Region.py
/gem5/configs/ruby/MOESI_AMD_Base.py
/gem5/src/SConscript
/gem5/src/arch/SConscript
/gem5/src/arch/hsail/Brig.h
/gem5/src/arch/hsail/Brig_new.hpp
/gem5/src/arch/hsail/SConscript
/gem5/src/arch/hsail/SConsopts
/gem5/src/arch/hsail/gen.py
/gem5/src/arch/hsail/generic_types.cc
/gem5/src/arch/hsail/generic_types.hh
/gem5/src/arch/hsail/gpu_decoder.hh
/gem5/src/arch/hsail/gpu_types.hh
/gem5/src/arch/hsail/insts/branch.cc
/gem5/src/arch/hsail/insts/branch.hh
/gem5/src/arch/hsail/insts/decl.hh
/gem5/src/arch/hsail/insts/gpu_static_inst.cc
/gem5/src/arch/hsail/insts/gpu_static_inst.hh
/gem5/src/arch/hsail/insts/main.cc
/gem5/src/arch/hsail/insts/mem.cc
/gem5/src/arch/hsail/insts/mem.hh
/gem5/src/arch/hsail/insts/mem_impl.hh
/gem5/src/arch/hsail/insts/pseudo_inst.cc
/gem5/src/arch/hsail/operand.cc
/gem5/src/arch/hsail/operand.hh
/gem5/src/gpu-compute/GPU.py
/gem5/src/gpu-compute/LdsState.py
/gem5/src/gpu-compute/SConscript
/gem5/src/gpu-compute/X86GPUTLB.py
/gem5/src/gpu-compute/brig_object.cc
/gem5/src/gpu-compute/brig_object.hh
/gem5/src/gpu-compute/cl_driver.cc
/gem5/src/gpu-compute/cl_driver.hh
/gem5/src/gpu-compute/cl_event.hh
/gem5/src/gpu-compute/code_enums.hh
/gem5/src/gpu-compute/compute_unit.cc
/gem5/src/gpu-compute/compute_unit.hh
/gem5/src/gpu-compute/condition_register_state.cc
/gem5/src/gpu-compute/condition_register_state.hh
/gem5/src/gpu-compute/dispatcher.cc
/gem5/src/gpu-compute/dispatcher.hh
/gem5/src/gpu-compute/exec_stage.cc
/gem5/src/gpu-compute/exec_stage.hh
/gem5/src/gpu-compute/fetch_stage.cc
/gem5/src/gpu-compute/fetch_stage.hh
/gem5/src/gpu-compute/fetch_unit.cc
/gem5/src/gpu-compute/fetch_unit.hh
/gem5/src/gpu-compute/global_memory_pipeline.cc
/gem5/src/gpu-compute/global_memory_pipeline.hh
/gem5/src/gpu-compute/gpu_dyn_inst.cc
/gem5/src/gpu-compute/gpu_dyn_inst.hh
/gem5/src/gpu-compute/gpu_exec_context.cc
/gem5/src/gpu-compute/gpu_exec_context.hh
/gem5/src/gpu-compute/gpu_static_inst.cc
/gem5/src/gpu-compute/gpu_static_inst.hh
/gem5/src/gpu-compute/gpu_tlb.cc
/gem5/src/gpu-compute/gpu_tlb.hh
/gem5/src/gpu-compute/hsa_code.hh
/gem5/src/gpu-compute/hsa_kernel_info.hh
/gem5/src/gpu-compute/hsa_object.cc
/gem5/src/gpu-compute/hsa_object.hh
/gem5/src/gpu-compute/hsail_code.cc
/gem5/src/gpu-compute/hsail_code.hh
/gem5/src/gpu-compute/kernel_cfg.cc
/gem5/src/gpu-compute/kernel_cfg.hh
/gem5/src/gpu-compute/lds_state.cc
/gem5/src/gpu-compute/lds_state.hh
/gem5/src/gpu-compute/local_memory_pipeline.cc
/gem5/src/gpu-compute/local_memory_pipeline.hh
/gem5/src/gpu-compute/misc.hh
/gem5/src/gpu-compute/ndrange.hh
/gem5/src/gpu-compute/of_scheduling_policy.cc
/gem5/src/gpu-compute/of_scheduling_policy.hh
/gem5/src/gpu-compute/pool_manager.cc
/gem5/src/gpu-compute/pool_manager.hh
/gem5/src/gpu-compute/qstruct.hh
/gem5/src/gpu-compute/rr_scheduling_policy.cc
/gem5/src/gpu-compute/rr_scheduling_policy.hh
/gem5/src/gpu-compute/schedule_stage.cc
/gem5/src/gpu-compute/schedule_stage.hh
/gem5/src/gpu-compute/scheduler.cc
/gem5/src/gpu-compute/scheduler.hh
/gem5/src/gpu-compute/scheduling_policy.hh
/gem5/src/gpu-compute/scoreboard_check_stage.cc
/gem5/src/gpu-compute/scoreboard_check_stage.hh
/gem5/src/gpu-compute/shader.cc
/gem5/src/gpu-compute/shader.hh
/gem5/src/gpu-compute/simple_pool_manager.cc
/gem5/src/gpu-compute/simple_pool_manager.hh
/gem5/src/gpu-compute/tlb_coalescer.cc
/gem5/src/gpu-compute/tlb_coalescer.hh
/gem5/src/gpu-compute/vector_register_file.cc
/gem5/src/gpu-compute/vector_register_file.hh
/gem5/src/gpu-compute/vector_register_state.cc
/gem5/src/gpu-compute/vector_register_state.hh
/gem5/src/gpu-compute/wavefront.cc
/gem5/src/gpu-compute/wavefront.hh
/gem5/src/mem/protocol/GPU_RfO-SQC.sm
/gem5/src/mem/protocol/GPU_RfO-TCC.sm
/gem5/src/mem/protocol/GPU_RfO-TCCdir.sm
/gem5/src/mem/protocol/GPU_RfO-TCP.sm
/gem5/src/mem/protocol/GPU_RfO.slicc
/gem5/src/mem/protocol/GPU_VIPER-SQC.sm
/gem5/src/mem/protocol/GPU_VIPER-TCC.sm
/gem5/src/mem/protocol/GPU_VIPER-TCP.sm
/gem5/src/mem/protocol/GPU_VIPER.slicc
/gem5/src/mem/protocol/GPU_VIPER_Baseline.slicc
/gem5/src/mem/protocol/GPU_VIPER_Region-TCC.sm
/gem5/src/mem/protocol/GPU_VIPER_Region.slicc
/gem5/src/mem/protocol/MOESI_AMD_Base-CorePair.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-L3cache.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-Region-CorePair.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-Region-dir.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-Region-msg.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-RegionBuffer.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-RegionDir.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-dir.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-msg.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-probeFilter.sm
/gem5/src/mem/protocol/MOESI_AMD_Base.slicc
/gem5/src/mem/protocol/RubySlicc_ComponentMapping.sm
/gem5/src/mem/protocol/RubySlicc_Exports.sm
/gem5/src/mem/protocol/RubySlicc_Types.sm
/gem5/src/mem/protocol/SConsopts
SConscript
profiler/Profiler.cc
slicc_interface/AbstractCacheEntry.hh
slicc_interface/AbstractController.cc
slicc_interface/AbstractController.hh
slicc_interface/RubySlicc_ComponentMapping.hh
structures/CacheMemory.cc
structures/CacheMemory.hh
structures/RubyCache.py
system/GPUCoalescer.cc
system/GPUCoalescer.hh
system/GPUCoalescer.py
system/RubyPort.cc
system/RubyPort.hh
system/RubySystem.cc
system/SConscript
system/Sequencer.cc
system/Sequencer.hh
system/Sequencer.py
system/VIPERCoalescer.cc
system/VIPERCoalescer.hh
system/VIPERCoalescer.py
system/WeightedLRUPolicy.cc
system/WeightedLRUPolicy.hh
system/WeightedLRUReplacementPolicy.py
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/tests/SConscript
/gem5/tests/configs/gpu-randomtest-ruby.py
/gem5/tests/configs/gpu-ruby.py
/gem5/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/config.ini
/gem5/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/simerr
/gem5/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/simout
/gem5/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/stats.txt
/gem5/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER/config.ini
/gem5/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER/simerr
/gem5/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER/simout
/gem5/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER/stats.txt
/gem5/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER_Baseline/config.ini
/gem5/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER_Baseline/simerr
/gem5/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER_Baseline/simout
/gem5/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER_Baseline/stats.txt
/gem5/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER_Region/config.ini
/gem5/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER_Region/simerr
/gem5/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER_Region/simout
/gem5/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER_Region/stats.txt
/gem5/tests/quick/se/04.gpu/test.py
/gem5/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/config.ini
/gem5/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/simerr
/gem5/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/simout
/gem5/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/stats.txt
/gem5/tests/quick/se/60.gpu-randomtest/test.py
/gem5/tests/test-progs/gpu-hello/bin/x86/linux/gpu-hello
/gem5/tests/test-progs/gpu-hello/bin/x86/linux/gpu-hello-kernel.asm
/gem5/tests/test-progs/gpu-hello/src/gpu-hello-kernel.cl
/gem5/tests/test-progs/gpu-hello/src/gpu-hello.cpp
/gem5/util/regress
11307:bd7d06ea90f5 19-Jan-2016 Tony Gutierrez <anthony.gutierrez@amd.com>

mem: write combining for ruby protocols

This patch adds support for write-combining in ruby.

11305:78c1e4f5dfc5 20-Jul-2015 Blake Hechtman <blake.hechtman@amd.com>

mem: misc flags for AMD gpu model

This patch add support to mark memory requests/packets with attributes defined
in HSA, such as memory order and scope.

11294:a368064a2ab5 11-Jan-2016 Andreas Hansson <andreas.hansson@arm.com>

scons: Enable -Wextra by default

Make best use of the compiler, and enable -Wextra as well as
-Wall. There are a few issues that had to be resolved, but they are
all trivial.

11284:b3926db25371 31-Dec-2015 Andreas Hansson <andreas.hansson@arm.com>

mem: Make cache terminology easier to understand

This patch changes the name of a bunch of packet flags and MSHR member
functions and variables to make the coherency protocol easier to
understand. In addition the patch adds and updates lots of
descriptions, explicitly spelling out assumptions.

The following name changes are made:

* the packet memInhibit flag is renamed to cacheResponding

* the packet sharedAsserted flag is renamed to hasSharers

* the packet NeedsExclusive attribute is renamed to NeedsWritable

* the packet isSupplyExclusive is renamed responderHadWritable

* the MSHR pendingDirty is renamed to pendingModified

The cache states, Modified, Owned, Exclusive, Shared are also called
out in the cache and MSHR code to make it easier to understand.

11266:452e10b868ea 20-Jul-2015 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: more flexible ruby tester support

This patch allows the ruby random tester to use ruby ports that may only
support instr or data requests. This patch is similar to a previous changeset
(8932:1b2c17565ac8) that was unfortunately broken by subsequent changesets.
This current patch implements the support in a more straight-forward way.
Since retries are now tested when running the ruby random tester, this patch
splits up the retry and drain check behavior so that RubyPort children, such
as the GPUCoalescer, can perform those operations correctly without having to
duplicate code. Finally, the patch also includes better DPRINTFs for
debugging the tester.

11210:64c0ebeae224 20-Jul-2015 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: added stl vector of ints to be used by SLICC

11209:d5a7a4da9f63 13-Nov-2015 Tony Gutierrez <anthony.gutierrez@amd.com>

slicc: fixes for the Address to Addr changeset (11025)

misc changes now that Address has become Addr including int to address util
function

11208:fa3e56b6e0b6 13-Nov-2015 Joe Gross <joseph.gross@amd.com>

ruby: add BoolVec

The BoolVec typedef and insertion operator overload function simplify usage of
vectors of type bool

11189:4237221d3e31 06-Nov-2015 Andreas Hansson <andreas.hansson@arm.com>

misc: Appease clang static analyzer

A few minor fixes to issues identified by the clang static analyzer.

11172:9261e98e4501 14-Oct-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: profiler: provide the number of vnets through ruby system

The aim is to ultimately do away with the static function
Network::getNumberOfVirtualNetworks().

11171:60d4dfa3241a 14-Oct-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: remove unused functionalRead() function.

Not required since functional reads cannot rely on messages that are inflight.

11170:1151cfea92e3 14-Oct-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: garnet: flexible: refactor flit

11169:44b5c183c3cd 12-Oct-2015 Andreas Hansson <andreas.hansson@arm.com>

misc: Add explicit overrides and fix other clang >= 3.5 issues

This patch adds explicit overrides as this is now required when using
"-Wall" with clang >= 3.5, the latter now part of the most recent
XCode. The patch consequently removes "virtual" for those methods
where "override" is added. The latter should be enough of an
indication.

As part of this patch, a few minor issues that clang >= 3.5 complains
about are also resolved (unused methods and variables).


/gem5/src/arch/alpha/process.hh
/gem5/src/arch/alpha/system.hh
/gem5/src/arch/alpha/tlb.hh
/gem5/src/arch/arm/table_walker.hh
/gem5/src/arch/arm/tlb.hh
/gem5/src/arch/generic/tlb.hh
/gem5/src/cpu/base.hh
/gem5/src/cpu/checker/cpu.hh
/gem5/src/cpu/minor/cpu.hh
/gem5/src/cpu/minor/func_unit.cc
/gem5/src/cpu/minor/pipeline.hh
/gem5/src/cpu/o3/cpu.hh
/gem5/src/cpu/pred/bpred_unit.hh
/gem5/src/cpu/simple/atomic.hh
/gem5/src/cpu/simple/base.hh
/gem5/src/cpu/simple/timing.hh
/gem5/src/cpu/testers/traffic_gen/traffic_gen.hh
/gem5/src/dev/alpha/backdoor.hh
/gem5/src/dev/alpha/tsunami.hh
/gem5/src/dev/alpha/tsunami_cchip.hh
/gem5/src/dev/alpha/tsunami_io.hh
/gem5/src/dev/alpha/tsunami_pchip.hh
/gem5/src/dev/copy_engine.hh
/gem5/src/dev/disk_image.hh
/gem5/src/dev/dma_device.hh
/gem5/src/dev/etherlink.hh
/gem5/src/dev/ethertap.hh
/gem5/src/dev/i2cbus.hh
/gem5/src/dev/i8254xGBe.hh
/gem5/src/dev/ide_ctrl.hh
/gem5/src/dev/ide_disk.hh
/gem5/src/dev/ns_gige.hh
/gem5/src/dev/pcidev.hh
/gem5/src/dev/sinic.hh
/gem5/src/dev/uart8250.hh
/gem5/src/dev/virtio/fs9p.hh
/gem5/src/mem/abstract_mem.hh
/gem5/src/mem/cache/cache.hh
/gem5/src/mem/cache/tags/base_set_assoc.hh
/gem5/src/mem/cache/tags/fa_lru.hh
/gem5/src/mem/dram_ctrl.hh
/gem5/src/mem/dramsim2.hh
/gem5/src/mem/page_table.hh
network/garnet/fixed-pipeline/GarnetLink_d.py
network/garnet/fixed-pipeline/NetworkLink_d.cc
network/garnet/fixed-pipeline/NetworkLink_d.hh
structures/RubyMemoryControl.hh
system/DMASequencer.hh
system/RubyPort.hh
system/RubySystem.hh
/gem5/src/mem/simple_mem.hh
/gem5/src/sim/clock_domain.hh
/gem5/src/sim/process.hh
/gem5/src/sim/root.hh
/gem5/src/sim/sim_events.hh
/gem5/src/sim/system.hh
/gem5/src/sim/ticked_object.hh
/gem5/src/sim/voltage_domain.hh
11168:f98eb2da15a4 12-Oct-2015 Andreas Hansson <andreas.hansson@arm.com>

misc: Remove redundant compiler-specific defines

This patch moves away from using M5_ATTR_OVERRIDE and the m5::hashmap
(and similar) abstractions, as these are no longer needed with gcc 4.7
and clang 3.1 as minimum compiler versions.


/gem5/src/arch/alpha/isa.hh
/gem5/src/arch/alpha/kernel_stats.hh
/gem5/src/arch/alpha/pagetable.hh
/gem5/src/arch/alpha/process.hh
/gem5/src/arch/alpha/system.hh
/gem5/src/arch/alpha/tlb.hh
/gem5/src/arch/arm/isa_device.hh
/gem5/src/arch/arm/kvm/armv8_cpu.hh
/gem5/src/arch/arm/kvm/base_cpu.hh
/gem5/src/arch/arm/kvm/gic.hh
/gem5/src/arch/arm/pagetable.hh
/gem5/src/arch/arm/pmu.hh
/gem5/src/arch/arm/table_walker.hh
/gem5/src/arch/arm/tlb.hh
/gem5/src/arch/arm/types.hh
/gem5/src/arch/generic/types.hh
/gem5/src/arch/mips/interrupts.hh
/gem5/src/arch/mips/tlb.hh
/gem5/src/arch/power/tlb.hh
/gem5/src/arch/power/types.hh
/gem5/src/arch/sparc/interrupts.hh
/gem5/src/arch/sparc/isa.hh
/gem5/src/arch/sparc/system.hh
/gem5/src/arch/sparc/tlb.hh
/gem5/src/arch/x86/decoder.hh
/gem5/src/arch/x86/interrupts.hh
/gem5/src/arch/x86/isa.hh
/gem5/src/arch/x86/pagetable.hh
/gem5/src/arch/x86/regs/msr.hh
/gem5/src/arch/x86/tlb.hh
/gem5/src/arch/x86/types.hh
/gem5/src/arch/x86/utility.hh
/gem5/src/base/compiler.hh
/gem5/src/base/cp_annotate.hh
/gem5/src/base/framebuffer.hh
/gem5/src/base/hashmap.hh
/gem5/src/base/inifile.hh
/gem5/src/base/pollevent.hh
/gem5/src/base/random.hh
/gem5/src/base/trace.hh
/gem5/src/base/vnc/vncserver.hh
/gem5/src/cpu/base.hh
/gem5/src/cpu/checker/cpu.hh
/gem5/src/cpu/decode_cache.hh
/gem5/src/cpu/inst_pb_trace.hh
/gem5/src/cpu/kvm/base.hh
/gem5/src/cpu/kvm/x86_cpu.hh
/gem5/src/cpu/minor/cpu.hh
/gem5/src/cpu/minor/pipeline.hh
/gem5/src/cpu/o3/cpu.hh
/gem5/src/cpu/o3/lsq_unit.hh
/gem5/src/cpu/o3/mem_dep_unit.hh
/gem5/src/cpu/o3/thread_state.hh
/gem5/src/cpu/pred/bpred_unit.hh
/gem5/src/cpu/simple/atomic.hh
/gem5/src/cpu/simple/base.hh
/gem5/src/cpu/simple/exec_context.hh
/gem5/src/cpu/simple/probes/simpoint.hh
/gem5/src/cpu/simple/timing.hh
/gem5/src/cpu/simple_thread.hh
/gem5/src/cpu/testers/rubytest/CheckTable.cc
/gem5/src/cpu/testers/rubytest/CheckTable.hh
/gem5/src/cpu/testers/traffic_gen/traffic_gen.hh
/gem5/src/cpu/thread_state.hh
/gem5/src/dev/alpha/backdoor.hh
/gem5/src/dev/alpha/tsunami.hh
/gem5/src/dev/alpha/tsunami_cchip.hh
/gem5/src/dev/alpha/tsunami_io.hh
/gem5/src/dev/alpha/tsunami_pchip.hh
/gem5/src/dev/arm/energy_ctrl.hh
/gem5/src/dev/arm/flash_device.hh
/gem5/src/dev/arm/generic_timer.hh
/gem5/src/dev/arm/gic_pl390.hh
/gem5/src/dev/arm/gpu_nomali.hh
/gem5/src/dev/arm/hdlcd.hh
/gem5/src/dev/arm/kmi.hh
/gem5/src/dev/arm/pl011.hh
/gem5/src/dev/arm/pl111.hh
/gem5/src/dev/arm/rtc_pl031.hh
/gem5/src/dev/arm/rv_ctrl.hh
/gem5/src/dev/arm/timer_cpulocal.hh
/gem5/src/dev/arm/timer_sp804.hh
/gem5/src/dev/arm/ufs_device.hh
/gem5/src/dev/arm/vgic.hh
/gem5/src/dev/copy_engine.hh
/gem5/src/dev/copy_engine_defs.hh
/gem5/src/dev/disk_image.hh
/gem5/src/dev/dma_device.hh
/gem5/src/dev/etherlink.hh
/gem5/src/dev/ethertap.hh
/gem5/src/dev/i2cbus.hh
/gem5/src/dev/i8254xGBe.hh
/gem5/src/dev/i8254xGBe_defs.hh
/gem5/src/dev/ide_ctrl.hh
/gem5/src/dev/ide_disk.hh
/gem5/src/dev/mips/malta.hh
/gem5/src/dev/mips/malta_cchip.hh
/gem5/src/dev/mips/malta_io.hh
/gem5/src/dev/mips/malta_pchip.hh
/gem5/src/dev/multi_etherlink.hh
/gem5/src/dev/multi_iface.hh
/gem5/src/dev/ns_gige.hh
/gem5/src/dev/pcidev.hh
/gem5/src/dev/pixelpump.hh
/gem5/src/dev/sinic.hh
/gem5/src/dev/sparc/dtod.hh
/gem5/src/dev/sparc/iob.hh
/gem5/src/dev/sparc/mm_disk.hh
/gem5/src/dev/tcp_iface.hh
/gem5/src/dev/uart8250.hh
/gem5/src/dev/virtio/base.hh
/gem5/src/dev/virtio/fs9p.hh
/gem5/src/dev/x86/cmos.hh
/gem5/src/dev/x86/i8042.hh
/gem5/src/dev/x86/i82094aa.hh
/gem5/src/dev/x86/i8237.hh
/gem5/src/dev/x86/i8254.hh
/gem5/src/dev/x86/i8259.hh
/gem5/src/dev/x86/speaker.hh
/gem5/src/kern/kernel_stats.hh
/gem5/src/mem/cache/cache.hh
/gem5/src/mem/cache/mshr_queue.hh
/gem5/src/mem/cache/prefetch/stride.hh
/gem5/src/mem/cache/tags/base_set_assoc.hh
/gem5/src/mem/cache/tags/fa_lru.hh
/gem5/src/mem/coherent_xbar.hh
/gem5/src/mem/comm_monitor.hh
/gem5/src/mem/dram_ctrl.hh
/gem5/src/mem/dramsim2.hh
/gem5/src/mem/mem_checker.hh
/gem5/src/mem/multi_level_page_table.hh
/gem5/src/mem/packet_queue.hh
/gem5/src/mem/page_table.hh
/gem5/src/mem/physical.hh
/gem5/src/mem/probes/base.hh
/gem5/src/mem/probes/mem_trace.hh
/gem5/src/mem/probes/stack_dist.hh
common/Address.hh
profiler/AddressProfiler.hh
profiler/Profiler.hh
structures/CacheMemory.cc
structures/CacheMemory.hh
structures/PerfectCacheMemory.hh
structures/PersistentTable.hh
structures/RubyMemoryControl.hh
structures/TBETable.hh
system/CacheRecorder.hh
system/DMASequencer.hh
system/RubyPort.hh
system/RubySystem.hh
system/Sequencer.cc
system/Sequencer.hh
/gem5/src/mem/simple_mem.hh
/gem5/src/mem/snoop_filter.hh
/gem5/src/mem/xbar.hh
/gem5/src/sim/clock_domain.hh
/gem5/src/sim/dvfs_handler.hh
/gem5/src/sim/eventq.cc
/gem5/src/sim/eventq.hh
/gem5/src/sim/fd_entry.hh
/gem5/src/sim/process.hh
/gem5/src/sim/root.hh
/gem5/src/sim/serialize.cc
/gem5/src/sim/sim_events.hh
/gem5/src/sim/sim_object.hh
/gem5/src/sim/system.hh
/gem5/src/sim/ticked_object.hh
/gem5/src/sim/voltage_domain.hh
11145:939f3919b108 29-Sep-2015 Joel Hestness <jthestness@gmail.com>

ruby: Fix CacheMemory allocate leak

If a cache entry permission was previously set to NotPresent, but the entry was
not deleted, a following cache allocation can cause the entry to be leaked by
setting the entry pointer to a newly allocated entry. To eliminate this
possibility, check if the new entry is different from the old one, and if so,
delete the old one.

11143:d2114f5629ff 29-Sep-2015 Joel Hestness <jthestness@gmail.com>

ruby: RubyPort delete snoop requests

In RubyPort::ruby_eviction_callback, prior changes fixed a memory leak caused
by instantiating separate packets for each port that the eviction was forwarded
to. That change, however, left the instantiated request to also leak. Allocate
it on the stack to avoid the leak.

11142:c5ac64b4b020 29-Sep-2015 Joel Hestness <jthestness@gmail.com>

ruby: Fix memory leak in AbstractController

Recent changes to memory access queuing allocate requests for packets sent to
memory controllers, but did not free the requests. Delete them to avoid leaks.

11141:526e6ad9bceb 29-Sep-2015 Joel Hestness <jthestness@gmail.com>

ruby: RubyMemoryControl delete requests

Changes to the RubyMemoryControl removed the dequeue function, which deleted
MemoryNode instances. This results in leaked MemoryNode instances. Correctly
delete these instances.

11124:5d38dc2f7d66 24-Sep-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: simple network: refactor code

Drops an unused variable and marks three variables as const.

11123:a8980f67b3fc 23-Sep-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: garnet: refactor code in network links

11122:721d3e248f75 23-Sep-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: bloom filters: refactor code

11121:370488a55495 23-Sep-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: abstract controller: mark some variables as const

11119:3be6083fd774 18-Sep-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: garnet: mark some variables as const

11118:75c1e564a725 18-Sep-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: print addresses in hex
Changeset 4872dbdea907 replaced Address by Addr, but did not make changes to
print statements. So the addresses which were being printed in hex earlier
along with their line address, were now being printed in decimals. This patch
adds a function printAddress(Addr) that can be used to print the address in hex
along with the lines address. This function has been put to use in some of the
places. At other places, change has been made to print just the address in
hex.

11116:d6fb95dbf3e2 17-Sep-2015 Tony Gutierrez <anthony.gutierrez@amd.com>

ruby: update WireBuffer API to match that of MessageBuffer

this patch updates the WireBuffer API to mirror the changes in revision 11111

11113:5a2e1b1b5c43 16-Sep-2015 Joe Gross <joe.gross@amd.com>

ruby: fix message buffer init order

The recent changes to make MessageBuffers SimObjects required them to be
initialized in a particular order, which could break some protocols. Fix this
by calling initNetQueues on the external nodes of each external link in the
constructor of Network.

This patch also refactors the duplicated code for checking network allocation
and setting net queues (which are called by initNetQueues) from the simple and
garnet networks to be in Network.

11111:6da33e720481 16-Sep-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: message buffer, timer table: significant changes

This patch changes MessageBuffer and TimerTable, two structures used for
buffering messages by components in ruby. These structures would no longer
maintain pointers to clock objects. Functions in these structures have been
changed to take as input current time in Tick. Similarly, these structures
will not operate on Cycle valued latencies for different operations. The
corresponding functions would need to be provided with these latencies by
components invoking the relevant functions. These latencies should also be
in Ticks.

I felt the need for these changes while trying to speed up ruby. The ultimate
aim is to eliminate Consumer class and replace it with an EventManager object in
the MessageBuffer and TimerTable classes. This object would be used for
scheduling events. The event itself would contain information on the object and
function to be invoked.

In hindsight, it seems I should have done this while I was moving away from use
of a single global clock in the memory system. That change led to introduction
of clock objects that replaced the global clock object. It never crossed my
mind that having clock object pointers is not a good design. And now I really
don't like the fact that we have separate consumer, receiver and sender
pointers in message buffers.


/gem5/src/mem/protocol/MESI_Three_Level-L0cache.sm
/gem5/src/mem/protocol/MESI_Three_Level-L1cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-L1cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-L2cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-dir.sm
/gem5/src/mem/protocol/MESI_Two_Level-dma.sm
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MI_example-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dma.sm
/gem5/src/mem/protocol/MOESI_hammer-cache.sm
/gem5/src/mem/protocol/MOESI_hammer-dir.sm
/gem5/src/mem/protocol/MOESI_hammer-dma.sm
/gem5/src/mem/protocol/Network_test-cache.sm
/gem5/src/mem/protocol/Network_test-dir.sm
/gem5/src/mem/protocol/RubySlicc_Defines.sm
/gem5/src/mem/protocol/RubySlicc_Exports.sm
/gem5/src/mem/protocol/RubySlicc_Types.sm
network/MessageBuffer.cc
network/MessageBuffer.hh
network/MessageBuffer.py
network/garnet/fixed-pipeline/NetworkInterface_d.cc
network/garnet/flexible-pipeline/NetworkInterface.cc
network/simple/PerfectSwitch.cc
network/simple/SimpleNetwork.py
network/simple/Switch.cc
network/simple/Throttle.cc
slicc_interface/AbstractController.cc
structures/TBETable.hh
structures/TimerTable.cc
structures/TimerTable.hh
system/DMASequencer.cc
system/RubyPort.cc
system/Sequencer.cc
/gem5/src/mem/slicc/ast/EnqueueStatementAST.py
/gem5/src/mem/slicc/ast/ObjDeclAST.py
/gem5/src/mem/slicc/ast/PeekStatementAST.py
/gem5/src/mem/slicc/ast/StallAndWaitStatementAST.py
/gem5/src/mem/slicc/symbols/StateMachine.py
11110:8647458d421d 16-Sep-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: remove unused function removeRequest()

11109:bf3d0f56a6ba 16-Sep-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: sequencer: remove commented out function printProgress()

11108:6342ddf6d733 16-Sep-2015 David Hashe <david.hashe@amd.com>

ruby: rename System.{hh,cc} to RubySystem.{hh,cc}

The eventual aim of this change is to pass RubySystem pointers through to
objects generated from the SLICC protocol code.

Because some of these objects need to dereference their RubySystem pointers,
they need access to the System.hh header file.

In src/mem/ruby/SConscript, the MakeInclude function creates single-line header
files in the build directory that do nothing except include the corresponding
header file from the source tree.

However, SLICC also generates a list of header files from its symbol table, and
writes it to mem/protocol/Types.hh in the build directory. This code assumes
that the header file name is the same as the class name.

The end result of this is the many of the generated slicc files try to include
RubySystem.hh, when the file they really need is System.hh. The path of least
resistence is just to rename System.hh to RubySystem.hh.

11096:efaacec43726 14-Sep-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: topology: refactor code.

11093:8049ffff6d68 12-Sep-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: perfect switch: refactor code
Refactored the code in operateVnet(), moved partly to a new function
operateMessageBuffer(). This is required since a later patch moves to having a
wakeup event per MessageBuffer instead of one event for the entire Switch.

11092:a51ef09e3a78 12-Sep-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: simple network: store Switch* in PerfectSwitch and Throttle
There are two reasons for doing so:

a. provide a source of clock to PerfectSwitch. A follow on patch removes sender
and receiver pointers from MessageBuffer means that the object owning the
buffer should have some way of providing timing info.

b. schedule events. A follow on patch removes the consumer class. So the
PerfectSwitch needs some EventManager object to schedule events on its own.

11087:3c4bda5a2f66 05-Sep-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: call setMRU from L1 controllers, not from sequencer
Currently the sequencer calls the function setMRU that updates the replacement
policy structures with the first level caches. While functionally this is
correct, the problem is that this requires calling findTagInSet() which is an
expensive function. This patch removes the calls to setMRU from the sequencer.
All controllers should now update the replacement policy on their own.

The set and the way index for a given cache entry can be found within the
AbstractCacheEntry structure. Use these indicies to update the replacement
policy structures.

11086:672cda252689 05-Sep-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: adds set and way indices to AbstractCacheEntry

11085:f1fe63d949c0 05-Sep-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: set: reimplement using std::bitset
The current Set data structure is slow and therefore is being reimplemented
using std::bitset. A maximum limit of 64 is being set on the number of
controllers of each type. This means that for simulating a system with more
controllers of a given type, one would need to change the value of the variable
NUMBER_BITS_PER_SET

11074:2763a59c73ff 01-Sep-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: remove random seed
We no longer use the C library based random number generator: random().
Instead we use the C++ library provided rng. So setting the random seed for
the RubySystem class has no effect. Hence the variable and the corresponding
option are being dropped.

11073:a8afeb8bc3f0 01-Sep-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: directory memory: drop unused variable.

11065:37e19af67f62 30-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: specify number of vnets for each protocol
The default value for number of virtual networks is being removed. Each protocol
should now specify the value it needs.

11064:386a5200e298 30-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: network: drop member m_in_use

This member indicates whether or not a particular virtual network is in use.
Instead of having a default big value for the number of virtual networks and
then checking whether a virtual network is in use, the next patch removes the
default value and the protocol configuration file would now specify the
number of virtual networks it requires.

Additionally, the patch also refactors some of the code used for computing the
virtual channel next in the round robin order.

11063:b254723105b5 30-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: garnet: mark few functions const in BaseGarnetNetwork.hh

11061:25b53a7195f7 29-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: eliminate type uint64 and int64
These types are being replaced with uint64_t and int64_t.

11060:a1c1c3aa359b 28-Aug-2015 Andreas Sandberg <andreas.sandberg@arm.com>

ruby: Use the const serialize interface in RubySystem

The new serialization code (kudos to Tim Jones) moves all of the state
mangling in RubySystem to memWriteback. This makes it possible to use
the new const serialization interface.

This changeset moves the cache recorder cleanup from the checkpoint()
method to drainResume() to make checkpointing truly constant and
updates the checkpointing code to use the new interface.

11059:40e622551656 27-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: handle llsc accesses through CacheEntry, not CacheMemory

The sequencer takes care of llsc accesses by calling upon functions
from the CacheMemory. This is unnecessary once the required CacheEntry object
is available. Thus some of the calls to findTagInSet() are avoided.

11052:3137d34acf29 21-Aug-2015 Andreas Hansson <andreas.hansson@arm.com>

ruby: Move Rubys cache class from Cache.py to RubyCache.py

This patch serves to avoid name clashes with the classic cache. For
some reason having two 'SimObject' files with the same name creates
problems.

11049:dfb0aa3f0649 19-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: reverts to changeset: bf82f1f7b040


/gem5/configs/ruby/Ruby.py
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.hh
/gem5/src/cpu/testers/rubytest/RubyTester.hh
/gem5/src/mem/protocol/MESI_Three_Level-L0cache.sm
/gem5/src/mem/protocol/MESI_Three_Level-L1cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-L1cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-L2cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-dir.sm
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_hammer-cache.sm
/gem5/src/mem/protocol/MOESI_hammer-dir.sm
/gem5/src/mem/protocol/RubySlicc_Types.sm
common/DataBlock.hh
common/Histogram.cc
common/Histogram.hh
common/SubBlock.cc
common/SubBlock.hh
common/TypeDefines.hh
filters/H3BloomFilter.cc
filters/H3BloomFilter.hh
filters/MultiBitSelBloomFilter.cc
filters/MultiBitSelBloomFilter.hh
network/MessageBuffer.cc
network/MessageBuffer.hh
network/garnet/flexible-pipeline/NetworkInterface.cc
network/garnet/flexible-pipeline/flit.cc
network/garnet/flexible-pipeline/flit.hh
network/simple/PerfectSwitch.cc
network/simple/PerfectSwitch.hh
network/simple/SimpleNetwork.cc
network/simple/SimpleNetwork.hh
network/simple/Switch.cc
network/simple/Throttle.cc
network/simple/Throttle.hh
profiler/AccessTraceForAddress.hh
profiler/AddressProfiler.cc
profiler/AddressProfiler.hh
profiler/Profiler.cc
profiler/Profiler.hh
profiler/StoreTrace.cc
profiler/StoreTrace.hh
slicc_interface/AbstractCacheEntry.cc
slicc_interface/AbstractCacheEntry.hh
slicc_interface/AbstractController.hh
structures/AbstractReplacementPolicy.cc
structures/AbstractReplacementPolicy.hh
structures/BankedArray.cc
structures/BankedArray.hh
structures/CacheMemory.cc
structures/CacheMemory.hh
structures/DirectoryMemory.cc
structures/DirectoryMemory.hh
structures/LRUPolicy.cc
structures/LRUPolicy.hh
structures/PseudoLRUPolicy.cc
structures/PseudoLRUPolicy.hh
structures/RubyMemoryControl.cc
structures/RubyMemoryControl.hh
system/CacheRecorder.cc
system/CacheRecorder.hh
system/RubySystem.py
system/Sequencer.cc
system/System.cc
system/System.hh
/gem5/src/mem/slicc/ast/EnumDeclAST.py
/gem5/src/mem/slicc/ast/FormalParamAST.py
/gem5/src/mem/slicc/ast/FuncCallExprAST.py
/gem5/src/mem/slicc/ast/FuncDeclAST.py
/gem5/src/mem/slicc/ast/InPortDeclAST.py
/gem5/src/mem/slicc/ast/MethodCallExprAST.py
/gem5/src/mem/slicc/ast/StateDeclAST.py
/gem5/src/mem/slicc/parser.py
/gem5/src/mem/slicc/symbols/Func.py
/gem5/src/mem/slicc/symbols/StateMachine.py
11047:dcf729f0bbfa 14-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: simple network: refactor code

Drops an unused variable and marks three variables as const.

11046:0cd13910b063 14-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: profiler: provide the number of vnets through ruby system

The aim is to ultimately do away with the static function
Network::getNumberOfVirtualNetworks().

11045:0bffd44521f5 14-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: directory memory: drop unused variable.

11043:d22f7d7dfd5c 14-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: garnet: flexible: refactor flit

11042:d34a75cb3646 14-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: DataBlock: adds a comment

11041:d3bae341e151 14-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: remove random seed

We no longer use the C library based random number generator: random().
Instead we use the C++ library provided rng. So setting the random seed for
the RubySystem class has no effect. Hence the variable and the corresponding
option are being dropped.

11040:ec668f8466eb 14-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: SubBlock: refactor code

11039:fe230bcf3f38 14-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: cache recorder: move check on block size to RubySystem.

11038:6d709f3c4c09 14-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: abstract controller: mark some variables as const

11037:91d6a2d95cf8 14-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: simple network: store Switch* in PerfectSwitch and Throttle

11036:3de670f298b1 14-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: remove unused functionalRead() function.

11035:690ecdba9324 14-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: perfect switch: refactor code

Refactored the code in operateVnet(), moved partly to a new function
operateMessageBuffer().

11034:a89984ca7d15 14-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: cache memory: drop {try,test}CacheAccess functions

11033:9a0022457323 14-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: call setMRU from L1 controllers, not from sequencer
Currently the sequencer calls the function setMRU that updates the replacement
policy structures with the first level caches. While functionally this is
correct, the problem is that this requires calling findTagInSet() which is an
expensive function. This patch removes the calls to setMRU from the sequencer.
All controllers should now update the replacement policy on their own.

The set and the way index for a given cache entry can be found within the
AbstractCacheEntry structure. Use these indicies to update the replacement
policy structures.

11032:dec9cb2c5cde 14-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: adds set and way indices to AbstractCacheEntry

11031:3815437cb231 14-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: eliminate type uint64 and int64

These types are being replaced with uint64_t and int64_t.

11030:17240f381d6a 14-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: slicc: use default argument value
Before this patch, while one could declare / define a function with default
argument values, but the actual function call would require one to specify
all the arguments. This patch changes the check for function arguments.
Now a function call needs to specify arguments that are at least as much as
those with default values and at most the total number of arguments taken
as input by the function.

11027:bf82f1f7b040 14-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: handle llsc accesses through CacheEntry, not CacheMemory

The sequencer takes care of llsc accesses by calling upon functions
from the CacheMemory. This is unnecessary once the required CacheEntry object
is available. Thus some of the calls to findTagInSet() are avoided.

11025:4872dbdea907 14-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: replace Address by Addr
This patch eliminates the type Address defined by the ruby memory system.
This memory system would now use the type Addr that is in use by the
rest of the system.


/gem5/src/cpu/testers/rubytest/Check.cc
/gem5/src/cpu/testers/rubytest/Check.hh
/gem5/src/cpu/testers/rubytest/CheckTable.cc
/gem5/src/cpu/testers/rubytest/CheckTable.hh
/gem5/src/cpu/testers/rubytest/RubyTester.hh
/gem5/src/mem/protocol/MESI_Three_Level-L0cache.sm
/gem5/src/mem/protocol/MESI_Three_Level-L1cache.sm
/gem5/src/mem/protocol/MESI_Three_Level-msg.sm
/gem5/src/mem/protocol/MESI_Two_Level-L1cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-L2cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-dir.sm
/gem5/src/mem/protocol/MESI_Two_Level-dma.sm
/gem5/src/mem/protocol/MESI_Two_Level-msg.sm
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MI_example-dma.sm
/gem5/src/mem/protocol/MI_example-msg.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-msg.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_token-msg.sm
/gem5/src/mem/protocol/MOESI_hammer-cache.sm
/gem5/src/mem/protocol/MOESI_hammer-dir.sm
/gem5/src/mem/protocol/MOESI_hammer-dma.sm
/gem5/src/mem/protocol/MOESI_hammer-msg.sm
/gem5/src/mem/protocol/Network_test-cache.sm
/gem5/src/mem/protocol/Network_test-dir.sm
/gem5/src/mem/protocol/Network_test-msg.sm
/gem5/src/mem/protocol/RubySlicc_ComponentMapping.sm
/gem5/src/mem/protocol/RubySlicc_Defines.sm
/gem5/src/mem/protocol/RubySlicc_Exports.sm
/gem5/src/mem/protocol/RubySlicc_MemControl.sm
/gem5/src/mem/protocol/RubySlicc_Types.sm
/gem5/src/mem/protocol/RubySlicc_Util.sm
common/Address.cc
common/Address.hh
common/SubBlock.cc
common/SubBlock.hh
common/TypeDefines.hh
filters/AbstractBloomFilter.hh
filters/BlockBloomFilter.cc
filters/BlockBloomFilter.hh
filters/BulkBloomFilter.cc
filters/BulkBloomFilter.hh
filters/GenericBloomFilter.cc
filters/GenericBloomFilter.hh
filters/H3BloomFilter.cc
filters/H3BloomFilter.hh
filters/LSB_CountingBloomFilter.cc
filters/LSB_CountingBloomFilter.hh
filters/MultiBitSelBloomFilter.cc
filters/MultiBitSelBloomFilter.hh
filters/MultiGrainBloomFilter.cc
filters/MultiGrainBloomFilter.hh
filters/NonCountingBloomFilter.cc
filters/NonCountingBloomFilter.hh
network/MessageBuffer.cc
network/MessageBuffer.hh
profiler/AccessTraceForAddress.hh
profiler/AddressProfiler.cc
profiler/AddressProfiler.hh
profiler/StoreTrace.cc
profiler/StoreTrace.hh
slicc_interface/AbstractCacheEntry.cc
slicc_interface/AbstractCacheEntry.hh
slicc_interface/AbstractController.cc
slicc_interface/AbstractController.hh
slicc_interface/RubyRequest.cc
slicc_interface/RubyRequest.hh
slicc_interface/RubySlicc_ComponentMapping.hh
slicc_interface/RubySlicc_Util.hh
structures/CacheMemory.cc
structures/CacheMemory.hh
structures/DirectoryMemory.cc
structures/DirectoryMemory.hh
structures/MemoryNode.hh
structures/PerfectCacheMemory.hh
structures/PersistentTable.cc
structures/PersistentTable.hh
structures/Prefetcher.cc
structures/Prefetcher.hh
structures/RubyMemoryControl.cc
structures/RubyMemoryControl.hh
structures/TBETable.hh
structures/TimerTable.cc
structures/TimerTable.hh
system/CacheRecorder.cc
system/CacheRecorder.hh
system/DMASequencer.cc
system/DMASequencer.hh
system/RubyPort.cc
system/RubyPort.hh
system/Sequencer.cc
system/Sequencer.hh
system/System.cc
/gem5/src/mem/slicc/ast/ActionDeclAST.py
/gem5/src/mem/slicc/ast/InPortDeclAST.py
/gem5/src/mem/slicc/ast/StallAndWaitStatementAST.py
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/mem/slicc/symbols/Type.py
11024:bc179fa0b91b 14-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: rename variables Addr to addr

Avoid clash between type Addr and variable name Addr.

11021:e8a6637afa4c 14-Aug-2015 Joel Hestness <jthestness@gmail.com>

ruby: Expose MessageBuffers as SimObjects

Expose MessageBuffers from SLICC controllers as SimObjects that can be
manipulated in Python. This patch has numerous benefits:
1) First and foremost, it exposes MessageBuffers as SimObjects that can be
manipulated in Python code. This allows parameters to be set and checked in
Python code to avoid obfuscating parameters within protocol files. Further, now
as SimObjects, MessageBuffer parameters are printed to config output files as a
way to track parameters across simulations (e.g. buffer sizes)

2) Cleans up special-case code for responseFromMemory buffers, and aligns their
instantiation and use with mandatoryQueue buffers. These two special buffers
are the only MessageBuffers that are exposed to components outside of SLICC
controllers, and they're both slave ends of these buffers. They should be
exposed outside of SLICC in the same way, and this patch does it.

3) Distinguishes buffer-specific parameters from buffer-to-network parameters.
Specifically, buffer size, randomization, ordering, recycle latency, and ports
are all specific to a MessageBuffer, while the virtual network ID and type are
intrinsics of how the buffer is connected to network ports. The former are
specified in the Python object, while the latter are specified in the
controller *.sm files. Unlike buffer-specific parameters, which may need to
change depending on the simulated system structure, buffer-to-network
parameters can be specified statically for most or all different simulated
systems.

11020:882ce080c9f7 14-Aug-2015 Joel Hestness <jthestness@gmail.com>

ruby: Change PerfectCacheMemory::lookup to return pointer

CacheMemory and DirectoryMemory lookup functions return pointers to entries
stored in the memory. Bring PerfectCacheMemory in line with this convention,
and clean up SLICC code generation that was in place solely to handle
references like that which was returned by PerfectCacheMemory::lookup.

11019:fc1e41e88fd3 14-Aug-2015 Joel Hestness <jthestness@gmail.com>

ruby: Remove the RubyCache/CacheMemory latency

The RubyCache (CacheMemory) latency parameter is only used for top-level caches
instantiated for Ruby coherence protocols. However, the top-level cache hit
latency is assessed by the Sequencer as accesses flow through to the cache
hierarchy. Further, protocol state machines should be enforcing these cache hit
latencies, but RubyCaches do not expose their latency to any existng state
machines through the SLICC/C++ interface. Thus, the RubyCache latency parameter
is superfluous for all caches. This is confusing for users.

As a step toward pushing L0/L1 cache hit latency into the top-level cache
controllers, move their latencies out of the RubyCache declarations and over to
their Sequencers. Eventually, these Sequencer parameters should be exposed as
parameters to the top-level cache controllers, which should assess the latency.
NOTE: Assessing these latencies in the cache controllers will require modifying
each to eliminate instantaneous Ruby hit callbacks in transitions that finish
accesses, which is likely a large undertaking.

11005:e7f403b6b76f 07-Aug-2015 Andreas Sandberg <andreas.sandberg@arm.com>

base: Declare a type for context IDs

Context IDs used to be declared as ad hoc (usually as int). This
changeset introduces a typedef for ContextIDs and a constant for
invalid context IDs.

10991:72781d410e48 04-Aug-2015 Timothy Jones <timothy.jones@cl.cam.ac.uk>

uby: Fix checkpointing and restore

There are 2 problems with the existing checkpoint and restore code in ruby.
The first is that when the event queue is altered by ruby during serialization,
some events that are currently scheduled cannot be found (e.g. the event to
stop simulation that always lives on the queue), causing a panic.
The second is that ruby is sometimes serialized after the memory system,
meaning that the dirty data in its cache is flushed back to memory too late
and so isn't included in the checkpoint.

These are fixed by implementing memory writeback in ruby, using the same
technique of hijacking the event queue, but first descheduling all events that
are currently on it. They are saved, along with their scheduled time, so that
the event queue can be faithfully reconstructed after writeback has finished.
Events with the AutoDelete flag set will delete themselves when they
are descheduled, causing an error when attempting to schedule them again.
This is fixed by simply not recording them when taking them off the queue.

Writeback is still implemented using flushing, so the cache recorder object,
that is created to generate the trace and manage flushing, is kept
around and used during serialization to write the trace to disk.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>

10987:a618349a7953 01-Aug-2015 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: removed invalid assert in message comparitor

It is perfectly valid to compare the same message and the greater than
operator should work correctly.

10986:4fbe4b0adb4d 20-Jul-2015 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: improved stall and wait debugging

Added dprintfs and asserts for identifying stall and wait bugs.

10983:6036e4555eda 20-Jul-2015 David Hashe <david.hashe@amd.com>

ruby: change router pipeline stages to 2

This patch changes the router pipeline stages from 4 to 2. The
canonical 4-stage router is conservative while a lower-latency router
with look ahead routing and speculative allocation is well acknowledged.

10982:a47c4db94389 20-Jul-2015 David Hashe <david.hashe@amd.com>

ruby: change advance_stage for flit_d

Sets m_stage.second to the second parameter of the function.
Then, for every place where advance_stage is called, adds
a cycle to the argument being passed.

10980:7de6f95a0817 20-Jul-2015 David Hashe <david.hashe@amd.com>

ruby: expose access permission to replacement policies

This patch adds support that allows the replacement policy to identify each
cache block's access permission. This information can be useful when making
replacement decisions.

10979:3c11859e4a81 20-Jul-2015 David Hashe <david.hashe@amd.com>

ruby: adds size and empty apis to the msg buffer stallmap

10978:436d5dde4bb7 20-Jul-2015 David Hashe <david.hashe@amd.com>

ruby: fix deadlock bug in banked array resource checks

The Ruby banked array resource checks (initiated from SLICC) did a check and
allocate at the same time. If a transition needs more than one resource, then
it might check/allocate resource #1, then fail to get resource #2. Another
transition might then try to get the same resources, but in reverse order.
Deadlock.

This patch separates resource checking and resource reservation into two
steps to avoid deadlock.

10977:9b3b9be42dd9 20-Jul-2015 David Hashe <david.hashe@amd.com>

ruby: Fix for stallAndWait bug

It was previously possible for a stalled message to be reordered after an
incomming message. This patch ensures that any stalled message stays in its
original request order.

10974:bbdf1177f250 20-Jul-2015 David Hashe <david.hashe@amd.com>

ruby: allocate a block in CacheMemory without updating LRU state

10973:4820cc8408b0 20-Jul-2015 David Hashe <david.hashe@amd.com>

ruby: speed up function used for cache walks

This patch adds a few helpful functions that allow .sm files to directly
invalidate all cache blocks using a trigger queue rather than rely on each
individual cache block to be invalidated via requests from the mandatory
queue.

10970:ea8bdb1d9f1e 20-Jul-2015 David Hashe <david.hashe@amd.com>

ruby: initialize replacement policies with their own simobjs

this is in preparation for other replacement policies that take additional
parameters.

10969:a588fceeb834 20-Jul-2015 David Hashe <david.hashe@amd.com>

ruby: give access to cache tag/data latencies from SLICC

This patch exposes the tag and data array latencies to the SLICC state machines
so that it can be used to determine the correct enqueue latency for response
messages.

10963:51f40b101a56 20-Jul-2015 David Hashe <david.hashe@amd.com>

slicc: support for multiple message types on the same buffer

This patch allows SLICC protocols to use more than one message type with a
message buffer. For example, you can declare two in ports as such:

in_port(ResponseQueue_in, ResponseMsg, responseFromDir, rank=3) { ... }
in_port(tgtResponseQueue_in, TgtResponseMsg, responseFromDir, rank=2) { ... }

10961:cf35e8b92a5c 20-Jul-2015 David Hashe <david.hashe@amd.com>

mem: Hit callback delay fix

This patch was created by Bihn Pham during his internship at AMD.

There is no need to delay hit callback response messages by a cycle because
the response latency is already incurred in the Ruby protocol. This ensures
correct timing of memory instructions.

10956:19515f842044 20-Jul-2015 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: re-added the addressToInt slicc interface function

This helper function is very useful converting address offsets to integers
that can be used for protocol specific destination mapping.

10954:255ebb0b32b4 20-Jul-2015 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: add useful dprints to sequencer

Added two data block dprints that are useful when tracking down data check
failures in the ruby random tester.

10928:afe7e137943a 24-Jul-2015 Brandon Potter <brandon.potter@amd.com>

ruby: dma sequencer: removes redundant code

10927:9689ead7b479 22-Jul-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: network: NetworkLink inherits from Consumer now.

10920:58fbfddff18d 10-Jul-2015 Brandon Potter <brandon.potter@amd.com>

ruby: replace global g_abs_controls with per-RubySystem var

This is another step in the process of removing global variables
from Ruby to enable multiple RubySystem instances in a single simulation.

The list of abstract controllers is per-RubySystem and should be
represented that way, rather than as a global.

Since this is the last remaining Ruby global variable, the
src/mem/ruby/Common/Global.* files are also removed.

10919:80069a602c83 10-Jul-2015 Brandon Potter <brandon.potter@amd.com>

ruby: replace global g_system_ptr with per-object pointers

This is another step in the process of removing global variables
from Ruby to enable multiple RubySystem instances in a single simulation.

With possibly multiple RubySystem objects, we can no longer use a global
variable to find "the" RubySystem object. Instead, each Ruby component
has to carry a pointer to the RubySystem object to which it belongs.

10918:dd3ab1f109ad 10-Jul-2015 Brandon Potter <brandon.potter@amd.com>

ruby: replace g_ruby_start with per-RubySystem m_start_cycle

This patch begins the process of removing global variables from the Ruby
source with the goal of eventually allowing users to create multiple Ruby
instances in a single simulation. Currently, users cannot do so because
several global variables and static members are referenced by the RubySystem
object in a way that assumes that there will only ever be a single RubySystem.
These need to be replaced with per-RubySystem equivalents.

This specific patch replaces the global var g_ruby_start, which is used
to calculate throughput statistics for Throttles in simple networks and
links in Garnet networks, with a RubySystem instance var m_start_cycle.

10917:c38f28fad4c3 10-Jul-2015 Brandon Potter <brandon.potter@amd.com>

ruby: remove extra whitespace and correct misspelled words

10913:38dbdeea7f1f 07-Jul-2015 Andreas Sandberg <andreas.sandberg@arm.com>

sim: Refactor and simplify the drain API

The drain() call currently passes around a DrainManager pointer, which
is now completely pointless since there is only ever one global
DrainManager in the system. It also contains vestiges from the time
when SimObjects had to keep track of their child objects that needed
draining.

This changeset moves all of the DrainState handling to the Drainable
base class and changes the drain() and drainResume() calls to reflect
this. Particularly, the drain() call has been updated to take no
parameters (the DrainManager argument isn't needed) and return a
DrainState instead of an unsigned integer (there is no point returning
anything other than 0 or 1 any more). Drainable objects should return
either DrainState::Draining (equivalent to returning 1 in the old
system) if they need more time to drain or DrainState::Drained
(equivalent to returning 0 in the old system) if they are already in a
consistent state. Returning DrainState::Running is considered an
error.

Drain done signalling is now done through the signalDrainDone() method
in the Drainable class instead of using the DrainManager directly. The
new call checks if the state of the object is DrainState::Draining
before notifying the drain manager. This means that it is safe to call
signalDrainDone() without first checking if the simulator has
requested draining. The intention here is to reduce the code needed to
implement draining in simple objects.


/gem5/src/arch/arm/table_walker.cc
/gem5/src/arch/arm/table_walker.hh
/gem5/src/arch/arm/tlb.hh
/gem5/src/cpu/kvm/base.cc
/gem5/src/cpu/kvm/base.hh
/gem5/src/cpu/minor/cpu.cc
/gem5/src/cpu/minor/cpu.hh
/gem5/src/cpu/minor/pipeline.cc
/gem5/src/cpu/minor/pipeline.hh
/gem5/src/cpu/o3/cpu.cc
/gem5/src/cpu/o3/cpu.hh
/gem5/src/cpu/simple/atomic.cc
/gem5/src/cpu/simple/atomic.hh
/gem5/src/cpu/simple/timing.cc
/gem5/src/cpu/simple/timing.hh
/gem5/src/cpu/testers/traffic_gen/traffic_gen.cc
/gem5/src/cpu/testers/traffic_gen/traffic_gen.hh
/gem5/src/dev/arm/flash_device.cc
/gem5/src/dev/arm/flash_device.hh
/gem5/src/dev/arm/ufs_device.cc
/gem5/src/dev/arm/ufs_device.hh
/gem5/src/dev/copy_engine.cc
/gem5/src/dev/copy_engine.hh
/gem5/src/dev/dma_device.cc
/gem5/src/dev/dma_device.hh
/gem5/src/dev/i8254xGBe.cc
/gem5/src/dev/i8254xGBe.hh
/gem5/src/dev/ide_disk.cc
/gem5/src/dev/ns_gige.cc
/gem5/src/dev/ns_gige.hh
/gem5/src/dev/sinic.cc
/gem5/src/dev/sinic.hh
/gem5/src/mem/cache/mshr_queue.cc
/gem5/src/mem/cache/mshr_queue.hh
/gem5/src/mem/dram_ctrl.cc
/gem5/src/mem/dram_ctrl.hh
/gem5/src/mem/dramsim2.cc
/gem5/src/mem/dramsim2.hh
/gem5/src/mem/packet_queue.cc
/gem5/src/mem/packet_queue.hh
structures/RubyMemoryControl.cc
structures/RubyMemoryControl.hh
system/DMASequencer.cc
system/DMASequencer.hh
system/RubyPort.cc
system/RubyPort.hh
system/Sequencer.cc
/gem5/src/mem/simple_mem.cc
/gem5/src/mem/simple_mem.hh
/gem5/src/mem/xbar.cc
/gem5/src/mem/xbar.hh
/gem5/src/sim/drain.cc
/gem5/src/sim/drain.hh
/gem5/src/sim/process.cc
/gem5/src/sim/process.hh
/gem5/src/sim/sim_object.cc
/gem5/src/sim/sim_object.hh
/gem5/src/sim/system.cc
/gem5/src/sim/system.hh
10912:b99a6662d7c2 07-Jul-2015 Andreas Sandberg <andreas.sandberg@arm.com>

sim: Decouple draining from the SimObject hierarchy

Draining is currently done by traversing the SimObject graph and
calling drain()/drainResume() on the SimObjects. This is not ideal
when non-SimObjects (e.g., ports) need draining since this means that
SimObjects owning those objects need to be aware of this.

This changeset moves the responsibility for finding objects that need
draining from SimObjects and the Python-side of the simulator to the
DrainManager. The DrainManager now maintains a set of all objects that
need draining. To reduce the overhead in classes owning non-SimObjects
that need draining, objects inheriting from Drainable now
automatically register with the DrainManager. If such an object is
destroyed, it is automatically unregistered. This means that drain()
and drainResume() should never be called directly on a Drainable
object.

While implementing the new functionality, the DrainManager has now
been made thread safe. In practice, this means that it takes a lock
whenever it manipulates the set of Drainable objects since SimObjects
in different threads may create Drainable objects
dynamically. Similarly, the drain counter is now an atomic_uint, which
ensures that it is manipulated correctly when objects signal that they
are done draining.

A nice side effect of these changes is that it makes the drain state
changes stricter, which the simulation scripts can exploit to avoid
redundant drains.

10910:32f3d1c454ec 07-Jul-2015 Andreas Sandberg <andreas.sandberg@arm.com>

sim: Make the drain state a global typed enum

The drain state enum is currently a part of the Drainable
interface. The same state machine will be used by the DrainManager to
identify the global state of the simulator. Make the drain state a
global typed enum to better cater for this usage scenario.

10905:a6ca6831e775 07-Jul-2015 Andreas Sandberg <andreas.sandberg@arm.com>

sim: Refactor the serialization base class

Objects that are can be serialized are supposed to inherit from the
Serializable class. This class is meant to provide a unified API for
such objects. However, so far it has mainly been used by SimObjects
due to some fundamental design limitations. This changeset redesigns
to the serialization interface to make it more generic and hide the
underlying checkpoint storage. Specifically:

* Add a set of APIs to serialize into a subsection of the current
object. Previously, objects that needed this functionality would
use ad-hoc solutions using nameOut() and section name
generation. In the new world, an object that implements the
interface has the methods serializeSection() and
unserializeSection() that serialize into a named /subsection/ of
the current object. Calling serialize() serializes an object into
the current section.

* Move the name() method from Serializable to SimObject as it is no
longer needed for serialization. The fully qualified section name
is generated by the main serialization code on the fly as objects
serialize sub-objects.

* Add a scoped ScopedCheckpointSection helper class. Some objects
need to serialize data structures, that are not deriving from
Serializable, into subsections. Previously, this was done using
nameOut() and manual section name generation. To simplify this,
this changeset introduces a ScopedCheckpointSection() helper
class. When this class is instantiated, it adds a new /subsection/
and subsequent serialization calls during the lifetime of this
helper class happen inside this section (or a subsection in case
of nested sections).

* The serialize() call is now const which prevents accidental state
manipulation during serialization. Objects that rely on modifying
state can use the serializeOld() call instead. The default
implementation simply calls serialize(). Note: The old-style calls
need to be explicitly called using the
serializeOld()/serializeSectionOld() style APIs. These are used by
default when serializing SimObjects.

* Both the input and output checkpoints now use their own named
types. This hides underlying checkpoint implementation from
objects that need checkpointing and makes it easier to change the
underlying checkpoint storage code.


/gem5/src/arch/alpha/interrupts.hh
/gem5/src/arch/alpha/isa.cc
/gem5/src/arch/alpha/isa.hh
/gem5/src/arch/alpha/kernel_stats.cc
/gem5/src/arch/alpha/kernel_stats.hh
/gem5/src/arch/alpha/pagetable.cc
/gem5/src/arch/alpha/pagetable.hh
/gem5/src/arch/alpha/process.cc
/gem5/src/arch/alpha/process.hh
/gem5/src/arch/alpha/system.cc
/gem5/src/arch/alpha/system.hh
/gem5/src/arch/alpha/tlb.cc
/gem5/src/arch/alpha/tlb.hh
/gem5/src/arch/arm/interrupts.hh
/gem5/src/arch/arm/isa.hh
/gem5/src/arch/arm/kvm/gic.cc
/gem5/src/arch/arm/kvm/gic.hh
/gem5/src/arch/arm/pagetable.hh
/gem5/src/arch/arm/pmu.cc
/gem5/src/arch/arm/pmu.hh
/gem5/src/arch/arm/tlb.cc
/gem5/src/arch/arm/tlb.hh
/gem5/src/arch/arm/types.hh
/gem5/src/arch/generic/types.hh
/gem5/src/arch/mips/interrupts.hh
/gem5/src/arch/mips/pagetable.cc
/gem5/src/arch/mips/pagetable.hh
/gem5/src/arch/mips/tlb.cc
/gem5/src/arch/mips/tlb.hh
/gem5/src/arch/power/pagetable.cc
/gem5/src/arch/power/pagetable.hh
/gem5/src/arch/power/tlb.cc
/gem5/src/arch/power/tlb.hh
/gem5/src/arch/sparc/interrupts.hh
/gem5/src/arch/sparc/isa.cc
/gem5/src/arch/sparc/isa.hh
/gem5/src/arch/sparc/pagetable.cc
/gem5/src/arch/sparc/pagetable.hh
/gem5/src/arch/sparc/system.cc
/gem5/src/arch/sparc/system.hh
/gem5/src/arch/sparc/tlb.cc
/gem5/src/arch/sparc/tlb.hh
/gem5/src/arch/x86/interrupts.cc
/gem5/src/arch/x86/interrupts.hh
/gem5/src/arch/x86/isa.cc
/gem5/src/arch/x86/isa.hh
/gem5/src/arch/x86/pagetable.cc
/gem5/src/arch/x86/pagetable.hh
/gem5/src/arch/x86/tlb.cc
/gem5/src/arch/x86/tlb.hh
/gem5/src/arch/x86/types.cc
/gem5/src/arch/x86/types.hh
/gem5/src/base/cp_annotate.cc
/gem5/src/base/cp_annotate.hh
/gem5/src/base/loader/symtab.cc
/gem5/src/base/loader/symtab.hh
/gem5/src/base/pollevent.cc
/gem5/src/base/pollevent.hh
/gem5/src/base/random.cc
/gem5/src/base/random.hh
/gem5/src/base/time.cc
/gem5/src/base/time.hh
/gem5/src/cpu/base.cc
/gem5/src/cpu/base.hh
/gem5/src/cpu/checker/cpu.cc
/gem5/src/cpu/checker/cpu.hh
/gem5/src/cpu/checker/thread_context.hh
/gem5/src/cpu/kvm/BaseKvmCPU.py
/gem5/src/cpu/kvm/base.cc
/gem5/src/cpu/kvm/base.hh
/gem5/src/cpu/kvm/x86_cpu.cc
/gem5/src/cpu/kvm/x86_cpu.hh
/gem5/src/cpu/minor/cpu.cc
/gem5/src/cpu/minor/cpu.hh
/gem5/src/cpu/o3/cpu.cc
/gem5/src/cpu/o3/cpu.hh
/gem5/src/cpu/o3/thread_state.hh
/gem5/src/cpu/simple/base.cc
/gem5/src/cpu/simple/base.hh
/gem5/src/cpu/simple_thread.cc
/gem5/src/cpu/simple_thread.hh
/gem5/src/cpu/testers/traffic_gen/traffic_gen.cc
/gem5/src/cpu/testers/traffic_gen/traffic_gen.hh
/gem5/src/cpu/thread_context.cc
/gem5/src/cpu/thread_context.hh
/gem5/src/cpu/thread_state.cc
/gem5/src/cpu/thread_state.hh
/gem5/src/dev/alpha/backdoor.cc
/gem5/src/dev/alpha/backdoor.hh
/gem5/src/dev/alpha/tsunami.cc
/gem5/src/dev/alpha/tsunami.hh
/gem5/src/dev/alpha/tsunami_cchip.cc
/gem5/src/dev/alpha/tsunami_cchip.hh
/gem5/src/dev/alpha/tsunami_io.cc
/gem5/src/dev/alpha/tsunami_io.hh
/gem5/src/dev/alpha/tsunami_pchip.cc
/gem5/src/dev/alpha/tsunami_pchip.hh
/gem5/src/dev/arm/energy_ctrl.cc
/gem5/src/dev/arm/energy_ctrl.hh
/gem5/src/dev/arm/flash_device.cc
/gem5/src/dev/arm/flash_device.hh
/gem5/src/dev/arm/generic_timer.cc
/gem5/src/dev/arm/generic_timer.hh
/gem5/src/dev/arm/gic_pl390.cc
/gem5/src/dev/arm/gic_pl390.hh
/gem5/src/dev/arm/hdlcd.cc
/gem5/src/dev/arm/hdlcd.hh
/gem5/src/dev/arm/kmi.cc
/gem5/src/dev/arm/kmi.hh
/gem5/src/dev/arm/pl011.cc
/gem5/src/dev/arm/pl011.hh
/gem5/src/dev/arm/pl111.cc
/gem5/src/dev/arm/pl111.hh
/gem5/src/dev/arm/rtc_pl031.cc
/gem5/src/dev/arm/rtc_pl031.hh
/gem5/src/dev/arm/rv_ctrl.cc
/gem5/src/dev/arm/rv_ctrl.hh
/gem5/src/dev/arm/timer_cpulocal.cc
/gem5/src/dev/arm/timer_cpulocal.hh
/gem5/src/dev/arm/timer_sp804.cc
/gem5/src/dev/arm/timer_sp804.hh
/gem5/src/dev/arm/ufs_device.cc
/gem5/src/dev/arm/ufs_device.hh
/gem5/src/dev/arm/vgic.cc
/gem5/src/dev/arm/vgic.hh
/gem5/src/dev/copy_engine.cc
/gem5/src/dev/copy_engine.hh
/gem5/src/dev/copy_engine_defs.hh
/gem5/src/dev/disk_image.cc
/gem5/src/dev/disk_image.hh
/gem5/src/dev/etherlink.cc
/gem5/src/dev/etherlink.hh
/gem5/src/dev/etherpkt.cc
/gem5/src/dev/etherpkt.hh
/gem5/src/dev/ethertap.cc
/gem5/src/dev/ethertap.hh
/gem5/src/dev/i2cbus.cc
/gem5/src/dev/i2cbus.hh
/gem5/src/dev/i8254xGBe.cc
/gem5/src/dev/i8254xGBe.hh
/gem5/src/dev/i8254xGBe_defs.hh
/gem5/src/dev/ide_ctrl.cc
/gem5/src/dev/ide_ctrl.hh
/gem5/src/dev/ide_disk.cc
/gem5/src/dev/ide_disk.hh
/gem5/src/dev/intel_8254_timer.cc
/gem5/src/dev/intel_8254_timer.hh
/gem5/src/dev/mc146818.cc
/gem5/src/dev/mc146818.hh
/gem5/src/dev/mips/malta.cc
/gem5/src/dev/mips/malta.hh
/gem5/src/dev/mips/malta_cchip.cc
/gem5/src/dev/mips/malta_cchip.hh
/gem5/src/dev/mips/malta_io.cc
/gem5/src/dev/mips/malta_io.hh
/gem5/src/dev/mips/malta_pchip.cc
/gem5/src/dev/mips/malta_pchip.hh
/gem5/src/dev/ns_gige.cc
/gem5/src/dev/ns_gige.hh
/gem5/src/dev/pcidev.cc
/gem5/src/dev/pcidev.hh
/gem5/src/dev/pktfifo.cc
/gem5/src/dev/pktfifo.hh
/gem5/src/dev/sinic.cc
/gem5/src/dev/sinic.hh
/gem5/src/dev/sparc/dtod.cc
/gem5/src/dev/sparc/dtod.hh
/gem5/src/dev/sparc/iob.cc
/gem5/src/dev/sparc/iob.hh
/gem5/src/dev/sparc/mm_disk.cc
/gem5/src/dev/sparc/mm_disk.hh
/gem5/src/dev/uart8250.cc
/gem5/src/dev/uart8250.hh
/gem5/src/dev/virtio/base.cc
/gem5/src/dev/virtio/base.hh
/gem5/src/dev/virtio/fs9p.cc
/gem5/src/dev/virtio/fs9p.hh
/gem5/src/dev/x86/cmos.cc
/gem5/src/dev/x86/cmos.hh
/gem5/src/dev/x86/i8042.cc
/gem5/src/dev/x86/i8042.hh
/gem5/src/dev/x86/i82094aa.cc
/gem5/src/dev/x86/i82094aa.hh
/gem5/src/dev/x86/i8237.cc
/gem5/src/dev/x86/i8237.hh
/gem5/src/dev/x86/i8254.cc
/gem5/src/dev/x86/i8254.hh
/gem5/src/dev/x86/i8259.cc
/gem5/src/dev/x86/i8259.hh
/gem5/src/dev/x86/speaker.cc
/gem5/src/dev/x86/speaker.hh
/gem5/src/kern/kernel_stats.cc
/gem5/src/kern/kernel_stats.hh
/gem5/src/mem/cache/cache.hh
/gem5/src/mem/cache/cache_impl.hh
/gem5/src/mem/multi_level_page_table.hh
/gem5/src/mem/multi_level_page_table_impl.hh
/gem5/src/mem/page_table.cc
/gem5/src/mem/page_table.hh
/gem5/src/mem/physical.cc
/gem5/src/mem/physical.hh
system/System.cc
system/System.hh
/gem5/src/python/m5/SimObject.py
/gem5/src/python/swig/core.i
/gem5/src/python/swig/pyobject.cc
/gem5/src/python/swig/pyobject.hh
/gem5/src/sim/clock_domain.cc
/gem5/src/sim/clock_domain.hh
/gem5/src/sim/cxx_manager.cc
/gem5/src/sim/cxx_manager.hh
/gem5/src/sim/dvfs_handler.cc
/gem5/src/sim/dvfs_handler.hh
/gem5/src/sim/eventq.cc
/gem5/src/sim/eventq.hh
/gem5/src/sim/process.cc
/gem5/src/sim/process.hh
/gem5/src/sim/root.cc
/gem5/src/sim/root.hh
/gem5/src/sim/serialize.cc
/gem5/src/sim/serialize.hh
/gem5/src/sim/sim_events.cc
/gem5/src/sim/sim_events.hh
/gem5/src/sim/sim_object.cc
/gem5/src/sim/sim_object.hh
/gem5/src/sim/system.cc
/gem5/src/sim/system.hh
/gem5/src/sim/ticked_object.cc
/gem5/src/sim/ticked_object.hh
/gem5/src/sim/voltage_domain.cc
/gem5/src/sim/voltage_domain.hh
10895:287285860dd6 04-Jul-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: drop NetworkMessage class

This patch drops the NetworkMessage class. The relevant data members and functions
have been moved to the Message class, which was the parent of NetworkMessage.

10893:f567e80c0714 04-Jul-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: remove message buffer node

This structure's only purpose was to provide a comparison function for
ordering messages in the MessageBuffer. The comparison function is now
being moved to the Message class itself. So we no longer require this
structure.

10886:fdd4a895f325 03-Jul-2015 Andreas Hansson <andreas.hansson@arm.com>

mem: Split WriteInvalidateReq into write and invalidate

WriteInvalidateReq ensures that a whole-line write does not incur the
cost of first doing a read exclusive, only to later overwrite the
data. This patch splits the existing WriteInvalidateReq into a
WriteLineReq, which is done locally, and an InvalidateReq that is sent
out throughout the memory system. The WriteLineReq re-uses the normal
WriteResp.

The change allows us to better express the difference between the
cache that is performing the write, and the ones that are merely
invalidating. As a consequence, we no longer have to rely on the
isTopLevel flag. Moreover, the actual memory in the system does not
see the intitial write, only the writeback. We were marking the
written line as dirty already, so there is really no need to also push
the write all the way to the memory.

The overall flow of the write-invalidate operation remains the same,
i.e. the operation is only carried out once the response for the
invalidate comes back. This patch adds the InvalidateResp for this
very reason.

10876:7544f29b7dfc 25-Jun-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: message: remove a data member added by mistake

I (Nilay) had mistakenly added a data member to the Message class in revision c1694b4032a6.
The data member is being removed.

10875:60eb3fef9c2d 25-Jun-2015 Jason Power <power.jg@gmail.com>

Ruby: Remove assert in RubyPort retry list logic

Remove the assert when adding a port to the RubyPort retry list.
Instead of asserting, just ignore the added port, since it's
already on the list.
Without this patch, Ruby+detailed fails for even the simplest tests

10849:30bbc9b60a8c 26-May-2015 Andreas Hansson <andreas.hansson@arm.com>

ruby: Deprecation warning for RubyMemoryControl

A step towards removing RubyMemoryControl and shift users to
DRAMCtrl. The latter is faster, more representative, very versatile,
and is integrated with power models.

10837:ecbab2522757 19-May-2015 Joel Hestness <jthestness@gmail.com>

ruby: Fix RubySystem warm-up and cool-down scope

The processes of warming up and cooling down Ruby caches are simulation-wide
processes, not just RubySystem instance-specific processes. Thus, the warm-up
and cool-down variables should be globally visible to any Ruby components
participating in either process. Make these variables static members and track
the warm-up and cool-down processes as appropriate.

This patch also has two side benefits:
1) It removes references to the RubySystem g_system_ptr, which are problematic
for allowing multiple RubySystem instances in a single simulation. Warmup and
cooldown variables being static (global) reduces the need for instance-specific
dereferences through the RubySystem.
2) From the AbstractController, it removes local RubySystem pointers, which are
used inconsistently with other uses of the RubySystem: 11 other uses reference
the RubySystem with the g_system_ptr. Only sequencers have local pointers.

10808:c1694b4032a6 29-Apr-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: set: replace long by unsigned long
UBSan complains about negative value being shifted

10783:631e736554c9 13-Apr-2015 Lena Olson <lena@cs.wisc.edu>

ruby: allow restoring from checkpoint when using DRAMCtrl

Restoring from a checkpoint with ruby + the DRAMCtrl memory model was not
working, because ruby and DRAMCtrl disagreed on the current tick during warmup.
Since there is no reason to do timing requests during warmup, use functional
requests instead.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>

10760:8f5993cfa916 23-Mar-2015 Steve Reinhardt <steve.reinhardt@amd.com>

mem: rename Locked/LOCKED to LockedRMW/LOCKED_RMW

Makes x86-style locked operations even more distinct from
LLSC operations. Using "locked" by itself should be
obviously ambiguous now.

10713:eddb533708cb 02-Mar-2015 Andreas Hansson <andreas.hansson@arm.com>

mem: Split port retry for all different packet classes

This patch fixes a long-standing isue with the port flow
control. Before this patch the retry mechanism was shared between all
different packet classes. As a result, a snoop response could get
stuck behind a request waiting for a retry, even if the send/recv
functions were split. This caused message-dependent deadlocks in
stress-test scenarios.

The patch splits the retry into one per packet (message) class. Thus,
sendTimingReq has a corresponding recvReqRetry, sendTimingResp has
recvRespRetry etc. Most of the changes to the code involve simply
clarifying what type of request a specific object was accepting.

The biggest change in functionality is in the cache downstream packet
queue, facing the memory. This queue was shared by requests and snoop
responses, and it is now split into two queues, each with their own
flow control, but the same physical MasterPort. These changes fixes
the previously seen deadlocks.


/gem5/src/arch/x86/pagetable_walker.cc
/gem5/src/arch/x86/pagetable_walker.hh
/gem5/src/cpu/kvm/base.hh
/gem5/src/cpu/minor/fetch1.cc
/gem5/src/cpu/minor/fetch1.hh
/gem5/src/cpu/minor/lsq.cc
/gem5/src/cpu/minor/lsq.hh
/gem5/src/cpu/o3/cpu.cc
/gem5/src/cpu/o3/cpu.hh
/gem5/src/cpu/o3/fetch.hh
/gem5/src/cpu/o3/fetch_impl.hh
/gem5/src/cpu/o3/lsq.hh
/gem5/src/cpu/o3/lsq_impl.hh
/gem5/src/cpu/simple/atomic.hh
/gem5/src/cpu/simple/timing.cc
/gem5/src/cpu/simple/timing.hh
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.hh
/gem5/src/cpu/testers/memtest/memtest.cc
/gem5/src/cpu/testers/memtest/memtest.hh
/gem5/src/cpu/testers/networktest/networktest.cc
/gem5/src/cpu/testers/networktest/networktest.hh
/gem5/src/cpu/testers/rubytest/RubyTester.hh
/gem5/src/cpu/testers/traffic_gen/traffic_gen.cc
/gem5/src/cpu/testers/traffic_gen/traffic_gen.hh
/gem5/src/dev/dma_device.cc
/gem5/src/dev/dma_device.hh
/gem5/src/mem/addr_mapper.cc
/gem5/src/mem/addr_mapper.hh
/gem5/src/mem/bridge.cc
/gem5/src/mem/bridge.hh
/gem5/src/mem/cache/base.cc
/gem5/src/mem/cache/base.hh
/gem5/src/mem/cache/cache.hh
/gem5/src/mem/cache/cache_impl.hh
/gem5/src/mem/coherent_xbar.cc
/gem5/src/mem/coherent_xbar.hh
/gem5/src/mem/comm_monitor.cc
/gem5/src/mem/comm_monitor.hh
/gem5/src/mem/dram_ctrl.cc
/gem5/src/mem/dram_ctrl.hh
/gem5/src/mem/dramsim2.cc
/gem5/src/mem/dramsim2.hh
/gem5/src/mem/external_slave.cc
/gem5/src/mem/mem_checker_monitor.cc
/gem5/src/mem/mem_checker_monitor.hh
/gem5/src/mem/mport.hh
/gem5/src/mem/noncoherent_xbar.cc
/gem5/src/mem/noncoherent_xbar.hh
/gem5/src/mem/packet_queue.cc
/gem5/src/mem/packet_queue.hh
/gem5/src/mem/port.cc
/gem5/src/mem/port.hh
/gem5/src/mem/qport.hh
slicc_interface/AbstractController.cc
slicc_interface/AbstractController.hh
structures/RubyMemoryControl.hh
system/DMASequencer.cc
system/DMASequencer.hh
system/RubyPort.cc
system/RubyPort.hh
/gem5/src/mem/simple_mem.cc
/gem5/src/mem/simple_mem.hh
/gem5/src/mem/tport.cc
/gem5/src/mem/tport.hh
/gem5/src/mem/xbar.cc
/gem5/src/mem/xbar.hh
/gem5/src/sim/system.hh
10706:4206946d60fe 26-Feb-2015 Jason Power <power.jg@gmail.com>

Ruby: Update backing store option to propagate through to all RubyPorts

Previously, the user would have to manually set access_backing_store=True
on all RubyPorts (Sequencers) in the config files.
Now, instead there is one global option that each RubyPort checks on
initialization.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>

10657:8bb4a9717eaa 22-Jan-2015 Andreas Hansson <andreas.hansson@arm.com>

mem: Always use SenderState for response routing in RubyPort

This patch aligns how the response routing is done in the RubyPort,
using the SenderState for both memory and I/O accesses. Before this
patch, only the I/O used the SenderState, whereas the memory accesses
relied on the src field in the packet. With this patch we shift to
using SenderState in both cases, thus not relying on the src field any
longer.

10653:e3fc6bc7f97e 22-Jan-2015 Andreas Hansson <andreas.hansson@arm.com>

mem: Clean up Request initialisation

This patch tidies up how we create and set the fields of a Request. In
essence it tries to use the constructor where possible (as opposed to
setPhys and setVirt), thus avoiding spreading the information across a
number of locations. In fact, setPhys is made private as part of this
patch, and a number of places where we callede setVirt instead uses
the appropriate constructor.

10563:755b18321206 02-Dec-2014 Andreas Hansson <andreas.hansson@arm.com>

mem: Add const getters for write packet data

This patch takes a first step in tightening up how we use the data
pointer in write packets. A const getter is added for the pointer
itself (getConstPtr), and a number of member functions are also made
const accordingly. In a range of places throughout the memory system
the new member is used.

The patch also removes the unused isReadWrite function.

10562:b99fdc295c34 02-Dec-2014 Andreas Hansson <andreas.hansson@arm.com>

mem: Remove null-check bypassing in Packet::getPtr

This patch removes the parameter that enables bypassing the null check
in the Packet::getPtr method. A number of call sites assume the value
to be non-null.

The one odd case is the RubyTester, which issues zero-sized
prefetches(!), and despite being reads they had no valid data
pointer. This is now fixed, but the size oddity remains (unless anyone
object or has any good suggestions).

Finally, in the Ruby Sequencer, appropriate checks are made for flush
packets as they have no valid data pointer.

10534:50bbc64efbb8 12-Nov-2014 Mitch Hayenga <mitch.hayenga@arm.com>

mem: Delete unused variable in Garnet NetworkLink

With recent changes OSX clang compilation fails due to an unused variable.

10525:77787650cbbc 06-Nov-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: provide a backing store
Ruby's functional accesses are not guaranteed to succeed as of now. While
this is not a problem for the protocols that are currently in the mainline
repo, it seems that coherence protocols for gpus rely on a backing store to
supply the correct data. The aim of this patch is to make this backing store
configurable i.e. it comes into play only when a particular option:
--access-backing-store is invoked.

The backing store has been there since M5 and GEMS were integrated. The only
difference is that earlier the system used to maintain the backing store and
ruby's copy was write-only. Sometime last year, we moved to data being
supplied supplied by ruby in SE mode simulations. And now we have patches on
the reviewboard, which remove ruby's copy of memory altogether and rely
completely on the system's memory to supply data. This patch adds back a
SimpleMemory member to RubySystem. This member is used only if the option:
access-backing-store is set to true. By default, the memory would not be
accessed.

10524:fff17530cef6 06-Nov-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: interface with classic memory controller
This patch is the final in the series. The whole series and this patch in
particular were written with the aim of interfacing ruby's directory controller
with the memory controller in the classic memory system. This is being done
since ruby's memory controller has not being kept up to date with the changes
going on in DRAMs. Classic's memory controller is more up to date and
supports multiple different types of DRAM. This also brings classic and
ruby ever more close. The patch also changes ruby's memory controller to
expose the same interface.


/gem5/configs/common/MemConfig.py
/gem5/configs/example/fs.py
/gem5/configs/example/ruby_direct_test.py
/gem5/configs/example/ruby_mem_test.py
/gem5/configs/example/ruby_random_test.py
/gem5/configs/example/se.py
/gem5/configs/ruby/MESI_Three_Level.py
/gem5/configs/ruby/MESI_Two_Level.py
/gem5/configs/ruby/MI_example.py
/gem5/configs/ruby/MOESI_CMP_directory.py
/gem5/configs/ruby/MOESI_CMP_token.py
/gem5/configs/ruby/MOESI_hammer.py
/gem5/configs/ruby/Ruby.py
/gem5/src/mem/protocol/MESI_Two_Level-dir.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_hammer-dir.sm
/gem5/src/mem/protocol/RubySlicc_Defines.sm
/gem5/src/mem/protocol/RubySlicc_Types.sm
SConscript
network/MessageBuffer.cc
slicc_interface/AbstractController.cc
slicc_interface/AbstractController.hh
slicc_interface/Controller.py
structures/Cache.py
structures/DirectoryMemory.py
structures/MemoryControl.cc
structures/MemoryControl.hh
structures/MemoryControl.py
structures/MemoryNode.cc
structures/MemoryNode.hh
structures/MemoryVector.hh
structures/RubyMemoryControl.cc
structures/RubyMemoryControl.hh
structures/RubyMemoryControl.py
structures/SConscript
system/RubySystem.py
system/Sequencer.py
system/System.cc
system/System.hh
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/python/swig/pyobject.cc
/gem5/tests/configs/memtest-ruby.py
/gem5/tests/configs/pc-simple-timing-ruby.py
/gem5/tests/configs/rubytest-ruby.py
/gem5/tests/configs/simple-timing-mp-ruby.py
/gem5/tests/configs/simple-timing-ruby.py
10523:5777a3e55603 06-Nov-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: remove the function functionalReadBuffers()
This function was added when I had incorrectly arrived at the conclusion
that such a function can improve the chances of a functional read succeeding.
As was later realized, this is not possible in the current setup. While the
code using this function was dropped long back, this function was not. Hence
the patch.

10522:13312d6e1caf 06-Nov-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: coherence protocols: remove data block from dirctory entry
This patch removes the data block present in the directory entry structure
of each protocol in gem5's mainline. Firstly, this is required for moving
towards common set of memory controllers for classic and ruby memory systems.
Secondly, the data block was being misused in several places. It was being
used for having free access to the physical memory instead of calling on the
memory controller.

From now on, the directory controller will not have a direct visibility into
the physical memory. The Memory Vector object now resides in the
Memory Controller class. This also means that some significant changes are
being made to the functional accesses in ruby.

10520:7740e0d97d48 06-Nov-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: remove sparse memory.
In my opinion, it creates needless complications in rest of the code.
Also, this structure hinders the move towards common set of code for
physical memory controllers.

10519:7a3ad4b09ce4 06-Nov-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: single physical memory in fs mode
Both ruby and the system used to maintain memory copies. With the changes
carried for programmed io accesses, only one single memory is required for
fs simulations. This patch sets the copy of memory that used to reside
with the system to null, so that no space is allocated, but address checks
can still be carried out. All the memory accesses now source and sink values
to the memory maintained by ruby.

10518:30e3715c9405 06-Nov-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: dma sequencer: remove RubyPort as parent class
As of now DMASequencer inherits from the RubyPort class. But the code in
RubyPort class is heavily tailored for the CPU Sequencer. There are parts of
the code that are not required at all for the DMA sequencer. Moreover, the
next patch uses the dma sequencer for carrying out memory accesses for all the
io devices. Hence, it is better to have a leaner dma sequencer.

10481:59fb5779ec6e 16-Oct-2014 Andreas Hansson <andreas.hansson@arm.com>

misc: Move AddrRangeList from port.hh to addr_range.hh

The new location seems like a better fit. The iterator typedefs are
removed in favour of using C++11 auto.

10472:399f35ed5cca 16-Oct-2014 Andreas Hansson <andreas.hansson@arm.com>

mem: Use shared_ptr for Ruby Message classes

This patch transitions the Ruby Message and its derived classes from
the ad-hoc RefCountingPtr to the c++11 shared_ptr. There are no
changes in behaviour, and the code modifications are mainly replacing
"new" with "make_shared".

The cloning of derived messages is slightly changed as they previously
relied on overriding the base-class through covariant return types.

10467:dcf27c8220ac 16-Oct-2014 Andreas Hansson <andreas.hansson@arm.com>

arch,x86,mem: Dynamically determine the ISA for Ruby store check

This patch makes the memory system ISA-agnostic by enabling the Ruby
Sequencer to dynamically determine if it has to do a store check. To
enable this check, the ISA is encoded as an enum, and the system
is able to provide the ISA to the Sequencer at run time.

10466:73b7549d979e 16-Oct-2014 Andreas Hansson <andreas.hansson@arm.com>

mem: Dynamically determine page bytes in memory components

This patch takes a step towards an ISA-agnostic memory
system by enabling the components to establish the page size after
instantiation. The swap operation in the memory is now also allowing
any granularity to avoid depending on the IntReg of the ISA.

10446:bb00790bc85c 11-Oct-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: network: garnet: add statistics for different activities
This patch adds some statistics to garnet that record the activity
of certain structures in the on-chip network. These statistics, in a later
patch, will be used for computing the energy consumed by the on-chip network.

10445:e9fe0dc3cda3 11-Oct-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: network: garnet: remove functions for computing power

10444:bbe7f8bd41ae 11-Oct-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: drop Orion network power model

Orion is being dropped from ruby. It would be replaced with DSENT
which has better models. Note that the power / energy numbers reported
after this patch has been applied are not for use.


network/garnet/fixed-pipeline/InputUnit_d.hh
network/garnet/fixed-pipeline/NetworkLink_d.hh
network/garnet/fixed-pipeline/OutputUnit_d.hh
network/garnet/fixed-pipeline/Router_d.hh
network/orion/Allocator/Arbiter.cc
network/orion/Allocator/Arbiter.hh
network/orion/Allocator/MatrixArbiter.cc
network/orion/Allocator/MatrixArbiter.hh
network/orion/Allocator/RRArbiter.cc
network/orion/Allocator/RRArbiter.hh
network/orion/Allocator/SConscript
network/orion/Allocator/SWAllocator.cc
network/orion/Allocator/SWAllocator.hh
network/orion/Allocator/VCAllocator.cc
network/orion/Allocator/VCAllocator.hh
network/orion/Buffer/AmpUnit.cc
network/orion/Buffer/AmpUnit.hh
network/orion/Buffer/BitlineUnit.cc
network/orion/Buffer/BitlineUnit.hh
network/orion/Buffer/Buffer.cc
network/orion/Buffer/Buffer.hh
network/orion/Buffer/DecoderUnit.cc
network/orion/Buffer/DecoderUnit.hh
network/orion/Buffer/MemUnit.cc
network/orion/Buffer/MemUnit.hh
network/orion/Buffer/OutdrvUnit.cc
network/orion/Buffer/OutdrvUnit.hh
network/orion/Buffer/PrechargeUnit.cc
network/orion/Buffer/PrechargeUnit.hh
network/orion/Buffer/Register.cc
network/orion/Buffer/Register.hh
network/orion/Buffer/SConscript
network/orion/Buffer/SRAM.cc
network/orion/Buffer/SRAM.hh
network/orion/Buffer/WordlineUnit.cc
network/orion/Buffer/WordlineUnit.hh
network/orion/Clock.cc
network/orion/Clock.hh
network/orion/ConfigFile.cc
network/orion/ConfigFile.hh
network/orion/Crossbar/Crossbar.cc
network/orion/Crossbar/Crossbar.hh
network/orion/Crossbar/MatrixCrossbar.cc
network/orion/Crossbar/MatrixCrossbar.hh
network/orion/Crossbar/MultreeCrossbar.cc
network/orion/Crossbar/MultreeCrossbar.hh
network/orion/Crossbar/SConscript
network/orion/FlipFlop.cc
network/orion/FlipFlop.hh
network/orion/NetworkPower.cc
network/orion/NetworkPower.hh
network/orion/OrionConfig.cc
network/orion/OrionConfig.hh
network/orion/OrionLink.cc
network/orion/OrionLink.hh
network/orion/OrionRouter.cc
network/orion/OrionRouter.hh
network/orion/SConscript
network/orion/TechParameter.cc
network/orion/TechParameter.hh
network/orion/Type.hh
network/orion/Wire.cc
network/orion/Wire.hh
network/orion/orion.hh
network/orion/router.cfg
10441:5377550e1e15 11-Oct-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: structures: coorect #ifndef macros in header files

10422:148b96b7bc77 01-Oct-2014 Andreas Hansson <andreas.hansson@arm.com>

misc: Fix issues identified by static analysis

Another bunch of issues addressed.

10412:6400a2ab4e22 27-Sep-2014 Andreas Hansson <andreas.hansson@arm.com>

misc: Fix a bunch of minor issues identified by static analysis

Add some missing initialisation, and fix a handful benign resource
leaks (including some false positives).

10370:4466307b8a2a 15-Sep-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: network: revert some of the changes from ad9c042dce54
The changeset ad9c042dce54 made changes to the structures under the network
directory to use a map of buffers instead of vector of buffers.
The reasoning was that not all vnets that are created are used and we
needlessly allocate more buffers than required and then iterate over them
while processing network messages. But the move to map resulted in a slow
down which was pointed out by Andreas Hansson. This patch moves things
back to using vector of message buffers.

10348:c91b23c72d5e 03-Sep-2014 Andreas Hansson <andreas.hansson@arm.com>

base: Use the global Mersenne twister throughout

This patch tidies up random number generation to ensure that it is
done consistently throughout the code base. In essence this involves a
clean-up of Ruby, and some code simplifications in the traffic
generator.

As part of this patch a bunch of skewed distributions (off-by-one etc)
have been fixed.

Note that a single global random number generator is used, and that
the object instantiation order will impact the behaviour (the sequence
of numbers will be unaffected, but if module A calles random before
module B then they would obviously see a different outcome). The
dependency on the instantiation order is true in any case due to the
execution-model of gem5, so we leave it as is. Also note that the
global ranom generator is not thread safe at this point.

Regressions using the memtest, TrafficGen or any Ruby tester are
affected and will be updated accordingly.

10318:98771a936b61 03-Sep-2014 Andreas Hansson <andreas.hansson@arm.com>

arch: Cleanup unused ISA traits constants

This patch prunes unused values, and also unifies how the values are
defined (not using an enum for ALPHA), aligning the use of int vs Addr
etc.

The patch also removes the duplication of PageBytes/PageShift and
VMPageSize/LogVMPageSize. For all ISAs the two pairs had identical
values and the latter has been removed.

10314:94b6b28fc968 01-Sep-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: remove typedef of Index as int64
The Index type defined as typedef int64 does not really provide any help
since in most places we use primitive types instead of Index. Also, the name
Index is very generic that it does not merit being used as a typename.

10312:08f4deeb5b48 01-Sep-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: PerfectSwitch: moves code to a per vnet helper function
This patch moves code from the wakeup() function to a operateVnet().
The aim is to improve the readiblity of the code.

10311:ad9c042dce54 01-Sep-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: message buffers: significant changes

This patch is the final patch in a series of patches. The aim of the series
is to make ruby more configurable than it was. More specifically, the
connections between controllers are not at all possible (unless one is ready
to make significant changes to the coherence protocol). Moreover the buffers
themselves are magically connected to the network inside the slicc code.
These connections are not part of the configuration file.

This patch makes changes so that these connections will now be made in the
python configuration files associated with the protocols. This requires
each state machine to expose the message buffers it uses for input and output.
So, the patch makes these buffers configurable members of the machines.

The patch drops the slicc code that usd to connect these buffers to the
network. Now these buffers are exposed to the python configuration system
as Master and Slave ports. In the configuration files, any master port
can be connected any slave port. The file pyobject.cc has been modified to
take care of allocating the actual message buffer. This is inline with how
other port connections work.


/gem5/configs/ruby/MESI_Three_Level.py
/gem5/configs/ruby/MESI_Two_Level.py
/gem5/configs/ruby/MI_example.py
/gem5/configs/ruby/MOESI_CMP_directory.py
/gem5/configs/ruby/MOESI_CMP_token.py
/gem5/configs/ruby/MOESI_hammer.py
/gem5/configs/ruby/Network_test.py
/gem5/configs/ruby/Ruby.py
/gem5/src/mem/protocol/MESI_Three_Level-L0cache.sm
/gem5/src/mem/protocol/MESI_Three_Level-L1cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-L1cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-L2cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-dir.sm
/gem5/src/mem/protocol/MESI_Two_Level-dma.sm
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MI_example-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dma.sm
/gem5/src/mem/protocol/MOESI_hammer-cache.sm
/gem5/src/mem/protocol/MOESI_hammer-dir.sm
/gem5/src/mem/protocol/MOESI_hammer-dma.sm
/gem5/src/mem/protocol/Network_test-cache.sm
/gem5/src/mem/protocol/Network_test-dir.sm
network/Network.cc
network/Network.hh
network/Network.py
network/garnet/BaseGarnetNetwork.cc
network/garnet/BaseGarnetNetwork.hh
network/garnet/fixed-pipeline/NetworkInterface_d.cc
network/garnet/fixed-pipeline/NetworkInterface_d.hh
network/garnet/flexible-pipeline/NetworkInterface.cc
network/garnet/flexible-pipeline/NetworkInterface.hh
network/garnet/flexible-pipeline/Router.cc
network/garnet/flexible-pipeline/flitBuffer.cc
network/garnet/flexible-pipeline/flitBuffer.hh
network/simple/PerfectSwitch.cc
network/simple/PerfectSwitch.hh
network/simple/SimpleNetwork.cc
network/simple/SimpleNetwork.hh
network/simple/Switch.cc
network/simple/Switch.hh
network/simple/Throttle.cc
network/simple/Throttle.hh
slicc_interface/AbstractController.cc
slicc_interface/AbstractController.hh
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/python/swig/pyobject.cc
10310:61c7f1d06575 01-Sep-2014 Nilay Vaish <nilay@cs.wisc.edu>

build opts: add MI_example to NULL ISA
A later changeset changes the file src/python/swig/pyobject.cc to include
a header file that includes a header file generated at build time depending
on the PROTOCOL in use. Since NULL ISA was not specifying any protocol,
this resulted in compilation problems. Hence, the changeset.

10304:a2f88c6d9e54 01-Sep-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: remove unused toString() from AbstractController

10303:71e0934af9f1 01-Sep-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: network: move getNumNodes() to base class
All the implementations were doing the same things.

10302:0e9e99e6369a 01-Sep-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: eliminate type Time
There is another type Time in src/base class which results in a conflict.

10301:44839e8febbd 01-Sep-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: move files from ruby/system to ruby/structures

The directory ruby/system is crowded and unorganized. Hence, the files the
hold actual physical structures, are being moved to the directory
ruby/structures. This includes Cache Memory, Directory Memory,
Memory Controller, Wire Buffer, TBE Table, Perfect Cache Memory, Timer Table,
Bank Array.

The directory ruby/systems has the glue code that holds these structures
together.


SConscript
buffers/MessageBuffer.cc
buffers/MessageBuffer.hh
buffers/MessageBufferNode.cc
buffers/MessageBufferNode.hh
buffers/SConscript
common/MachineID.hh
common/NetDest.hh
network/MessageBuffer.cc
network/MessageBuffer.hh
network/MessageBufferNode.cc
network/MessageBufferNode.hh
network/SConscript
network/garnet/BaseGarnetNetwork.cc
network/garnet/fixed-pipeline/NetworkInterface_d.cc
network/garnet/flexible-pipeline/NetworkInterface.cc
network/simple/PerfectSwitch.cc
network/simple/SimpleNetwork.cc
network/simple/Switch.cc
network/simple/Throttle.cc
profiler/Profiler.hh
recorder/CacheRecorder.cc
recorder/CacheRecorder.hh
recorder/SConscript
slicc_interface/AbstractController.hh
slicc_interface/RubySlicc_ComponentMapping.hh
structures/AbstractReplacementPolicy.hh
structures/BankedArray.cc
structures/BankedArray.hh
structures/Cache.py
structures/CacheMemory.cc
structures/CacheMemory.hh
structures/DirectoryMemory.cc
structures/DirectoryMemory.hh
structures/DirectoryMemory.py
structures/LRUPolicy.hh
structures/MemoryControl.cc
structures/MemoryControl.hh
structures/MemoryControl.py
structures/MemoryNode.cc
structures/MemoryNode.hh
structures/MemoryVector.hh
structures/PerfectCacheMemory.hh
structures/PersistentTable.cc
structures/PersistentTable.hh
structures/Prefetcher.hh
structures/PseudoLRUPolicy.hh
structures/RubyMemoryControl.cc
structures/RubyMemoryControl.hh
structures/RubyMemoryControl.py
structures/SConscript
structures/SparseMemory.cc
structures/SparseMemory.hh
structures/TBETable.hh
structures/TimerTable.cc
structures/TimerTable.hh
structures/WireBuffer.cc
structures/WireBuffer.hh
structures/WireBuffer.py
system/AbstractReplacementPolicy.hh
system/BankedArray.cc
system/BankedArray.hh
system/Cache.py
system/CacheMemory.cc
system/CacheMemory.hh
system/CacheRecorder.cc
system/CacheRecorder.hh
system/DirectoryMemory.cc
system/DirectoryMemory.hh
system/DirectoryMemory.py
system/LRUPolicy.hh
system/MachineID.hh
system/MemoryControl.cc
system/MemoryControl.hh
system/MemoryControl.py
system/MemoryNode.cc
system/MemoryNode.hh
system/MemoryVector.hh
system/PerfectCacheMemory.hh
system/PersistentTable.cc
system/PersistentTable.hh
system/PseudoLRUPolicy.hh
system/RubyMemoryControl.cc
system/RubyMemoryControl.hh
system/RubyMemoryControl.py
system/RubyPort.hh
system/SConscript
system/Sequencer.hh
system/SparseMemory.cc
system/SparseMemory.hh
system/System.hh
system/TBETable.hh
system/TimerTable.cc
system/TimerTable.hh
system/WireBuffer.cc
system/WireBuffer.hh
system/WireBuffer.py
/gem5/src/mem/slicc/symbols/Type.py
10231:cb2e6950956d 31-May-2014 Steve Reinhardt <steve.reinhardt@amd.com>

style: eliminate equality tests with true and false

Using '== true' in a boolean expression is totally redundant,
and using '== false' is pretty verbose (and arguably less
readable in most cases) compared to '!'.

It's somewhat of a pet peeve, perhaps, but I had some time
waiting for some tests to run and decided to clean these up.

Unfortunately, SLICC appears not to have the '!' operator,
so I had to leave the '== false' tests in the SLICC code.

10226:056363356d15 23-May-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: message buffer: drop dequeue_getDelayCycles()
The functionality of updating and returning the delay cycles would now be
performed by the dequeue() function itself.

10163:e8608cdddae2 19-Apr-2014 Marco Elver <marco.elver@ed.ac.uk>

ruby: recorder: Fix (de-)serializing with different cache block-sizes

Upon aggregating records, serialize system's cache-block size, as the
cache-block size can be different when restoring from a checkpoint. This way,
we can correctly read all records when restoring from a checkpoints, even if
the cache-block size is different.

Note, that it is only possible to restore from a checkpoint if the
desired cache-block size is smaller or equal to the cache-block size
when the checkpoint was taken; we can split one larger request into
multiple small ones, but it is not reliable to do the opposite.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>

10133:0749c3ec92f4 23-Mar-2014 Andreas Hansson <andreas.hansson@arm.com>

ruby: Move Ruby debug flags to ruby dir and remove stale options

This patch moves the Ruby-related debug flags to the ruby
sub-directory, and also removes the state SConsopts that add the
no-longer-used NO_VECTOR_BOUNDS_CHECK.

10123:e958cdc5c669 20-Mar-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: consumer: avoid accessing wakeup times when waking up
Each consumer object maintains a set of tick values when the object is supposed
to wakeup and do some processing. As of now, the object accesses this set both
when scheduling a wakeup event and when the object actually wakes up. The set
is accessed during wakeup to remove the current tick value from the set. This
functionality is now being moved to the scheduling function where ticks are
removed at a later time.

10122:1268f1fd2714 20-Mar-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: garnet: convert network interfaces into clocked objects
This helps in configuring the network interfaces from the python script and
these objects no longer rely on the network object for the timing information.

10117:37e333de580f 20-Mar-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: no piobus in se mode
Piobus was recently added to se scripts for ruby so that the interrupt
controller can be connected to something (required since the interrupt
controller sends address range messages). This patch removes the piobus
and instead, the pio port of ruby port will now ignore the range change
messages in se mode.

10115:0e0a0dd558db 17-Mar-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: remove some of the unnecessary code

10097:c7fe7555d587 02-Mar-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: message buffer: changes related to tracking push/pop times
The last pop operation is now tracked as a Tick instead of in Cycles.
This helps in avoiding use of the receiver's clock during the enqueue
operation.

10096:e0167dda38dc 02-Mar-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: make the max_size variable of the MessageBuffer unsigned

10094:5be102721895 02-Mar-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: profiler: statically allocate stats variable
Couple of users observed segmentation fault when the simulator tries to
register the statistical variable m_IncompleteTimes. It seems that there
is some problem with the initialization of these variables when allocated
in the constructor.

10090:4eec7bdde5b0 23-Feb-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: route all packets through ruby port
Currently, the interrupt controller in x86 is connected to the io bus
directly. Therefore the packets between the io devices and the interrupt
controller do not go through ruby. This patch changes ruby port so that
these packets arrive at the ruby port first, which then routes them to their
destination. Note that the patch does not make these packets go through the
ruby network. That would happen in a subsequent patch.

10089:bc3126a05a7f 23-Feb-2014 Andreas Hansson <andreas.hansson@arm.com>

ruby: Simplify RubyPort flow control and routing

This patch simplfies the retry logic in the RubyPort, avoiding
redundant attributes, and enforcing more stringent checks on the
interactions with the normal ports. The patch also simplifies the
routing done by the RubyPort, using the port identifiers instead of a
heavy-weight sender state.

The patch also fixes a bug in the sending of responses from PIO
ports. Previously these responses bypassed the queue in the queued
port, and ignored the return value, potentially leading to response
packets being lost.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>

10087:86f3b546c214 23-Feb-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: message buffer: refactor code
Code in two of the functions was exactly the same. This patch moves
this code to a new function which is called from the two functions
mentioned initially.

10086:bd1089db3a88 23-Feb-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: remove few not required #includes

10085:b9891fbae4c8 23-Feb-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: slicc: remove unused COPY_HEAD functionality

10082:70f350b13ec0 21-Feb-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: network: move message buffers to base network class.

10081:26670ac8244e 21-Feb-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: network: garnet: fixed: removes net_ptr from links

10080:7a1bfe330d14 21-Feb-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: cache: remove not required variable m_cache_name

10079:fb7859dc2273 20-Feb-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: network: garnet: fixed: removes next cycle functions
At several places, there are functions that take a cycle value as input
and performs some computation. Along with each such function, another
function was being defined that simply added one more cycle to input and
computed the same function. This patch removes this second copy of the
function. Places where these functions were being called have been updated
to use the original function with argument being current cycle + 1.

10078:9400a90ec5d1 20-Feb-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: controller: slight code refactoring

10076:f81d94b53661 20-Feb-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: network: removes unused code.

10074:0e013fa647ac 20-Feb-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: message buffer: removes some unecessary functions.

10059:b29a58680b47 06-Feb-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: memory controller: use MemoryNode *

10012:ec5a5bfb941d 10-Jan-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: move all statistics to stats.txt, eliminate ruby.stats

10008:5176f0a71e56 04-Jan-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: add a three level MESI protocol.

The first two levels (L0, L1) are private to the core, the third level (L2)is
possibly shared. The protocol supports clustered designs. For example, one
can have two sets of two cores. Each core has an L0 and L1 cache. There are
two L2 controllers where each set accesses only one of the L2 controllers.

10005:8c2b0dc16ccd 04-Jan-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: add support for clusters

A cluster over here means a set of controllers that can be accessed only by a
certain set of cores. For example, consider a two level hierarchy. Assume
there are 4 L1 controllers (private) and 2 L2 controllers. We can have two
different hierarchies here:

a. the address space is partitioned between the two L2 controllers. Each L1
controller accesses both the L2 controllers. In this case, each L1 controller
is a cluster initself.

b. both the L2 controllers can cache any address. An L1 controller has access
to only one of the L2 controllers. In this case, each L2 controller
along with the L1 controllers that access it, form a cluster.

This patch allows for each controller to have a cluster ID, which is 0 by
default. By setting the cluster ID properly, one can instantiate hierarchies
with clusters. Note that the coherence protocol might have to be changed as
well.

10004:5d8b72563869 04-Jan-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: some small changes

9996:150338b8ba12 20-Dec-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: slicc: replace max_in_port_rank with number of inports

This patch replaces max_in_port_rank with the number of inports. The use of
max_in_port_rank was causing spurious re-builds and incorrect initialization
of variables in ruby related regression tests. This was due to the variable
value being used across threads while compiling when it was not meant to be.

Since the number of inports is state machine specific value, this problem
should get solved.

9995:2df9c3856989 20-Dec-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: declare variables to be unsigned in Address.hh

9946:ebd44da818d5 30-Oct-2013 Emilio Castillo <castilloe@unican.es>

ruby: Fixed a deadlock when restoring a checkpoint with garnet
This patch fixes a problem where in Garnet, the enqueue time in the
VCallocator and the SWallocator which is of type Cycles was being stored
inside a variable with int type.

This lead to a known problem restoring checkpoints with garnet & the fixed
pipeline enabled. That value was really big and didn't fit in the variable
overflowing it, therefore some conditions on the VC allocation stage & the
SW allocation stage were not met and the packets didn't advance through the
network, leading to a deadlock panic right after the checkpoint was restored.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>

9923:cdd51a15e9be 15-Oct-2013 Steve Reinhardt <steve.reinhardt@amd.com>

ruby: eliminate non-determinism from ruby.stats output

Get rid of non-deterministic "stats" in ruby.stats output
such as time & date of run, elapsed & CPU time used,
and memory usage. These values cause spurious
miscomparisons when looking at output diffs (though
they don't affect regressions, since the regressions
pass/fail status currently ignores ruby.stats entirely).

Most of this information is already captured in other
places (time & date in stdout, elapsed time & mem usage
in stats.txt), where the regression script is smart
enough to filter it out. It seems easier to get rid of
the redundant output rather than teaching the
regression tester to ignore the same information in
two different places.

9869:a204694db4f9 11-Sep-2013 Joel Hestness <jthestness@gmail.com>

ruby: Fix Topology throttle connections

The Topology source sets up input and output buffers for each of the external
nodes of a topology by indexing on Ruby's generated controller unique IDs.
These unique IDs are found by adding the MachineType_base_number to the version
number of each controller (see any generated *_Controller.cc - init() calls
getToNetQueue and getFromNetQueue using m_version + base). However, the
Topology object used the cntrl_id - which is required to be unique across all
controllers - to index the controllers list as they are being connected to
their input and output buffers. If the cntrl_ids did not match the Ruby unique
ID, the throttles end up connected to incorrectly indexed nodes in the network,
resulting in packets traversing incorrect network paths. This patch fixes the
Topology indexing scheme by using the Ruby unique ID to match that of the
SimpleNetwork buffer vectors.

9866:94dac7d7bb88 11-Sep-2013 Joel Hestness <jthestness@gmail.com>

ruby: Statically allocate stats in SimpleNetwork, Switch, Throttle

The previous changeset (9863:9483739f83ee) used STL vector containers to
dynamically allocate stats in the Ruby SimpleNetwork, Switch and Throttle. For
gcc versions before at least 4.6.3, this causes the standard vector allocator
to call Stats copy constructors (a no-no, since stats should be allocated in
the body of each SimObject instance). Since the size of these stats arrays is
known at compile time (NOTE: after code generation), this patch changes their
allocation to be static rather than using an STL vector.

9863:9483739f83ee 06-Sep-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: network: convert to gem5 style stats

9861:022a71603c7e 06-Sep-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: profiler: removes function resourceUsage()

9860:7248fa3e6e0f 06-Sep-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: remove undefined message size type
This message size type does not work well with one of the statistical
variables. It also seems unnecessary.

9859:1bd310386038 06-Sep-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: network: removes reset functionality

9858:f2417ecf5cc9 06-Sep-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: network: shorten variable names

9856:69bb50791e25 06-Sep-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: converts sparse memory stats to gem5 style

9850:87d6b41749e9 04-Sep-2013 Andreas Hansson <andreas.hansson@arm.com>

arch: Resurrect the NOISA build target and rename it NULL

This patch makes it possible to once again build gem5 without any
ISA. The main purpose is to enable work around the interconnect and
memory system without having to build any CPU models or device models.

The regress script is updated to include the NULL ISA target. Currently
no regressions make use of it, but all the testers could (and perhaps
should) transition to it.

9819:e4b12145f4eb 07-Aug-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: slicc: move some code to AbstractController
Some of the code in StateMachine.py file is added to all the controllers and
is independent of the controller definition. This code is being moved to the
AbstractController class which is the parent class of all controllers.

9814:7ad2b0186a32 18-Jul-2013 Andreas Hansson <andreas.hansson@arm.com>

mem: Set the cache line size on a system level

This patch removes the notion of a peer block size and instead sets
the cache line size on the system level.

Previously the size was set per cache, and communicated through the
interconnect. There were plenty checks to ensure that everyone had the
same size specified, and these checks are now removed. Another benefit
that is not yet harnessed is that the cache line size is now known at
construction time, rather than after the port binding. Hence, the
block size can be locally stored and does not have to be queried every
time it is used.

A follow-on patch updates the configuration scripts accordingly.

9799:5aed42e54180 28-Jun-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: network: remove reconfiguration code
This code seems not to be of any use now. There is no path in the simulator
that allows for reconfiguring the network. A better approach would be to
take a checkpoint and start the simulation from the checkpoint with the new
configuration.

9793:6e6cefc1db1f 27-Jun-2013 Akash Bagdia <akash.bagdia@arm.com>

sim: Add the notion of clock domains to all ClockedObjects

This patch adds the notion of source- and derived-clock domains to the
ClockedObjects. As such, all clock information is moved to the clock
domain, and the ClockedObjects are grouped into domains.

The clock domains are either source domains, with a specific clock
period, or derived domains that have a parent domain and a divider
(potentially chained). For piece of logic that runs at a derived clock
(a ratio of the clock its parent is running at) the necessary derived
clock domain is created from its corresponding parent clock
domain. For now, the derived clock domain only supports a divider,
thus ensuring a lower speed compared to its parent. Multiplier
functionality implies a PLL logic that has not been modelled yet
(create a separate clock instead).

The clock domains should be used as a mechanism to provide a
controllable clock source that affects clock for every clocked object
lying beneath it. The clock of the domain can (in a future patch) be
controlled by a handler responsible for dynamic frequency scaling of
the respective clock domains.

All the config scripts have been retro-fitted with clock domains. For
the System a default SrcClockDomain is created. For CPUs that run at a
different speed than the system, there is a seperate clock domain
created. This domain incorporates the CPU and the associated
caches. As before, Ruby runs under its own clock domain.

The clock period of all domains are pre-computed, such that no virtual
functions or multiplications are needed when calling
clockPeriod. Instead, the clock period is pre-computed when any
changes occur. For this to be possible, each clock domain tracks its
children.


/gem5/configs/common/CacheConfig.py
/gem5/configs/common/Simulation.py
/gem5/configs/example/fs.py
/gem5/configs/example/memtest.py
/gem5/configs/example/ruby_direct_test.py
/gem5/configs/example/ruby_fs.py
/gem5/configs/example/ruby_mem_test.py
/gem5/configs/example/ruby_network_test.py
/gem5/configs/example/ruby_random_test.py
/gem5/configs/example/se.py
/gem5/configs/ruby/MESI_CMP_directory.py
/gem5/configs/ruby/MI_example.py
/gem5/configs/ruby/MOESI_CMP_directory.py
/gem5/configs/ruby/MOESI_CMP_token.py
/gem5/configs/ruby/MOESI_hammer.py
/gem5/configs/ruby/Network_test.py
/gem5/configs/ruby/Ruby.py
/gem5/src/arch/alpha/AlphaSystem.py
/gem5/src/arch/mips/MipsSystem.py
/gem5/src/cpu/BaseCPU.py
/gem5/src/cpu/dummy_checker.cc
/gem5/src/cpu/o3/checker.cc
/gem5/src/dev/Ethernet.py
system/RubyMemoryControl.py
/gem5/src/sim/ClockDomain.py
/gem5/src/sim/ClockedObject.py
/gem5/src/sim/SConscript
/gem5/src/sim/clock_domain.cc
/gem5/src/sim/clock_domain.hh
/gem5/src/sim/clocked_object.hh
/gem5/tests/configs/base_config.py
/gem5/tests/configs/memtest-ruby.py
/gem5/tests/configs/memtest.py
/gem5/tests/configs/o3-timing-mp-ruby.py
/gem5/tests/configs/o3-timing-ruby.py
/gem5/tests/configs/pc-simple-timing-ruby.py
/gem5/tests/configs/rubytest-ruby.py
/gem5/tests/configs/simple-atomic-mp-ruby.py
/gem5/tests/configs/simple-timing-mp-ruby.py
/gem5/tests/configs/simple-timing-ruby.py
/gem5/tests/configs/tgen-simple-dram.py
/gem5/tests/configs/tgen-simple-mem.py
/gem5/tests/configs/twosys-tsunami-simple-atomic.py
9788:5558ee8dd7d9 27-Jun-2013 Akash Bagdia <akash.bagdia@arm.com>

config: Remove redundant explicit setting of default clocks

This patch removes the explicit setting of the clock period for
certain instances of CoherentBus, NonCoherentBus and IOCache where the
specified clock is same as the default value of the system clock. As
all the values used are the defaults, there are no performance
changes. There are similar cases where the toL2Bus is set to use the
parent CPU clock which is already the default behaviour.

The main motivation for these simplifications is to ease the
introduction of clock domains.

9773:915be89faf30 25-Jun-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: profiler: lots of inter-related changes
The patch started of with removing the global variables from the profiler for
profiling the miss latency of requests made to the cache. The corrresponding
histograms have been moved to the Sequencer. These are combined together when
the histograms are printed. Separate histograms are now maintained for
tracking latency of all requests together, of hits only and of misses only.

A particular set of histograms used to use the type GenericMachineType defined
in one of the protocol files. This patch removes this type. Now, everything
that relied on this type would use MachineType instead. To do this, SLICC has
been changed so that multiple machine types can be declared by a controller
in its preamble.

9771:57aac1719f86 24-Jun-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: remove the three files related to profiling
This patch removes the following three files: RubySlicc_Profiler.sm,
RubySlicc_Profiler_interface.cc and RubySlicc_Profiler_interface.hh.
Only one function prototyped in the file RubySlicc_Profiler.sm. Rest of the
code appearing in any of these files is not in use. Therefore, these files
are being removed.

That one single function, profileMsgDelay(), is being moved to the protocol
files where it is in use. If we need any of these deleted functions, I think
the right way to make them visible is to have the AbstractController class in
a .sm and let the controller state machine inherit from this class. The
AbstractController class can then have the prototypes of these profiling
functions in its definition.

9770:a0ee1b3aec39 24-Jun-2013 Joel Hestness <jthestness@gmail.com>, Nilay Vaish <nilay@cs.wisc.edu>

ruby: MessageBuffer: Remove unused m_size variable

The m_size variable attempted to track m_prio_heap.size(), but it did so
incorrectly due to the functions reanalyzeMessages and reanalyzeAllMessages().
Since this variable is intended to track m_prio_heap.size(), we can simply
replace instances where m_size is referenced with m_prio_heap.size(), which
has the added bonus of removing the need for m_size.

Note: This patch also removes an extraneous DPRINTF format string designator
from reanalyzeAllMessages()

Committed by: Nilay Vaish <nilay@cs.wisc.edu>

9766:488a71df39bc 18-Jun-2013 Lena Olson <lena@cs.wisc.edu>

ruby: restrict Address to being a type and not a variable name
Change all occurrances of Address as a variable name to instead use Addr.
Address is an allowed name in slicc even when Address is also being used as a
type, leading to declarations of "Address Address". While this works, it
prevents adding another field of type Address because the compiler then thinks
Address is a variable name, not type.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>

9747:fbe79534d024 09-Jun-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: remove several unused variables in Profiler
This patch removes per processor cycle count, histogram for filter stats,
histogram for multicasts, histogram for prefetch wait, some function
prototypes that do not have definitions.

9746:7d235b709425 09-Jun-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: remove periodic event from Profiler
The Profiler class does not need an event for dumping statistics
periodically. This is because there is a method for dumping statistics
for all the sim objects periodically. Since Ruby is a sim object, its
statistics are also included.

9745:884ad4638236 09-Jun-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: stats: use gem5's stats for cache and memory controllers
This moves event and transition count statistics for cache controllers to
gem5's statistics. It does the same for the statistics associated with the
memory controller in ruby.

All the cache/directory/dma controllers individually collect the event and
transition counts. A callback function, collateStats(), has been added that
is invoked on the controller version 0 of each controller class. This
function adds all the individual controller statistics to a vector
variables. All the code for registering the statistical variables and
collating them is generated by SLICC. The patch removes the files
*_Profiler.{cc,hh} and *_ProfileDumper.{cc,hh} which were earlier used for
collecting and dumping statistics respectively.

9744:9ab496e12335 09-Jun-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: remove undefined functions in Address class

9692:67d9da312ef0 21-May-2013 Nilay Vaish <nilay@cs.wisc.edu>, Malek Musleh <malek.musleh@gmail.com>

ruby: add stats to .sm files, remove cache profiler
This patch changes the way cache statistics are collected in ruby.

As of now, there is separate entity called CacheProfiler which holds
statistical variables for caches. The CacheMemory class defines different
functions for accessing the CacheProfiler. These functions are then invoked
in the .sm files. I find this approach opaque and prone to error. Secondly,
we probably should not be paying the cost of a function call for recording
statistics.

Instead, this patch allows for accessing statistical variables in the
.sm files. The collection would become transparent. Secondly, it would happen
in place, so no function calls. The patch also removes the CacheProfiler class.

9670:fa4eedccce17 23-Apr-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: patch checkpoint restore with garnet
Due to recent changes to clocking system in Ruby and the way Ruby restores
state from a checkpoint, garnet was failing to run from a checkpointed state.
The problem is that Ruby resets the time to zero while warming up the caches.
If any component records a local copy of the time (read calls curCycle())
before the simulation has started, then that component will not operate until
that time is reached. In the context of this particular patch, the Garnet
Network class calls curCycle() at multiple places. Any non-operational
component can block in requests in the memory system, which the system
interprets as a deadlock. This patch makes changes so that Garnet can
successfully run from checkpointed state.

It adds a globally visible time at which the actual execution started. This
time is initialized in RubySystem::startup() function. This variable is only
meant for components with in Ruby. This replaces the private variable that
was maintained within Garnet since it is not possible to figure out the
correct time when the value of this variable can be set.

The patch also does away with all cases where curCycle() is called with in
some Ruby component before the system has actually started executing. This
is required due to the quirky manner in which ruby restores from a checkpoint.

9662:59a7df953d5e 22-Apr-2013 Andreas Hansson <andreas.hansson@arm.com>

mem: Replace check with panic where inhibited should not happen

This patch changes the SimpleTimingPort and RubyPort to panic on
inhibited requests as this should never happen in either of the
cases. The SimpleTimingPort is only used for the I/O devices PIO port
and the DMA devices config port and should thus never see an inhibited
request. Similarly, the SimpleTimingPort is also used for the
MessagePort in x86, and there should also not be any cases where the
port sees an inhibited request.

9648:f10eb34e3e38 22-Apr-2013 Dam Sunwoo <dam.sunwoo@arm.com>

sim: separate nextCycle() and clockEdge() in clockedObjects

Previously, nextCycle() could return the *current* cycle if the current tick was
already aligned with the clock edge. This behavior is not only confusing (not
quite what the function name implies), but also caused problems in the
drainResume() function. When exiting/re-entering the sim loop (e.g., to take
checkpoints), the CPUs will drain and resume. Due to the previous behavior of
nextCycle(), the CPU tick events were being rescheduled in the same ticks that
were already processed before draining. This caused divergence from runs that
did not exit/re-entered the sim loop. (Initially a cycle difference, but a
significant impact later on.)

This patch separates out the two behaviors (nextCycle() and clockEdge()),
uses nextCycle() in drainResume, and uses clockEdge() everywhere else.
Nothing (other than name) should change except for the drainResume timing.

9633:3bf3100e9fa1 09-Apr-2013 Joel Hestness <jthestness@gmail.com>

Ruby: Fix RubyPort evict packet memory leak

When using the o3 or inorder CPUs with many Ruby protocols, the caches may
need to forward invalidations to the CPUs. The RubyPort was instantiating a
packet to be sent to the CPUs to signal the eviction, but the packets were
not being freed by the CPUs. Consistent with the classic memory model, stack
allocate the packet and heap allocate the request so on
ruby_eviction_callback() completion, the packet deconstructor is called, and
deletes the request (*Note: stack allocating the request causes double
deletion, since it will be deleted in the packet destructor). This results in
the least memory allocations without memory errors.

9632:476febc1aff0 09-Apr-2013 Joel Hestness <jthestness@gmail.com>

Ruby: Delete packet requests during warmup

When warming up caches in Ruby, the CacheRecorder sends fetch requests into
Ruby Sequencers with packet types that require responses. Since responses are
never generated for these CacheRecorder requests, the requests are not deleted
in the packet destructor called from the Ruby hit callback. Free the request.

9629:c52b4c5f46f8 09-Apr-2013 Jason Power <powerjg@cs.wisc.edu>

Ruby: More descriptive message buffer connection fatal

When connecting message buffers between Ruby controllers, it is
easy to mistakenly connect multiple controllers to the same message
buffer. This patch prints a more descriptive fatal message than the
previous assert statement in order to facilitate easier debugging.

9627:fa31189e1fb5 07-Apr-2013 Joel Hestness <jthestness@gmail.com>

Ruby System, Cache Recorder: Use delete [] for trace vars

The cache trace variables are array allocated uint8_t* in the RubySystem and
the Ruby CacheRecorder, but the code used delete to free the memory, resulting
in Valgrind memory errors. Change these deletes to delete [] to get rid of the
errors.

9603:bf5e46a02a38 22-Mar-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: message buffer: correct previous errors
A recent set of patches added support for multiple clock domains to ruby.
I had made some errors while writing those patches. The sender was using
the receiver side clock while enqueuing a message in the buffer. Those
errors became visible while creating (or restoring from) checkpoints. The
errors also become visible when a multi eventq scenario occurs.

9602:21f39f6c1e92 22-Mar-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: message buffer: remove _ptr from some variables
The names were getting too long.

9601:fe4eb64480bf 22-Mar-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: message buffer node: used Tick in place of Cycles
The message buffer node used to keep time in terms of Cycles. Since the
sender and the receiver can have different clock periods, storing node
time in cycles requires some conversion. Instead store the time directly
in Ticks.

9600:34df8f24be7e 22-Mar-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: consumer: avoid using receiver side clock
A set of patches was recently committed to allow multiple clock domains
in ruby. In those patches, I had inadvertently made an incorrect use of
the clocks. Suppose object A needs to schedule an event on object B. It
was possible that A accesses B's clock to schedule the event. This is not
possible in actual system. Hence, changes are being to the Consumer class
so as to avoid such happenings. Note that in a multi eventq simulation,
this can possibly lead to an incorrect simulation.

There are two functions in the Consumer class that are used for scheduling
events. The first function takes in the relative delay over the current time
as the argument and adds the current time to it for scheduling the event.
The second function takes in the absolute time (in ticks) for scheduling the
event. The first function is now being moved to protected section of the
class so that only objects of the derived classes can use it. All other
objects will have to specify absolute time while scheduling an event
for some consumer.

9599:e95479c2926f 22-Mar-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: remove unsued profile functions

9598:a58b28c17d7f 22-Mar-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: keep histogram of outstanding requests in seq
The histogram for tracking outstanding counts per cycle is maintained
in the profiler. For a parallel implementation of the memory system, we
need that this histogram is maintained locally. Hence it will now be
kept in the sequencer itself. The resulting histograms will be merged
when the stats are printed.

9596:aa73a81cf92c 22-Mar-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: move stall and wakeup functions to AbstractController
These functions are currently implemented in one of the files related to Slicc.
Since these are purely C++ functions, they are better suited to be in the base
class.

9595:470016acf37d 22-Mar-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: connect two controllers using only message buffers
This patch modifies ruby so that two controllers can be connected to each
other with only message buffers in between. Before this patch, all the
controllers had to be connected to the network for them to communicate
with each other. With this patch, one can have protocols where a controller
is not connected to the network, but communicates with another controller
through a message buffer.

9594:219ad5fe8c04 22-Mar-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: convert Topology to regular class
The Topology class in Ruby does not need to inherit from SimObject class.
This patch turns it into a regular class. The topology object is now created
in the constructor of the Network class. All the parameters for the topology
class have been moved to the network class.

9593:9441ca79f3c8 22-Mar-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: network: move routers from topology to network

9586:3c62e3b7f658 15-Mar-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: set: corrects csprintf() call introduced by 7d95b650c9b6

9580:d1e6329cd367 07-Mar-2013 Andreas Hansson <andreas.hansson@arm.com>

ruby: Fix gcc 4.8 maybe-uninitialized compilation error

This patch fixes the one-and-only gcc 4.8 compilation error, being a
warning about "maybe uninitialized" in Orion.

9577:91cac7c9c636 06-Mar-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: remove the functional copy of memory in se mode
This patch removes the functional copy of the memory that was maintained in
the se mode. Now ruby itself will provide the data.

9576:2c094ad4dc70 06-Mar-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: garnet: fixed: implement functional access

9572:13ae8000f771 03-Mar-2013 Blake Hechtman <bah13@duke.edu>, Nilay Vaish <nilay@cs.wisc.edu>

ruby: fixes functional writes to RubyRequest
The functional write code was assuming that all writes are block sized,
which may not be true for Ruby Requests. This bug can lead to a buffer
overflow.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>

9563:08d097040f90 28-Feb-2013 Dibakar Gope <gope@wisc.edu>, Nilay Vaish <nilay@cs.wisc.edu>

ruby: mesi coherence protocol: invalidate lock
The MESI CMP directory coherence protocol, while transitioning from SM to IM,
did not invalidate the lock that it might have taken on a cache line. This
patch adds an action for doing so.

The problem was found by Dibakar, but I was not happy with his proposed
solution. So I implemented a different solution.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>

9560:322472967603 19-Feb-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: remove unused variable m_print_config in class Topology

9557:8666e81607a6 19-Feb-2013 Andreas Hansson <andreas.hansson@arm.com>

scons: Fix warnings issued by clang 3.2svn (XCode 4.6)

This patch fixes the warnings that clang3.2svn emit due to the "-Wall"
flag. There is one case of an uninitialised value in the ARM neon ISA
description, and then a whole range of unused private fields that are
pruned.

9554:406fbcf60223 19-Feb-2013 Andreas Hansson <andreas.hansson@arm.com>

scons: Add warning for missing declarations

This patch enables warnings for missing declarations. To avoid issues
with SWIG-generated code, the warning is only applied to non-SWIG
code.

9550:e0e2c8f83d08 19-Feb-2013 Andreas Hansson <andreas.hansson@arm.com>

scons: Fix up numerous warnings about name shadowing

This patch address the most important name shadowing warnings (as
produced when using gcc/clang with -Wshadow). There are many
locations where constructor parameters and function parameters shadow
local variables, but these are left unchanged.

9545:508784fad4e5 19-Feb-2013 Andreas Hansson <andreas.hansson@arm.com>

sim: Make clock private and access using clockPeriod()

This patch makes the clock member private to the ClockedObject and
forces all children to access it using clockPeriod(). This makes it
impossible to inadvertently change the clock, and also makes it easier
to transition to a situation where the clock is derived from e.g. a
clock domain, or through a multiplier.

9542:683991c46ac8 19-Feb-2013 Andreas Hansson <andreas.hansson@arm.com>

mem: Add predecessor to SenderState base class

This patch adds a predecessor field to the SenderState base class to
make the process of linking them up more uniform, and enable a
traversal of the stack without knowing the specific type of the
subclasses.

There are a number of simplifications done as part of changing the
SenderState, particularly in the RubyTest.

9511:615456167b9d 14-Feb-2013 Andreas Hansson <andreas.hansson@arm.com>

Ruby: Fix compilation errors on gcc 4.7 and clang 3.2

This patch fixes a few (recently added) errors that prevented gem5 from
compiling on more recent versions of gcc and clang.

9508:dde110931867 10-Feb-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: enable multiple clock domains
This patch allows ruby to have multiple clock domains. As I understand
with this patch, controllers can have different frequencies. The entire
network needs to run at a single frequency.

The idea is that with in an object, time is treated in terms of cycles.
But the messages that are passed from one entity to another should contain
the time in Ticks. As of now, this is only true for the message buffers,
but not for the links in the network. As I understand the code, all the
entities in different networks (simple, garnet-fixed, garnet-flexible) should
be clocked at the same frequency.

Another problem is that the directory controller has to operate at the same
frequency as the ruby system. This is because the memory controller does
not make use of the Message Buffer, and instead implements a buffer of its
own. So, it has no idea of the frequency at which the directory controller
is operating and uses ruby system's frequency for scheduling events.

9507:d2ab6d889fc7 10-Feb-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: replace Time with Cycles (final patch in the series)
This patch is as of now the final patch in the series of patches that replace
Time with Cycles.This patch further replaces Time with Cycles in Sequencer,
Profiler, different protocols and related entities.

Though Time has not been completely removed, the places where it is in use
seem benign as of now.

9506:f5335ac67f41 10-Feb-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: replace Time with Cycles in garnet fixed and flexible

9505:66b3ed9a176e 10-Feb-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: replace Time with Tick in replacement policy classes

9504:5c6de9a7f8d8 10-Feb-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: convert block size, memory size to unsigned

9503:98ad73bdc579 10-Feb-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: replace Time with Cycles in MessageBuffer

9502:45cd0bc6c507 10-Feb-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: replace Time with Cycles in Memory Controller

9501:378817542866 10-Feb-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: Replace Time with Cycles in SequencerMessage

9500:9c3e3d1c7a87 10-Feb-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: replace Time with Cycles in Message class
Concomitant changes are being committed as well, including the io operator<<
for the Cycles class.

9499:b03b556a8fbb 10-Feb-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: replaces Time with Cycles in many places
The patch started of with replacing Time with Cycles in the Consumer class.
But to get ruby to compile, the rest of the changes had to be carried out.
Subsequent patches will further this process, till we completely replace
Time with Cycles.


/gem5/src/mem/protocol/MESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MESI_CMP_directory-dma.sm
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MI_example-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dma.sm
/gem5/src/mem/protocol/MOESI_hammer-cache.sm
/gem5/src/mem/protocol/MOESI_hammer-dir.sm
/gem5/src/mem/protocol/MOESI_hammer-dma.sm
/gem5/src/mem/protocol/Network_test-cache.sm
/gem5/src/mem/protocol/RubySlicc_Exports.sm
/gem5/src/mem/protocol/RubySlicc_Types.sm
/gem5/src/mem/protocol/RubySlicc_Util.sm
buffers/MessageBuffer.cc
buffers/MessageBuffer.hh
buffers/MessageBufferNode.hh
common/Consumer.cc
common/Consumer.hh
network/BasicLink.hh
network/BasicLink.py
network/garnet/fixed-pipeline/GarnetLink_d.py
network/garnet/fixed-pipeline/InputUnit_d.hh
network/garnet/fixed-pipeline/NetworkInterface_d.cc
network/garnet/fixed-pipeline/NetworkLink_d.hh
network/garnet/fixed-pipeline/OutputUnit_d.hh
network/garnet/fixed-pipeline/Router_d.cc
network/garnet/fixed-pipeline/SWallocator_d.cc
network/garnet/fixed-pipeline/Switch_d.cc
network/garnet/fixed-pipeline/VCallocator_d.cc
network/garnet/flexible-pipeline/GarnetLink.py
network/garnet/flexible-pipeline/NetworkInterface.cc
network/garnet/flexible-pipeline/NetworkLink.hh
network/garnet/flexible-pipeline/Router.cc
network/garnet/flexible-pipeline/Router.hh
network/simple/PerfectSwitch.cc
network/simple/Switch.cc
network/simple/Switch.hh
network/simple/Throttle.cc
network/simple/Throttle.hh
slicc_interface/AbstractCacheEntry.hh
slicc_interface/AbstractController.hh
slicc_interface/Controller.py
slicc_interface/RubySlicc_Util.hh
system/Cache.py
system/CacheMemory.hh
system/RubyMemoryControl.cc
system/RubyMemoryControl.hh
system/RubyMemoryControl.py
system/Sequencer.cc
system/TimerTable.cc
system/TimerTable.hh
system/WireBuffer.cc
system/WireBuffer.hh
/gem5/src/mem/slicc/ast/EnqueueStatementAST.py
/gem5/src/mem/slicc/ast/FuncCallExprAST.py
/gem5/src/mem/slicc/ast/InfixOperatorExprAST.py
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/mem/slicc/symbols/Type.py
9497:2759161b9d7f 10-Feb-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: modifies histogram add() function
This patch modifies the Histogram class' add() function so that it can add
linear histograms as well. The function assumes that the left end point of
the ranges of the two histograms are the same. It also assumes that when
the ranges of the two histogram are changed to accomodate an element not in
the range, the factor used in changing the range is same for both the
histograms.

This function is then used in removing one of the calls to the global
profiler*. The histograms for recording the delays incurred in processing
different requests are now maintained by the controllers. The profiler
adds these histograms when it needs to print the stats.

9496:28d88a0fda74 10-Feb-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: record fully busy cycle with in the controller
This patch does several things. First, the counter for fully busy cycles for a
controller is now kept with in the controller, instead of being part of the profiler.
Second, the topology class no longer keeps an array of controllers which was only
used for printing stats. Instead, ruby system will now ask each controller to print
the stats. Thirdly, the statistical variable for recording how many different types
were created is being moved in to the controller from the profiler. Note that for
printing, the profiler will collate results from different controllers.

9492:d4953634e9ee 31-Jan-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: correct computation of number of bits required for address
The number of bits required for an address was set to floorLog2(memory size).
This is correct under the assumption that the memory size is a power of 2,
which is not always true. Hence, floorLog2 is being replaced with ceilLog2.

9484:e96ff45795bc 28-Jan-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: remove get_time()
This patch replaces get_time() in *.sm files with curCycle() which
is now possible since controllers are clocked objects.

9475:736909f5c13b 17-Jan-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: remove calls to g_system_ptr->getTime()
This patch further removes calls to g_system_ptr->getTime() where ever other
clocked objects are available for providing current time.

9467:8da5ee073b92 14-Jan-2013 Malek Musleh <malek.musleh@gmail.com>

ruby sequencer: converts cycles to ticks in deadlock panic()
This patch converts the panic() print outs in the Sequencer::wakeup()
call from ruby cycles to Ticks(). This makes it easier to debug deadlocks
with the ProtocolTrace flag so the issue time indicated in the panic message
can be quickly searched for.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>

9466:23e13ad7091f 14-Jan-2013 Nilay Vaish <nilay@cs.wisc.edu>

Ruby: remove reference to g_system_ptr from class Message
This patch was initiated so as to remove reference to g_system_ptr,
the pointer to Ruby System that is used for getting the current time.
That simple change actual requires changing a lot many things in slicc and
garnet. All these changes are related to how time is handled.

In most of the places, g_system_ptr has been replaced by another clock
object. The changes have been done under the assumption that all the
components in the memory system are on the same clock frequency, but the
actual clocks might be distributed.


common/Global.hh
network/garnet/BaseGarnetNetwork.cc
network/garnet/fixed-pipeline/GarnetNetwork_d.cc
network/garnet/fixed-pipeline/InputUnit_d.cc
network/garnet/fixed-pipeline/InputUnit_d.hh
network/garnet/fixed-pipeline/NetworkInterface_d.cc
network/garnet/fixed-pipeline/NetworkLink_d.cc
network/garnet/fixed-pipeline/NetworkLink_d.hh
network/garnet/fixed-pipeline/OutputUnit_d.cc
network/garnet/fixed-pipeline/OutputUnit_d.hh
network/garnet/fixed-pipeline/RoutingUnit_d.cc
network/garnet/fixed-pipeline/SWallocator_d.cc
network/garnet/fixed-pipeline/Switch_d.cc
network/garnet/fixed-pipeline/VCallocator_d.cc
network/garnet/fixed-pipeline/VirtualChannel_d.cc
network/garnet/fixed-pipeline/VirtualChannel_d.hh
network/garnet/fixed-pipeline/flitBuffer_d.cc
network/garnet/fixed-pipeline/flitBuffer_d.hh
network/garnet/fixed-pipeline/flit_d.cc
network/garnet/fixed-pipeline/flit_d.hh
network/garnet/flexible-pipeline/GarnetNetwork.cc
network/garnet/flexible-pipeline/NetworkInterface.cc
network/garnet/flexible-pipeline/NetworkLink.cc
network/garnet/flexible-pipeline/Router.cc
network/garnet/flexible-pipeline/flit.cc
network/garnet/flexible-pipeline/flit.hh
network/garnet/flexible-pipeline/flitBuffer.cc
network/garnet/flexible-pipeline/flitBuffer.hh
network/orion/NetworkPower.cc
slicc_interface/Message.hh
slicc_interface/NetworkMessage.hh
slicc_interface/RubyRequest.hh
slicc_interface/RubySlicc_Util.hh
structures/Prefetcher.hh
system/DMASequencer.cc
system/Sequencer.cc
system/WireBuffer.cc
/gem5/src/mem/slicc/ast/EnqueueStatementAST.py
/gem5/src/mem/slicc/symbols/Type.py
9465:4ae4f3f4b870 14-Jan-2013 Nilay Vaish <nilay@cs.wisc.edu>

Ruby: use ClockedObject in Consumer class
Many Ruby structures inherit from the Consumer, which is used for scheduling
events. The Consumer used to relay on an Event Manager for scheduling events
and on g_system_ptr for time. With this patch, the Consumer will now use a
ClockedObject to schedule events and to query for current time. This resulted
in several structures being converted from SimObjects to ClockedObjects. Also,
the MessageBuffer class now requires a pointer to a ClockedObject so as to
query for time.

9389:8f8c911ab5a7 07-Jan-2013 Andreas Hansson <andreas.hansson@arm.com>

ruby: Fix missing cxx_header in Switch

This patch addresses a warning related to the swig interface
generation for the Switch class. The cxx_header is now specified
correctly, and the header in question has got a few includes added to
make it all compile.

9364:e5fc9d588132 11-Dec-2012 Nilay Vaish <nilay@cs.wisc.edu>

ruby: change slicc to allow for constructor args
The patch adds support to slicc for recognizing arguments that should be
passed to the constructor of a class. I did not like the fact that an explicit
check was being carried on the type 'TBETable' to figure out the arguments to
be passed to the constructor.
The patch also moves some of the member variables that are declared for all
the controllers to the base class AbstractController.

9363:e2616dc035ce 11-Dec-2012 Nilay Vaish <nilay@cs.wisc.edu>

ruby: add a prefetcher
This patch adds a prefetcher for the ruby memory system. The prefetcher
is based on a prefetcher implemented by others (well, I don't know
who wrote the original). The prefetcher does stride-based prefetching,
both unit and non-unit. It obseves the misses in the cache and trains on
these. After the training period is over, the prefetcher starts issuing
prefetch requests to the controller.

9362:d7f4abbf52e3 11-Dec-2012 Nilay Vaish <nilay@cs.wisc.edu>

ruby: add functions for computing next stride/page address

9356:b279bad40aa3 16-Nov-2012 Nilay Vaish <nilay@cs.wisc.edu>

sim: have a curTick per eventq
This patch adds a _curTick variable to an eventq. This variable is updated
whenever an event is serviced in function serviceOne(), or all events upto
a particular time are processed in function serviceEvents(). This change
helps when there are eventqs that do not make use of curTick for scheduling
events.

9354:7691ec6b173b 10-Nov-2012 Nilay Vaish <nilay@cs.wisc.edu>

ruby: support functional accesses in garnet flexible network

9353:b25c55c87d60 10-Nov-2012 Nilay Vaish <nilay@cs.wisc.edu>

ruby: bug in functionalRead, revert recent changes
Recent changes to functionalRead() in the memory system was not correct.
The change allowed for returning data from the first message found in
the buffers of the memory system. This is not correct since it is possible
that a timing message has data from an older state of the block.

The changes are being reverted.

9350:ddb946b131c8 02-Nov-2012 Hamid Reza Khaleghzadeh <khaleghzadeh@gmail.com>, Lluc Alvarez <lluc.alvarez@bsc.es>, Nilay Vaish <nilay@cs.wisc.edu>

ruby: reset and dump stats along with reset of the system
This patch adds support to ruby so that the statistics maintained by ruby
are reset/dumped when the statistics for the rest of the system are
reset/dumped. For resetting the statistics, ruby now provides the
resetStats() function that a sim object can provide. As a consequence, the
clearStats() function has been removed from RubySystem. For dumping stats,
Ruby now adds a callback event to the dumpStatsQueue. The exit callback that
ruby used to add earlier is being removed.

Created by: Hamid Reza Khaleghzadeh.
Improved by: Lluc Alvarez, Nilay Vaish
Committed by: Nilay Vaish

9342:6fec8f26e56d 02-Nov-2012 Andreas Sandberg <Andreas.Sandberg@arm.com>

sim: Move the draining interface into a separate base class

This patch moves the draining interface from SimObject to a separate
class that can be used by any object needing draining. However,
objects not visible to the Python code (i.e., objects not deriving
from SimObject) still depend on their parents informing them when to
drain. This patch also gets rid of the CountedDrainEvent (which isn't
really an event) and replaces it with a DrainManager.


/gem5/src/arch/arm/table_walker.cc
/gem5/src/arch/arm/table_walker.hh
/gem5/src/cpu/o3/cpu.cc
/gem5/src/cpu/o3/cpu.hh
/gem5/src/cpu/simple/atomic.cc
/gem5/src/cpu/simple/atomic.hh
/gem5/src/cpu/simple/timing.cc
/gem5/src/cpu/simple/timing.hh
/gem5/src/cpu/testers/traffic_gen/traffic_gen.cc
/gem5/src/cpu/testers/traffic_gen/traffic_gen.hh
/gem5/src/dev/copy_engine.cc
/gem5/src/dev/copy_engine.hh
/gem5/src/dev/dma_device.cc
/gem5/src/dev/dma_device.hh
/gem5/src/dev/i8254xGBe.cc
/gem5/src/dev/i8254xGBe.hh
/gem5/src/dev/ide_disk.cc
/gem5/src/dev/io_device.cc
/gem5/src/dev/io_device.hh
/gem5/src/dev/ns_gige.cc
/gem5/src/dev/ns_gige.hh
/gem5/src/dev/pcidev.cc
/gem5/src/dev/pcidev.hh
/gem5/src/dev/sinic.cc
/gem5/src/dev/sinic.hh
/gem5/src/mem/bus.cc
/gem5/src/mem/bus.hh
/gem5/src/mem/cache/base.cc
/gem5/src/mem/cache/base.hh
/gem5/src/mem/coherent_bus.cc
/gem5/src/mem/coherent_bus.hh
/gem5/src/mem/noncoherent_bus.cc
/gem5/src/mem/noncoherent_bus.hh
/gem5/src/mem/packet_queue.cc
/gem5/src/mem/packet_queue.hh
/gem5/src/mem/qport.hh
system/MemoryControl.hh
system/RubyMemoryControl.cc
system/RubyMemoryControl.hh
system/RubyPort.cc
system/RubyPort.hh
system/Sequencer.cc
/gem5/src/mem/simple_dram.cc
/gem5/src/mem/simple_dram.hh
/gem5/src/mem/simple_mem.cc
/gem5/src/mem/simple_mem.hh
/gem5/src/python/SConscript
/gem5/src/python/m5/SimObject.py
/gem5/src/python/m5/__init__.py
/gem5/src/python/m5/internal/__init__.py
/gem5/src/python/m5/simulate.py
/gem5/src/python/swig/drain.i
/gem5/src/python/swig/event.i
/gem5/src/python/swig/pyevent.cc
/gem5/src/python/swig/pyevent.hh
/gem5/src/sim/SConscript
/gem5/src/sim/drain.cc
/gem5/src/sim/drain.hh
/gem5/src/sim/serialize.hh
/gem5/src/sim/sim_events.cc
/gem5/src/sim/sim_object.cc
/gem5/src/sim/sim_object.hh
/gem5/src/sim/system.cc
/gem5/src/sim/system.hh
9338:97b4a2be1e5b 02-Nov-2012 Andreas Sandberg <Andreas.Sandberg@arm.com>

sim: Include object header files in SWIG interfaces

When casting objects in the generated SWIG interfaces, SWIG uses
classical C-style casts ( (Foo *)bar; ). In some cases, this can
degenerate into the equivalent of a reinterpret_cast (mainly if only a
forward declaration of the type is available). This usually works for
most compilers, but it is known to break if multiple inheritance is
used anywhere in the object hierarchy.

This patch introduces the cxx_header attribute to Python SimObject
definitions, which should be used to specify a header to include in
the SWIG interface. The header should include the declaration of the
wrapped object. We currently don't enforce header the use of the
header attribute, but a warning will be generated for objects that do
not use it.


/gem5/src/SConscript
/gem5/src/arch/alpha/AlphaInterrupts.py
/gem5/src/arch/alpha/AlphaSystem.py
/gem5/src/arch/alpha/AlphaTLB.py
/gem5/src/arch/arm/ArmInterrupts.py
/gem5/src/arch/arm/ArmNativeTrace.py
/gem5/src/arch/arm/ArmSystem.py
/gem5/src/arch/arm/ArmTLB.py
/gem5/src/arch/mips/MipsInterrupts.py
/gem5/src/arch/mips/MipsSystem.py
/gem5/src/arch/mips/MipsTLB.py
/gem5/src/arch/power/PowerInterrupts.py
/gem5/src/arch/power/PowerTLB.py
/gem5/src/arch/sparc/SparcInterrupts.py
/gem5/src/arch/sparc/SparcNativeTrace.py
/gem5/src/arch/sparc/SparcSystem.py
/gem5/src/arch/sparc/SparcTLB.py
/gem5/src/arch/x86/X86LocalApic.py
/gem5/src/arch/x86/X86NativeTrace.py
/gem5/src/arch/x86/X86System.py
/gem5/src/arch/x86/X86TLB.py
/gem5/src/arch/x86/bios/ACPI.py
/gem5/src/arch/x86/bios/E820.py
/gem5/src/arch/x86/bios/IntelMP.py
/gem5/src/arch/x86/bios/SMBios.py
/gem5/src/base/CPA.py
/gem5/src/base/vnc/Vnc.py
/gem5/src/cpu/BaseCPU.py
/gem5/src/cpu/CheckerCPU.py
/gem5/src/cpu/ExeTracer.py
/gem5/src/cpu/FuncUnit.py
/gem5/src/cpu/IntelTrace.py
/gem5/src/cpu/IntrControl.py
/gem5/src/cpu/LegionTrace.py
/gem5/src/cpu/NativeTrace.py
/gem5/src/cpu/inorder/InOrderCPU.py
/gem5/src/cpu/inorder/InOrderTrace.py
/gem5/src/cpu/inteltrace.hh
/gem5/src/cpu/o3/FUPool.py
/gem5/src/cpu/simple/AtomicSimpleCPU.py
/gem5/src/cpu/simple/BaseSimpleCPU.py
/gem5/src/cpu/simple/TimingSimpleCPU.py
/gem5/src/cpu/static_inst.hh
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.py
/gem5/src/cpu/testers/memtest/MemTest.py
/gem5/src/cpu/testers/networktest/NetworkTest.py
/gem5/src/cpu/testers/rubytest/RubyTester.py
/gem5/src/cpu/testers/traffic_gen/TrafficGen.py
/gem5/src/dev/BadDevice.py
/gem5/src/dev/CopyEngine.py
/gem5/src/dev/Device.py
/gem5/src/dev/DiskImage.py
/gem5/src/dev/Ethernet.py
/gem5/src/dev/Ide.py
/gem5/src/dev/Pci.py
/gem5/src/dev/Platform.py
/gem5/src/dev/SimpleDisk.py
/gem5/src/dev/Terminal.py
/gem5/src/dev/Uart.py
/gem5/src/dev/alpha/AlphaBackdoor.py
/gem5/src/dev/alpha/Tsunami.py
/gem5/src/dev/alpha/tsunami_io.hh
/gem5/src/dev/arm/RealView.py
/gem5/src/dev/arm/pl011.hh
/gem5/src/dev/arm/realview.hh
/gem5/src/dev/arm/timer_cpulocal.hh
/gem5/src/dev/copy_engine.hh
/gem5/src/dev/mips/Malta.py
/gem5/src/dev/mips/malta_io.hh
/gem5/src/dev/sparc/T1000.py
/gem5/src/dev/x86/Cmos.py
/gem5/src/dev/x86/I8042.py
/gem5/src/dev/x86/I82094AA.py
/gem5/src/dev/x86/I8237.py
/gem5/src/dev/x86/I8254.py
/gem5/src/dev/x86/I8259.py
/gem5/src/dev/x86/Pc.py
/gem5/src/dev/x86/PcSpeaker.py
/gem5/src/dev/x86/SouthBridge.py
/gem5/src/dev/x86/X86IntPin.py
/gem5/src/dev/x86/speaker.hh
/gem5/src/mem/AbstractMemory.py
/gem5/src/mem/AddrMapper.py
/gem5/src/mem/Bridge.py
/gem5/src/mem/Bus.py
/gem5/src/mem/CommMonitor.py
/gem5/src/mem/MemObject.py
/gem5/src/mem/SimpleDRAM.py
/gem5/src/mem/SimpleMemory.py
/gem5/src/mem/cache/BaseCache.py
/gem5/src/mem/cache/prefetch/Prefetcher.py
/gem5/src/mem/cache/tags/iic_repl/Repl.py
network/BasicLink.py
network/BasicRouter.py
network/Network.py
network/fault_model/FaultModel.py
network/garnet/BaseGarnetNetwork.py
network/garnet/fixed-pipeline/GarnetLink_d.py
network/garnet/fixed-pipeline/GarnetNetwork_d.py
network/garnet/fixed-pipeline/GarnetRouter_d.py
network/garnet/flexible-pipeline/GarnetLink.py
network/garnet/flexible-pipeline/GarnetNetwork.py
network/garnet/flexible-pipeline/GarnetRouter.py
network/simple/SimpleLink.py
network/simple/SimpleNetwork.py
profiler/Profiler.py
slicc_interface/Controller.py
system/Cache.py
system/DirectoryMemory.py
system/MemoryControl.py
system/RubyMemoryControl.py
system/RubySystem.py
system/Sequencer.py
system/WireBuffer.py
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/python/m5/SimObject.py
/gem5/src/sim/BaseTLB.py
/gem5/src/sim/ClockedObject.py
/gem5/src/sim/InstTracer.py
/gem5/src/sim/Process.py
/gem5/src/sim/Root.py
/gem5/src/sim/System.py
9302:c2e70a9bc340 15-Oct-2012 Nilay Vaish <nilay@cs.wisc.edu>

ruby: improved support for functional accesses
This patch adds support to different entities in the ruby memory system
for more reliable functional read/write accesses. Only the simple network
has been augmented as of now. Later on Garnet will also support functional
accesses.
The patch adds functional access code to all the different types of messages
that protocols can send around. These messages are functionally accessed
by going through the buffers maintained by the network entities.
The patch also rectifies some of the bugs found in coherence protocols while
testing the patch.

With this patch applied, functional writes always succeed. But functional
reads can still fail.


/gem5/configs/example/ruby_mem_test.py
/gem5/src/mem/protocol/MESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MESI_CMP_directory-msg.sm
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MI_example-msg.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-msg.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_token-msg.sm
/gem5/src/mem/protocol/MOESI_hammer-cache.sm
/gem5/src/mem/protocol/MOESI_hammer-dir.sm
/gem5/src/mem/protocol/MOESI_hammer-msg.sm
/gem5/src/mem/protocol/Network_test-msg.sm
/gem5/src/mem/protocol/RubySlicc_Exports.sm
/gem5/src/mem/protocol/RubySlicc_MemControl.sm
buffers/MessageBuffer.cc
buffers/MessageBuffer.hh
buffers/MessageBufferNode.hh
network/Network.hh
network/simple/PerfectSwitch.cc
network/simple/SimpleNetwork.cc
network/simple/SimpleNetwork.hh
network/simple/Switch.cc
network/simple/Switch.hh
slicc_interface/AbstractController.hh
slicc_interface/Message.hh
slicc_interface/NetworkMessage.hh
slicc_interface/RubyRequest.cc
slicc_interface/RubyRequest.hh
slicc_interface/RubySlicc_Util.hh
system/MemoryControl.cc
system/MemoryControl.hh
system/RubyMemoryControl.cc
system/RubyMemoryControl.hh
system/System.cc
/gem5/src/mem/slicc/ast/TypeDeclAST.py
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/mem/slicc/symbols/SymbolTable.py
/gem5/src/mem/slicc/symbols/Type.py
9300:7edfd33b40e2 15-Oct-2012 Nilay Vaish <nilay@cs.wisc.edu>

ruby: register multiple memory controllers
Currently the Ruby System maintains pointer to only one of the memory
controllers. But there can be multiple controllers in the system. This
patch adds a vector of memory controllers.

9299:bfd2ccb8841b 15-Oct-2012 Nilay Vaish <nilay@cs.wisc.edu>

ruby: remove AbstractMemOrCache
The only place where this abstract class is in use is the memory controller,
which it self is an abstract class. Does not seem useful at all.

9297:b6d1e257d488 15-Oct-2012 Nilay Vaish <nilay@cs.wisc.edu>

ruby banked array: do away with event scheduling
It seems unecessary that the BankedArray class needs to schedule an event
to figure out when the access ends. Instead only the time for the end of access
needs to be tracked.

9296:f4ba9a861e65 15-Oct-2012 Nilay Vaish <nilay@cs.wisc.edu>

ruby: reset timing after cache warm up
Ruby system was recently converted to a clocked object. Such objects maintain
state related to the time that has passed so far. During the cache warmup, Ruby
system changes its own time and the global time. Later on, the global time is
restored. So Ruby system also needs to reset its own time.

9294:8fb03b13de02 15-Oct-2012 Andreas Hansson <andreas.hansson@arm.com>

Port: Add protocol-agnostic ports in the port hierarchy

This patch adds an additional level of ports in the inheritance
hierarchy, separating out the protocol-specific and protocl-agnostic
parts. All the functionality related to the binding of ports is now
confined to use BaseMaster/BaseSlavePorts, and all the
protocol-specific parts stay in the Master/SlavePort. In the future it
will be possible to add other protocol-specific implementations.

The functions used in the binding of ports, i.e. getMaster/SlavePort
now use the base classes, and the index parameter is updated to use
the PortID typedef with the symbolic InvalidPortID as the default.


/gem5/src/arch/arm/table_walker.cc
/gem5/src/arch/arm/table_walker.hh
/gem5/src/arch/arm/tlb.cc
/gem5/src/arch/arm/tlb.hh
/gem5/src/arch/x86/interrupts.hh
/gem5/src/arch/x86/pagetable_walker.cc
/gem5/src/arch/x86/pagetable_walker.hh
/gem5/src/arch/x86/tlb.cc
/gem5/src/arch/x86/tlb.hh
/gem5/src/cpu/base.cc
/gem5/src/cpu/base.hh
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.cc
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.hh
/gem5/src/cpu/testers/memtest/memtest.cc
/gem5/src/cpu/testers/memtest/memtest.hh
/gem5/src/cpu/testers/networktest/networktest.cc
/gem5/src/cpu/testers/networktest/networktest.hh
/gem5/src/cpu/testers/rubytest/RubyTester.cc
/gem5/src/cpu/testers/rubytest/RubyTester.hh
/gem5/src/cpu/testers/traffic_gen/traffic_gen.cc
/gem5/src/cpu/testers/traffic_gen/traffic_gen.hh
/gem5/src/dev/copy_engine.cc
/gem5/src/dev/copy_engine.hh
/gem5/src/dev/dma_device.cc
/gem5/src/dev/dma_device.hh
/gem5/src/dev/io_device.cc
/gem5/src/dev/io_device.hh
/gem5/src/dev/pcidev.hh
/gem5/src/dev/x86/i82094aa.hh
/gem5/src/mem/addr_mapper.cc
/gem5/src/mem/addr_mapper.hh
/gem5/src/mem/bridge.cc
/gem5/src/mem/bridge.hh
/gem5/src/mem/bus.cc
/gem5/src/mem/bus.hh
/gem5/src/mem/cache/base.cc
/gem5/src/mem/cache/base.hh
/gem5/src/mem/comm_monitor.cc
/gem5/src/mem/comm_monitor.hh
/gem5/src/mem/mem_object.cc
/gem5/src/mem/mem_object.hh
/gem5/src/mem/port.cc
/gem5/src/mem/port.hh
system/RubyPort.cc
system/RubyPort.hh
/gem5/src/mem/simple_dram.cc
/gem5/src/mem/simple_dram.hh
/gem5/src/mem/simple_mem.cc
/gem5/src/mem/simple_mem.hh
/gem5/src/python/swig/pyobject.cc
/gem5/src/sim/system.cc
/gem5/src/sim/system.hh
/gem5/src/sim/tlb.hh
9275:ef43e69c837a 02-Oct-2012 Nilay Vaish <nilay@cs.wisc.edu>

ruby: makes some members non-static
This patch makes some of the members (profiler, network, memory vector)
of ruby system non-static.

9274:ba635023d4bb 02-Oct-2012 Nilay Vaish <nilay@cs.wisc.edu>

ruby: changes to simple network
This patch makes the Switch structure inherit from BasicRouter, as is
done in two other networks.

9270:92aad0e984ff 02-Oct-2012 Nilay Vaish <nilay@cs.wisc.edu>

ruby: move functional access to ruby system
This patch moves the code for functional accesses to ruby system. This is
because the subsequent patches add support for making functional accesses
to the messages in the interconnect. Making those accesses from the ruby port
would be cumbersome.

9245:e215ee9db617 23-Sep-2012 Joel Hestness <hestness@cs.wisc.edu>

RubyPort and Sequencer: Fix draining

Fix the drain functionality of the RubyPort to only call drain on child ports
during a system-wide drain process, instead of calling each time that a
ruby_hit_callback is executed.

This fixes the issue of the RubyPort ports being reawakened during the drain
simulation, possibly with work they didn't previously have to complete. If
they have new work, they may call process on the drain event that they had
not registered work for, causing an assertion failure when completing the
drain event.

Also, in RubyPort, set the drainEvent to NULL when there are no events
to be drained. If not set to NULL, the drain loop can result in stale
drainEvents used.

9231:cecc64db9b3b 18-Sep-2012 Nilay Vaish <nilay@cs.wisc.edu>

ruby: eliminate typedef integer_t

9230:33eb3c8a98b9 18-Sep-2012 Nilay Vaish <nilay@cs.wisc.edu>

ruby: avoid using g_system_ptr for event scheduling
This patch removes the use of g_system_ptr for event scheduling. Each consumer
object now needs to specify upfront an EventManager object it would use for
scheduling events. This makes the ruby memory system more amenable for a
multi-threaded simulation.

9224:b0539d08bda8 14-Sep-2012 Andreas Hansson <andreas.hansson@arm.com>

scons: Use c++0x with gcc >= 4.4 instead of 4.6

This patch shifts the version of gcc for which we enable c++0x from
4.6 to 4.4 The more long term plan is to see what the c++0x features
can bring and what level of support would be enabled simply by bumping
the required version of gcc from 4.3 to 4.4.

A few minor things had to be fixed in the code base, most notably the
choice of a hashmap implementation. In the Ruby Sequencer there were
also a few minor issues that gcc 4.4 was not too happy about.

9216:a5f937d152bf 11-Sep-2012 Andreas Hansson <andreas.hansson@arm.com>

clang: Fix issues identified by the clang static analyzer

This patch addresses a few minor issues reported by the clang static
analyzer.

The analysis was run with:

scan-build -disable-checker deadcode \
-enable-checker experimental.core \
-disable-checker experimental.core.CastToStruct \
-enable-checker experimental.cpluscplus

9209:f9633070689b 11-Sep-2012 Nilay Vaish <nilay@cs.wisc.edu>

Ruby: Use uint32_t instead of uint32 everywhere

9208:2451e60d4555 11-Sep-2012 Nilay Vaish <nilay@cs.wisc.edu>

Ruby: Use uint8_t instead of uint8 everywhere

9206:f6483789d23a 10-Sep-2012 Nilay Vaish <nilay@cs.wisc.edu>

Ruby System: Convert to Clocked Object
This patch moves Ruby System from being a SimObject to recently introduced
ClockedObject.

9184:a1a8f137b796 07-Sep-2012 Andreas Hansson <andreas.hansson@arm.com>

Param: Transition to Cycles for relevant parameters

This patch is a first step to using Cycles as a parameter type. The
main affected modules are the CPUs and the Ruby caches. There are
definitely plenty more places that are affected, but this patch serves
as a starting point to making the transition.

An important part of this patch is to actually enable parameters to be
specified as Param.Cycles which involves some changes to params.py.

9182:43da8ae0f36e 05-Sep-2012 Joel Hestness <hestness@cs.wisc.edu>

Ruby Memory Controller: Fix clocking

9181:42807286d6cb 28-Aug-2012 Jason Power <power.jg@gmail.com>

Ruby: Correct DataBlock =operator
The =operator for the DataBlock class was incorrectly interpreting the class
member m_alloc. This variable stands for whether the assigned memory for the
data block needs to be freed or not by the class itself. It seems that the
=operator interpreted the variable as whether the memory is assigned to the
data block. This wrong interpretation was causing values not to propagate
to RubySystem::m_mem_vec_ptr. This caused major issues with restoring from
checkpoints when using a protocol which verified that the cache data was
consistent with the backing store (i.e. MOESI-hammer).

9173:631daf17b0be 27-Aug-2012 Nilay Vaish <nilay@cs.wisc.edu>

Ruby: remove README.debugging and Decommissioning_note
These files were relevant when Ruby was part of GEMS. They are not required
any longer.

9171:ae88ecf37145 27-Aug-2012 Nilay Vaish <nilay@cs.wisc.edu>

Ruby: Remove RubyEventQueue
This patch removes RubyEventQueue. Consumer objects now rely on RubySystem
or themselves for scheduling events.


/gem5/src/cpu/testers/directedtest/RubyDirectedTester.cc
/gem5/src/cpu/testers/rubytest/Check.cc
/gem5/src/cpu/testers/rubytest/RubyTester.cc
buffers/MessageBuffer.cc
buffers/MessageBuffer.hh
common/Consumer.cc
common/Consumer.hh
common/Global.cc
common/Global.hh
common/SConscript
common/TypeDefines.hh
eventqueue/RubyEventQueue.cc
eventqueue/RubyEventQueue.hh
eventqueue/RubyEventQueueNode.cc
eventqueue/RubyEventQueueNode.hh
eventqueue/SConscript
network/garnet/BaseGarnetNetwork.cc
network/garnet/fixed-pipeline/GarnetNetwork_d.cc
network/garnet/fixed-pipeline/InputUnit_d.cc
network/garnet/fixed-pipeline/InputUnit_d.hh
network/garnet/fixed-pipeline/NetworkInterface_d.cc
network/garnet/fixed-pipeline/NetworkLink_d.cc
network/garnet/fixed-pipeline/OutVcState_d.cc
network/garnet/fixed-pipeline/OutputUnit_d.cc
network/garnet/fixed-pipeline/OutputUnit_d.hh
network/garnet/fixed-pipeline/Router_d.cc
network/garnet/fixed-pipeline/SWallocator_d.cc
network/garnet/fixed-pipeline/Switch_d.cc
network/garnet/fixed-pipeline/VCallocator_d.cc
network/garnet/fixed-pipeline/VirtualChannel_d.cc
network/garnet/fixed-pipeline/VirtualChannel_d.hh
network/garnet/fixed-pipeline/flitBuffer_d.cc
network/garnet/fixed-pipeline/flit_d.cc
network/garnet/fixed-pipeline/flit_d.hh
network/garnet/flexible-pipeline/GarnetNetwork.cc
network/garnet/flexible-pipeline/NetworkInterface.cc
network/garnet/flexible-pipeline/NetworkLink.cc
network/garnet/flexible-pipeline/Router.cc
network/garnet/flexible-pipeline/flit.cc
network/garnet/flexible-pipeline/flitBuffer.cc
network/orion/NetworkPower.cc
network/simple/PerfectSwitch.cc
network/simple/Throttle.cc
profiler/Profiler.cc
profiler/Profiler.hh
profiler/StoreTrace.cc
profiler/StoreTrace.hh
slicc_interface/Message.hh
slicc_interface/RubySlicc_Util.hh
system/CacheMemory.cc
system/CacheMemory.hh
system/RubyMemoryControl.cc
system/RubyPort.cc
system/Sequencer.cc
system/Sequencer.hh
system/System.cc
system/System.hh
system/TimerTable.cc
system/TimerTable.hh
system/WireBuffer.cc
system/WireBuffer.hh
/gem5/src/mem/slicc/ast/AST.py
/gem5/src/mem/slicc/ast/FuncCallExprAST.py
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/mem/slicc/symbols/Type.py
9170:88d422d737db 27-Aug-2012 Nilay Vaish <nilay@cs.wisc.edu>

Ruby Memory Vector: Allow more than 4GB of memory
The memory size variable was a 32-bit int. This meant that the size of the
memory was limited to 4GB. This patch changes the type of the variable to
64-bit to support larger memory sizes. Thanks to Raghuraman Balasubramanian
for bringing this to notice.

9163:3b5e13ac1940 22-Aug-2012 Andreas Hansson <andreas.hansson@arm.com>

Port: Extend the QueuedPort interface and use where appropriate

This patch extends the queued port interfaces with methods for
scheduling the transmission of a timing request/response. The methods
are named similar to the corresponding sendTiming(Snoop)Req/Resp,
replacing the "send" with "sched". As the queues are currently
unbounded, the methods always succeed and hence do not return a value.

This functionality was previously provided in the subclasses by
calling PacketQueue::schedSendTiming with the appropriate
parameters. With this change, there is no need to introduce these
extra methods in the subclasses, and the use of the queued interface
is more uniform and explicit.

9155:4c67c26fa76e 19-Aug-2012 Nilay Vaish <nilay@cs.wisc.edu>

Ruby Banked Array: add copyrights

9154:198352d722e4 17-Aug-2012 Jason Power <power.jg@gmail.com>

Ruby: Add RubySystem parameter to MemoryControl
This guarantees that RubySystem object is created before the MemoryController
object is created.

9152:86c0e6ca5e7c 15-Aug-2012 Anthony Gutierrez <atgutier@umich.edu>

O3,ARM: fix some problems with drain/switchout functionality and add Drain DPRINTFs

This patch fixes some problems with the drain/switchout functionality
for the O3 cpu and for the ARM ISA and adds some useful debug print
statements.

This is an incremental fix as there are still a few bugs/mem leaks with the
switchout code. Particularly when switching from an O3CPU to a
TimingSimpleCPU. However, when switching from O3 to O3 cores with the ARM ISA
I haven't encountered any more assertion failures; now the kernel will
typically panic inside of simulation.

9148:a7a72f42919e 10-Aug-2012 Jason Power <powerjg@cs.wisc.edu>

Ruby: Clean up topology changes
This patch moves instantiateTopology into Ruby.py and removes the
mem/ruby/network/topologies directory. It also adds some extra inheritance to
the topologies to clean up some issues in the existing topologies.

9138:b4d0bdb52694 01-Aug-2012 Jason Power <powerjg@cs.wisc.edu>

Ruby NetDest: add assert for bad element in netdest

9117:49116b947194 12-Jul-2012 Nilay Vaish <nilay@cs.wisc.edu>

Ruby: remove config information from ruby.stats
This patch removes printConfig() functions from all structures in Ruby.
Most of the information is already part of config.ini, and where ever it
is not, it would become in due course.


buffers/MessageBuffer.hh
filters/GenericBloomFilter.hh
network/Network.hh
network/Topology.cc
network/Topology.hh
network/garnet/fixed-pipeline/GarnetNetwork_d.cc
network/garnet/fixed-pipeline/GarnetNetwork_d.hh
network/garnet/fixed-pipeline/InputUnit_d.cc
network/garnet/fixed-pipeline/InputUnit_d.hh
network/garnet/fixed-pipeline/NetworkInterface_d.cc
network/garnet/fixed-pipeline/NetworkInterface_d.hh
network/garnet/fixed-pipeline/OutputUnit_d.cc
network/garnet/fixed-pipeline/OutputUnit_d.hh
network/garnet/fixed-pipeline/Router_d.cc
network/garnet/fixed-pipeline/Router_d.hh
network/garnet/flexible-pipeline/GarnetNetwork.cc
network/garnet/flexible-pipeline/GarnetNetwork.hh
network/garnet/flexible-pipeline/NetworkInterface.cc
network/garnet/flexible-pipeline/NetworkInterface.hh
network/garnet/flexible-pipeline/Router.cc
network/garnet/flexible-pipeline/Router.hh
network/simple/PerfectSwitch.cc
network/simple/PerfectSwitch.hh
network/simple/SimpleNetwork.cc
network/simple/SimpleNetwork.hh
network/simple/Switch.cc
network/simple/Switch.hh
network/simple/Throttle.cc
network/simple/Throttle.hh
profiler/Profiler.cc
profiler/Profiler.hh
slicc_interface/AbstractController.hh
system/AbstractMemOrCache.hh
system/CacheMemory.cc
system/CacheMemory.hh
system/DMASequencer.cc
system/DMASequencer.hh
system/DirectoryMemory.cc
system/DirectoryMemory.hh
system/MemoryControl.cc
system/MemoryControl.hh
system/PerfectCacheMemory.hh
system/PersistentTable.hh
system/RubyMemoryControl.cc
system/RubyMemoryControl.hh
system/Sequencer.cc
system/Sequencer.hh
system/SparseMemory.hh
system/System.cc
system/System.hh
system/TBETable.hh
system/TimerTable.hh
system/WireBuffer.cc
system/WireBuffer.hh
9116:9171e26543fa 12-Jul-2012 Nilay Vaish <nilay@cs.wisc.edu>

Ruby: remove some unused stuff from SLICC files

9114:8b0ce484dfdc 11-Jul-2012 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: improved DRAM reset comment

9109:6bce09259194 11-Jul-2012 Brad Beckmann <Brad.Beckmann@amd.com>

# User Brad Beckmann <Brad.Beckmann@amd.com>
ruby: fixed fatal print statement

9107:66b2e1ce53da 11-Jul-2012 Brad Beckmann <Brad.Beckmann@amd.com>

# User Brad Beckmann <Brad.Beckmann@amd.com>
ruby: fixed msgptr print call

9105:b576c490e7d1 11-Jul-2012 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: banked cache array resource model

This patch models a cache as separate tag and data arrays. The patch exposes
the banked array as another resource that is checked by SLICC before a
transition is allowed to execute. This is similar to how TBE entries and slots
in output ports are modeled.

9104:27d56b644e78 11-Jul-2012 Joel Hestness <hestness@cs.utexas.edu>

ruby: tag and data cache access support

Updates to Ruby to support statistics counting of cache accesses. This feature
serves multiple purposes beyond simple stats collection. It provides the
foundation for ruby to model the cache tag and data arrays as physical
resources, as well as provide the necessary input data for McPAT power
modeling.

9103:956796e06b7f 11-Jul-2012 Nuwan Jayasena <Nuwan.Jayasena@amd.com>

ruby: adds reset function to Ruby memory controllers

9102:5464eb9a684b 11-Jul-2012 Nuwan Jayasena <Nuwan.Jayasena@amd.com>

ruby: memory controllers now inherit from an abstract "MemoryControl" class

9100:3caf131d7a95 11-Jul-2012 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: changes how Topologies are created

Instead of just passing a list of controllers to the makeTopology function
in src/mem/ruby/network/topologies/<Topo>.py we pass in a function pointer
which knows how to make the topology, possibly with some extra state set
in the configs/ruby/<protocol>.py file. Thus, we can move all of the files
from network/topologies to configs/topologies. A new class BaseTopology
is added which all topologies in configs/topologies must inheirit from and
follow its API.

9090:e4e22240398f 09-Jul-2012 Andreas Hansson <andreas.hansson@arm.com>

Port: Make getAddrRanges const

This patch makes getAddrRanges const throughout the code base. There
is no reason why it should not be, and making it const prevents adding
any unintentional side-effects.

9088:73eeda352933 09-Jul-2012 Andreas Hansson <andreas.hansson@arm.com>

Port: Add isSnooping to slave port (asking master port)

This patch adds isSnooping to the slave port, and thus avoids going
through getMasterPort to be able to ask the master. Over the course of
the next few patches, all getMasterPort/getSlavePort in Port and
MemObject are to be protocol agnostic, and the snooping is part of the
protocol layer.

The function is already present on the master port, where it is
implemented by the module itself, e.g. a cache. On the slave side, it
is merely asking the connected master port. The same name is used by
both functions despite their difference in behaviour. The initial
design used isMasterSnooping on the slave port side, but the more
verbose function name was later changed.

9012:6d64aa6a26af 22-May-2012 Nilay Vaish <nilay@cs.wisc.edu>

Ruby: Remove the unused src/mem/ruby/common/Driver.* files.

9011:52574306c576 22-May-2012 Nilay Vaish <nilay@cs.wisc.edu>

Ruby Sequencer: Schedule deadlock check event at correct time
The scheduling of the deadlock check event was being done incorrectly as the
clock was not being multiplied, so as to convert the time into ticks. This
patch removes that bug.

8978:4388495beb44 04-May-2012 Andreas Hansson <andreas.hansson@arm.com>

Ruby: Ensure snoop requests are sent using sendTimingSnoopReq

This patch fixes a bug that caused snoop requests to be placed in a
packet queue. Instead, the packet is now sent immediately using
sendTimingSnoopReq, thus bypassing the packet queue and any normal
responses waiting to be sent.

8975:7f36d4436074 01-May-2012 Andreas Hansson <andreas.hansson@arm.com>

MEM: Separate requests and responses for timing accesses

This patch moves send/recvTiming and send/recvTimingSnoop from the
Port base class to the MasterPort and SlavePort, and also splits them
into separate member functions for requests and responses:
send/recvTimingReq, send/recvTimingResp, and send/recvTimingSnoopReq,
send/recvTimingSnoopResp. A master port sends requests and receives
responses, and also receives snoop requests and sends snoop
responses. A slave port has the reciprocal behaviour as it receives
requests and sends responses, and sends snoop requests and receives
snoop responses.

For all MemObjects that have only master ports or slave ports (but not
both), e.g. a CPU, or a PIO device, this patch merely adds more
clarity to what kind of access is taking place. For example, a CPU
port used to call sendTiming, and will now call
sendTimingReq. Similarly, a response previously came back through
recvTiming, which is now recvTimingResp. For the modules that have
both master and slave ports, e.g. the bus, the behaviour was
previously relying on branches based on pkt->isRequest(), and this is
now replaced with a direct call to the apprioriate member function
depending on the type of access. Please note that send/recvRetry is
still shared by all the timing accessors and remains in the Port base
class for now (to maintain the current bus functionality and avoid
changing the statistics of all regressions).

The packet queue is split into a MasterPort and SlavePort version to
facilitate the use of the new timing accessors. All uses of the
PacketQueue are updated accordingly.

With this patch, the type of packet (request or response) is now well
defined for each type of access, and asserts on pkt->isRequest() and
pkt->isResponse() are now moved to the appropriate send member
functions. It is also worth noting that sendTimingSnoopReq no longer
returns a boolean, as the semantics do not alow snoop requests to be
rejected or stalled. All these assumptions are now excplicitly part of
the port interface itself.


/gem5/src/arch/x86/pagetable_walker.cc
/gem5/src/arch/x86/pagetable_walker.hh
/gem5/src/cpu/base.cc
/gem5/src/cpu/base.hh
/gem5/src/cpu/inorder/cpu.cc
/gem5/src/cpu/inorder/cpu.hh
/gem5/src/cpu/inorder/resources/cache_unit.cc
/gem5/src/cpu/o3/cpu.cc
/gem5/src/cpu/o3/cpu.hh
/gem5/src/cpu/o3/fetch_impl.hh
/gem5/src/cpu/o3/lsq.hh
/gem5/src/cpu/o3/lsq_impl.hh
/gem5/src/cpu/o3/lsq_unit.hh
/gem5/src/cpu/o3/lsq_unit_impl.hh
/gem5/src/cpu/simple/timing.cc
/gem5/src/cpu/simple/timing.hh
/gem5/src/cpu/testers/directedtest/InvalidateGenerator.cc
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.cc
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.hh
/gem5/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
/gem5/src/cpu/testers/memtest/memtest.cc
/gem5/src/cpu/testers/memtest/memtest.hh
/gem5/src/cpu/testers/networktest/networktest.cc
/gem5/src/cpu/testers/networktest/networktest.hh
/gem5/src/cpu/testers/rubytest/Check.cc
/gem5/src/cpu/testers/rubytest/RubyTester.cc
/gem5/src/cpu/testers/rubytest/RubyTester.hh
/gem5/src/dev/io_device.cc
/gem5/src/dev/io_device.hh
/gem5/src/mem/bridge.cc
/gem5/src/mem/bridge.hh
/gem5/src/mem/bus.cc
/gem5/src/mem/bus.hh
/gem5/src/mem/cache/base.hh
/gem5/src/mem/cache/cache.hh
/gem5/src/mem/cache/cache_impl.hh
/gem5/src/mem/mport.hh
/gem5/src/mem/packet_queue.cc
/gem5/src/mem/packet_queue.hh
/gem5/src/mem/port.cc
/gem5/src/mem/port.hh
/gem5/src/mem/qport.hh
system/RubyPort.cc
system/RubyPort.hh
/gem5/src/mem/tport.cc
/gem5/src/mem/tport.hh
/gem5/src/sim/system.hh
8970:1fc1256d5798 28-Apr-2012 Nilay Vaish <nilay@cs.wisc.edu>

Garnet: Correct computation of link utilization
The computation for link utilization was incorrect for the flexible network.
The utilization was being divided twice by the total time.

8967:fc2c4db64ded 25-Apr-2012 Nilay Vaish <nilay@cs.wisc.edu>

Ruby: Remove extra statements from Sequencer

8949:3fa1ee293096 14-Apr-2012 Andreas Hansson <andreas.hansson@arm.com>

MEM: Remove the Broadcast destination from the packet

This patch simplifies the packet by removing the broadcast flag and
instead more firmly relying on (and enforcing) the semantics of
transactions in the classic memory system, i.e. request packets are
routed from a master to a slave based on the address, and when they
are created they have neither a valid source, nor destination. On
their way to the slave, the request packet is updated with a source
field for all modules that multiplex packets from multiple master
(e.g. a bus). When a request packet is turned into a response packet
(at the final slave), it moves the potentially populated source field
to the destination field, and the response packet is routed through
any multiplexing components back to the master based on the
destination field.

Modules that connect multiplexing components, such as caches and
bridges store any existing source and destination field in the sender
state as a stack (just as before).

The packet constructor is simplified in that there is no longer a need
to pass the Packet::Broadcast as the destination (this was always the
case for the classic memory system). In the case of Ruby, rather than
using the parameter to the constructor we now rely on setDest, as
there is already another three-argument constructor in the packet
class.

In many places where the packet information was printed as part of
DPRINTFs, request packets would be printed with a numeric "dest" that
would always be -1 (Broadcast) and that field is now removed from the
printing.

8948:e95ee70f876c 14-Apr-2012 Andreas Hansson <andreas.hansson@arm.com>

MEM: Separate snoops and normal memory requests/responses

This patch introduces port access methods that separates snoop
request/responses from normal memory request/responses. The
differentiation is made for functional, atomic and timing accesses and
builds on the introduction of master and slave ports.

Before the introduction of this patch, the packets belonging to the
different phases of the protocol (request -> [forwarded snoop request
-> snoop response]* -> response) all use the same port access
functions, even though the snoop packets flow in the opposite
direction to the normal packet. That is, a coherent master sends
normal request and receives responses, but receives snoop requests and
sends snoop responses (vice versa for the slave). These two distinct
phases now use different access functions, as described below.

Starting with the functional access, a master sends a request to a
slave through sendFunctional, and the request packet is turned into a
response before the call returns. In a system without cache coherence,
this is all that is needed from the functional interface. For the
cache-coherent scenario, a slave also sends snoop requests to coherent
masters through sendFunctionalSnoop, with responses returned within
the same packet pointer. This is currently used by the bus and caches,
and the LSQ of the O3 CPU. The send/recvFunctional and
send/recvFunctionalSnoop are moved from the Port super class to the
appropriate subclass.

Atomic accesses follow the same flow as functional accesses, with
request being sent from master to slave through sendAtomic. In the
case of cache-coherent ports, a slave can send snoop requests to a
master through sendAtomicSnoop. Just as for the functional access
methods, the atomic send and receive member functions are moved to the
appropriate subclasses.

The timing access methods are different from the functional and atomic
in that requests and responses are separated in time and
send/recvTiming are used for both directions. Hence, a master uses
sendTiming to send a request to a slave, and a slave uses sendTiming
to send a response back to a master, at a later point in time. Snoop
requests and responses travel in the opposite direction, similar to
what happens in functional and atomic accesses. With the introduction
of this patch, it is possible to determine the direction of packets in
the bus, and no longer necessary to look for both a master and a slave
port with the requested port id.

In contrast to the normal recvFunctional, recvAtomic and recvTiming
that are pure virtual functions, the recvFunctionalSnoop,
recvAtomicSnoop and recvTimingSnoop have a default implementation that
calls panic. This is to allow non-coherent master and slave ports to
not implement these functions.

8946:fb6c89334b86 14-Apr-2012 Andreas Hansson <andreas.hansson@arm.com>

clang/gcc: Fix compilation issues with clang 3.0 and gcc 4.6

This patch addresses a number of minor issues that cause problems when
compiling with clang >= 3.0 and gcc >= 4.6. Most importantly, it
avoids using the deprecated ext/hash_map and instead uses
unordered_map (and similarly so for the hash_set). To make use of the
new STL containers, g++ and clang has to be invoked with "-std=c++0x",
and this is now added for all gcc versions >= 4.6, and for clang >=
3.0. For gcc >= 4.3 and <= 4.5 and clang <= 3.0 we use the tr1
unordered_map to avoid the deprecation warning.

The addition of c++0x in turn causes a few problems, as the
compiler is more stringent and adds a number of new warnings. Below,
the most important issues are enumerated:

1) the use of namespaces is more strict, e.g. for isnan, and all
headers opening the entire namespace std are now fixed.

2) another other issue caused by the more stringent compiler is the
narrowing of the embedded python, which used to be a char array,
and is now unsigned char since there were values larger than 128.

3) a particularly odd issue that arose with the new c++0x behaviour is
found in range.hh, where the operator< causes gcc to complain about
the template type parsing (the "<" is interpreted as the beginning
of a template argument), and the problem seems to be related to the
begin/end members introduced for the range-type iteration, which is
a new feature in c++11.

As a minor update, this patch also fixes the build flags for the clang
debug target that used to be shared with gcc and incorrectly use
"-ggdb".

8943:f954ee138ca3 12-Apr-2012 Andreas Hansson <andreas.hansson@arm.com>

Ruby: Ensure order-dependent iteration uses an ordered map

This patch fixes a bug in Ruby that caused non-deterministic
simulation when changing the underlying hash map implementation. The
reason is order-dependent behaviour in combination with iteration over
the hash map contents. The two locations where a sorted container is
assumed are now changed to make use of a std::map instead of the
unordered hash map.

With this change, the stats changes slightly and the follow-on
changeset will update the relevant statistics.

8937:225590437eb2 06-Apr-2012 Brad Beckmann <Brad.Beckmann@amd.com>

sim-ruby: checkpointing fixes and dependent eventq improvements

Fixes checkpointing with respect to lost events after swapping event queues.
Also adds DPRINTFs to better understand what's going on when Ruby serializes
and unserializes.

8932:1b2c17565ac8 06-Apr-2012 Brad Beckmann <Brad.Beckmann@amd.com>

rubytest: seperated read and write ports.

This patch allows the ruby tester to support protocols where the i-cache and d-cache
are managed by seperate controllers.

8931:7a1dfb191e3f 06-Apr-2012 Andreas Hansson <andreas.hansson@arm.com>

MEM: Enable multiple distributed generalized memories

This patch removes the assumption on having on single instance of
PhysicalMemory, and enables a distributed memory where the individual
memories in the system are each responsible for a single contiguous
address range.

All memories inherit from an AbstractMemory that encompasses the basic
behaviuor of a random access memory, and provides untimed access
methods. What was previously called PhysicalMemory is now
SimpleMemory, and a subclass of AbstractMemory. All future types of
memory controllers should inherit from AbstractMemory.

To enable e.g. the atomic CPU and RubyPort to access the now
distributed memory, the system has a wrapper class, called
PhysicalMemory that is aware of all the memories in the system and
their associated address ranges. This class thus acts as an
infinitely-fast bus and performs address decoding for these "shortcut"
accesses. Each memory can specify that it should not be part of the
global address map (used e.g. by the functional memories by some
testers). Moreover, each memory can be configured to be reported to
the OS configuration table, useful for populating ATAG structures, and
any potential ACPI tables.

Checkpointing support currently assumes that all memories have the
same size and organisation when creating and resuming from the
checkpoint. A future patch will enable a more flexible
re-organisation.


/gem5/configs/common/FSConfig.py
/gem5/configs/example/memtest.py
/gem5/configs/example/ruby_direct_test.py
/gem5/configs/example/ruby_mem_test.py
/gem5/configs/example/ruby_network_test.py
/gem5/configs/example/ruby_random_test.py
/gem5/configs/example/se.py
/gem5/configs/ruby/MESI_CMP_directory.py
/gem5/configs/ruby/MI_example.py
/gem5/configs/ruby/MOESI_CMP_directory.py
/gem5/configs/ruby/MOESI_CMP_token.py
/gem5/configs/ruby/MOESI_hammer.py
/gem5/configs/ruby/Network_test.py
/gem5/configs/ruby/Ruby.py
/gem5/configs/splash2/cluster.py
/gem5/configs/splash2/run.py
/gem5/src/arch/alpha/remote_gdb.cc
/gem5/src/arch/alpha/remote_gdb.hh
/gem5/src/arch/arm/ArmSystem.py
/gem5/src/arch/arm/linux/system.cc
/gem5/src/arch/arm/remote_gdb.hh
/gem5/src/arch/arm/system.cc
/gem5/src/arch/mips/remote_gdb.hh
/gem5/src/arch/sparc/SparcSystem.py
/gem5/src/arch/sparc/remote_gdb.hh
/gem5/src/base/remote_gdb.cc
/gem5/src/base/remote_gdb.hh
/gem5/src/cpu/checker/thread_context.hh
/gem5/src/cpu/inorder/thread_context.hh
/gem5/src/cpu/o3/fetch_impl.hh
/gem5/src/cpu/ozone/cpu.hh
/gem5/src/cpu/simple/atomic.cc
/gem5/src/cpu/simple/atomic.hh
/gem5/src/dev/alpha/backdoor.cc
/gem5/src/dev/arm/RealView.py
/gem5/src/dev/ide_disk.hh
/gem5/src/mem/AbstractMemory.py
/gem5/src/mem/PhysicalMemory.py
/gem5/src/mem/SConscript
/gem5/src/mem/SimpleMemory.py
/gem5/src/mem/abstract_mem.cc
/gem5/src/mem/abstract_mem.hh
/gem5/src/mem/cache/mshr.cc
/gem5/src/mem/physical.cc
/gem5/src/mem/physical.hh
system/RubyPort.cc
/gem5/src/mem/simple_mem.cc
/gem5/src/mem/simple_mem.hh
/gem5/src/sim/System.py
/gem5/src/sim/system.cc
/gem5/src/sim/system.hh
/gem5/tests/configs/inorder-timing.py
/gem5/tests/configs/memtest-ruby.py
/gem5/tests/configs/memtest.py
/gem5/tests/configs/o3-timing-checker.py
/gem5/tests/configs/o3-timing-mp.py
/gem5/tests/configs/o3-timing.py
/gem5/tests/configs/rubytest-ruby.py
/gem5/tests/configs/simple-atomic-dummychecker.py
/gem5/tests/configs/simple-atomic-mp.py
/gem5/tests/configs/simple-atomic.py
/gem5/tests/configs/simple-timing-mp-ruby.py
/gem5/tests/configs/simple-timing-mp.py
/gem5/tests/configs/simple-timing-ruby.py
/gem5/tests/configs/simple-timing.py
8923:820111f58fbb 30-Mar-2012 Andreas Hansson <andreas.hansson@arm.com>

Ruby: Remove the physMemPort and instead access memory directly

This patch removes the physMemPort from the RubySequencer and instead
uses the system pointer to access the physmem. The system already
keeps track of the physmem and the valid memory address ranges, and
with this patch we merely make use of that existing functionality. The
memory is modified so that it is possible to call the access functions
(atomic and functional) without going through the port, and the memory
is allowed to be unconnected, i.e. have no ports (since Ruby does not
attach it like the conventional memory system).

8922:17f037ad8918 30-Mar-2012 William Wang <william.wang@arm.com>

MEM: Introduce the master/slave port sub-classes in C++

This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.

The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.

The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.

The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.


/gem5/src/arch/arm/table_walker.cc
/gem5/src/arch/arm/table_walker.hh
/gem5/src/arch/arm/tlb.cc
/gem5/src/arch/arm/tlb.hh
/gem5/src/arch/x86/interrupts.cc
/gem5/src/arch/x86/interrupts.hh
/gem5/src/arch/x86/pagetable_walker.cc
/gem5/src/arch/x86/pagetable_walker.hh
/gem5/src/arch/x86/tlb.cc
/gem5/src/arch/x86/tlb.hh
/gem5/src/cpu/base.cc
/gem5/src/cpu/base.hh
/gem5/src/cpu/checker/cpu.hh
/gem5/src/cpu/inorder/resources/cache_unit.hh
/gem5/src/cpu/o3/cpu.hh
/gem5/src/cpu/o3/lsq_unit.hh
/gem5/src/cpu/o3/lsq_unit_impl.hh
/gem5/src/cpu/ozone/OzoneCPU.py
/gem5/src/cpu/ozone/cpu.hh
/gem5/src/cpu/ozone/cpu_impl.hh
/gem5/src/cpu/ozone/front_end.hh
/gem5/src/cpu/ozone/front_end_impl.hh
/gem5/src/cpu/ozone/lw_lsq.hh
/gem5/src/cpu/ozone/lw_lsq_impl.hh
/gem5/src/cpu/simple/atomic.cc
/gem5/src/cpu/simple/atomic.hh
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.cc
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.hh
/gem5/src/cpu/testers/memtest/memtest.cc
/gem5/src/cpu/testers/memtest/memtest.hh
/gem5/src/cpu/testers/networktest/networktest.cc
/gem5/src/cpu/testers/networktest/networktest.hh
/gem5/src/cpu/testers/rubytest/RubyTester.cc
/gem5/src/cpu/testers/rubytest/RubyTester.hh
/gem5/src/dev/copy_engine.cc
/gem5/src/dev/copy_engine.hh
/gem5/src/dev/io_device.cc
/gem5/src/dev/io_device.hh
/gem5/src/dev/pcidev.hh
/gem5/src/dev/x86/i82094aa.cc
/gem5/src/dev/x86/i82094aa.hh
/gem5/src/dev/x86/intdev.cc
/gem5/src/dev/x86/intdev.hh
/gem5/src/kern/tru64/tru64_events.cc
/gem5/src/mem/bridge.cc
/gem5/src/mem/bridge.hh
/gem5/src/mem/bus.cc
/gem5/src/mem/bus.hh
/gem5/src/mem/cache/base.cc
/gem5/src/mem/cache/base.hh
/gem5/src/mem/cache/builder.cc
/gem5/src/mem/cache/cache.hh
/gem5/src/mem/cache/cache_impl.hh
/gem5/src/mem/fs_translating_port_proxy.cc
/gem5/src/mem/fs_translating_port_proxy.hh
/gem5/src/mem/mem_object.cc
/gem5/src/mem/mem_object.hh
/gem5/src/mem/mport.cc
/gem5/src/mem/mport.hh
/gem5/src/mem/physical.cc
/gem5/src/mem/physical.hh
/gem5/src/mem/port.cc
/gem5/src/mem/port.hh
/gem5/src/mem/port_proxy.hh
/gem5/src/mem/qport.hh
system/RubyPort.cc
system/RubyPort.hh
/gem5/src/mem/se_translating_port_proxy.cc
/gem5/src/mem/se_translating_port_proxy.hh
/gem5/src/mem/tport.cc
/gem5/src/mem/tport.hh
/gem5/src/python/swig/pyobject.cc
/gem5/src/sim/system.cc
/gem5/src/sim/system.hh
/gem5/src/sim/tlb.hh
8916:7d95b650c9b6 23-Mar-2012 Andreas Hansson <andreas.hansson@arm.com>

Ruby: Fix Set::print for 32-bit hosts

This patch fixes a compilation error caused by a length mismatch on
32-bit hosts. The ifdef and sprintf is replaced by a csprintf.

8914:8c3bd7bea667 22-Mar-2012 Andreas Hansson <andreas.hansson@arm.com>

MEM: Split SimpleTimingPort into PacketQueue and ports

This patch decouples the queueing and the port interactions to
simplify the introduction of the master and slave ports. By separating
the queueing functionality from the port itself, it becomes much
easier to distinguish between master and slave ports, and still retain
the queueing ability for both (without code duplication).

As part of the split into a PacketQueue and a port, there is now also
a hierarchy of two port classes, QueuedPort and SimpleTimingPort. The
QueuedPort is useful for ports that want to leave the packet
transmission of outgoing packets to the queue and is used by both
master and slave ports. The SimpleTimingPort inherits from the
QueuedPort and adds the implemention of recvTiming and recvFunctional
through recvAtomic.

The PioPort and MessagePort are cleaned up as part of the changes.

8913:8b223e308b08 22-Mar-2012 Andreas Hansson <andreas.hansson@arm.com>

Scons: Remove Werror=False in SConscript files

This patch removes the overriding of "-Werror" in a handful of
cases. The code compiles with gcc 4.6.3 and clang 3.0 without any
warnings, and thus without any errors. There are no functional changes
introduced by this patch. In the future, rather than ypassing
"-Werror", address the warnings.

8903:c739a3a829f5 19-Mar-2012 Tushar Krishna <tushar@csail.mit.edu>

Garnet: Stats at vnet granularity + code cleanup

This patch
(1) Moves redundant code from fixed and flexible networks to BaseGarnetNetwork.
(2) Prints network stats at vnet granularity.

8874:9e2a4cf89be6 02-Mar-2012 Andreas Hansson <andreas.hansson@arm.com>

Ruby: Rename RubyPort::sendTiming to avoid overriding base class

This patch renames the sendTiming member function in the RubyPort to
avoid inadvertently hiding Port::sendTiming (discovered through some
rather painful debugging). The RubyPort does, in fact, rely on the
functionality of the queued port and the implementation merely
schedules a send the next cycle. The new name for the member function
is sendNextCycle to better reflect this behaviour.

In the unlikely event that we ever shift to using C++11 the member
functions in Port should have a "final" identifier to prevent any
overriding in derived classes.

8851:7e966326ef5b 24-Feb-2012 Andreas Hansson <andreas.hansson@arm.com>

MEM: Move port creation to the memory object(s) construction

This patch moves all port creation from the getPort method to be
consistently done in the MemObject's constructor. This is possible
thanks to the Swig interface passing the length of the vector ports.
Previously there was a mix of: 1) creating the ports as members (at
object construction time) and using getPort for the name resolution,
or 2) dynamically creating the ports in the getPort call. This is now
uniform. Furthermore, objects that would not be complete without a
port have these ports as members rather than having pointers to
dynamically allocated ports.

This patch also enables an elaboration-time enumeration of all the
ports in the system which can be used to determine the masterId.

8839:eeb293859255 13-Feb-2012 Andreas Hansson <andreas.hansson@arm.com>

MEM: Introduce the master/slave port roles in the Python classes

This patch classifies all ports in Python as either Master or Slave
and enforces a binding of master to slave. Conceptually, a master (such
as a CPU or DMA port) issues requests, and receives responses, and
conversely, a slave (such as a memory or a PIO device) receives
requests and sends back responses. Currently there is no
differentiation between coherent and non-coherent masters and slaves.

The classification as master/slave also involves splitting the dual
role port of the bus into a master and slave port and updating all the
system assembly scripts to use the appropriate port. Similarly, the
interrupt devices have to have their int_port split into a master and
slave port. The intdev and its children have minimal changes to
facilitate the extra port.

Note that this patch does not enforce any port typing in the C++
world, it merely ensures that the Python objects have a notion of the
port roles and are connected in an appropriate manner. This check is
carried when two ports are connected, e.g. bus.master =
memory.port. The following patches will make use of the
classifications and specialise the C++ ports into masters and slaves.


/gem5/configs/common/CacheConfig.py
/gem5/configs/common/FSConfig.py
/gem5/configs/example/fs.py
/gem5/configs/example/ruby_fs.py
/gem5/configs/example/se.py
/gem5/configs/ruby/Ruby.py
/gem5/src/arch/arm/ArmTLB.py
/gem5/src/arch/x86/X86LocalApic.py
/gem5/src/arch/x86/X86TLB.py
/gem5/src/arch/x86/interrupts.hh
/gem5/src/cpu/BaseCPU.py
/gem5/src/cpu/simple/AtomicSimpleCPU.py
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.py
/gem5/src/cpu/testers/memtest/MemTest.py
/gem5/src/cpu/testers/networktest/NetworkTest.py
/gem5/src/cpu/testers/rubytest/RubyTester.py
/gem5/src/dev/Device.py
/gem5/src/dev/Ethernet.py
/gem5/src/dev/Pci.py
/gem5/src/dev/alpha/Tsunami.py
/gem5/src/dev/arm/RealView.py
/gem5/src/dev/x86/I82094AA.py
/gem5/src/dev/x86/Pc.py
/gem5/src/dev/x86/SouthBridge.py
/gem5/src/dev/x86/i82094aa.hh
/gem5/src/dev/x86/intdev.hh
/gem5/src/mem/Bridge.py
/gem5/src/mem/Bus.py
/gem5/src/mem/PhysicalMemory.py
/gem5/src/mem/cache/BaseCache.py
system/RubyPort.cc
system/Sequencer.py
/gem5/src/python/m5/SimObject.py
/gem5/src/python/m5/params.py
/gem5/src/sim/System.py
/gem5/tests/configs/inorder-timing.py
/gem5/tests/configs/memtest-ruby.py
/gem5/tests/configs/memtest.py
/gem5/tests/configs/o3-timing-mp-ruby.py
/gem5/tests/configs/o3-timing-mp.py
/gem5/tests/configs/o3-timing-ruby.py
/gem5/tests/configs/o3-timing.py
/gem5/tests/configs/pc-o3-timing.py
/gem5/tests/configs/pc-simple-atomic.py
/gem5/tests/configs/pc-simple-timing.py
/gem5/tests/configs/realview-o3-dual.py
/gem5/tests/configs/realview-o3.py
/gem5/tests/configs/realview-simple-atomic-dual.py
/gem5/tests/configs/realview-simple-atomic.py
/gem5/tests/configs/realview-simple-timing-dual.py
/gem5/tests/configs/realview-simple-timing.py
/gem5/tests/configs/rubytest-ruby.py
/gem5/tests/configs/simple-atomic-mp-ruby.py
/gem5/tests/configs/simple-atomic-mp.py
/gem5/tests/configs/simple-atomic.py
/gem5/tests/configs/simple-timing-mp.py
/gem5/tests/configs/simple-timing.py
/gem5/tests/configs/tsunami-inorder.py
/gem5/tests/configs/tsunami-o3-dual.py
/gem5/tests/configs/tsunami-o3.py
/gem5/tests/configs/tsunami-simple-atomic-dual.py
/gem5/tests/configs/tsunami-simple-atomic.py
/gem5/tests/configs/tsunami-simple-timing-dual.py
/gem5/tests/configs/tsunami-simple-timing.py
/gem5/tests/configs/twosys-tsunami-simple-atomic.py
8832:247fee427324 12-Feb-2012 Ali Saidi <Ali.Saidi@ARM.com>

mem: Add a master ID to each request object.

This change adds a master id to each request object which can be
used identify every device in the system that is capable of issuing a request.
This is part of the way to removing the numCpus+1 stats in the cache and
replacing them with the master ids. This is one of a series of changes
that make way for the stats output to be changed to python.


/gem5/src/arch/arm/isa.cc
/gem5/src/arch/arm/table_walker.cc
/gem5/src/arch/arm/table_walker.hh
/gem5/src/arch/x86/intmessage.hh
/gem5/src/arch/x86/pagetable_walker.cc
/gem5/src/arch/x86/pagetable_walker.hh
/gem5/src/cpu/base.cc
/gem5/src/cpu/base.hh
/gem5/src/cpu/base_dyn_inst.hh
/gem5/src/cpu/checker/cpu.cc
/gem5/src/cpu/checker/cpu.hh
/gem5/src/cpu/checker/cpu_impl.hh
/gem5/src/cpu/inorder/resources/cache_unit.cc
/gem5/src/cpu/inorder/resources/fetch_unit.cc
/gem5/src/cpu/inorder/resources/tlb_unit.hh
/gem5/src/cpu/o3/fetch_impl.hh
/gem5/src/cpu/simple/atomic.cc
/gem5/src/cpu/simple/base.cc
/gem5/src/cpu/simple/timing.cc
/gem5/src/cpu/testers/directedtest/DirectedGenerator.cc
/gem5/src/cpu/testers/directedtest/DirectedGenerator.hh
/gem5/src/cpu/testers/directedtest/InvalidateGenerator.cc
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.py
/gem5/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
/gem5/src/cpu/testers/memtest/MemTest.py
/gem5/src/cpu/testers/memtest/memtest.cc
/gem5/src/cpu/testers/memtest/memtest.hh
/gem5/src/cpu/testers/networktest/NetworkTest.py
/gem5/src/cpu/testers/networktest/networktest.cc
/gem5/src/cpu/testers/networktest/networktest.hh
/gem5/src/cpu/testers/rubytest/Check.cc
/gem5/src/cpu/testers/rubytest/RubyTester.cc
/gem5/src/cpu/testers/rubytest/RubyTester.hh
/gem5/src/cpu/testers/rubytest/RubyTester.py
/gem5/src/dev/io_device.cc
/gem5/src/dev/io_device.hh
/gem5/src/mem/cache/cache_impl.hh
/gem5/src/mem/cache/prefetch/Prefetcher.py
/gem5/src/mem/cache/prefetch/base.cc
/gem5/src/mem/cache/prefetch/base.hh
/gem5/src/mem/cache/prefetch/ghb.cc
/gem5/src/mem/cache/prefetch/ghb.hh
/gem5/src/mem/cache/prefetch/stride.cc
/gem5/src/mem/cache/tags/iic.cc
/gem5/src/mem/port.cc
/gem5/src/mem/request.hh
recorder/CacheRecorder.cc
system/RubyPort.cc
/gem5/src/sim/system.cc
/gem5/src/sim/system.hh
8828:e8fd0fc4a417 10-Feb-2012 Nilay Vaish <nilay@cs.wisc.edu>

Ruby: Remove isTagPresent() calls from Sequencer.cc
This patch removes the calls to isTagPresent() from Sequencer.cc. These
calls are made just for setting the cache block to have been most recently
used. The calls have been folded in to the function setMRU().

8798:adaa92be9037 16-Jan-2012 Gabe Black <gblack@eecs.umich.edu>

Merge yet again with the main repository.

8795:0909f8ed7aa0 07-Jan-2012 Gabe Black <gblack@eecs.umich.edu>

Merge with main repository.

8737:770ccf3af571 31-Jan-2012 Koan-Sin Tan <koansin.tan@gmail.com>

clang: Enable compiling gem5 using clang 2.9 and 3.0

This patch adds the necessary flags to the SConstruct and SConscript
files for compiling using clang 2.9 and later (on Ubuntu et al and OSX
XCode 4.2), and also cleans up a bunch of compiler warnings found by
clang. Most of the warnings are related to hidden virtual functions,
comparisons with unsigneds >= 0, and if-statements with empty
bodies. A number of mismatches between struct and class are also
fixed. clang 2.8 is not working as it has problems with class names
that occur in multiple namespaces (e.g. Statistics in
kernel_stats.hh).

clang has a bug (http://llvm.org/bugs/show_bug.cgi?id=7247) which
causes confusion between the container std::set and the function
Packet::set, and this is currently addressed by not including the
entire namespace std, but rather selecting e.g. "using std::vector" in
the appropriate places.


/gem5/SConstruct
/gem5/ext/libelf/SConscript
/gem5/src/SConscript
/gem5/src/arch/alpha/tlb.cc
/gem5/src/arch/alpha/tlb.hh
/gem5/src/arch/arm/insts/static_inst.hh
/gem5/src/arch/arm/insts/vfp.hh
/gem5/src/arch/arm/isa/templates/basic.isa
/gem5/src/arch/arm/miscregs.cc
/gem5/src/arch/generic/memhelpers.hh
/gem5/src/arch/mips/faults.cc
/gem5/src/arch/mips/faults.hh
/gem5/src/arch/x86/bios/acpi.hh
/gem5/src/arch/x86/bios/intelmp.cc
/gem5/src/arch/x86/bios/intelmp.hh
/gem5/src/arch/x86/bios/smbios.hh
/gem5/src/base/fast_alloc.cc
/gem5/src/base/range_map.hh
/gem5/src/base/remote_gdb.hh
/gem5/src/base/stl_helpers.hh
/gem5/src/cpu/base.cc
/gem5/src/cpu/base.hh
/gem5/src/cpu/func_unit.hh
/gem5/src/cpu/inorder/cpu.cc
/gem5/src/cpu/inorder/cpu.hh
/gem5/src/cpu/inorder/resource.cc
/gem5/src/cpu/inorder/resource.hh
/gem5/src/cpu/inorder/resource_pool.cc
/gem5/src/cpu/inorder/resource_pool.hh
/gem5/src/cpu/inorder/resources/cache_unit.hh
/gem5/src/cpu/inorder/thread_context.cc
/gem5/src/cpu/nativetrace.hh
/gem5/src/cpu/o3/bpred_unit.hh
/gem5/src/cpu/o3/commit.hh
/gem5/src/cpu/o3/cpu.cc
/gem5/src/cpu/o3/cpu.hh
/gem5/src/cpu/o3/decode.hh
/gem5/src/cpu/o3/decode_impl.hh
/gem5/src/cpu/o3/fetch.hh
/gem5/src/cpu/o3/fu_pool.cc
/gem5/src/cpu/o3/fu_pool.hh
/gem5/src/cpu/o3/iew.hh
/gem5/src/cpu/o3/iew_impl.hh
/gem5/src/cpu/o3/inst_queue.hh
/gem5/src/cpu/o3/inst_queue_impl.hh
/gem5/src/cpu/o3/lsq.hh
/gem5/src/cpu/o3/lsq_unit.hh
/gem5/src/cpu/o3/mem_dep_unit.cc
/gem5/src/cpu/o3/mem_dep_unit.hh
/gem5/src/cpu/o3/rename.hh
/gem5/src/cpu/o3/sat_counter.hh
/gem5/src/cpu/quiesce_event.hh
/gem5/src/cpu/sched_list.hh
/gem5/src/cpu/simple/atomic.cc
/gem5/src/cpu/simple/atomic.hh
/gem5/src/cpu/simple/base.cc
/gem5/src/cpu/simple/base.hh
/gem5/src/cpu/simple/timing.cc
/gem5/src/cpu/simple/timing.hh
/gem5/src/cpu/static_inst.hh
/gem5/src/dev/alpha/tsunami_cchip.cc
/gem5/src/dev/alpha/tsunami_io.cc
/gem5/src/dev/arm/pl111.cc
/gem5/src/dev/arm/pl111.hh
/gem5/src/dev/copy_engine.cc
/gem5/src/dev/disk_image.cc
/gem5/src/dev/disk_image.hh
/gem5/src/dev/ide_ctrl.cc
/gem5/src/dev/ns_gige.cc
/gem5/src/dev/pciconfigall.cc
/gem5/src/dev/pcidev.cc
/gem5/src/mem/cache/base.hh
/gem5/src/mem/cache/tags/iic.cc
/gem5/src/mem/cache/tags/iic_repl/gen.cc
/gem5/src/mem/cache/tags/iic_repl/gen.hh
/gem5/src/mem/cache/tags/iic_repl/repl.hh
/gem5/src/mem/packet.hh
network/garnet/fixed-pipeline/GarnetNetwork_d.cc
system/Sequencer.hh
/gem5/src/python/m5/SimObject.py
/gem5/src/sim/core.hh
/gem5/src/sim/process.cc
/gem5/src/sim/process.hh
/gem5/src/sim/process_impl.hh
/gem5/src/sim/serialize.cc
/gem5/src/sim/sim_object.cc
/gem5/src/sim/sim_object.hh
/gem5/src/sim/syscall_emul.hh
8731:bb0aaf3ffa18 30-Jan-2012 Andreas Hansson <andreas.hansson@arm.com>

MEM: Make the RubyPort physMemPort a PioPort instead of M5Port

This patch makes the physMemPort of the RubyPort a PioPort rather than
an M5Port. This reflects the fact that the M5Port and PioPort have
different roles. The M5Port is really a coherent slave that is
connected to the CPUs and other coherent masters of the system,
e.g. DMA ports. The PioPort, on the other hand, is a master port that
is connected to the memory and other slaves, for example the pio
devices.

This simplifies future changes into master/slave ports and is
consistent with the port roles throughout the system.

8717:5c253f1031d7 23-Jan-2012 Nilay Vaish <nilay@cs.wisc.edu>

O3, Ruby: Forward invalidations from Ruby to O3 CPU
This patch implements the functionality for forwarding invalidations and
replacements from the L1 cache of the Ruby memory system to the O3 CPU. The
implementation adds a list of ports to RubyPort. Whenever a replacement or an
invalidation is performed, the L1 cache forwards this to all the ports, which
is the LSQ in case of the O3 CPU.

8712:7f762428a9f5 17-Jan-2012 William Wang <william.wang@arm.com>

MEM: Remove the functional ports from the memory system

The functional ports are no longer used and this patch cleans up the
legacy that is still present in buses, memories, CPUs etc. Note that
this does not refer to the class FunctionalPort (already removed), but
rather ports with the name (and use) functional.

8711:c7e14f52c682 17-Jan-2012 Andreas Hansson <andreas.hansson@arm.com>

MEM: Separate queries for snooping and address ranges

This patch simplifies the address-range determination mechanism and
also unifies the naming across ports and devices. It further splits
the queries for determining if a port is snooping and what address
ranges it responds to (aiming towards a separation of
cache-maintenance ports and pure memory-mapped ports). Default
behaviours are such that most ports do not have to define isSnooping,
and master ports need not implement getAddrRanges.


/gem5/src/arch/x86/interrupts.cc
/gem5/src/arch/x86/interrupts.hh
/gem5/src/arch/x86/pagetable_walker.cc
/gem5/src/arch/x86/pagetable_walker.hh
/gem5/src/cpu/base.cc
/gem5/src/cpu/base.hh
/gem5/src/cpu/inorder/resources/cache_unit.cc
/gem5/src/cpu/inorder/resources/cache_unit.hh
/gem5/src/cpu/o3/cpu.hh
/gem5/src/cpu/ozone/front_end.hh
/gem5/src/cpu/ozone/front_end_impl.hh
/gem5/src/cpu/ozone/lw_lsq.hh
/gem5/src/cpu/ozone/lw_lsq_impl.hh
/gem5/src/cpu/simple/atomic.cc
/gem5/src/cpu/testers/memtest/memtest.cc
/gem5/src/cpu/testers/memtest/memtest.hh
/gem5/src/cpu/testers/networktest/networktest.cc
/gem5/src/cpu/testers/networktest/networktest.hh
/gem5/src/dev/arm/gic.cc
/gem5/src/dev/arm/gic.hh
/gem5/src/dev/arm/pl111.cc
/gem5/src/dev/arm/pl111.hh
/gem5/src/dev/copy_engine.hh
/gem5/src/dev/io_device.cc
/gem5/src/dev/io_device.hh
/gem5/src/dev/pciconfigall.cc
/gem5/src/dev/pciconfigall.hh
/gem5/src/dev/pcidev.cc
/gem5/src/dev/pcidev.hh
/gem5/src/dev/sinic.cc
/gem5/src/dev/sparc/iob.cc
/gem5/src/dev/sparc/iob.hh
/gem5/src/dev/uart8250.cc
/gem5/src/dev/uart8250.hh
/gem5/src/dev/x86/i8042.cc
/gem5/src/dev/x86/i8042.hh
/gem5/src/dev/x86/i82094aa.hh
/gem5/src/dev/x86/intdev.cc
/gem5/src/dev/x86/intdev.hh
/gem5/src/kern/tru64/tru64_events.cc
/gem5/src/mem/bridge.cc
/gem5/src/mem/bridge.hh
/gem5/src/mem/bus.cc
/gem5/src/mem/bus.hh
/gem5/src/mem/cache/base.cc
/gem5/src/mem/cache/base.hh
/gem5/src/mem/cache/cache.hh
/gem5/src/mem/cache/cache_impl.hh
/gem5/src/mem/physical.cc
/gem5/src/mem/physical.hh
/gem5/src/mem/port.hh
system/RubyPort.cc
/gem5/src/mem/tport.hh
/gem5/src/sim/system.hh
8706:b1838faf3bcc 17-Jan-2012 Andreas Hansson <andreas.hansson@arm.com>

MEM: Add port proxies instead of non-structural ports

Port proxies are used to replace non-structural ports, and thus enable
all ports in the system to correspond to a structural entity. This has
the advantage of accessing memory through the normal memory subsystem
and thus allowing any constellation of distributed memories, address
maps, etc. Most accesses are done through the "system port" that is
used for loading binaries, debugging etc. For the entities that belong
to the CPU, e.g. threads and thread contexts, they wrap the CPU data
port in a port proxy.

The following replacements are made:
FunctionalPort > PortProxy
TranslatingPort > SETranslatingPortProxy
VirtualPort > FSTranslatingPortProxy


/gem5/configs/common/FSConfig.py
/gem5/configs/example/se.py
/gem5/configs/ruby/Ruby.py
/gem5/src/arch/alpha/freebsd/system.cc
/gem5/src/arch/alpha/linux/process.cc
/gem5/src/arch/alpha/linux/system.cc
/gem5/src/arch/alpha/linux/system.hh
/gem5/src/arch/alpha/linux/threadinfo.hh
/gem5/src/arch/alpha/remote_gdb.cc
/gem5/src/arch/alpha/stacktrace.cc
/gem5/src/arch/alpha/system.cc
/gem5/src/arch/alpha/system.hh
/gem5/src/arch/alpha/tru64/process.cc
/gem5/src/arch/alpha/tru64/system.cc
/gem5/src/arch/alpha/utility.cc
/gem5/src/arch/alpha/vtophys.cc
/gem5/src/arch/alpha/vtophys.hh
/gem5/src/arch/arm/linux/process.cc
/gem5/src/arch/arm/linux/system.cc
/gem5/src/arch/arm/process.cc
/gem5/src/arch/arm/stacktrace.cc
/gem5/src/arch/arm/system.cc
/gem5/src/arch/arm/system.hh
/gem5/src/arch/arm/utility.cc
/gem5/src/arch/arm/vtophys.cc
/gem5/src/arch/mips/linux/process.cc
/gem5/src/arch/mips/linux/system.cc
/gem5/src/arch/mips/linux/threadinfo.hh
/gem5/src/arch/mips/stacktrace.cc
/gem5/src/arch/mips/utility.cc
/gem5/src/arch/power/linux/process.cc
/gem5/src/arch/power/process.cc
/gem5/src/arch/sparc/linux/syscalls.cc
/gem5/src/arch/sparc/process.cc
/gem5/src/arch/sparc/solaris/process.cc
/gem5/src/arch/sparc/system.cc
/gem5/src/arch/sparc/system.hh
/gem5/src/arch/sparc/utility.cc
/gem5/src/arch/sparc/vtophys.cc
/gem5/src/arch/x86/bios/intelmp.cc
/gem5/src/arch/x86/bios/intelmp.hh
/gem5/src/arch/x86/bios/smbios.cc
/gem5/src/arch/x86/bios/smbios.hh
/gem5/src/arch/x86/linux/syscalls.cc
/gem5/src/arch/x86/linux/system.cc
/gem5/src/arch/x86/process.cc
/gem5/src/arch/x86/stacktrace.cc
/gem5/src/arch/x86/system.cc
/gem5/src/base/loader/elf_object.cc
/gem5/src/base/loader/elf_object.hh
/gem5/src/base/loader/hex_file.cc
/gem5/src/base/loader/hex_file.hh
/gem5/src/base/loader/object_file.cc
/gem5/src/base/loader/object_file.hh
/gem5/src/base/remote_gdb.cc
/gem5/src/cpu/checker/thread_context.hh
/gem5/src/cpu/inorder/cpu.cc
/gem5/src/cpu/inorder/cpu.hh
/gem5/src/cpu/inorder/resources/cache_unit.cc
/gem5/src/cpu/inorder/resources/cache_unit.hh
/gem5/src/cpu/inorder/thread_context.cc
/gem5/src/cpu/inorder/thread_context.hh
/gem5/src/cpu/o3/cpu.cc
/gem5/src/cpu/o3/cpu.hh
/gem5/src/cpu/o3/lsq.hh
/gem5/src/cpu/o3/lsq_impl.hh
/gem5/src/cpu/o3/thread_context.hh
/gem5/src/cpu/o3/thread_context_impl.hh
/gem5/src/cpu/ozone/cpu.hh
/gem5/src/cpu/ozone/cpu_impl.hh
/gem5/src/cpu/simple/atomic.cc
/gem5/src/cpu/simple/atomic.hh
/gem5/src/cpu/simple/timing.cc
/gem5/src/cpu/simple/timing.hh
/gem5/src/cpu/simple_thread.cc
/gem5/src/cpu/simple_thread.hh
/gem5/src/cpu/thread_context.hh
/gem5/src/cpu/thread_state.cc
/gem5/src/cpu/thread_state.hh
/gem5/src/dev/simple_disk.cc
/gem5/src/kern/tru64/tru64.hh
/gem5/src/kern/tru64/tru64_events.cc
/gem5/src/mem/SConscript
/gem5/src/mem/fs_translating_port_proxy.cc
/gem5/src/mem/fs_translating_port_proxy.hh
/gem5/src/mem/port.hh
/gem5/src/mem/port_impl.hh
/gem5/src/mem/port_proxy.hh
system/RubyPort.cc
system/RubyPortProxy.cc
system/RubyPortProxy.hh
system/SConscript
system/Sequencer.py
/gem5/src/mem/se_translating_port_proxy.cc
/gem5/src/mem/se_translating_port_proxy.hh
/gem5/src/mem/translating_port.cc
/gem5/src/mem/translating_port.hh
/gem5/src/mem/vport.cc
/gem5/src/mem/vport.hh
/gem5/src/sim/arguments.hh
/gem5/src/sim/process.cc
/gem5/src/sim/process.hh
/gem5/src/sim/process_impl.hh
/gem5/src/sim/syscall_emul.cc
/gem5/src/sim/syscall_emul.hh
/gem5/src/sim/system.cc
/gem5/src/sim/system.hh
/gem5/src/sim/vptr.hh
/gem5/tests/configs/inorder-timing.py
/gem5/tests/configs/memtest-ruby.py
/gem5/tests/configs/memtest.py
/gem5/tests/configs/o3-timing-mp.py
/gem5/tests/configs/o3-timing.py
/gem5/tests/configs/rubytest-ruby.py
/gem5/tests/configs/simple-atomic-mp.py
/gem5/tests/configs/simple-atomic.py
/gem5/tests/configs/simple-timing-mp-ruby.py
/gem5/tests/configs/simple-timing-mp.py
/gem5/tests/configs/simple-timing-ruby.py
/gem5/tests/configs/simple-timing.py
8693:99ba36eaa789 12-Jan-2012 Nilay Vaish <nilay@cs.wisc.edu>

PerfectCacheMemory: Remove references to CacheMsg
The definition for the class CacheMsg was removed long back. Some declaration
had still survived, which was recently removed. Since the PerfectCacheMemory
class relied on this particular declaration, its absence let to compilation
breaking down. Hence this patch.

8688:5ca9dd977386 11-Jan-2012 Nilay Vaish <nilay@cs.wisc.edu>

Ruby: Resurrect Cache Warmup Capability
This patch resurrects ruby's cache warmup capability. It essentially
makes use of all the infrastructure that was added to the controllers,
memories and the cache recorder.

8686:71ac9dda5432 11-Jan-2012 Nilay Vaish <nilay@cs.wisc.edu>

Ruby Port: Add a list of cpu ports attached to this port

8685:2854ed06ce05 11-Jan-2012 Nilay Vaish <nilay@cs.wisc.edu>

Ruby EventQueue: Remove unused functions

8684:9a2ac57eb22c 11-Jan-2012 Nilay Vaish <nilay@cs.wisc.edu>

Ruby Sparse Memory: Add function for collating blocks
This patch adds function to the Sparse Memory so that the blocks can be
recorded in a cache trace. The blocks are added to the cache recorder
which can later write them into a file.

8683:9feb100066e1 11-Jan-2012 Nilay Vaish <nilay@cs.wisc.edu>

Ruby: Add infrastructure for recording cache contents
This patch changes CacheRecorder, CacheMemory, CacheControllers
so that the contents of a cache can be recorded for checkpointing
purposes.

8682:d70d2dfb1c20 11-Jan-2012 Nilay Vaish <nilay@cs.wisc.edu>

Ruby Memory Vector: Functions for collating and populating pages
This patch adds functions to the memory vector class that can be used for
collating memory pages to raw trace and for populating pages from a raw
trace.

8681:db978f3bcf51 10-Jan-2012 Nilay Vaish <nilay@cs.wisc.edu>

Ruby: remove the files related to the tracer
The Ruby Tracer is out of date with the changes that are being carried
out to support checkpointing. Hence, it needs to be removed.

8677:e7f6268d7ef3 10-Jan-2012 Nilay Vaish <nilay@cs.wisc.edu>

Sparse Memory: Simplify the structure for an entry
The SparseMemEntry structure includes just one void* pointer. It seems
unnecessary that we have a structure for this. The patch removes the
structure and makes use of a typedef on void* instead.

8653:15d4da9d2042 07-Jan-2012 Nilay Vaish <nilay@cs.wisc.edu>

Ruby Cache: Add param for marking caches as instruction only

8651:c3d878fbdaea 06-Jan-2012 Nilay Vaish <nilay@cs.wisc.edu>

AbstractController: Remove some of the unused functions

8650:33a48f15e94a 06-Jan-2012 Nilay Vaish <nilay@cs.wisc.edu>

Ruby Set: Move NUMBER_WORDS_PER_SET to Set.hh
This constant is currently in System.hh, but is only used in Set.hh. It
is being moved to Set.hh to remove this artificial dependence of Set.hh
on System.hh.

8645:89929730804b 31-Dec-2011 Nilay Vaish<nilay@cs.wisc.edu>

Ruby: Shuffle some of the included files
This patch adds and removes included files from some of the files so as to
organize remove some false dependencies and include some files directly
instead of transitively.

8644:acf68e5a8cd7 31-Dec-2011 Nilay Vaish<nilay@cs.wisc.edu>

SLICC: Use pointers for directory entries
SLICC uses pointers for cache and TBE entries but not for directory entries.
This patch changes the protocols, SLICC and Ruby memory system so that even
directory entries are referenced using pointers.

8641:4d3ecac1abec 13-Dec-2011 Nathan Binkert <nate@binkert.org>

gcc: fix unused variable warnings from GCC 4.6.1

8619:2f1875b5f107 23-Nov-2011 Tushar Krishna <tushar@csail.mit.edu>

Topology: bug fix in external link initialization

8615:e66a566f2cfa 14-Nov-2011 Nilay Vaish<nilay@cs.wisc.edu>

Ruby: Process packet instead of RubyRequest in Sequencer
This patch changes the implementation of Ruby's recvTiming() function so
that it pushes a packet in to the Sequencer instead of a RubyRequest. This
requires changes in the Sequencer's makeRequest() and issueRequest()
functions, as they also need to operate on a Packet instead of RubyRequest.

8612:df3b7a1e883f 04-Nov-2011 Tushar Krishna <tushar@csail.mit.edu>

GARNET: adding a fault model for resilient on-chip network research.

This patch adds a fault model, which provides the probability of a number of
architectural faults in the interconnection network (e.g., data corruption,
misrouting). These probabilities can be used to realistically inject faults
in GARNET and faithfully evaluate the effectiveness of novel resilient NoC
architectures.

8608:02d7ac5fb855 03-Nov-2011 Nilay Vaish<nilay@cs.wisc.edu>

Ruby: Remove some unused typedefs
This patch removes some of the unused typedefs. It also moves
some of the typedefs from Global.hh to TypeDefines.hh. The patch
also eliminates the file NodeID.hh.

8607:5fb918115c07 31-Oct-2011 Gabe Black <gblack@eecs.umich.edu>

GCC: Get everything working with gcc 4.6.1.

And by "everything" I mean all the quick regressions.

8602:836f8fad4a4c 28-Oct-2011 Nilay Vaish<nilay@cs.wisc.edu>

Ruby: Reorganize mapping of components
In RubySlicc_ComponentMapping.hh, certain '#define's have been used for
mapping MachineType to GenericMachineType. These '#define's are being
eliminated and the code will now be generated by SLICC instead. Also
are being eliminated some of the unused functions from
RubySlicc_ComponentMapping.sm.

8581:56f97760eadd 22-Sep-2011 Steve Reinhardt <steve.reinhardt@amd.com>

event: minor cleanup
Initialize flags via the Event constructor instead of calling
setFlags() in the body of the derived class's constructor. I
forget exactly why, but this made life easier when implementing
multi-queue support.

Also rename Event::getFlags() to isFlagSet() to better match
common usage, and get rid of some unused Event methods.

8532:8f27cf8971fe 01-Sep-2011 Lisa Hsu <Lisa.Hsu@amd.com>

Functional Accesses: Update states to support Broadcast/Snooping protocols.

In the current implementation of Functional Accesses, it's very hard to
implement broadcast or snooping protocols where the memory has no idea if it
has exclusive access to a cache block or not. Without this knowledge, making
sure the RW vs. RO permissions are right are next to impossible. So we add a
new state called Backing_Store to enable the conveyance that this is the backup
storage for a block, so that it can be written if it is the only possibly RW
block in the system, or written even if there is another RW block in the
system, without causing problems.

Also, a small change to actually set the m_name field for each Controller so
that debugging can be easier. Now you can access a controller's name just by
controller->getName().

8531:bfc59fbde824 29-Aug-2011 Nilay Vaish<nilay@cs.wisc.edu>

SLICC: Pass arguments by reference
Arguments to functions were being passed by value. This patch
changes SLICC so that arguments are passed by reference.

8530:3aaa99208a84 29-Aug-2011 Nilay Vaish<nilay@cs.wisc.edu>

Ruby: Remove some unused code

8529:00ca5af1b954 26-Aug-2011 Nilay Vaish<nilay@cs.wisc.edu>

Ruby: Eliminate modulo op for computing set size.

8505:442804117f95 15-Aug-2011 Nilay Vaish<nilay@cs.wisc.edu>

Ruby: Initialize some variables.

8492:1ad244a20877 08-Aug-2011 Nilay Vaish<nilay@cs.wisc.edu>

BuildEnv: Eliminate RUBY as build environment variable
This patch replaces RUBY with PROTOCOL in all the SConscript files as
the environment variable that decides whether or not certain components
of the simulator are compiled.

8485:7a9a7f2a3d46 03-Aug-2011 Nilay Vaish<nilay@cs.wisc.edu>

Ruby: Remove files and includes not in use

8483:b5052cad1fd3 02-Aug-2011 Gabe Black <gblack@eecs.umich.edu>

Scons: Make some Action objects fit the abreviated output format.

8456:5204873afc05 06-Jul-2011 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: added generic dma machine

8439:559ef3da5dac 01-Jul-2011 Nilay Vaish<nilay@cs.wisc.edu>

Ruby: Commit files missing from previous commit
The previous commit on functional access support in Ruby did not have
some of the files required. This patch adds those files to the repository.

8436:5648986156db 30-Jun-2011 Brad Beckmann <Brad.Beckmann@amd.com>, Nilay Vaish <nilay@cs.wisc.edu>

Ruby: Add support for functional accesses
This patch rpovides functional access support in Ruby. Currently only
the M5Port of RubyPort supports functional accesses. The support for
functional through the PioPort will be added as a separate patch.


/gem5/configs/example/ruby_direct_test.py
/gem5/configs/example/ruby_fs.py
/gem5/configs/example/ruby_mem_test.py
/gem5/configs/example/ruby_network_test.py
/gem5/configs/example/ruby_random_test.py
/gem5/configs/example/se.py
/gem5/configs/ruby/MESI_CMP_directory.py
/gem5/configs/ruby/MI_example.py
/gem5/configs/ruby/MOESI_CMP_directory.py
/gem5/configs/ruby/MOESI_CMP_token.py
/gem5/configs/ruby/MOESI_hammer.py
/gem5/configs/ruby/Ruby.py
/gem5/src/cpu/testers/memtest/MemTest.py
/gem5/src/cpu/testers/memtest/memtest.cc
/gem5/src/cpu/testers/memtest/memtest.hh
/gem5/src/mem/packet.cc
/gem5/src/mem/packet.hh
/gem5/src/mem/protocol/MESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MESI_CMP_directory-dma.sm
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MI_example-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dma.sm
/gem5/src/mem/protocol/MOESI_hammer-cache.sm
/gem5/src/mem/protocol/MOESI_hammer-dir.sm
/gem5/src/mem/protocol/MOESI_hammer-dma.sm
/gem5/src/mem/protocol/RubySlicc_Exports.sm
network/Network.cc
network/Network.py
profiler/Profiler.cc
profiler/Profiler.py
recorder/Tracer.cc
recorder/Tracer.py
slicc_interface/AbstractController.hh
slicc_interface/Controller.py
slicc_interface/SConscript
system/Cache.py
system/DirectoryMemory.cc
system/DirectoryMemory.py
system/RubyPort.cc
system/RubyPort.hh
system/RubySystem.py
system/SConscript
system/Sequencer.py
system/System.cc
system/System.hh
/gem5/src/mem/slicc/ast/MemberExprAST.py
/gem5/tests/configs/memtest-ruby.py
/gem5/tests/configs/rubytest-ruby.py
/gem5/tests/configs/simple-timing-mp-ruby.py
/gem5/tests/configs/simple-timing-ruby.py
8434:0412ba528ad6 24-Jun-2011 Joel Hestness <hestness@cs.utexas.edu>

Ruby: remove unused functions in CacheMemory: get/setMemoryValue

8351:f897d0483b06 14-Jun-2011 Nilay Vaish<nilay@cs.wisc.edu>

Ruby: Correct set LONG_BITS and INDEX_SHIFT in class Set.
The code for Set class was written under the assumption that
std::numeric_limits<long>::digits returns the number of bits used for
data type long, which was presumed to be either 32 or 64. But return value
is actually one less, that is, it is either 31 or 63. The value is now
being incremented by 1 so as to correctly set it.

8341:30daf1dd5c91 08-Jun-2011 Nilay Vaish<nilay@cs.wisc.edu>

Ruby: Correctly set access permissions for directory entries
The access permissions for the directory entries are not being set correctly.
This is because pointers are not used for handling directory entries.
function. get and set functions for access permissions have been added to the
Controller state machine. The changePermission() function provided by the
AbstractEntry and AbstractCacheEntry classes has been exposed to SLICC
code once again. The set_permission() functionality has been removed.

NOTE: Each protocol will have to define these get and set functions in order
to compile successfully.

8332:23711432221f 02-Jun-2011 Nathan Binkert <nate@binkert.org>

copyright: clean up copyright blocks


/gem5/src/arch/alpha/kgdb.h
/gem5/src/arch/alpha/remote_gdb.cc
/gem5/src/arch/arm/remote_gdb.cc
/gem5/src/arch/generic/debugfaults.hh
/gem5/src/arch/sparc/remote_gdb.cc
/gem5/src/arch/x86/insts/badmicroop.cc
/gem5/src/arch/x86/insts/badmicroop.hh
/gem5/src/arch/x86/isa/formats/nop.isa
/gem5/src/base/random_mt.cc
/gem5/src/base/remote_gdb.cc
/gem5/src/dev/ide_wdcreg.h
/gem5/src/dev/sparc/dtod.hh
network/orion/Allocator/Arbiter.cc
network/orion/Allocator/Arbiter.hh
network/orion/Allocator/MatrixArbiter.cc
network/orion/Allocator/MatrixArbiter.hh
network/orion/Allocator/RRArbiter.cc
network/orion/Allocator/RRArbiter.hh
network/orion/Allocator/SWAllocator.cc
network/orion/Allocator/SWAllocator.hh
network/orion/Allocator/VCAllocator.cc
network/orion/Allocator/VCAllocator.hh
network/orion/Buffer/AmpUnit.cc
network/orion/Buffer/AmpUnit.hh
network/orion/Buffer/BitlineUnit.cc
network/orion/Buffer/BitlineUnit.hh
network/orion/Buffer/Buffer.cc
network/orion/Buffer/Buffer.hh
network/orion/Buffer/DecoderUnit.cc
network/orion/Buffer/DecoderUnit.hh
network/orion/Buffer/MemUnit.cc
network/orion/Buffer/MemUnit.hh
network/orion/Buffer/OutdrvUnit.cc
network/orion/Buffer/OutdrvUnit.hh
network/orion/Buffer/PrechargeUnit.cc
network/orion/Buffer/PrechargeUnit.hh
network/orion/Buffer/Register.cc
network/orion/Buffer/Register.hh
network/orion/Buffer/SRAM.cc
network/orion/Buffer/SRAM.hh
network/orion/Buffer/WordlineUnit.cc
network/orion/Buffer/WordlineUnit.hh
network/orion/Clock.cc
network/orion/Clock.hh
network/orion/Crossbar/Crossbar.cc
network/orion/Crossbar/Crossbar.hh
network/orion/Crossbar/MatrixCrossbar.cc
network/orion/Crossbar/MatrixCrossbar.hh
network/orion/Crossbar/MultreeCrossbar.cc
network/orion/Crossbar/MultreeCrossbar.hh
network/orion/FlipFlop.cc
network/orion/FlipFlop.hh
network/orion/OrionLink.cc
network/orion/OrionLink.hh
network/orion/OrionRouter.cc
network/orion/OrionRouter.hh
network/orion/TechParameter.cc
network/orion/TechParameter.hh
network/orion/Type.hh
network/orion/Wire.cc
network/orion/Wire.hh
/gem5/src/sim/fault_fwd.hh
/gem5/src/sim/root.cc
/gem5/src/sim/root.hh
/gem5/src/unittest/unittest.cc
/gem5/src/unittest/unittest.hh
8330:681497e0356b 31-May-2011 Tushar Krishna <tushar@csail.mit.edu>

orion: bug fix in link power, and some reorg

8329:24a00a6d5992 31-May-2011 Tushar Krishna <tushar@csail.mit.edu>

garnet: added network ptr to links to be used by orion

8322:19949c6de823 23-May-2011 Steve Reinhardt <steve.reinhardt@amd.com>

config: tweak ruby configs to clean up hierarchy

Re-enabling implicit parenting (see previous patch) causes current
Ruby config scripts to create some strange hierarchies and generate
several warnings. This patch makes three general changes to address
these issues.

1. The order of object creation in the ruby config files makes the L1
caches children of the sequencer rather than the controller; these
config ciles are rewritten to assign the L1 caches to the
controller first.

2. The assignment of the sequencer list to system.ruby.cpu_ruby_ports
causes the sequencers to be children of system.ruby, generating
warnings because they are already parented to their respective
controllers. Changing this attribute to _cpu_ruby_ports fixes this
because the leading underscore means this is now treated as a plain
Python attribute rather than a child assignment. As a result, the
configuration hierarchy changes such that, e.g.,
system.ruby.cpu_ruby_ports0 becomes system.l1_cntrl0.sequencer.

3. In the topology classes, the routers become children of some random
internal link node rather than direct children of the topology.
The topology classes are rewritten to assign the routers to the
topology object first.

8313:1eaa1fbd2212 21-May-2011 Tushar Krishna <tushar@csail.mit.edu>

garnet: use vnet_type from protocol to decide buffer depths

The virtual channels within "response" vnets are made buffers_per_data_vc
deep (default=4), while virtual channels within other vnets are made
buffers_per_ctrl_vc deep (default = 1). This is for accurate power estimates.

8308:79cf09f5a234 18-May-2011 Tushar Krishna <tushar@csail.mit.edu>

slicc: added vnet_type field to identify response vnets from others

Identifying response vnets versus other vnets will allow garnet to
determine which vnets will carry data packets, and which will carry
ctrl packets, and use appropriate buffer sizes (since data packets are larger
than ctrl packets). This in turn allows the orion power model to accurately
estimate buffer power.

8307:76f7c2858c5c 18-May-2011 Tushar Krishna <tushar@csail.mit.edu>

garnet: rename and rearrange config parameters.

Renamed (message) class to vnet for consistency with rest of ruby.
Moved some parameters specific to fixed/flexible garnet networks into their
corresponding py files.

8292:0990d8c19b64 07-May-2011 Tushar Krishna <tushar@csail.mit.edu>

network: added Torus and Pt2Pt topologies

8289:f64b07758814 05-May-2011 Korey Sewell <ksewell@umich.edu>

ruby: use RubyMemory flag & remove setDebug() functionality
The RubyMemory flag wasnt used in the code, creating large gaps in trace output. Replace cprintfs w/dprintfs
using RubyMemory in memory controller. DPRINTF also deprecate the usage of the setDebug() pure virtual
function in the AbstractMemoryOrCache Class as well the m_debug/cprintf functions in MemoryControl.hh/cc

8266:66a3187a6714 02-May-2011 Korey Sewell <ksewell@umich.edu>

ruby: dbg: use system ticks instead of cycles

8263:8743998edfd3 28-Apr-2011 Brad Beckmann <Brad.Beckmann@amd.com>

network: set the ExtLink bw to 16 bytes

Therefore all links by default are 16 bytes wide and thus work with Garnet's
uniform link bandwidth assumption.

8262:89d0e7c17d1e 28-Apr-2011 Brad Beckmann <Brad.Beckmann@amd.com>

garnet: removed flit_width from Routers

8261:39e42ccddd63 28-Apr-2011 Brad Beckmann <Brad.Beckmann@amd.com>

network: adjusted default endpoint bandwidth

The simple network's endpoint bandwidth value is used to adjust the overall
bandwidth of the network. Specifically, the ration between endpoint bandwidth
and the MESSAGE_SIZE_MULTIPLIER determines the increase. By setting the value
to 1000, that means the bandwdith factor specified in the links translates to
the link bandwidth in bytes. Previously, it was increasing that value by 10.

This patch will likely require a reset of the ruby regression tester stats.

8260:f113f73dd494 28-Apr-2011 Brad Beckmann <Brad.Beckmann@amd.com>

network: removed the unused network-wide latency param

8259:36987780169e 28-Apr-2011 Brad Beckmann <Brad.Beckmann@amd.com>

network: moved network config params

Moved the buffer_size, endpoint_bandwidth, and adaptive_routing params out of
the top-level parent network object and to only those networks that actually
use those parameters.

8258:7c377f5162f8 28-Apr-2011 Brad Beckmann <Brad.Beckmann@amd.com>

network: basic link bw for garnet and simple networks

This patch ensures that both Garnet and the simple networks use the bw value
specified in the topology. To do so, the patch generalizes the specification
of bw for basic links. This value is then translated to the specific value
used by the simple and Garnet networks. Since Garent does not support
non-uniformed link bandwidth, the patch also adds a check to ensure all bws are
equal.

8257:7226aebb77b4 28-Apr-2011 Brad Beckmann <Brad.Beckmann@amd.com>

network: convert links & switches to first class C++ SimObjects

This patch converts links and switches from second class simobjects that were
virtually ignored by the networks (both simple and Garnet) to first class
simobjects that directly correspond to c++ ojbects manipulated by the
topology and network classes. This is especially true for Garnet, where the
links and switches directly correspond to specific C++ objects.

By making this change, many aspects of the Topology class were simplified.


/gem5/configs/ruby/MESI_CMP_directory.py
/gem5/configs/ruby/MI_example.py
/gem5/configs/ruby/MOESI_CMP_directory.py
/gem5/configs/ruby/MOESI_CMP_token.py
/gem5/configs/ruby/MOESI_hammer.py
/gem5/configs/ruby/Network_test.py
/gem5/configs/ruby/Ruby.py
/gem5/src/mem/protocol/RubySlicc_Exports.sm
network/BasicLink.cc
network/BasicLink.hh
network/BasicLink.py
network/BasicRouter.cc
network/BasicRouter.hh
network/BasicRouter.py
network/Network.hh
network/Network.py
network/SConscript
network/Topology.cc
network/Topology.hh
network/garnet/fixed-pipeline/CreditLink_d.hh
network/garnet/fixed-pipeline/GarnetLink_d.cc
network/garnet/fixed-pipeline/GarnetLink_d.hh
network/garnet/fixed-pipeline/GarnetLink_d.py
network/garnet/fixed-pipeline/GarnetNetwork_d.cc
network/garnet/fixed-pipeline/GarnetNetwork_d.hh
network/garnet/fixed-pipeline/GarnetRouter_d.py
network/garnet/fixed-pipeline/NetworkLink_d.cc
network/garnet/fixed-pipeline/NetworkLink_d.hh
network/garnet/fixed-pipeline/Router_d.cc
network/garnet/fixed-pipeline/Router_d.hh
network/garnet/fixed-pipeline/SConscript
network/garnet/flexible-pipeline/GarnetLink.cc
network/garnet/flexible-pipeline/GarnetLink.hh
network/garnet/flexible-pipeline/GarnetLink.py
network/garnet/flexible-pipeline/GarnetNetwork.cc
network/garnet/flexible-pipeline/GarnetNetwork.hh
network/garnet/flexible-pipeline/GarnetRouter.py
network/garnet/flexible-pipeline/NetworkLink.cc
network/garnet/flexible-pipeline/NetworkLink.hh
network/garnet/flexible-pipeline/Router.cc
network/garnet/flexible-pipeline/Router.hh
network/garnet/flexible-pipeline/SConscript
network/orion/NetworkPower.cc
network/simple/SimpleNetwork.cc
network/simple/SimpleNetwork.hh
network/topologies/Crossbar.py
network/topologies/Mesh.py
network/topologies/MeshDirCorners.py
slicc_interface/AbstractController.hh
slicc_interface/Controller.py
8256:2284cec55ef4 28-Apr-2011 Brad Beckmann <Brad.Beckmann@amd.com>

garnet: cleaned up flexible network header file

8255:73089f793a0a 28-Apr-2011 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: moved topology to the top network directory

Moved the Topology class to the top network directory because it is shared by
both the simple and Garnet networks.

8254:779d775abc11 28-Apr-2011 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: removed dated comment in SimpleNetwork

8232:b28d06a175be 15-Apr-2011 Nathan Binkert <nate@binkert.org>

trace: reimplement the DTRACE function so it doesn't use a vector
At the same time, rename the trace flags to debug flags since they
have broader usage than simply tracing. This means that
--trace-flags is now --debug-flags and --trace-help is now --debug-help


/gem5/src/SConscript
/gem5/src/arch/alpha/interrupts.hh
/gem5/src/arch/alpha/kernel_stats.cc
/gem5/src/arch/alpha/linux/process.cc
/gem5/src/arch/alpha/linux/system.cc
/gem5/src/arch/alpha/process.cc
/gem5/src/arch/alpha/remote_gdb.cc
/gem5/src/arch/alpha/stacktrace.hh
/gem5/src/arch/alpha/system.cc
/gem5/src/arch/alpha/tlb.cc
/gem5/src/arch/alpha/vtophys.cc
/gem5/src/arch/arm/faults.cc
/gem5/src/arch/arm/isa.cc
/gem5/src/arch/arm/isa.hh
/gem5/src/arch/arm/isa/includes.isa
/gem5/src/arch/arm/nativetrace.cc
/gem5/src/arch/arm/predecoder.cc
/gem5/src/arch/arm/process.cc
/gem5/src/arch/arm/remote_gdb.cc
/gem5/src/arch/arm/stacktrace.hh
/gem5/src/arch/arm/tlb.cc
/gem5/src/arch/arm/types.hh
/gem5/src/arch/mips/faults.cc
/gem5/src/arch/mips/isa.cc
/gem5/src/arch/mips/isa/includes.isa
/gem5/src/arch/mips/linux/process.cc
/gem5/src/arch/mips/locked_mem.hh
/gem5/src/arch/mips/process.cc
/gem5/src/arch/mips/stacktrace.hh
/gem5/src/arch/mips/tlb.cc
/gem5/src/arch/power/process.cc
/gem5/src/arch/power/stacktrace.hh
/gem5/src/arch/power/tlb.cc
/gem5/src/arch/sparc/interrupts.hh
/gem5/src/arch/sparc/isa.cc
/gem5/src/arch/sparc/isa/includes.isa
/gem5/src/arch/sparc/process.cc
/gem5/src/arch/sparc/remote_gdb.cc
/gem5/src/arch/sparc/stacktrace.hh
/gem5/src/arch/sparc/tlb.cc
/gem5/src/arch/sparc/ua2005.cc
/gem5/src/arch/sparc/vtophys.cc
/gem5/src/arch/x86/faults.cc
/gem5/src/arch/x86/insts/microregop.cc
/gem5/src/arch/x86/insts/static_inst.hh
/gem5/src/arch/x86/interrupts.cc
/gem5/src/arch/x86/isa/includes.isa
/gem5/src/arch/x86/nativetrace.cc
/gem5/src/arch/x86/pagetable_walker.cc
/gem5/src/arch/x86/predecoder.cc
/gem5/src/arch/x86/predecoder.hh
/gem5/src/arch/x86/process.cc
/gem5/src/arch/x86/stacktrace.hh
/gem5/src/arch/x86/tlb.cc
/gem5/src/arch/x86/vtophys.cc
/gem5/src/base/debug.cc
/gem5/src/base/debug.hh
/gem5/src/base/loader/aout_object.cc
/gem5/src/base/loader/ecoff_object.cc
/gem5/src/base/loader/elf_object.cc
/gem5/src/base/loader/raw_object.cc
/gem5/src/base/mysql.cc
/gem5/src/base/remote_gdb.cc
/gem5/src/base/trace.cc
/gem5/src/base/trace.hh
/gem5/src/base/vnc/vncserver.cc
/gem5/src/cpu/SConscript
/gem5/src/cpu/activity.cc
/gem5/src/cpu/base.cc
/gem5/src/cpu/base_dyn_inst_impl.hh
/gem5/src/cpu/exetrace.cc
/gem5/src/cpu/exetrace.hh
/gem5/src/cpu/inorder/cpu.cc
/gem5/src/cpu/inorder/first_stage.cc
/gem5/src/cpu/inorder/inorder_dyn_inst.cc
/gem5/src/cpu/inorder/inorder_dyn_inst.hh
/gem5/src/cpu/inorder/inorder_trace.cc
/gem5/src/cpu/inorder/pipeline_stage.cc
/gem5/src/cpu/inorder/reg_dep_map.cc
/gem5/src/cpu/inorder/resource.cc
/gem5/src/cpu/inorder/resource_pool.cc
/gem5/src/cpu/inorder/resource_sked.cc
/gem5/src/cpu/inorder/resources/agen_unit.cc
/gem5/src/cpu/inorder/resources/bpred_unit.cc
/gem5/src/cpu/inorder/resources/branch_predictor.cc
/gem5/src/cpu/inorder/resources/cache_unit.cc
/gem5/src/cpu/inorder/resources/decode_unit.cc
/gem5/src/cpu/inorder/resources/execution_unit.cc
/gem5/src/cpu/inorder/resources/fetch_seq_unit.cc
/gem5/src/cpu/inorder/resources/fetch_unit.cc
/gem5/src/cpu/inorder/resources/graduation_unit.cc
/gem5/src/cpu/inorder/resources/inst_buffer.cc
/gem5/src/cpu/inorder/resources/mult_div_unit.cc
/gem5/src/cpu/inorder/resources/use_def.cc
/gem5/src/cpu/inorder/thread_context.cc
/gem5/src/cpu/inteltrace.hh
/gem5/src/cpu/intr_control.cc
/gem5/src/cpu/nativetrace.cc
/gem5/src/cpu/o3/bpred_unit_impl.hh
/gem5/src/cpu/o3/commit_impl.hh
/gem5/src/cpu/o3/cpu.cc
/gem5/src/cpu/o3/decode_impl.hh
/gem5/src/cpu/o3/fetch_impl.hh
/gem5/src/cpu/o3/free_list.cc
/gem5/src/cpu/o3/free_list.hh
/gem5/src/cpu/o3/iew.hh
/gem5/src/cpu/o3/iew_impl.hh
/gem5/src/cpu/o3/inst_queue_impl.hh
/gem5/src/cpu/o3/lsq_impl.hh
/gem5/src/cpu/o3/lsq_unit.hh
/gem5/src/cpu/o3/lsq_unit_impl.hh
/gem5/src/cpu/o3/mem_dep_unit.hh
/gem5/src/cpu/o3/mem_dep_unit_impl.hh
/gem5/src/cpu/o3/regfile.hh
/gem5/src/cpu/o3/rename_impl.hh
/gem5/src/cpu/o3/rename_map.cc
/gem5/src/cpu/o3/rob_impl.hh
/gem5/src/cpu/o3/scoreboard.cc
/gem5/src/cpu/o3/scoreboard.hh
/gem5/src/cpu/o3/store_set.cc
/gem5/src/cpu/o3/thread_context_impl.hh
/gem5/src/cpu/pc_event.cc
/gem5/src/cpu/pred/2bit_local.cc
/gem5/src/cpu/pred/btb.cc
/gem5/src/cpu/quiesce_event.cc
/gem5/src/cpu/simple/atomic.cc
/gem5/src/cpu/simple/base.cc
/gem5/src/cpu/simple/timing.cc
/gem5/src/cpu/simple_thread.hh
/gem5/src/cpu/testers/directedtest/InvalidateGenerator.cc
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.cc
/gem5/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
/gem5/src/cpu/testers/memtest/memtest.cc
/gem5/src/cpu/testers/networktest/networktest.cc
/gem5/src/cpu/testers/rubytest/Check.cc
/gem5/src/cpu/testers/rubytest/CheckTable.cc
/gem5/src/cpu/testers/rubytest/RubyTester.cc
/gem5/src/cpu/thread_context.cc
/gem5/src/dev/alpha/backdoor.cc
/gem5/src/dev/alpha/tsunami_cchip.cc
/gem5/src/dev/alpha/tsunami_io.cc
/gem5/src/dev/alpha/tsunami_pchip.cc
/gem5/src/dev/copy_engine.cc
/gem5/src/dev/disk_image.cc
/gem5/src/dev/etherbus.cc
/gem5/src/dev/etherlink.cc
/gem5/src/dev/ethertap.cc
/gem5/src/dev/i8254xGBe.cc
/gem5/src/dev/i8254xGBe.hh
/gem5/src/dev/ide_ctrl.cc
/gem5/src/dev/ide_disk.cc
/gem5/src/dev/intel_8254_timer.cc
/gem5/src/dev/intel_8254_timer.hh
/gem5/src/dev/io_device.cc
/gem5/src/dev/isa_fake.cc
/gem5/src/dev/mc146818.cc
/gem5/src/dev/ns_gige.cc
/gem5/src/dev/pciconfigall.cc
/gem5/src/dev/pcidev.cc
/gem5/src/dev/simple_disk.cc
/gem5/src/dev/sinic.cc
/gem5/src/dev/sparc/iob.cc
/gem5/src/dev/sparc/mm_disk.cc
/gem5/src/dev/terminal.cc
/gem5/src/dev/uart8250.cc
/gem5/src/dev/x86/cmos.cc
/gem5/src/dev/x86/i8042.cc
/gem5/src/dev/x86/i82094aa.cc
/gem5/src/dev/x86/i8254.cc
/gem5/src/dev/x86/i8259.cc
/gem5/src/dev/x86/speaker.cc
/gem5/src/kern/linux/events.cc
/gem5/src/kern/linux/linux.cc
/gem5/src/kern/system_events.cc
/gem5/src/kern/tru64/tru64.hh
/gem5/src/kern/tru64/tru64_events.cc
/gem5/src/mem/bridge.cc
/gem5/src/mem/bus.cc
/gem5/src/mem/cache/base.cc
/gem5/src/mem/cache/base.hh
/gem5/src/mem/cache/cache_impl.hh
/gem5/src/mem/cache/mshr.cc
/gem5/src/mem/cache/prefetch/base.cc
/gem5/src/mem/cache/prefetch/ghb.cc
/gem5/src/mem/cache/prefetch/stride.cc
/gem5/src/mem/cache/tags/iic.cc
/gem5/src/mem/cache/tags/lru.cc
/gem5/src/mem/page_table.cc
/gem5/src/mem/physical.cc
/gem5/src/mem/port.cc
buffers/MessageBuffer.cc
common/NetDest.hh
network/garnet/fixed-pipeline/NetworkInterface_d.cc
network/garnet/fixed-pipeline/Switch_d.cc
network/garnet/flexible-pipeline/NetworkInterface.cc
network/garnet/flexible-pipeline/Router.cc
network/simple/PerfectSwitch.cc
network/simple/Throttle.cc
network/simple/Topology.cc
system/CacheMemory.cc
system/DMASequencer.cc
system/DirectoryMemory.cc
system/RubyPort.cc
system/Sequencer.cc
system/SparseMemory.cc
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/mem/tport.cc
/gem5/src/python/m5/debug.py
/gem5/src/python/m5/main.py
/gem5/src/python/m5/trace.py
/gem5/src/python/swig/debug.i
/gem5/src/python/swig/trace.i
/gem5/src/sim/eventq.cc
/gem5/src/sim/eventq.hh
/gem5/src/sim/faults.cc
/gem5/src/sim/pseudo_inst.cc
/gem5/src/sim/root.cc
/gem5/src/sim/sim_object.cc
/gem5/src/sim/syscall_emul.cc
/gem5/src/sim/syscall_emul.hh
/gem5/src/sim/system.cc
8229:78bf55f23338 15-Apr-2011 Nathan Binkert <nate@binkert.org>

includes: sort all includes


/gem5/src/arch/alpha/faults.cc
/gem5/src/arch/alpha/isa.hh
/gem5/src/arch/alpha/isa/main.isa
/gem5/src/arch/alpha/linux/system.cc
/gem5/src/arch/alpha/mt.hh
/gem5/src/arch/alpha/process.cc
/gem5/src/arch/alpha/remote_gdb.cc
/gem5/src/arch/alpha/remote_gdb.hh
/gem5/src/arch/alpha/tlb.cc
/gem5/src/arch/alpha/tru64/process.cc
/gem5/src/arch/alpha/types.hh
/gem5/src/arch/alpha/utility.hh
/gem5/src/arch/arm/faults.cc
/gem5/src/arch/arm/faults.hh
/gem5/src/arch/arm/insts/macromem.cc
/gem5/src/arch/arm/insts/static_inst.cc
/gem5/src/arch/arm/insts/vfp.hh
/gem5/src/arch/arm/intregs.hh
/gem5/src/arch/arm/isa/includes.isa
/gem5/src/arch/arm/linux/atag.hh
/gem5/src/arch/arm/linux/linux.cc
/gem5/src/arch/arm/linux/process.cc
/gem5/src/arch/arm/linux/process.hh
/gem5/src/arch/arm/linux/system.cc
/gem5/src/arch/arm/locked_mem.hh
/gem5/src/arch/arm/pagetable.hh
/gem5/src/arch/arm/predecoder.hh
/gem5/src/arch/arm/process.hh
/gem5/src/arch/arm/registers.hh
/gem5/src/arch/arm/remote_gdb.cc
/gem5/src/arch/arm/system.cc
/gem5/src/arch/arm/system.hh
/gem5/src/arch/arm/table_walker.cc
/gem5/src/arch/arm/table_walker.hh
/gem5/src/arch/arm/tlb.hh
/gem5/src/arch/arm/vtophys.hh
/gem5/src/arch/generic/debugfaults.hh
/gem5/src/arch/generic/types.hh
/gem5/src/arch/mips/dsp.cc
/gem5/src/arch/mips/dsp.hh
/gem5/src/arch/mips/isa.cc
/gem5/src/arch/mips/isa.hh
/gem5/src/arch/mips/isa/includes.isa
/gem5/src/arch/mips/isa_traits.hh
/gem5/src/arch/mips/linux/linux.cc
/gem5/src/arch/mips/linux/process.cc
/gem5/src/arch/mips/linux/process.hh
/gem5/src/arch/mips/linux/system.cc
/gem5/src/arch/mips/mt.hh
/gem5/src/arch/mips/process.cc
/gem5/src/arch/mips/process.hh
/gem5/src/arch/mips/system.cc
/gem5/src/arch/mips/system.hh
/gem5/src/arch/mips/tlb.cc
/gem5/src/arch/mips/tlb.hh
/gem5/src/arch/mips/utility.cc
/gem5/src/arch/mips/utility.hh
/gem5/src/arch/mips/vtophys.hh
/gem5/src/arch/power/insts/floating.hh
/gem5/src/arch/power/insts/integer.hh
/gem5/src/arch/power/isa/includes.isa
/gem5/src/arch/power/linux/linux.cc
/gem5/src/arch/power/linux/process.cc
/gem5/src/arch/power/linux/process.hh
/gem5/src/arch/power/process.hh
/gem5/src/arch/power/tlb.hh
/gem5/src/arch/power/vtophys.hh
/gem5/src/arch/sparc/isa.hh
/gem5/src/arch/sparc/isa/includes.isa
/gem5/src/arch/sparc/isa_traits.hh
/gem5/src/arch/sparc/linux/linux.cc
/gem5/src/arch/sparc/linux/process.cc
/gem5/src/arch/sparc/locked_mem.hh
/gem5/src/arch/sparc/mmapped_ipr.hh
/gem5/src/arch/sparc/nativetrace.cc
/gem5/src/arch/sparc/process.cc
/gem5/src/arch/sparc/process.hh
/gem5/src/arch/sparc/remote_gdb.cc
/gem5/src/arch/sparc/remote_gdb.hh
/gem5/src/arch/sparc/solaris/process.cc
/gem5/src/arch/sparc/solaris/solaris.cc
/gem5/src/arch/sparc/system.cc
/gem5/src/arch/sparc/tlb.cc
/gem5/src/arch/sparc/tlb_map.hh
/gem5/src/arch/sparc/types.hh
/gem5/src/arch/sparc/utility.hh
/gem5/src/arch/sparc/vtophys.cc
/gem5/src/arch/x86/bios/acpi.cc
/gem5/src/arch/x86/bios/intelmp.hh
/gem5/src/arch/x86/emulenv.hh
/gem5/src/arch/x86/faults.hh
/gem5/src/arch/x86/insts/badmicroop.cc
/gem5/src/arch/x86/insts/macroop.hh
/gem5/src/arch/x86/insts/microfpop.cc
/gem5/src/arch/x86/insts/microldstop.cc
/gem5/src/arch/x86/insts/micromediaop.cc
/gem5/src/arch/x86/interrupts.cc
/gem5/src/arch/x86/interrupts.hh
/gem5/src/arch/x86/isa.hh
/gem5/src/arch/x86/isa/includes.isa
/gem5/src/arch/x86/linux/linux.cc
/gem5/src/arch/x86/linux/process.cc
/gem5/src/arch/x86/linux/process.hh
/gem5/src/arch/x86/linux/syscalls.cc
/gem5/src/arch/x86/linux/system.cc
/gem5/src/arch/x86/linux/system.hh
/gem5/src/arch/x86/microcode_rom.hh
/gem5/src/arch/x86/nativetrace.cc
/gem5/src/arch/x86/pagetable_walker.cc
/gem5/src/arch/x86/pagetable_walker.hh
/gem5/src/arch/x86/predecoder.hh
/gem5/src/arch/x86/process.cc
/gem5/src/arch/x86/process.hh
/gem5/src/arch/x86/registers.hh
/gem5/src/arch/x86/remote_gdb.cc
/gem5/src/arch/x86/system.cc
/gem5/src/arch/x86/tlb.cc
/gem5/src/arch/x86/tlb.hh
/gem5/src/base/cp_annotate.cc
/gem5/src/base/cp_annotate.hh
/gem5/src/base/cprintf.hh
/gem5/src/base/debug.cc
/gem5/src/base/fast_alloc.hh
/gem5/src/base/fenv.c
/gem5/src/base/hostinfo.cc
/gem5/src/base/inet.hh
/gem5/src/base/inifile.cc
/gem5/src/base/loader/aout_object.cc
/gem5/src/base/loader/elf_object.cc
/gem5/src/base/loader/elf_object.hh
/gem5/src/base/loader/hex_file.cc
/gem5/src/base/loader/object_file.cc
/gem5/src/base/loader/symtab.cc
/gem5/src/base/misc.cc
/gem5/src/base/mysql.hh
/gem5/src/base/output.cc
/gem5/src/base/pollevent.cc
/gem5/src/base/pollevent.hh
/gem5/src/base/range_map.hh
/gem5/src/base/remote_gdb.cc
/gem5/src/base/remote_gdb.hh
/gem5/src/base/socket.cc
/gem5/src/base/statistics.cc
/gem5/src/base/statistics.hh
/gem5/src/base/stats/info.hh
/gem5/src/base/stats/mysql.cc
/gem5/src/base/stats/output.cc
/gem5/src/base/stats/text.cc
/gem5/src/base/stats/text.hh
/gem5/src/base/str.hh
/gem5/src/base/time.hh
/gem5/src/base/trace.cc
/gem5/src/base/vnc/convert.cc
/gem5/src/base/vnc/vncserver.cc
/gem5/src/base/vnc/vncserver.hh
/gem5/src/cpu/activity.cc
/gem5/src/cpu/activity.hh
/gem5/src/cpu/base.cc
/gem5/src/cpu/base.hh
/gem5/src/cpu/base_dyn_inst_impl.hh
/gem5/src/cpu/checker/cpu.cc
/gem5/src/cpu/checker/cpu.hh
/gem5/src/cpu/checker/cpu_impl.hh
/gem5/src/cpu/cpuevent.hh
/gem5/src/cpu/exetrace.cc
/gem5/src/cpu/func_unit.hh
/gem5/src/cpu/inorder/cpu.cc
/gem5/src/cpu/inorder/cpu.hh
/gem5/src/cpu/inorder/first_stage.cc
/gem5/src/cpu/inorder/first_stage.hh
/gem5/src/cpu/inorder/inorder_cpu_builder.cc
/gem5/src/cpu/inorder/inorder_dyn_inst.cc
/gem5/src/cpu/inorder/inorder_dyn_inst.hh
/gem5/src/cpu/inorder/inorder_trace.cc
/gem5/src/cpu/inorder/pipeline_stage.cc
/gem5/src/cpu/inorder/pipeline_stage.hh
/gem5/src/cpu/inorder/pipeline_traits.5stage.cc
/gem5/src/cpu/inorder/pipeline_traits.5stage.hh
/gem5/src/cpu/inorder/pipeline_traits.9stage.cc
/gem5/src/cpu/inorder/pipeline_traits.9stage.hh
/gem5/src/cpu/inorder/pipeline_traits.9stage.smt2.cc
/gem5/src/cpu/inorder/pipeline_traits.9stage.smt2.hh
/gem5/src/cpu/inorder/pipeline_traits.hh
/gem5/src/cpu/inorder/reg_dep_map.cc
/gem5/src/cpu/inorder/resource.cc
/gem5/src/cpu/inorder/resource.hh
/gem5/src/cpu/inorder/resource_pool.9stage.cc
/gem5/src/cpu/inorder/resource_pool.cc
/gem5/src/cpu/inorder/resource_pool.hh
/gem5/src/cpu/inorder/resource_sked.cc
/gem5/src/cpu/inorder/resource_sked.hh
/gem5/src/cpu/inorder/resources/agen_unit.hh
/gem5/src/cpu/inorder/resources/bpred_unit.hh
/gem5/src/cpu/inorder/resources/branch_predictor.hh
/gem5/src/cpu/inorder/resources/cache_unit.cc
/gem5/src/cpu/inorder/resources/cache_unit.hh
/gem5/src/cpu/inorder/resources/decode_unit.hh
/gem5/src/cpu/inorder/resources/execution_unit.cc
/gem5/src/cpu/inorder/resources/execution_unit.hh
/gem5/src/cpu/inorder/resources/fetch_seq_unit.hh
/gem5/src/cpu/inorder/resources/fetch_unit.cc
/gem5/src/cpu/inorder/resources/fetch_unit.hh
/gem5/src/cpu/inorder/resources/graduation_unit.hh
/gem5/src/cpu/inorder/resources/inst_buffer.cc
/gem5/src/cpu/inorder/resources/inst_buffer.hh
/gem5/src/cpu/inorder/resources/mem_dep_unit.hh
/gem5/src/cpu/inorder/resources/mult_div_unit.cc
/gem5/src/cpu/inorder/resources/mult_div_unit.hh
/gem5/src/cpu/inorder/resources/resource_list.hh
/gem5/src/cpu/inorder/resources/tlb_unit.cc
/gem5/src/cpu/inorder/resources/tlb_unit.hh
/gem5/src/cpu/inorder/resources/use_def.cc
/gem5/src/cpu/inorder/resources/use_def.hh
/gem5/src/cpu/inorder/thread_context.cc
/gem5/src/cpu/inorder/thread_context.hh
/gem5/src/cpu/inorder/thread_state.cc
/gem5/src/cpu/intr_control.cc
/gem5/src/cpu/intr_control.hh
/gem5/src/cpu/nativetrace.hh
/gem5/src/cpu/o3/base_dyn_inst.cc
/gem5/src/cpu/o3/bpred_unit.hh
/gem5/src/cpu/o3/bpred_unit_impl.hh
/gem5/src/cpu/o3/checker_builder.cc
/gem5/src/cpu/o3/commit.cc
/gem5/src/cpu/o3/commit.hh
/gem5/src/cpu/o3/commit_impl.hh
/gem5/src/cpu/o3/cpu.cc
/gem5/src/cpu/o3/cpu.hh
/gem5/src/cpu/o3/cpu_policy.hh
/gem5/src/cpu/o3/decode.cc
/gem5/src/cpu/o3/dyn_inst.hh
/gem5/src/cpu/o3/fetch.cc
/gem5/src/cpu/o3/fetch.hh
/gem5/src/cpu/o3/fetch_impl.hh
/gem5/src/cpu/o3/free_list.cc
/gem5/src/cpu/o3/fu_pool.hh
/gem5/src/cpu/o3/iew.cc
/gem5/src/cpu/o3/iew.hh
/gem5/src/cpu/o3/iew_impl.hh
/gem5/src/cpu/o3/impl.hh
/gem5/src/cpu/o3/inst_queue.cc
/gem5/src/cpu/o3/inst_queue.hh
/gem5/src/cpu/o3/isa_specific.hh
/gem5/src/cpu/o3/lsq.hh
/gem5/src/cpu/o3/lsq_unit.hh
/gem5/src/cpu/o3/lsq_unit_impl.hh
/gem5/src/cpu/o3/mem_dep_unit.cc
/gem5/src/cpu/o3/rename.hh
/gem5/src/cpu/o3/scoreboard.hh
/gem5/src/cpu/o3/thread_context.cc
/gem5/src/cpu/o3/thread_context.hh
/gem5/src/cpu/ozone/back_end.hh
/gem5/src/cpu/ozone/back_end_impl.hh
/gem5/src/cpu/ozone/base_dyn_inst.cc
/gem5/src/cpu/ozone/checker_builder.cc
/gem5/src/cpu/ozone/cpu.hh
/gem5/src/cpu/ozone/cpu_builder.cc
/gem5/src/cpu/ozone/cpu_impl.hh
/gem5/src/cpu/ozone/dyn_inst.hh
/gem5/src/cpu/ozone/dyn_inst_impl.hh
/gem5/src/cpu/ozone/ea_list.cc
/gem5/src/cpu/ozone/front_end.hh
/gem5/src/cpu/ozone/front_end_impl.hh
/gem5/src/cpu/ozone/inorder_back_end.hh
/gem5/src/cpu/ozone/inorder_back_end_impl.hh
/gem5/src/cpu/ozone/inst_queue.cc
/gem5/src/cpu/ozone/inst_queue.hh
/gem5/src/cpu/ozone/inst_queue_impl.hh
/gem5/src/cpu/ozone/lsq_unit.cc
/gem5/src/cpu/ozone/lsq_unit.hh
/gem5/src/cpu/ozone/lw_back_end.hh
/gem5/src/cpu/ozone/lw_lsq.cc
/gem5/src/cpu/ozone/lw_lsq.hh
/gem5/src/cpu/ozone/lw_lsq_impl.hh
/gem5/src/cpu/ozone/ozone_base_dyn_inst.cc
/gem5/src/cpu/ozone/ozone_impl.hh
/gem5/src/cpu/ozone/rename_table.cc
/gem5/src/cpu/ozone/simple_base_dyn_inst.cc
/gem5/src/cpu/ozone/simple_cpu_builder.cc
/gem5/src/cpu/ozone/simple_impl.hh
/gem5/src/cpu/pc_event.cc
/gem5/src/cpu/profile.cc
/gem5/src/cpu/profile.hh
/gem5/src/cpu/quiesce_event.cc
/gem5/src/cpu/sched_list.hh
/gem5/src/cpu/simple/atomic.cc
/gem5/src/cpu/simple/base.cc
/gem5/src/cpu/simple/base.hh
/gem5/src/cpu/simple/timing.cc
/gem5/src/cpu/simple/timing.hh
/gem5/src/cpu/simple_thread.hh
/gem5/src/cpu/static_inst.cc
/gem5/src/cpu/static_inst.hh
/gem5/src/cpu/testers/directedtest/InvalidateGenerator.cc
/gem5/src/cpu/testers/directedtest/InvalidateGenerator.hh
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.hh
/gem5/src/cpu/testers/memtest/memtest.cc
/gem5/src/cpu/testers/memtest/memtest.hh
/gem5/src/cpu/testers/networktest/networktest.cc
/gem5/src/cpu/testers/networktest/networktest.hh
/gem5/src/cpu/testers/rubytest/CheckTable.cc
/gem5/src/cpu/testers/rubytest/RubyTester.hh
/gem5/src/cpu/thread_context.hh
/gem5/src/cpu/thread_state.hh
/gem5/src/cpu/trace/opt_cpu.cc
/gem5/src/cpu/trace/reader/ibm_reader.hh
/gem5/src/cpu/trace/reader/itx_reader.hh
/gem5/src/cpu/trace/reader/mem_trace_reader.hh
/gem5/src/cpu/trace/trace_cpu.cc
/gem5/src/dev/alpha/tsunami.cc
/gem5/src/dev/alpha/tsunami_io.cc
/gem5/src/dev/alpha/tsunami_io.hh
/gem5/src/dev/alpha/tsunami_pchip.cc
/gem5/src/dev/arm/amba_device.cc
/gem5/src/dev/arm/amba_device.hh
/gem5/src/dev/arm/kmi.cc
/gem5/src/dev/arm/kmi.hh
/gem5/src/dev/arm/pl111.cc
/gem5/src/dev/disk_image.cc
/gem5/src/dev/disk_image.hh
/gem5/src/dev/etherbus.hh
/gem5/src/dev/etherdump.hh
/gem5/src/dev/etherint.cc
/gem5/src/dev/etherlink.cc
/gem5/src/dev/etherlink.hh
/gem5/src/dev/ethertap.cc
/gem5/src/dev/ethertap.hh
/gem5/src/dev/ide_ctrl.hh
/gem5/src/dev/ide_disk.cc
/gem5/src/dev/ide_disk.hh
/gem5/src/dev/intel_8254_timer.hh
/gem5/src/dev/io_device.cc
/gem5/src/dev/isa_fake.hh
/gem5/src/dev/mc146818.cc
/gem5/src/dev/mips/malta.cc
/gem5/src/dev/mips/malta_cchip.hh
/gem5/src/dev/mips/malta_io.cc
/gem5/src/dev/mips/malta_pchip.cc
/gem5/src/dev/mips/malta_pchip.hh
/gem5/src/dev/pciconfigall.hh
/gem5/src/dev/platform.hh
/gem5/src/dev/ps2.cc
/gem5/src/dev/simple_disk.hh
/gem5/src/dev/sparc/iob.cc
/gem5/src/dev/sparc/iob.hh
/gem5/src/dev/sparc/mm_disk.cc
/gem5/src/dev/sparc/mm_disk.hh
/gem5/src/dev/terminal.cc
/gem5/src/dev/terminal.hh
/gem5/src/dev/x86/i8042.hh
/gem5/src/dev/x86/i82094aa.hh
/gem5/src/dev/x86/i8259.hh
/gem5/src/dev/x86/intdev.hh
/gem5/src/dev/x86/pc.cc
/gem5/src/dev/x86/south_bridge.hh
/gem5/src/kern/kernel_stats.cc
/gem5/src/kern/kernel_stats.hh
/gem5/src/kern/linux/events.cc
/gem5/src/kern/linux/printk.cc
/gem5/src/kern/operatingsystem.cc
/gem5/src/kern/tru64/dump_mbuf.cc
/gem5/src/kern/tru64/printf.cc
/gem5/src/kern/tru64/tru64.hh
/gem5/src/kern/tru64/tru64_events.cc
/gem5/src/mem/bridge.hh
/gem5/src/mem/bus.hh
/gem5/src/mem/cache/base.hh
/gem5/src/mem/cache/blk.hh
/gem5/src/mem/cache/builder.cc
/gem5/src/mem/cache/cache.hh
/gem5/src/mem/cache/cache_impl.hh
/gem5/src/mem/cache/mshr_queue.hh
/gem5/src/mem/cache/prefetch/base.cc
/gem5/src/mem/cache/prefetch/stride.hh
/gem5/src/mem/cache/tags/base.cc
/gem5/src/mem/cache/tags/base.hh
/gem5/src/mem/cache/tags/cacheset.hh
/gem5/src/mem/cache/tags/fa_lru.hh
/gem5/src/mem/cache/tags/iic.cc
/gem5/src/mem/cache/tags/iic.hh
/gem5/src/mem/cache/tags/iic_repl/gen.cc
/gem5/src/mem/cache/tags/iic_repl/repl.hh
/gem5/src/mem/cache/tags/lru.cc
/gem5/src/mem/cache/tags/lru.hh
/gem5/src/mem/packet.cc
/gem5/src/mem/packet.hh
/gem5/src/mem/page_table.cc
/gem5/src/mem/physical.cc
buffers/MessageBuffer.hh
common/NetDest.cc
common/Set.hh
filters/GenericBloomFilter.hh
network/Network.cc
network/garnet/BaseGarnetNetwork.hh
network/garnet/fixed-pipeline/GarnetNetwork_d.cc
network/garnet/fixed-pipeline/GarnetNetwork_d.hh
network/garnet/fixed-pipeline/InputUnit_d.hh
network/garnet/fixed-pipeline/NetworkInterface_d.cc
network/garnet/fixed-pipeline/NetworkInterface_d.hh
network/garnet/fixed-pipeline/NetworkLink_d.cc
network/garnet/fixed-pipeline/NetworkLink_d.hh
network/garnet/fixed-pipeline/OutVcState_d.cc
network/garnet/fixed-pipeline/OutVcState_d.hh
network/garnet/fixed-pipeline/OutputUnit_d.hh
network/garnet/fixed-pipeline/Router_d.cc
network/garnet/fixed-pipeline/Router_d.hh
network/garnet/fixed-pipeline/RoutingUnit_d.cc
network/garnet/fixed-pipeline/RoutingUnit_d.hh
network/garnet/fixed-pipeline/SWallocator_d.cc
network/garnet/fixed-pipeline/SWallocator_d.hh
network/garnet/fixed-pipeline/Switch_d.cc
network/garnet/fixed-pipeline/Switch_d.hh
network/garnet/fixed-pipeline/VCallocator_d.cc
network/garnet/fixed-pipeline/VCallocator_d.hh
network/garnet/fixed-pipeline/VirtualChannel_d.hh
network/garnet/fixed-pipeline/flitBuffer_d.hh
network/garnet/flexible-pipeline/FlexibleConsumer.hh
network/garnet/flexible-pipeline/GarnetNetwork.cc
network/garnet/flexible-pipeline/GarnetNetwork.hh
network/garnet/flexible-pipeline/NetworkInterface.cc
network/garnet/flexible-pipeline/NetworkInterface.hh
network/garnet/flexible-pipeline/NetworkLink.cc
network/garnet/flexible-pipeline/NetworkLink.hh
network/garnet/flexible-pipeline/Router.cc
network/garnet/flexible-pipeline/Router.hh
network/garnet/flexible-pipeline/VCarbiter.cc
network/garnet/flexible-pipeline/VCarbiter.hh
network/garnet/flexible-pipeline/flitBuffer.hh
network/orion/Allocator/Arbiter.cc
network/orion/Allocator/MatrixArbiter.hh
network/orion/Allocator/RRArbiter.cc
network/orion/Allocator/RRArbiter.hh
network/orion/Allocator/SWAllocator.cc
network/orion/Allocator/VCAllocator.cc
network/orion/Buffer/Buffer.cc
network/orion/Buffer/DecoderUnit.hh
network/orion/Buffer/OutdrvUnit.cc
network/orion/Buffer/PrechargeUnit.cc
network/orion/Buffer/Register.cc
network/orion/Buffer/SRAM.cc
network/orion/Buffer/SRAM.hh
network/orion/Buffer/WordlineUnit.cc
network/orion/Clock.cc
network/orion/ConfigFile.hh
network/orion/Crossbar/Crossbar.cc
network/orion/Crossbar/MatrixCrossbar.cc
network/orion/Crossbar/MatrixCrossbar.hh
network/orion/Crossbar/MultreeCrossbar.cc
network/orion/Crossbar/MultreeCrossbar.hh
network/orion/FlipFlop.cc
network/orion/NetworkPower.cc
network/orion/NetworkPower.hh
network/orion/OrionConfig.cc
network/orion/OrionConfig.hh
network/orion/OrionLink.cc
network/orion/OrionRouter.cc
network/orion/TechParameter.cc
network/orion/Wire.cc
network/orion/orion.hh
network/simple/PerfectSwitch.hh
network/simple/Switch.cc
network/simple/Throttle.cc
network/simple/Throttle.hh
network/simple/Topology.cc
profiler/CacheProfiler.hh
profiler/Profiler.cc
profiler/Profiler.hh
recorder/CacheRecorder.cc
recorder/CacheRecorder.hh
recorder/Tracer.hh
slicc_interface/AbstractEntry.hh
slicc_interface/RubyRequest.hh
slicc_interface/RubySlicc_ComponentMapping.cc
slicc_interface/RubySlicc_includes.hh
system/CacheMemory.hh
system/RubyPort.cc
system/RubyPort.hh
system/Sequencer.cc
system/Sequencer.hh
system/WireBuffer.hh
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/mem/tport.hh
/gem5/src/mem/translating_port.cc
/gem5/src/mem/vport.hh
/gem5/src/python/swig/core.i
/gem5/src/python/swig/event.i
/gem5/src/python/swig/inet.i
/gem5/src/python/swig/pyobject.cc
/gem5/src/python/swig/sim_object.i
/gem5/src/python/swig/stats.i
/gem5/src/python/swig/system.i
/gem5/src/sim/faults.cc
/gem5/src/sim/faults.hh
/gem5/src/sim/init.cc
/gem5/src/sim/process.cc
/gem5/src/sim/process_impl.hh
/gem5/src/sim/pseudo_inst.cc
/gem5/src/sim/serialize.cc
/gem5/src/sim/serialize.hh
/gem5/src/sim/stat_control.cc
/gem5/src/sim/syscall_emul.cc
/gem5/src/sim/syscall_emul.hh
/gem5/src/sim/system.cc
/gem5/src/sim/tlb.cc
/gem5/src/sim/vptr.hh
/gem5/src/unittest/cprintftest.cc
/gem5/src/unittest/cprintftime.cc
/gem5/src/unittest/initest.cc
/gem5/src/unittest/rangemaptest.cc
/gem5/src/unittest/stattest.cc
/gem5/src/unittest/symtest.cc
/gem5/util/ccdrv/devtime.c
/gem5/util/m5/m5.c
/gem5/util/statetrace/arch/amd64/tracechild.cc
/gem5/util/statetrace/arch/amd64/tracechild.hh
/gem5/util/statetrace/arch/arm/tracechild.cc
/gem5/util/statetrace/arch/arm/tracechild.hh
/gem5/util/statetrace/arch/i686/tracechild.cc
/gem5/util/statetrace/arch/i686/tracechild.hh
/gem5/util/statetrace/arch/sparc/tracechild.cc
/gem5/util/statetrace/arch/sparc/tracechild.hh
/gem5/util/statetrace/base/regstate.hh
/gem5/util/statetrace/base/statetrace.cc
/gem5/util/statetrace/base/tracechild.cc
/gem5/util/tap/tap.cc
/gem5/util/term/term.c
8214:02cb69e5cfeb 06-Apr-2011 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: fixes to support more types of RubyRequests

8193:c7302d55d644 31-Mar-2011 Lisa Hsu <Lisa.Hsu@amd.com>

CacheMemory: add allocateVoid() that is == allocate() but no return value.
This function duplicates the functionality of allocate() exactly, except that it does not return
a return value. In protocols where you just want to allocate a block
but do not want that block to be your implicitly passed cache_entry, use this function.
Otherwise, SLICC will complain if you do not consume the pointer returned by allocate(),
and if you do a dummy assignment Entry foo := cache.allocate(address), the C++
compiler will complain of an unused variable. This is kind of a hack to get around
those issues, but suggestions welcome.

8191:777459f7c61f 31-Mar-2011 Lisa Hsu <Lisa.Hsu@amd.com>

Ruby: Add new object called WireBuffer to mimic a Wire.
This is a substitute for MessageBuffers between controllers where you don't
want messages to actually go through the Network, because requests/responses can
always get reordered wrt to one another (even if you turn off Randomization and turn on Ordered)
because you are, after all, going through a network with contention. For systems where you model
multiple controllers that are very tightly coupled and do not actually go through a network,
it is a pain to have to write a coherence protocol to account for mixed up request/response orderings
despite the fact that it's completely unrealistic. This is *not* meant as a substitute for real
MessageBuffers when messages do in fact go over a network.

8188:20dbef14192d 31-Mar-2011 Lisa Hsu <Lisa.Hsu@amd.com>

Ruby: pass Packet->Req->contextId() to Ruby.
It is useful for Ruby to understand from whence request packets came.
This has all request packets going into Ruby pass the contextId value, if
it exists. This supplants the old libruby proc_id value passed around in
all the Messages, so I've also removed the unused unsigned proc_id; member
generated by SLICC for all Message types.

8184:a8d64545cda6 28-Mar-2011 Somayeh Sardashti <somayeh@cs.wisc.edu>

This patch supports cache flushing in MOESI_hammer

8174:e21f6e70169e 22-Mar-2011 Nilay Vaish<nilay@cs.wisc.edu>

Ruby: Remove CacheMsg class from SLICC
The goal of the patch is to do away with the CacheMsg class currently in use
in coherence protocols. In place of CacheMsg, the RubyRequest class will used.
This class is already present in slicc_interface/RubyRequest.hh. In fact,
objects of class CacheMsg are generated by copying values from a RubyRequest
object.

8173:2c47dc111abd 21-Mar-2011 Tushar Krishna <tushar@csail.mit.edu>

This patch makes garnet use the info about active and inactive vnets during allocation and power estimations etc

8172:bdb039c42553 21-Mar-2011 Tushar Krishna <tushar@csail.mit.edu>

fix garnet fleible pipeline

8171:19444b1f092c 21-Mar-2011 Tushar Krishna <tushar@csail.mit.edu>

This patch adds the network tester for simple and garnet networks.
The tester code is in testers/networktest.
The tester can be invoked by configs/example/ruby_network_test.py.
A dummy coherence protocol called Network_test is also addded for network-only simulations and testing. The protocol takes in messages from the tester and just pushes them into the network in the appropriate vnet, without storing any state.

8165:5955406f7ed0 19-Mar-2011 Nilay Vaish<nilay@cs.wisc.edu>

Ruby: Convert CacheRequestType to RubyRequestType
This patch converts CacheRequestType to RubyRequestType so that both the
protocol dependent and independent code makes use of the same request type.

8164:b043c0efa024 19-Mar-2011 Nilay Vaish<nilay@cs.wisc.edu>

Ruby: Convert AccessModeType to RubyAccessMode
This patch converts AccessModeType to RubyAccessMode so that both the
protocol dependent and independent code uses the same access mode.

8162:5f69f1b0039e 19-Mar-2011 Brad Beckmann <Brad.Beckmann@amd.com>

Ruby: dma retry fix

This patch fixes the problem where Ruby would fail to call sendRetry on ports
after it nacked the port. This patch is particularly helpful for bursty dma
requests which often include several packets.

8161:ebb373fcb206 19-Mar-2011 Brad Beckmann <Brad.Beckmann@amd.com>

RubyPort: minor fixes to trace flag and dprintfs

8160:0b3252d3b400 19-Mar-2011 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: added useful dma progress dprintf

8132:b0ecadb07742 17-Mar-2011 Lisa Hsu <Lisa.Hsu@amd.com>

Ruby: minor bugfix, line did not adhere to some macro usage conventions.

8131:03f7df749b9d 17-Mar-2011 Lisa Hsu <Lisa.Hsu@amd.com>

Ruby: expose a simple mod function in slicc interface.

8125:05d2937bacbf 11-Mar-2011 Gabe Black <gblack@eecs.umich.edu>

Gems: Eliminate the now unused GEMS_ROOT scons variable.

8124:0dc6769af3a1 11-Mar-2011 Gabe Black <gblack@eecs.umich.edu>

Ruby: Get rid of the dead ruby tester.

None of the code in the ruby tester directory is compiled or referred to
outside of that directory. This change eliminates it. If it's needed in the
future, it can be revived from the history. In the mean time, this removes
clutter and the only use of the GEMS_ROOT scons variable.

8101:2e1ee8ec6266 01-Mar-2011 Nilay Vaish<nilay@cs.wisc.edu>

Ruby: Fix DPRINTF bugs in PerfectSwitch and MessageBuffer
At a couple of places in PerfectSwitch.cc and MessageBuffer.cc, DPRINTF()
has not been provided with correct number of arguments. The patch fixes these
bugs.

8099:265202bbac87 01-Mar-2011 Gabe Black <gblack@eecs.umich.edu>

Ruby: Mention that Ruby's bound checking option only applies to Ruby.

8094:baf4b5f6782e 27-Feb-2011 Nathan Binkert <nate@binkert.org>

getopt: Remove GPL code.
This code is unused and should never have been committed

8093:05a2f6ac1f8e 25-Feb-2011 Nilay Vaish<nilay@cs.wisc.edu>

Ruby: Remove store buffer
This patch removes the store buffer from Ruby. It is not in use currently.
Since libruby is being and store buffer makes calls to libruby, it is not
possible to maintain it until substantial changes are made.

8092:6782b51ae8a8 25-Feb-2011 Nilay Vaish<nilay@cs.wisc.edu>

Ruby: Remove libruby
This patch removes libruby_internal.hh, libruby.hh and libruby.cc. It moves
the contents to libruby.hh to RubyRequest.hh and RubyRequest.cc files.

8091:04078b1214dd 25-Feb-2011 Nilay Vaish<nilay@cs.wisc.edu>

Ruby: Make Address.hh independent of RubySystem
This patch changes Address.hh so that it is not dependent on RubySystem.
This dependence seems unecessary. All those functions that depend on
RubySystem have been moved to Address.cc file.

8090:722a0d28ee83 25-Feb-2011 Nilay Vaish<nilay@cs.wisc.edu>

Ruby: Make DataBlock.hh independent of RubySystem
This patch changes DataBlock.hh so that it is not dependent on RubySystem.
This dependence seems unecessary. All those functions that depende on
RubySystem have been moved to DataBlock.cc file.

8086:bf0335d98250 23-Feb-2011 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: automate permission setting

This patch integrates permissions with cache and memory states, and then
automates the setting of permissions within the generated code. No longer
does one need to manually set the permissions within the setState funciton.
This patch will faciliate easier functional access support by always correctly
setting permissions for both cache and memory states.

8084:d1bb88080be4 23-Feb-2011 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: cleaned up access permission enum

8054:9138d38eccd7 23-Feb-2011 Korey Sewell <ksewell@umich.edu>

ruby: cleaning up RubyQueue and RubyNetwork dprintfs
Overall, continue to progress Ruby debug messages to more of the normal M5
debug message style
- add a name() to the Ruby Throttle & PerfectSwitch objects so that the debug output
isn't littered w/"global:" everywhere.
- clean up messages that print over multiple lines when possible
- clean up duplicate prints in the message buffer

7973:e5550966464a 14-Feb-2011 Nilay Vaish<nilay@cs.wisc.edu>

Ruby: Improve Change PerfectSwitch's wakeup function
Currently the wakeup function for the PerfectSwitch contains three loops -

loop on number of virtual networks
loop on number of incoming links
loop till all messages for this (link, network) have been routed

With an 8 processor mesh network and Hammer protocol, about 11-12% of the
was observed to have been spent in this function, which is the highest
amongst all the functions. It was found that the innermost loop is executed
about 45 times per invocation of the wakeup function, when each invocation
of the wakeup function processes just about one message.

The patch tries to do away with the redundant executions of the innermost
loop. Counters have been added for each virtual network that record the
number of messages that need to be routed for that virtual network. The
inner loops are only executed when the number of messages for that particular
virtual network > 0. This does away with almost 80% of the executions of the
innermost loop. The function now consumes about 5-6% of the total execution
time.

7940:d6294150a32e 09-Feb-2011 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: removed duplicate make response call

7929:68f37178b408 07-Feb-2011 Nilay Vaish<nilay@cs.wisc.edu>

Orion: Replace printf() with fatal()
The code for Orion 2.0 makes use of printf() at several places where there as
an error in configuration of the model. These have been replaced with fatal().

7928:5f2a2deb377d 07-Feb-2011 Korey Sewell <ksewell@umich.edu>

ruby: add stdio header in SRAM.hh
missing header file caused RUBY_FS to not compile

7922:7532067f818e 07-Feb-2011 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: support to stallAndWait the mandatory queue

By stalling and waiting the mandatory queue instead of recycling it, one can
ensure that no incoming messages are starved when the mandatory queue puts
signficant of pressure on the L1 cache controller (i.e. the ruby memtester).

7921:351f1761765f 07-Feb-2011 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: minor fix to deadlock panic message

7919:3a02353d6e43 07-Feb-2011 Joel Hestness <hestness@cs.utexas.edu>

garnet: Split network power in ruby.stats

Split out dynamic and static power numbers for printing to ruby.stats

7917:d9afb18a5008 07-Feb-2011 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: numa bit fix for sparse memory

7915:bc39c93a5519 07-Feb-2011 Brad Beckmann <Brad.Beckmann@amd.com>

mem: Added support for Null data packet

The packet now identifies whether static or dynamic data has been allocated and
is used by Ruby to determine whehter to copy the data pointer into the ruby
request. Subsequently, Ruby can be told not to update phys memory when
receiving packets.

7910:8a92b39be50e 07-Feb-2011 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Fix RubyPort to properly handle retrys

7909:eee578ed2130 07-Feb-2011 Joel Hestness <hestness@cs.utexas.edu>

Ruby: Fix to return cache block size to CPU for split data transfers

7908:4e83ebb67794 07-Feb-2011 Joel Hestness <hestness@cs.utexas.edu>

Ruby: Add support for locked memory accesses in X86_FS

7907:d648b8409d4c 07-Feb-2011 Joel Hestness <hestness@cs.utexas.edu>

Ruby: Update the Ruby request type names for LL/SC

7906:5ccd97218ca0 07-Feb-2011 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Assert for x86 misaligned access

This patch ensures only aligned access are passed to ruby and includes a fix
to the DPRINTF address print.

7904:6f5299ff8260 07-Feb-2011 Brad Beckmann <Brad.Beckmann@amd.com>

MOESI_hammer: Added full-bit directory support

7896:46e9b3bf447f 07-Feb-2011 Tushar Krishna <tushar@csail.mit.edu>

garnet: added orion2.0 for network power calculation


network/garnet/fixed-pipeline/InputUnit_d.cc
network/garnet/fixed-pipeline/InputUnit_d.hh
network/garnet/fixed-pipeline/NetworkLink_d.hh
network/garnet/fixed-pipeline/Router_d.cc
network/garnet/fixed-pipeline/Router_d.hh
network/garnet/fixed-pipeline/VCallocator_d.cc
network/garnet/fixed-pipeline/VCallocator_d.hh
network/orion/Allocator/Arbiter.cc
network/orion/Allocator/Arbiter.hh
network/orion/Allocator/MatrixArbiter.cc
network/orion/Allocator/MatrixArbiter.hh
network/orion/Allocator/RRArbiter.cc
network/orion/Allocator/RRArbiter.hh
network/orion/Allocator/SConscript
network/orion/Allocator/SWAllocator.cc
network/orion/Allocator/SWAllocator.hh
network/orion/Allocator/VCAllocator.cc
network/orion/Allocator/VCAllocator.hh
network/orion/Buffer/AmpUnit.cc
network/orion/Buffer/AmpUnit.hh
network/orion/Buffer/BitlineUnit.cc
network/orion/Buffer/BitlineUnit.hh
network/orion/Buffer/Buffer.cc
network/orion/Buffer/Buffer.hh
network/orion/Buffer/DecoderUnit.cc
network/orion/Buffer/DecoderUnit.hh
network/orion/Buffer/MemUnit.cc
network/orion/Buffer/MemUnit.hh
network/orion/Buffer/OutdrvUnit.cc
network/orion/Buffer/OutdrvUnit.hh
network/orion/Buffer/PrechargeUnit.cc
network/orion/Buffer/PrechargeUnit.hh
network/orion/Buffer/Register.cc
network/orion/Buffer/Register.hh
network/orion/Buffer/SConscript
network/orion/Buffer/SRAM.cc
network/orion/Buffer/SRAM.hh
network/orion/Buffer/WordlineUnit.cc
network/orion/Buffer/WordlineUnit.hh
network/orion/Clock.cc
network/orion/Clock.hh
network/orion/ConfigFile.cc
network/orion/ConfigFile.hh
network/orion/Crossbar/Crossbar.cc
network/orion/Crossbar/Crossbar.hh
network/orion/Crossbar/MatrixCrossbar.cc
network/orion/Crossbar/MatrixCrossbar.hh
network/orion/Crossbar/MultreeCrossbar.cc
network/orion/Crossbar/MultreeCrossbar.hh
network/orion/Crossbar/SConscript
network/orion/FlipFlop.cc
network/orion/FlipFlop.hh
network/orion/NetworkPower.cc
network/orion/NetworkPower.hh
network/orion/OrionConfig.cc
network/orion/OrionConfig.hh
network/orion/OrionLink.cc
network/orion/OrionLink.hh
network/orion/OrionRouter.cc
network/orion/OrionRouter.hh
network/orion/SConscript
network/orion/SIM_port.hh
network/orion/SIM_power.hh
network/orion/SIM_power_test.hh
network/orion/TechParameter.cc
network/orion/TechParameter.hh
network/orion/Type.hh
network/orion/Wire.cc
network/orion/Wire.hh
network/orion/orion.hh
network/orion/parm_technology.hh
network/orion/power_arbiter.cc
network/orion/power_arbiter.hh
network/orion/power_array.cc
network/orion/power_array.hh
network/orion/power_bus.cc
network/orion/power_bus.hh
network/orion/power_crossbar.cc
network/orion/power_crossbar.hh
network/orion/power_ll.cc
network/orion/power_ll.hh
network/orion/power_router_init.cc
network/orion/power_router_init.hh
network/orion/power_static.cc
network/orion/power_static.hh
network/orion/power_utils.cc
network/orion/power_utils.hh
network/orion/router.cfg
7895:8439266ec9e5 07-Feb-2011 Tushar Krishna <tushar@csail.mit.edu>

garnet: separate data and ctrl VCs

Separate data VCs and ctrl VCs in garnet, as ctrl VCs have 1 buffer per VC,
while data VCs have > 1 buffers per VC. This is for correct power estimations.

7839:9e556fb25900 17-Jan-2011 Nilay Vaish<nilay@cs.wisc.edu>

Change interface between coherence protocols and CacheMemory
The purpose of this patch is to change the way CacheMemory interfaces with
coherence protocols. Currently, whenever a cache controller (defined in the
protocol under consideration) needs to carry out any operation on a cache
block, it looks up the tag hash map and figures out whether or not the block
exists in the cache. In case it does exist, the operation is carried out
(which requires another lookup). As observed through profiling of different
protocols, multiple such lookups take place for a given cache block. It was
noted that the tag lookup takes anything from 10% to 20% of the simulation
time. In order to reduce this time, this patch is being posted.

I have to acknowledge that the many of the thoughts that went in to this
patch belong to Brad.

Changes to CacheMemory, TBETable and AbstractCacheEntry classes:
1. The lookup function belonging to CacheMemory class now returns a pointer
to a cache block entry, instead of a reference. The pointer is NULL in case
the block being looked up is not present in the cache. Similar change has
been carried out in the lookup function of the TBETable class.
2. Function for setting and getting access permission of a cache block have
been moved from CacheMemory class to AbstractCacheEntry class.
3. The allocate function in CacheMemory class now returns pointer to the
allocated cache entry.

Changes to SLICC:
1. Each action now has implicit variables - cache_entry and tbe. cache_entry,
if != NULL, must point to the cache entry for the address on which the action
is being carried out. Similarly, tbe should also point to the transaction
buffer entry of the address on which the action is being carried out.
2. If a cache entry or a transaction buffer entry is passed on as an
argument to a function, it is presumed that a pointer is being passed on.
3. The cache entry and the tbe pointers received __implicitly__ by the
actions, are passed __explicitly__ to the trigger function.
4. While performing an action, set/unset_cache_entry, set/unset_tbe are to
be used for setting / unsetting cache entry and tbe pointers respectively.
5. is_valid() and is_invalid() has been made available for testing whether
a given pointer 'is not NULL' and 'is NULL' respectively.
6. Local variables are now available, but they are assumed to be pointers
always.
7. It is now possible for an object of the derieved class to make calls to
a function defined in the interface.
8. An OOD token has been introduced in SLICC. It is same as the NULL token
used in C/C++. If you are wondering, OOD stands for Out Of Domain.
9. static_cast can now taken an optional parameter that asks for casting the
given variable to a pointer of the given type.
10. Functions can be annotated with 'return_by_pointer=yes' to return a
pointer.
11. StateMachine has two new variables, EntryType and TBEType. EntryType is
set to the type which inherits from 'AbstractCacheEntry'. There can only be
one such type in the machine. TBEType is set to the type for which 'TBE' is
used as the name.

All the protocols have been modified to conform with the new interface.


/gem5/src/mem/protocol/MESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_hammer-cache.sm
/gem5/src/mem/protocol/MOESI_hammer-dir.sm
/gem5/src/mem/protocol/RubySlicc_Types.sm
slicc_interface/AbstractCacheEntry.cc
slicc_interface/AbstractCacheEntry.hh
system/CacheMemory.cc
system/CacheMemory.hh
system/TBETable.hh
/gem5/src/mem/slicc/ast/ActionDeclAST.py
/gem5/src/mem/slicc/ast/FormalParamAST.py
/gem5/src/mem/slicc/ast/FuncCallExprAST.py
/gem5/src/mem/slicc/ast/IfStatementAST.py
/gem5/src/mem/slicc/ast/InPortDeclAST.py
/gem5/src/mem/slicc/ast/IsValidPtrExprAST.py
/gem5/src/mem/slicc/ast/LocalVariableAST.py
/gem5/src/mem/slicc/ast/MethodCallExprAST.py
/gem5/src/mem/slicc/ast/OodAST.py
/gem5/src/mem/slicc/ast/ReturnStatementAST.py
/gem5/src/mem/slicc/ast/StaticCastAST.py
/gem5/src/mem/slicc/ast/TypeDeclAST.py
/gem5/src/mem/slicc/ast/__init__.py
/gem5/src/mem/slicc/parser.py
/gem5/src/mem/slicc/symbols/Func.py
/gem5/src/mem/slicc/symbols/StateMachine.py
7832:de7601e6e19d 10-Jan-2011 Nathan Binkert <nate@binkert.org>

ruby: get rid of ruby's Debug.hh

Get rid of the Debug class
Get rid of ASSERT and use assert
Use DPRINTFR for ProtocolTrace

7823:dac01f14f20f 08-Jan-2011 Steve Reinhardt <steve.reinhardt@amd.com>

Replace curTick global variable with accessor functions.
This step makes it easy to replace the accessor functions
(which still access a global variable) with ones that access
per-thread curTick values.


/gem5/src/arch/alpha/isa/decoder.isa
/gem5/src/arch/alpha/kernel_stats.cc
/gem5/src/arch/alpha/tru64/process.cc
/gem5/src/arch/arm/table_walker.cc
/gem5/src/arch/mips/isa.cc
/gem5/src/arch/mips/isa/formats/mt.isa
/gem5/src/arch/mips/locked_mem.hh
/gem5/src/arch/mips/mt.hh
/gem5/src/arch/sparc/ua2005.cc
/gem5/src/arch/x86/interrupts.cc
/gem5/src/base/cp_annotate.cc
/gem5/src/base/cp_annotate.hh
/gem5/src/base/fast_alloc.cc
/gem5/src/base/misc.cc
/gem5/src/base/remote_gdb.cc
/gem5/src/base/statistics.hh
/gem5/src/base/stats/mysql.cc
/gem5/src/base/stats/output.cc
/gem5/src/base/trace.hh
/gem5/src/cpu/base.cc
/gem5/src/cpu/base.hh
/gem5/src/cpu/checker/cpu.cc
/gem5/src/cpu/checker/cpu_impl.hh
/gem5/src/cpu/inorder/cpu.cc
/gem5/src/cpu/inorder/cpu.hh
/gem5/src/cpu/inorder/inorder_dyn_inst.cc
/gem5/src/cpu/inorder/pipeline_stage.cc
/gem5/src/cpu/inorder/reg_dep_map.cc
/gem5/src/cpu/inorder/resource.cc
/gem5/src/cpu/inorder/resource_pool.9stage.cc
/gem5/src/cpu/inorder/resource_pool.cc
/gem5/src/cpu/inorder/resources/branch_predictor.cc
/gem5/src/cpu/inorder/resources/cache_unit.cc
/gem5/src/cpu/inorder/resources/execution_unit.cc
/gem5/src/cpu/inorder/resources/fetch_seq_unit.cc
/gem5/src/cpu/inorder/resources/graduation_unit.cc
/gem5/src/cpu/inorder/resources/mult_div_unit.cc
/gem5/src/cpu/o3/commit_impl.hh
/gem5/src/cpu/o3/cpu.cc
/gem5/src/cpu/o3/cpu.hh
/gem5/src/cpu/o3/fetch_impl.hh
/gem5/src/cpu/o3/inst_queue_impl.hh
/gem5/src/cpu/o3/lsq_impl.hh
/gem5/src/cpu/o3/lsq_unit.hh
/gem5/src/cpu/o3/lsq_unit_impl.hh
/gem5/src/cpu/o3/thread_context_impl.hh
/gem5/src/cpu/ozone/back_end.hh
/gem5/src/cpu/ozone/cpu.hh
/gem5/src/cpu/ozone/cpu_impl.hh
/gem5/src/cpu/ozone/front_end_impl.hh
/gem5/src/cpu/ozone/inorder_back_end.hh
/gem5/src/cpu/ozone/inst_queue_impl.hh
/gem5/src/cpu/ozone/lsq_unit.hh
/gem5/src/cpu/ozone/lsq_unit_impl.hh
/gem5/src/cpu/ozone/lw_back_end_impl.hh
/gem5/src/cpu/ozone/lw_lsq.hh
/gem5/src/cpu/ozone/lw_lsq_impl.hh
/gem5/src/cpu/pc_event.cc
/gem5/src/cpu/simple/atomic.cc
/gem5/src/cpu/simple/base.cc
/gem5/src/cpu/simple/timing.cc
/gem5/src/cpu/simple_thread.cc
/gem5/src/cpu/static_inst.cc
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.cc
/gem5/src/cpu/testers/memtest/memtest.cc
/gem5/src/cpu/testers/rubytest/Check.cc
/gem5/src/cpu/testers/rubytest/RubyTester.cc
/gem5/src/cpu/trace/trace_cpu.cc
/gem5/src/dev/alpha/backdoor.cc
/gem5/src/dev/arm/pl011.cc
/gem5/src/dev/arm/pl111.cc
/gem5/src/dev/arm/rv_ctrl.cc
/gem5/src/dev/arm/timer_sp804.cc
/gem5/src/dev/etherbus.cc
/gem5/src/dev/etherdump.cc
/gem5/src/dev/etherlink.cc
/gem5/src/dev/ethertap.cc
/gem5/src/dev/i8254xGBe.cc
/gem5/src/dev/ide_disk.cc
/gem5/src/dev/intel_8254_timer.cc
/gem5/src/dev/io_device.cc
/gem5/src/dev/mc146818.cc
/gem5/src/dev/mc146818.hh
/gem5/src/dev/ns_gige.cc
/gem5/src/dev/sinic.cc
/gem5/src/dev/uart8250.cc
/gem5/src/kern/kernel_stats.cc
/gem5/src/mem/bridge.cc
/gem5/src/mem/bus.cc
/gem5/src/mem/cache/base.cc
/gem5/src/mem/cache/base.hh
/gem5/src/mem/cache/blk.hh
/gem5/src/mem/cache/cache_impl.hh
/gem5/src/mem/cache/mshr.cc
/gem5/src/mem/cache/mshr.hh
/gem5/src/mem/cache/mshr_queue.hh
/gem5/src/mem/cache/tags/fa_lru.cc
/gem5/src/mem/cache/tags/iic.cc
/gem5/src/mem/cache/tags/lru.cc
/gem5/src/mem/dram.cc
/gem5/src/mem/mport.cc
/gem5/src/mem/packet.hh
/gem5/src/mem/request.hh
eventqueue/RubyEventQueue.hh
system/RubyPort.cc
system/Sequencer.cc
system/System.cc
/gem5/src/mem/tport.cc
/gem5/src/mem/tport.hh
/gem5/src/python/m5/simulate.py
/gem5/src/python/swig/core.i
/gem5/src/python/swig/stats.i
/gem5/src/sim/core.cc
/gem5/src/sim/core.hh
/gem5/src/sim/eventq.cc
/gem5/src/sim/eventq.hh
/gem5/src/sim/init.cc
/gem5/src/sim/pseudo_inst.cc
/gem5/src/sim/serialize.cc
/gem5/src/sim/serialize.hh
/gem5/src/sim/sim_events.cc
/gem5/src/sim/sim_exit.hh
/gem5/src/sim/sim_object.hh
/gem5/src/sim/simulate.cc
/gem5/src/sim/stat_control.cc
/gem5/src/sim/stat_control.hh
/gem5/src/sim/syscall_emul.cc
/gem5/src/sim/syscall_emul.hh
/gem5/src/unittest/stattest.cc
7811:a8fc35183c10 03-Jan-2011 Steve Reinhardt <steve.reinhardt@amd.com>

Make commenting on close namespace brackets consistent.

Ran all the source files through 'perl -pi' with this script:

s|\s*(};?\s*)?/\*\s*(end\s*)?namespace\s*(\S+)\s*\*/(\s*})?|} // namespace $3|;
s|\s*};?\s*//\s*(end\s*)?namespace\s*(\S+)\s*|} // namespace $2\n|;
s|\s*};?\s*//\s*(\S+)\s*namespace\s*|} // namespace $1\n|;

Also did a little manual editing on some of the arch/*/isa_traits.hh files
and src/SConscript.


/gem5/src/SConscript
/gem5/src/arch/alpha/mt.hh
/gem5/src/arch/alpha/pagetable.cc
/gem5/src/arch/alpha/tlb.cc
/gem5/src/arch/arm/faults.hh
/gem5/src/arch/arm/isa_traits.hh
/gem5/src/arch/arm/kernel_stats.hh
/gem5/src/arch/arm/nativetrace.cc
/gem5/src/arch/arm/nativetrace.hh
/gem5/src/arch/arm/tlb.hh
/gem5/src/arch/mips/dsp.hh
/gem5/src/arch/mips/faults.hh
/gem5/src/arch/mips/isa_traits.hh
/gem5/src/arch/mips/kernel_stats.hh
/gem5/src/arch/mips/linux/threadinfo.hh
/gem5/src/arch/power/faults.hh
/gem5/src/arch/power/insts/branch.hh
/gem5/src/arch/power/insts/condition.hh
/gem5/src/arch/power/insts/floating.hh
/gem5/src/arch/power/insts/integer.hh
/gem5/src/arch/power/insts/mem.hh
/gem5/src/arch/power/insts/misc.hh
/gem5/src/arch/power/insts/static_inst.hh
/gem5/src/arch/power/isa.hh
/gem5/src/arch/power/isa_traits.hh
/gem5/src/arch/power/locked_mem.hh
/gem5/src/arch/power/microcode_rom.hh
/gem5/src/arch/power/miscregs.hh
/gem5/src/arch/power/mmaped_ipr.hh
/gem5/src/arch/power/pagetable.cc
/gem5/src/arch/power/pagetable.hh
/gem5/src/arch/power/predecoder.hh
/gem5/src/arch/power/registers.hh
/gem5/src/arch/power/remote_gdb.hh
/gem5/src/arch/power/stacktrace.hh
/gem5/src/arch/power/tlb.hh
/gem5/src/arch/power/types.hh
/gem5/src/arch/power/utility.cc
/gem5/src/arch/power/utility.hh
/gem5/src/arch/power/vtophys.hh
/gem5/src/arch/sparc/faults.hh
/gem5/src/arch/sparc/kernel_stats.hh
/gem5/src/arch/sparc/nativetrace.cc
/gem5/src/arch/sparc/nativetrace.hh
/gem5/src/arch/sparc/tlb.cc
/gem5/src/arch/sparc/vtophys.cc
/gem5/src/arch/x86/cpuid.cc
/gem5/src/arch/x86/nativetrace.cc
/gem5/src/arch/x86/nativetrace.hh
/gem5/src/arch/x86/registers.hh
/gem5/src/arch/x86/tlb.cc
/gem5/src/arch/x86/utility.cc
/gem5/src/base/cprintf.cc
/gem5/src/base/cprintf.hh
/gem5/src/base/hashmap.hh
/gem5/src/base/inet.cc
/gem5/src/base/inet.hh
/gem5/src/base/mysql.cc
/gem5/src/base/mysql.hh
/gem5/src/base/statistics.cc
/gem5/src/base/statistics.hh
/gem5/src/base/stats/info.hh
/gem5/src/base/stats/mysql.cc
/gem5/src/base/stats/mysql.hh
/gem5/src/base/stats/mysql_run.hh
/gem5/src/base/stats/output.cc
/gem5/src/base/stats/output.hh
/gem5/src/base/stats/text.cc
/gem5/src/base/stats/text.hh
/gem5/src/base/stats/types.hh
/gem5/src/base/stats/visit.cc
/gem5/src/base/stats/visit.hh
/gem5/src/base/stl_helpers.hh
/gem5/src/base/trace.cc
/gem5/src/base/trace.hh
/gem5/src/base/varargs.hh
/gem5/src/cpu/exetrace.cc
/gem5/src/cpu/exetrace.hh
/gem5/src/cpu/inorder/inorder_trace.cc
/gem5/src/cpu/inorder/inorder_trace.hh
/gem5/src/cpu/inteltrace.cc
/gem5/src/cpu/inteltrace.hh
/gem5/src/cpu/legiontrace.cc
/gem5/src/cpu/legiontrace.hh
/gem5/src/cpu/nativetrace.cc
/gem5/src/cpu/nativetrace.hh
/gem5/src/dev/copy_engine_defs.hh
/gem5/src/dev/i8254xGBe_defs.hh
/gem5/src/dev/sinic.cc
/gem5/src/dev/sinic.hh
/gem5/src/dev/sinicreg.hh
/gem5/src/dev/x86/cmos.hh
/gem5/src/dev/x86/i8042.hh
/gem5/src/dev/x86/i82094aa.hh
/gem5/src/dev/x86/i8237.hh
/gem5/src/dev/x86/i8254.hh
/gem5/src/dev/x86/i8259.hh
/gem5/src/dev/x86/intdev.hh
/gem5/src/dev/x86/speaker.hh
/gem5/src/kern/kernel_stats.cc
/gem5/src/kern/kernel_stats.hh
common/Address.hh
/gem5/src/python/m5/SimObject.py
/gem5/src/python/m5/params.py
/gem5/src/python/swig/stats.i
/gem5/src/sim/core.cc
/gem5/src/sim/core.hh
/gem5/src/sim/insttracer.hh
/gem5/src/sim/pseudo_inst.cc
/gem5/src/sim/pseudo_inst.hh
/gem5/src/sim/stat_control.cc
/gem5/src/sim/stat_control.hh
7806:fbf4b1b18202 23-Dec-2010 Nilay Vaish<nilay@cs.wisc.edu>

PerfectCacheMemory: Add return statements to two functions.
Two functions in src/mem/ruby/system/PerfectCacheMemory.hh, tryCacheAccess()
and cacheProbe(), end with calls to panic(). Both of these functions have
return type other than void. Any file that includes this header file fails
to compile because of the missing return statement. This patch adds dummy
values so as to avoid the compiler warnings.

7805:f249937228b5 23-Dec-2010 Nilay Vaish<nilay@cs.wisc.edu>

This patch removes the WARN_* and ERROR_* from src/mem/ruby/common/Debug.hh file. These statements have been replaced with warn(), panic() and fatal() defined in src/base/misc.hh

7793:f6cbeb8712d3 08-Dec-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: remove Ruby asserts for m5.fast

This diff is for changing the way ASSERT is handled in Ruby. m5.fast
compiles out the assert statements by using the macro NDEBUG. Ruby uses the
macro RUBY_NO_ASSERT to do so. This macro has been removed and NDEBUG has
been put in its place.

7780:42da07116e12 01-Dec-2010 Nilay Vaish <nilay@cs.wisc.edu>

ruby: Converted old ruby debug calls to M5 debug calls

This patch developed by Nilay Vaish converts all the old GEMS-style ruby
debug calls to the appropriate M5 debug calls.

7768:cdb18c1b51ea 19-Nov-2010 Ali Saidi <Ali.Saidi@ARM.com>

SCons: Support building without an ISA

7632:acf43d6bbc18 24-Aug-2010 Brad Beckmann <Brad.Beckmann@amd.com>

testers: move testers to a new directory

This patch moves the testers to a new subdirectory under src/cpu and includes
the necessary fixes to work with latest m5 initialization patches.


/gem5/configs/example/determ_test.py
/gem5/configs/example/memtest-ruby.py
/gem5/configs/example/ruby_direct_test.py
/gem5/configs/example/rubytest.py
/gem5/configs/ruby/MOESI_hammer.py
/gem5/src/cpu/directedtest/DirectedGenerator.cc
/gem5/src/cpu/directedtest/DirectedGenerator.hh
/gem5/src/cpu/directedtest/InvalidateGenerator.cc
/gem5/src/cpu/directedtest/InvalidateGenerator.hh
/gem5/src/cpu/directedtest/RubyDirectedTester.cc
/gem5/src/cpu/directedtest/RubyDirectedTester.hh
/gem5/src/cpu/directedtest/RubyDirectedTester.py
/gem5/src/cpu/directedtest/SConscript
/gem5/src/cpu/directedtest/SeriesRequestGenerator.cc
/gem5/src/cpu/directedtest/SeriesRequestGenerator.hh
/gem5/src/cpu/memtest/MemTest.py
/gem5/src/cpu/memtest/SConscript
/gem5/src/cpu/memtest/memtest.cc
/gem5/src/cpu/memtest/memtest.hh
/gem5/src/cpu/rubytest/Check.cc
/gem5/src/cpu/rubytest/Check.hh
/gem5/src/cpu/rubytest/CheckTable.cc
/gem5/src/cpu/rubytest/CheckTable.hh
/gem5/src/cpu/rubytest/RubyTester.cc
/gem5/src/cpu/rubytest/RubyTester.hh
/gem5/src/cpu/rubytest/RubyTester.py
/gem5/src/cpu/rubytest/SConscript
/gem5/src/cpu/testers/directedtest/DirectedGenerator.cc
/gem5/src/cpu/testers/directedtest/DirectedGenerator.hh
/gem5/src/cpu/testers/directedtest/InvalidateGenerator.cc
/gem5/src/cpu/testers/directedtest/InvalidateGenerator.hh
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.cc
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.hh
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.py
/gem5/src/cpu/testers/directedtest/SConscript
/gem5/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
/gem5/src/cpu/testers/directedtest/SeriesRequestGenerator.hh
/gem5/src/cpu/testers/memtest/MemTest.py
/gem5/src/cpu/testers/memtest/SConscript
/gem5/src/cpu/testers/memtest/memtest.cc
/gem5/src/cpu/testers/memtest/memtest.hh
/gem5/src/cpu/testers/rubytest/Check.cc
/gem5/src/cpu/testers/rubytest/Check.hh
/gem5/src/cpu/testers/rubytest/CheckTable.cc
/gem5/src/cpu/testers/rubytest/CheckTable.hh
/gem5/src/cpu/testers/rubytest/RubyTester.cc
/gem5/src/cpu/testers/rubytest/RubyTester.hh
/gem5/src/cpu/testers/rubytest/RubyTester.py
/gem5/src/cpu/testers/rubytest/SConscript
system/RubyPort.cc
system/Sequencer.cc
7567:238f99c9f441 20-Aug-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Stall and wait input messages instead of recycling

This patch allows messages to be stalled in their input buffers and wait
until a corresponding address changes state. In order to make this work,
all in_ports must be ranked in order of dependence and those in_ports that
may unblock an address, must wake up the stalled messages. Alot of this
complexity is handled in slicc and the specification files simply
annotate the in_ports.

7566:6919df046bba 20-Aug-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Recycle latency fix for hammer

Patch allows each individual message buffer to have different recycle latencies
and allows the overall recycle latency to be specified at the cmd line. The
patch also adds profiling info to make sure no one processor's requests are
recycled too much.

7565:9fc3475e8175 20-Aug-2010 Brad Beckmann <Brad.Beckmann@amd.com>

MOESI_hammer: break down miss latency stalled cycles

This patch tracks the number of cycles a transaction is delayed at different
points of the request-forward-response loop.

7564:3559d47839a1 20-Aug-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: added probe filter support to hammer

7563:406e98960def 20-Aug-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: fixed DirectoryMemory's numa_high_bit configuration

This fix includes the off-by-one bit selection bug for numa mapping.

7562:ec3b148b14f3 20-Aug-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Reset ruby stats in RubySystem unserialize

The main purpose for clearing stats in the unserialize process is so
that the profiler can correctly set its start time to the unserialized
value of curTick.

7560:29d5891a96d6 20-Aug-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Added SC fail indication to trace profiling

7558:6c3f81b176da 20-Aug-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Fixed RubyPort sendTiming callbacks

Fixed RubyPort schedSendTiming calls to match ruby frequency.

7553:fcdd99057b8a 20-Aug-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Resurrected Ruby's deterministic tests

Added the request series and invalidate deterministic tests as new cpu models
and removed the no longer needed ruby tests

7550:7d97cec15818 20-Aug-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: fix ruby llsc support to sync sc outcomes

Added support so that ruby can determine the outcome of store conditional
operations and reflect that outcome to M5 physical memory and cpus.

7549:08dbd22d58a0 20-Aug-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Fixed L2 cache miss profiling

Fixed L2 cache miss profiling for the MOESI_CMP_token protocol

7548:764a7401e217 20-Aug-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Added bcast msg profiling to hammer and token

7547:a5ddcb2abfa1 20-Aug-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Added consolidated network msg stats

7546:84e8f914b3b8 20-Aug-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Reincarnated the responding machine profiling

This patch adds back to ruby the capability to understand the response time
for messages that hit in different levels of the cache heirarchy.
Specifically add support for the MI_example, MOESI_hammer, and MOESI_CMP_token
protocols.

7544:90c5eb6a5e66 20-Aug-2010 Brad Beckmann <Brad.Beckmann@amd.com>

memtest: Memtester support for DMA

This patch adds DMA testing to the Memtester and is inherits many changes from
Polina's old tester_dma_extension patch. Since Ruby does not work in atomic
mode, the atomic mode options are removed.

7543:e660ab620115 20-Aug-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Added ruby_request_type ostream def to libruby.hh

7540:86c3bf056a0d 20-Aug-2010 Brad Beckmann <Brad.Beckmann@amd.com>

config: Added the topology description to m5 config.ini

7537:8178df9c17c4 20-Aug-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Fixed printout when Sequencer detects a deadlock

7496:10510cc7bb9f 08-Jul-2010 Brad Beckmann <Brad.Beckmann@amd.com>

garnet: Added topology print function to Garnet printStats

7495:2e8e5bb0b4c2 08-Jul-2010 Tushar Krishna <Tushar.Krishna@amd.com>

NetworkMessage copy constructor fix

7486:3006bde825fd 22-Jun-2010 Tushar Krishna <Tushar.Krishna@amd.com>

style: updated garnet to match M5 coding style


network/garnet/BaseGarnetNetwork.cc
network/garnet/BaseGarnetNetwork.hh
network/garnet/NetworkHeader.hh
network/garnet/fixed-pipeline/CreditLink_d.hh
network/garnet/fixed-pipeline/GarnetNetwork_d.cc
network/garnet/fixed-pipeline/GarnetNetwork_d.hh
network/garnet/fixed-pipeline/InputUnit_d.cc
network/garnet/fixed-pipeline/InputUnit_d.hh
network/garnet/fixed-pipeline/NetworkInterface_d.cc
network/garnet/fixed-pipeline/NetworkInterface_d.hh
network/garnet/fixed-pipeline/NetworkLink_d.cc
network/garnet/fixed-pipeline/NetworkLink_d.hh
network/garnet/fixed-pipeline/OutVcState_d.cc
network/garnet/fixed-pipeline/OutVcState_d.hh
network/garnet/fixed-pipeline/OutputUnit_d.cc
network/garnet/fixed-pipeline/OutputUnit_d.hh
network/garnet/fixed-pipeline/Router_d.cc
network/garnet/fixed-pipeline/Router_d.hh
network/garnet/fixed-pipeline/RoutingUnit_d.cc
network/garnet/fixed-pipeline/RoutingUnit_d.hh
network/garnet/fixed-pipeline/SWallocator_d.cc
network/garnet/fixed-pipeline/SWallocator_d.hh
network/garnet/fixed-pipeline/Switch_d.cc
network/garnet/fixed-pipeline/Switch_d.hh
network/garnet/fixed-pipeline/VCallocator_d.cc
network/garnet/fixed-pipeline/VCallocator_d.hh
network/garnet/fixed-pipeline/VirtualChannel_d.cc
network/garnet/fixed-pipeline/VirtualChannel_d.hh
network/garnet/fixed-pipeline/flitBuffer_d.cc
network/garnet/fixed-pipeline/flitBuffer_d.hh
network/garnet/fixed-pipeline/flit_d.cc
network/garnet/fixed-pipeline/flit_d.hh
network/garnet/flexible-pipeline/FlexibleConsumer.hh
network/garnet/flexible-pipeline/GarnetNetwork.cc
network/garnet/flexible-pipeline/GarnetNetwork.hh
network/garnet/flexible-pipeline/InVcState.cc
network/garnet/flexible-pipeline/InVcState.hh
network/garnet/flexible-pipeline/NetworkInterface.cc
network/garnet/flexible-pipeline/NetworkInterface.hh
network/garnet/flexible-pipeline/NetworkLink.cc
network/garnet/flexible-pipeline/NetworkLink.hh
network/garnet/flexible-pipeline/OutVcState.cc
network/garnet/flexible-pipeline/OutVcState.hh
network/garnet/flexible-pipeline/Router.cc
network/garnet/flexible-pipeline/Router.hh
network/garnet/flexible-pipeline/VCarbiter.cc
network/garnet/flexible-pipeline/VCarbiter.hh
network/garnet/flexible-pipeline/flit.cc
network/garnet/flexible-pipeline/flit.hh
network/garnet/flexible-pipeline/flitBuffer.cc
network/garnet/flexible-pipeline/flitBuffer.hh
network/garnet/flexible-pipeline/netconfig.defaults
7456:8b9be6e12c9b 11-Jun-2010 Nathan Binkert <nate@binkert.org>

ruby: get rid of PrioHeap and use STL

One big difference is that PrioHeap puts the smallest element at the
top of the heap, whereas stl puts the largest element on top, so I
changed all comparisons so they did the right thing.

Some usage of PrioHeap was simply changed to a std::vector, using sort
at the right time, other usage had me just use the various heap functions
in the stl.

7455:586f99bf0dc4 11-Jun-2010 Nathan Binkert <nate@binkert.org>

ruby: get rid of the Map class

7454:3a3e8e8cce1b 11-Jun-2010 Nathan Binkert <nate@binkert.org>

ruby: get rid of Vector and use STL
add a couple of helper functions to base for deleteing all pointers in
a container and outputting containers to a stream


/gem5/src/base/stl_helpers.hh
/gem5/src/cpu/rubytest/CheckTable.cc
/gem5/src/cpu/rubytest/CheckTable.hh
/gem5/src/cpu/rubytest/RubyTester.cc
/gem5/src/cpu/rubytest/RubyTester.hh
/gem5/src/mem/gems_common/Map.hh
/gem5/src/mem/gems_common/PrioHeap.hh
/gem5/src/mem/gems_common/Vector.hh
buffers/MessageBuffer.hh
common/DataBlock.hh
common/Histogram.cc
common/Histogram.hh
common/NetDest.cc
common/NetDest.hh
common/SubBlock.cc
common/SubBlock.hh
eventqueue/RubyEventQueue.hh
filters/BlockBloomFilter.cc
filters/BlockBloomFilter.hh
filters/BulkBloomFilter.cc
filters/BulkBloomFilter.hh
filters/H3BloomFilter.cc
filters/H3BloomFilter.hh
filters/LSB_CountingBloomFilter.cc
filters/LSB_CountingBloomFilter.hh
filters/MultiBitSelBloomFilter.cc
filters/MultiBitSelBloomFilter.hh
filters/MultiGrainBloomFilter.cc
filters/MultiGrainBloomFilter.hh
filters/NonCountingBloomFilter.cc
filters/NonCountingBloomFilter.hh
network/Network.cc
network/Network.hh
network/garnet/fixed-pipeline/GarnetNetwork_d.cc
network/garnet/fixed-pipeline/GarnetNetwork_d.hh
network/garnet/fixed-pipeline/InputUnit_d.cc
network/garnet/fixed-pipeline/InputUnit_d.hh
network/garnet/fixed-pipeline/NetworkInterface_d.cc
network/garnet/fixed-pipeline/NetworkInterface_d.hh
network/garnet/fixed-pipeline/NetworkLink_d.cc
network/garnet/fixed-pipeline/NetworkLink_d.hh
network/garnet/fixed-pipeline/OutputUnit_d.cc
network/garnet/fixed-pipeline/OutputUnit_d.hh
network/garnet/fixed-pipeline/Router_d.cc
network/garnet/fixed-pipeline/Router_d.hh
network/garnet/fixed-pipeline/RoutingUnit_d.cc
network/garnet/fixed-pipeline/RoutingUnit_d.hh
network/garnet/fixed-pipeline/SWallocator_d.cc
network/garnet/fixed-pipeline/SWallocator_d.hh
network/garnet/fixed-pipeline/Switch_d.cc
network/garnet/fixed-pipeline/Switch_d.hh
network/garnet/fixed-pipeline/VCallocator_d.cc
network/garnet/fixed-pipeline/VCallocator_d.hh
network/garnet/flexible-pipeline/GarnetNetwork.cc
network/garnet/flexible-pipeline/GarnetNetwork.hh
network/garnet/flexible-pipeline/NetworkInterface.cc
network/garnet/flexible-pipeline/NetworkInterface.hh
network/garnet/flexible-pipeline/NetworkLink.cc
network/garnet/flexible-pipeline/NetworkLink.hh
network/garnet/flexible-pipeline/Router.cc
network/garnet/flexible-pipeline/Router.hh
network/simple/PerfectSwitch.cc
network/simple/PerfectSwitch.hh
network/simple/SimpleNetwork.cc
network/simple/SimpleNetwork.hh
network/simple/Switch.cc
network/simple/Switch.hh
network/simple/Throttle.cc
network/simple/Throttle.hh
network/simple/Topology.cc
network/simple/Topology.hh
profiler/AddressProfiler.cc
profiler/CacheProfiler.cc
profiler/CacheProfiler.hh
profiler/MemCntrlProfiler.cc
profiler/MemCntrlProfiler.hh
profiler/Profiler.cc
profiler/Profiler.hh
system/CacheMemory.cc
system/CacheMemory.hh
system/MemoryVector.hh
system/Sequencer.cc
system/System.cc
system/System.hh
system/TimerTable.cc
tester/DeterministicDriver.cc
tester/DeterministicDriver.hh
tester/RaceyDriver.cc
tester/RaceyDriver.hh
/gem5/src/mem/slicc/symbols/StateMachine.py
7453:1a5db3dd0f62 11-Jun-2010 Nathan Binkert <nate@binkert.org>

ruby: get rid of RefCnt and Allocator stuff use base/refcnt.hh

This was somewhat tricky because the RefCnt API was somewhat odd. The
biggest confusion was that the the RefCnt object's constructor that
took a TYPE& cloned the object. I created an explicit virtual clone()
function for things that took advantage of this version of the
constructor. I was conservative and used clone() when I was in doubt
of whether or not it was necessary. I still think that there are
probably too many instances of clone(), but hopefully not too many.

I converted several instances of const MsgPtr & to a simple MsgPtr.
If the function wants to avoid the overhead of creating another
reference, then it should just use a regular pointer instead of a ref
counting ptr.

There were a couple of instances where refcounted objects were created
on the stack. This seems pretty dangerous since if you ever
accidentally make a reference to that object with a ref counting
pointer, bad things are bound to happen.

7450:2302e04c506e 07-Jun-2010 Steve Reinhardt <stever@gmail.com>

scons: make RUBY a regular (non-global) sticky var
and force it to True for builds that imply Ruby protocols
(else unexpected things happen when testing these builds
with RUBY=False).

7089:9ea24d102d66 01-Jun-2010 Nathan Binkert <nate@binkert.org>

style: clean up ruby's Set class

Further cleanup should probably be done to make this class be non-Ruby
specific and put it in src/base.

There are probably several cases where this class is used, std::bitset
could be used instead.

7056:b66b558578bd 02-Apr-2010 Nathan Binkert <nate@binkert.org>

ruby: get rid of gems_common/util.hh and .cc and use stuff in src/base

7055:4e24742201d7 02-Apr-2010 Nathan Binkert <nate@binkert.org>

ruby: get "using namespace" out of headers
In addition to obvious changes, this required a slight change to the slicc
grammar to allow types with :: in them. Otherwise slicc barfs on std::string
which we need for the headers that slicc generates.


/gem5/src/cpu/rubytest/Check.cc
/gem5/src/cpu/rubytest/Check.hh
/gem5/src/cpu/rubytest/CheckTable.cc
/gem5/src/cpu/rubytest/RubyTester.cc
/gem5/src/cpu/rubytest/RubyTester.hh
/gem5/src/mem/gems_common/Vector.hh
/gem5/src/mem/protocol/MESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MESI_SCMP_bankdirectory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L2cache.sm
/gem5/src/mem/protocol/MSI_MOSI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MSI_MOSI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MSI_MOSI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MSI_MOSI_CMP_directory-msg.sm
/gem5/src/mem/protocol/RubySlicc_Exports.sm
/gem5/src/mem/protocol/RubySlicc_Profiler.sm
/gem5/src/mem/protocol/RubySlicc_Util.sm
buffers/MessageBuffer.cc
common/Address.cc
common/Address.hh
common/Driver.hh
common/NetDest.cc
common/NetDest.hh
common/Set.cc
common/Set.hh
common/SubBlock.cc
common/SubBlock.hh
eventqueue/RubyEventQueue.cc
filters/AbstractBloomFilter.hh
filters/BlockBloomFilter.cc
filters/BlockBloomFilter.hh
filters/BulkBloomFilter.cc
filters/BulkBloomFilter.hh
filters/GenericBloomFilter.cc
filters/GenericBloomFilter.hh
filters/H3BloomFilter.cc
filters/H3BloomFilter.hh
filters/LSB_CountingBloomFilter.cc
filters/LSB_CountingBloomFilter.hh
filters/MultiBitSelBloomFilter.cc
filters/MultiBitSelBloomFilter.hh
filters/MultiGrainBloomFilter.cc
filters/MultiGrainBloomFilter.hh
filters/NonCountingBloomFilter.cc
filters/NonCountingBloomFilter.hh
libruby.cc
network/Network.hh
network/garnet/NetworkHeader.hh
network/garnet/fixed-pipeline/GarnetNetwork_d.cc
network/garnet/fixed-pipeline/GarnetNetwork_d.hh
network/garnet/fixed-pipeline/InputUnit_d.cc
network/garnet/fixed-pipeline/InputUnit_d.hh
network/garnet/fixed-pipeline/NetworkInterface_d.cc
network/garnet/fixed-pipeline/NetworkInterface_d.hh
network/garnet/fixed-pipeline/NetworkLink_d.hh
network/garnet/fixed-pipeline/OutputUnit_d.cc
network/garnet/fixed-pipeline/OutputUnit_d.hh
network/garnet/fixed-pipeline/Router_d.cc
network/garnet/fixed-pipeline/Router_d.hh
network/garnet/fixed-pipeline/SWallocator_d.hh
network/garnet/fixed-pipeline/Switch_d.hh
network/garnet/fixed-pipeline/VCallocator_d.hh
network/garnet/fixed-pipeline/VirtualChannel_d.hh
network/garnet/fixed-pipeline/flitBuffer_d.cc
network/garnet/fixed-pipeline/flitBuffer_d.hh
network/garnet/fixed-pipeline/flit_d.cc
network/garnet/fixed-pipeline/flit_d.hh
network/garnet/flexible-pipeline/GarnetNetwork.cc
network/garnet/flexible-pipeline/GarnetNetwork.hh
network/garnet/flexible-pipeline/NetworkInterface.cc
network/garnet/flexible-pipeline/NetworkInterface.hh
network/garnet/flexible-pipeline/NetworkLink.hh
network/garnet/flexible-pipeline/Router.cc
network/garnet/flexible-pipeline/Router.hh
network/garnet/flexible-pipeline/VCarbiter.hh
network/garnet/flexible-pipeline/flit.cc
network/garnet/flexible-pipeline/flit.hh
network/garnet/flexible-pipeline/flitBuffer.cc
network/garnet/flexible-pipeline/flitBuffer.hh
network/simple/PerfectSwitch.cc
network/simple/SimpleNetwork.cc
network/simple/SimpleNetwork.hh
network/simple/Switch.cc
network/simple/Throttle.cc
network/simple/Throttle.hh
network/simple/Topology.cc
profiler/AccessTraceForAddress.cc
profiler/AccessTraceForAddress.hh
profiler/AddressProfiler.cc
profiler/AddressProfiler.hh
profiler/CacheProfiler.cc
profiler/Profiler.cc
profiler/Profiler.hh
profiler/StoreTrace.cc
profiler/StoreTrace.hh
recorder/CacheRecorder.cc
recorder/TraceRecord.cc
recorder/TraceRecord.hh
recorder/Tracer.cc
slicc_interface/AbstractCacheEntry.hh
slicc_interface/AbstractController.hh
slicc_interface/AbstractEntry.hh
slicc_interface/NetworkMessage.hh
slicc_interface/RubySlicc_Profiler_interface.cc
slicc_interface/RubySlicc_Profiler_interface.hh
system/CacheMemory.cc
system/CacheMemory.hh
system/DMASequencer.cc
system/DirectoryMemory.cc
system/DirectoryMemory.hh
system/MemoryControl.cc
system/MemoryControl.hh
system/PerfectCacheMemory.hh
system/PersistentTable.cc
system/PersistentTable.hh
system/RubyPort.hh
system/Sequencer.cc
system/Sequencer.hh
system/SparseMemory.cc
system/SparseMemory.hh
system/System.cc
system/System.hh
system/TBETable.hh
system/TimerTable.cc
system/TimerTable.hh
/gem5/src/mem/slicc/ast/EnumDeclAST.py
/gem5/src/mem/slicc/ast/LiteralExprAST.py
/gem5/src/mem/slicc/parser.py
/gem5/src/mem/slicc/symbols/Func.py
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/mem/slicc/symbols/Type.py
7054:7d6862b80049 31-Mar-2010 Nathan Binkert <nate@binkert.org>

style: another ruby style pass

7048:2ab58c54de63 24-Mar-2010 Nathan Binkert <nate@binkert.org>

ruby: continue style pass

7044:8a05ebc9d372 23-Mar-2010 Korey Sewell <ksewell@umich.edu>

m5merge(2): another merge of regression stats

7039:bc0b6ea676b5 22-Mar-2010 Nathan Binkert <nate@binkert.org>

ruby: style pass


buffers/MessageBuffer.cc
buffers/MessageBuffer.hh
buffers/MessageBufferNode.cc
buffers/MessageBufferNode.hh
common/Address.cc
common/Address.hh
common/Consumer.hh
common/DataBlock.cc
common/DataBlock.hh
common/Debug.cc
common/Debug.hh
common/Driver.cc
common/Driver.hh
common/Global.cc
common/Global.hh
common/Histogram.cc
common/Histogram.hh
common/Message.cc
common/NetDest.cc
common/NetDest.hh
common/SConscript
common/SubBlock.cc
common/SubBlock.hh
eventqueue/RubyEventQueue.cc
eventqueue/RubyEventQueue.hh
eventqueue/RubyEventQueueNode.cc
eventqueue/RubyEventQueueNode.hh
filters/AbstractBloomFilter.hh
filters/BlockBloomFilter.cc
filters/BlockBloomFilter.hh
filters/BulkBloomFilter.cc
filters/BulkBloomFilter.hh
filters/GenericBloomFilter.cc
filters/GenericBloomFilter.hh
filters/H3BloomFilter.cc
filters/H3BloomFilter.hh
filters/LSB_CountingBloomFilter.cc
filters/LSB_CountingBloomFilter.hh
filters/MultiBitSelBloomFilter.cc
filters/MultiBitSelBloomFilter.hh
filters/MultiGrainBloomFilter.cc
filters/MultiGrainBloomFilter.hh
filters/NonCountingBloomFilter.cc
filters/NonCountingBloomFilter.hh
libruby.cc
libruby.hh
libruby_internal.hh
slicc_interface/AbstractCacheEntry.cc
slicc_interface/AbstractCacheEntry.hh
slicc_interface/AbstractController.hh
slicc_interface/AbstractEntry.cc
slicc_interface/AbstractEntry.hh
slicc_interface/AbstractProtocol.hh
slicc_interface/Message.hh
slicc_interface/NetworkMessage.hh
slicc_interface/RubySlicc_ComponentMapping.cc
slicc_interface/RubySlicc_ComponentMapping.hh
slicc_interface/RubySlicc_Profiler_interface.cc
slicc_interface/RubySlicc_Profiler_interface.hh
slicc_interface/RubySlicc_Util.hh
slicc_interface/RubySlicc_includes.hh
system/AbstractMemOrCache.hh
system/AbstractReplacementPolicy.hh
system/CacheMemory.cc
system/CacheMemory.hh
system/DMASequencer.cc
system/DMASequencer.hh
system/DirectoryMemory.cc
system/DirectoryMemory.hh
system/LRUPolicy.hh
system/MachineID.hh
system/MemoryControl.cc
system/MemoryControl.hh
system/MemoryNode.cc
system/MemoryNode.hh
system/MemoryVector.hh
system/NodeID.hh
system/PerfectCacheMemory.hh
system/PersistentTable.cc
system/PersistentTable.hh
system/PseudoLRUPolicy.hh
system/RubyPort.cc
system/RubyPort.hh
system/Sequencer.cc
system/Sequencer.hh
system/SparseMemory.cc
system/SparseMemory.hh
system/System.cc
system/System.hh
system/TBETable.hh
system/TimerTable.cc
system/TimerTable.hh
7035:b78b3a9e205f 22-Mar-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: improved isReadWrite fix me comment

7032:9f938aea1942 22-Mar-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Reorganized Ruby topology and protocol files

7030:a200627c3d42 22-Mar-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Disable adaptive routing by for faster simulation perf.

7029:9a48c447bc19 22-Mar-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Changed the default set size to 1

Previously, the set size was set to 4. This was mostly do to the fact that a
crazy graduate student use to create networks with 256 l2 cache banks. Now it
is far more likely that users will create systems with less than 64 of any
particular controller type. Therefore Ruby should be optimized for a set size
of 1.

7027:46b02e79bf2c 22-Mar-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Adds configurable bit selection for numa mapping

7026:3f4c23e9d67d 22-Mar-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Added flag to disable mem_vec allocation

The RubySystem flag no_mem_vec will disable Ruby from allocating it's memory
data array.

7025:9adf5b0ccc79 22-Mar-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Ruby support for sparse memory

The patch includes direct support for the MI example protocol.

7024:30883414ad10 22-Mar-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Finally removed bash code cira. 2001ish!

7023:185ad61a4117 22-Mar-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Ruby support for LLSC

7021:0b3c02da71b3 22-Mar-2010 Tushar Krishna <tushar@csail.mit.edu>

ruby: Fix multiple wakeups in Ruby Eventqueue

Fix bug in Ruby Event queue to avoid multiple wakeups of same consumer in
same cycle

7020:34a5bdcce1e6 22-Mar-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Removed the obsolete file specified network files


network/simple/Network_Files/GarnetFileMaker.py
network/simple/Network_Files/NUCA_Procs-16_ProcsPerChip-16_L2Banks-16_Memories-16.txt
network/simple/Network_Files/NUCA_Procs-16_ProcsPerChip-16_L2Banks-16_Memories-4.txt
network/simple/Network_Files/NUCA_Procs-16_ProcsPerChip-16_L2Banks-16_Memories-8.txt
network/simple/Network_Files/NUCA_Procs-16_ProcsPerChip-1_L2Banks-16_Memories-16.txt
network/simple/Network_Files/NUCA_Procs-16_ProcsPerChip-4_L2Banks-16_Memories-16.txt
network/simple/Network_Files/NUCA_Procs-16_ProcsPerChip-4_L2Banks-16_Memories-4.txt
network/simple/Network_Files/NUCA_Procs-16_ProcsPerChip-4_L2Banks-32_Memories-4.txt
network/simple/Network_Files/NUCA_Procs-16_ProcsPerChip-4_L2Banks-4_Memories-16.txt
network/simple/Network_Files/NUCA_Procs-16_ProcsPerChip-4_L2Banks-4_Memories-4.txt
network/simple/Network_Files/NUCA_Procs-1_ProcsPerChip-1_L2Banks-1_Memories-1.txt
network/simple/Network_Files/NUCA_Procs-1_ProcsPerChip-1_L2Banks-256_Memories-1.txt
network/simple/Network_Files/NUCA_Procs-1_ProcsPerChip-1_L2Banks-32_Memories-1.txt
network/simple/Network_Files/NUCA_Procs-1_ProcsPerChip-1_L2Banks-64_Memories-1.txt
network/simple/Network_Files/NUCA_Procs-2_ProcsPerChip-1_L2Banks-2_Memories-2.txt
network/simple/Network_Files/NUCA_Procs-2_ProcsPerChip-2_L2Banks-2_Memories-2.txt
network/simple/Network_Files/NUCA_Procs-32_ProcsPerChip-32_L2Banks-32_Memories-16.txt
network/simple/Network_Files/NUCA_Procs-32_ProcsPerChip-32_L2Banks-32_Memories-4.txt
network/simple/Network_Files/NUCA_Procs-4_ProcsPerChip-1_L2Banks-4_Memories-4.txt
network/simple/Network_Files/NUCA_Procs-4_ProcsPerChip-4_L2Banks-4_Memories-4.txt
network/simple/Network_Files/NUCA_Procs-7_ProcsPerChip-7_L2Banks-7_Memories-7.txt
network/simple/Network_Files/NUCA_Procs-8_ProcsPerChip-1_L2Banks-8_Memories-8.txt
network/simple/Network_Files/NUCA_Procs-8_ProcsPerChip-4_L2Banks-8_Memories-8.txt
network/simple/Network_Files/NUCA_Procs-8_ProcsPerChip-8_L2Banks-256_Memories-8.txt
network/simple/Network_Files/NUCA_Procs-8_ProcsPerChip-8_L2Banks-8_Memories-8.txt
network/simple/Network_Files/NetworkFileMaker.py
network/simple/Network_Files/TLC_Procs-8_ProcsPerChip-8_L2Banks-256_Memories-8.txt
network/simple/Network_Files/TOKEN_CMP_Procs-16_ProcsPerChip-16_L2Banks-16_Memories-16.txt
network/simple/Network_Files/TOKEN_CMP_Procs-16_ProcsPerChip-4_L2Banks-16_Memories-16.txt
7019:a49fd5febdce 22-Mar-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Added copyright to many Ruby *.py files

7010:c769c45253c9 22-Mar-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Removed deprecated stats from the main profiler

7009:44ed5e0c7228 16-Mar-2010 Nathan Binkert <nate@binkert.org>

orion: Make declarations match definition

7008:90c097fb76e1 14-Mar-2010 Nathan Binkert <nate@binkert.org>

ruby: Fix copyrights on files
Mostly files missed during import or screwed up during import

7003:5af96fb1ebde 12-Mar-2010 Nathan Binkert <nate@binkert.org>

bugfix: since pow() causes a bug don't use it
It's a power of two anyway, so why use it in the first place.

7002:48a19d52d939 10-Mar-2010 Nathan Binkert <nate@binkert.org>

ruby: get rid of std-includes.hh
Do not use "using namespace std;" in headers
Include header files as needed

6971:12cfde8f819b 10-Feb-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: fixed data block assignment fix

Fixed data block assignment to not delete if not internally allocated.

6968:33d2b758697b 01-Feb-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Added FS support to the simple mesh topology

Added full-system support to the simple mesh toplogy by allowing dma contrllers
to be attached to router zero in the network.

6926:775342cda4db 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: removed last level cache support

Removed the last level cache support and MOESI_hammer's dependency on it.
Replaces the LLC support with the more generic MachineType count.

6922:1620cffaa3b6 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Removed static members in RubyPort including hitcallback
Removed static members in RubyPort and removed the ruby request unique id.

6921:fd852ed8c6b4 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Removed the old config interface

Removed the old config interface from RubySystem and libruby.

6920:e031f09a7dcc 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Re-enabled orion power models

Removed the dummy power function implementations so that Orion can implement
them correctly. Since Orion lacks modular design, this patch simply enables
scons to compile it. There are no python configuration changes in this patch.

6918:9b57f0108bc8 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Converted Garnet to M5 configuration

6917:341a71fd2600 29-Jan-2010 Steve Reinhardt <steve.reinhardt@amd.com>

Garnet: reorganize directory tree.
Rename the ruby/network/garnet-foo directories to garnet/foo.
Move the common NetworkHeader.hh file from garnet-fixed-pipeline
up to the common garnet directory.
Fix up include paths.


network/garnet-fixed-pipeline/CreditLink_d.hh
network/garnet-fixed-pipeline/GarnetNetwork_d.cc
network/garnet-fixed-pipeline/GarnetNetwork_d.hh
network/garnet-fixed-pipeline/InputUnit_d.cc
network/garnet-fixed-pipeline/InputUnit_d.hh
network/garnet-fixed-pipeline/NetworkHeader.hh
network/garnet-fixed-pipeline/NetworkInterface_d.cc
network/garnet-fixed-pipeline/NetworkInterface_d.hh
network/garnet-fixed-pipeline/NetworkLink_d.cc
network/garnet-fixed-pipeline/NetworkLink_d.hh
network/garnet-fixed-pipeline/OutVcState_d.cc
network/garnet-fixed-pipeline/OutVcState_d.hh
network/garnet-fixed-pipeline/OutputUnit_d.cc
network/garnet-fixed-pipeline/OutputUnit_d.hh
network/garnet-fixed-pipeline/Router_d.cc
network/garnet-fixed-pipeline/Router_d.hh
network/garnet-fixed-pipeline/RoutingUnit_d.cc
network/garnet-fixed-pipeline/RoutingUnit_d.hh
network/garnet-fixed-pipeline/SConscript
network/garnet-fixed-pipeline/SWallocator_d.cc
network/garnet-fixed-pipeline/SWallocator_d.hh
network/garnet-fixed-pipeline/Switch_d.cc
network/garnet-fixed-pipeline/Switch_d.hh
network/garnet-fixed-pipeline/VCallocator_d.cc
network/garnet-fixed-pipeline/VCallocator_d.hh
network/garnet-fixed-pipeline/VirtualChannel_d.cc
network/garnet-fixed-pipeline/VirtualChannel_d.hh
network/garnet-fixed-pipeline/flitBuffer_d.cc
network/garnet-fixed-pipeline/flitBuffer_d.hh
network/garnet-fixed-pipeline/flit_d.cc
network/garnet-fixed-pipeline/flit_d.hh
network/garnet-flexible-pipeline/FlexibleConsumer.hh
network/garnet-flexible-pipeline/GarnetNetwork.cc
network/garnet-flexible-pipeline/GarnetNetwork.hh
network/garnet-flexible-pipeline/InVcState.cc
network/garnet-flexible-pipeline/InVcState.hh
network/garnet-flexible-pipeline/NetworkConfig.hh
network/garnet-flexible-pipeline/NetworkInterface.cc
network/garnet-flexible-pipeline/NetworkInterface.hh
network/garnet-flexible-pipeline/NetworkLink.cc
network/garnet-flexible-pipeline/NetworkLink.hh
network/garnet-flexible-pipeline/OutVcState.cc
network/garnet-flexible-pipeline/OutVcState.hh
network/garnet-flexible-pipeline/Router.cc
network/garnet-flexible-pipeline/Router.hh
network/garnet-flexible-pipeline/SConscript
network/garnet-flexible-pipeline/VCarbiter.cc
network/garnet-flexible-pipeline/VCarbiter.hh
network/garnet-flexible-pipeline/flit.cc
network/garnet-flexible-pipeline/flit.hh
network/garnet-flexible-pipeline/flitBuffer.cc
network/garnet-flexible-pipeline/flitBuffer.hh
network/garnet-flexible-pipeline/netconfig.defaults
network/garnet/NetworkHeader.hh
network/garnet/fixed-pipeline/CreditLink_d.hh
network/garnet/fixed-pipeline/GarnetNetwork_d.cc
network/garnet/fixed-pipeline/GarnetNetwork_d.hh
network/garnet/fixed-pipeline/InputUnit_d.cc
network/garnet/fixed-pipeline/InputUnit_d.hh
network/garnet/fixed-pipeline/NetworkInterface_d.cc
network/garnet/fixed-pipeline/NetworkInterface_d.hh
network/garnet/fixed-pipeline/NetworkLink_d.cc
network/garnet/fixed-pipeline/NetworkLink_d.hh
network/garnet/fixed-pipeline/OutVcState_d.cc
network/garnet/fixed-pipeline/OutVcState_d.hh
network/garnet/fixed-pipeline/OutputUnit_d.cc
network/garnet/fixed-pipeline/OutputUnit_d.hh
network/garnet/fixed-pipeline/Router_d.cc
network/garnet/fixed-pipeline/Router_d.hh
network/garnet/fixed-pipeline/RoutingUnit_d.cc
network/garnet/fixed-pipeline/RoutingUnit_d.hh
network/garnet/fixed-pipeline/SConscript
network/garnet/fixed-pipeline/SWallocator_d.cc
network/garnet/fixed-pipeline/SWallocator_d.hh
network/garnet/fixed-pipeline/Switch_d.cc
network/garnet/fixed-pipeline/Switch_d.hh
network/garnet/fixed-pipeline/VCallocator_d.cc
network/garnet/fixed-pipeline/VCallocator_d.hh
network/garnet/fixed-pipeline/VirtualChannel_d.cc
network/garnet/fixed-pipeline/VirtualChannel_d.hh
network/garnet/fixed-pipeline/flitBuffer_d.cc
network/garnet/fixed-pipeline/flitBuffer_d.hh
network/garnet/fixed-pipeline/flit_d.cc
network/garnet/fixed-pipeline/flit_d.hh
network/garnet/flexible-pipeline/FlexibleConsumer.hh
network/garnet/flexible-pipeline/GarnetNetwork.cc
network/garnet/flexible-pipeline/GarnetNetwork.hh
network/garnet/flexible-pipeline/InVcState.cc
network/garnet/flexible-pipeline/InVcState.hh
network/garnet/flexible-pipeline/NetworkConfig.hh
network/garnet/flexible-pipeline/NetworkInterface.cc
network/garnet/flexible-pipeline/NetworkInterface.hh
network/garnet/flexible-pipeline/NetworkLink.cc
network/garnet/flexible-pipeline/NetworkLink.hh
network/garnet/flexible-pipeline/OutVcState.cc
network/garnet/flexible-pipeline/OutVcState.hh
network/garnet/flexible-pipeline/Router.cc
network/garnet/flexible-pipeline/Router.hh
network/garnet/flexible-pipeline/SConscript
network/garnet/flexible-pipeline/VCarbiter.cc
network/garnet/flexible-pipeline/VCarbiter.hh
network/garnet/flexible-pipeline/flit.cc
network/garnet/flexible-pipeline/flit.hh
network/garnet/flexible-pipeline/flitBuffer.cc
network/garnet/flexible-pipeline/flitBuffer.hh
network/garnet/flexible-pipeline/netconfig.defaults
6916:a421f60f0e87 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Added a mesh topology

6903:27f47cf65ab7 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: convert to M5 MemorySize
Converted both ruby caches and directory memory to use the M5 MemorySize python
type.

6901:a375402313df 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: added data print to ruby request

6899:f8057af86bf7 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: added the GEMS ruby tester

6897:cfeb3d9563dd 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: cleaned up ruby profilers
Cleaned up the ruby profilers by moving the memory controller profiling code
out of the main profiler object and into a separate object similar to the
current CacheProfiler. Both the CacheProfiler and MemCntrlProfiler are
specific to a particular Ruby object, CacheMemory and MemoryControl
respectively. Therefore, these profilers should not be SimObjects and
created by the python configuration system, but instead private objects. This
simplifies the creation of these profilers.

6896:649e40aad897 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Removed RubySystem::getNumberOfSequencers
removed the static function RubySystem::getNumberOfSequencers and replaced
it with a python config variable

6895:5f3d2d3f977e 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: added ruby stats print
Moved the previous rubymem stats print feature to ruby System so that ruby
stats are printed on simulation exit.

6894:fcd9e5ed33f7 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: fixed Set.cc bug to allow zero sized sets
This is necessary for example when no dma sequencers are necessary in the
simulated system.

6893:9cdf9b65d946 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: FS support using the new configuration system

6891:77451885bb00 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Removed out_link_vec from Consumer
Removed the out_line_vec data structure from the Consumer. I'm not sure
what this did before, but currently it has no usefulness.

6890:87dea2f9f791 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Convered ruby tracing support usage of sequencer
Modified ruby's tracing support to no longer rely on the RubySystem map
to convert a sequencer string name to a sequencer pointer. As a
temporary solution, the code uses the sim_object find function.
Eventually, we should develop a better fix.

6889:323cd43a3c46 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Memory Controller Profiler with new config system
This patch includes a rather substantial change to the memory controller
profiler in order to work with the new configuration system. Most
noteably, the mem_cntrl_profiler no longer uses a string map, but instead
a vector. Eventually this support should be removed from the main
profiler and go into a separate object. Each memory controller should have
a pointer to that new mem_cntrl profile object.

6888:de8e755aca4f 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Converted MOESI_hammer dma cntrl to new config system

6887:b10cae7bacf4 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Added the cache profiler to the new config system

6886:3137c3d41107 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Converted the sequencer deadlock event to m5 eventq

6885:e07489ad819f 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Wrapped ruby events into m5 events
Wrapped ruby events using the m5 event object. Removed the prio_heap
from ruby's event queue and instead schedule ruby events on the m5 event
queue.

6884:28a5d2e6b1ff 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Removed the tech_nm variable from RubySystem

6883:f57e272cf8a1 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Added clock to ruby system
As a first step to migrate ruby to the M5 eventqueue, added a clock
variable to the ruby system.

6882:898047a3672c 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Ruby changes required to use the python config system
This patch includes the necessary changes to connect ruby objects using
the python configuration system. Mainly it consists of removing
unnecessary ruby object pointers and connecting the necessary object
pointers using the generated param objects. This patch includes the
slicc changes necessary to connect generated ruby objects together using
the python configuraiton system.

6881:5a61a8a9009a 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: connects sm queues to the network

6880:a9e3c07205a8 29-Jan-2010 Steve Reinhardt <steve.reinhardt@amd.com>

ruby: Calculate system total memory capacity in Python
rather than in RubySystem object.

6879:c07cf29b5a33 29-Jan-2010 Steve Reinhardt <steve.reinhardt@amd.com>

ruby: Add support for generating topologies in Python.

6877:2a1a3d916ca8 29-Jan-2010 Steve Reinhardt <steve.reinhardt@amd.com>

ruby: Make SLICC-generated objects SimObjects.
Also add SLICC support for state-machine parameter defaults
(passed through to Python as SimObject Param defaults).

6876:a658c315512c 29-Jan-2010 Steve Reinhardt <steve.reinhardt@amd.com>

ruby: Convert most Ruby objects to M5 SimObjects.
The necessary companion conversion of Ruby objects generated by SLICC
are converted to M5 SimObjects in the following patch, so this patch
alone does not compile.
Conversion of Garnet network models is also handled in a separate
patch; that code is temporarily disabled from compiling to allow
testing of interim code.


/gem5/configs/example/memtest-ruby.py
/gem5/src/mem/SConscript
SConscript
common/Debug.cc
common/Debug.hh
common/Debug.py
common/SConscript
config/MESI_CMP_directory.rb
config/MI_example-homogeneous.rb
config/MI_example.rb
config/MOESI_CMP_directory.rb
config/MOESI_CMP_token.rb
config/MOESI_hammer-homogeneous.rb
config/MOESI_hammer.rb
config/SConscript
config/TwoLevel_SplitL1UnifiedL2.rb
config/assert.rb
config/cfg.rb
config/defaults.rb
config/libruby_cfg_test.cc
config/print_cfg.rb
config/util.rb
eventqueue/RubyEventQueue.cc
libruby.cc
network/Network.cc
network/Network.hh
network/Network.py
network/SConscript
network/garnet-fixed-pipeline/GarnetNetwork_d.cc
network/garnet-fixed-pipeline/GarnetNetwork_d.hh
network/garnet-fixed-pipeline/SConscript
network/garnet-flexible-pipeline/GarnetNetwork.cc
network/garnet-flexible-pipeline/GarnetNetwork.hh
network/garnet-flexible-pipeline/NetworkConfig.hh
network/garnet-flexible-pipeline/SConscript
network/orion/SConscript
network/simple/HierarchicalSwitchTopology.hh
network/simple/PtToPtTopology.hh
network/simple/SConscript
network/simple/SimpleNetwork.cc
network/simple/SimpleNetwork.hh
network/simple/SimpleNetwork.py
network/simple/Topology.cc
network/simple/Topology.hh
network/simple/Torus2DTopology.hh
profiler/Profiler.cc
profiler/Profiler.hh
profiler/Profiler.py
profiler/SConscript
recorder/SConscript
recorder/Tracer.cc
recorder/Tracer.hh
recorder/Tracer.py
slicc_interface/AbstractController.hh
slicc_interface/Controller.py
slicc_interface/SConscript
system/Cache.py
system/CacheMemory.cc
system/CacheMemory.hh
system/DMASequencer.cc
system/DMASequencer.hh
system/DirectoryMemory.cc
system/DirectoryMemory.hh
system/DirectoryMemory.py
system/MemoryControl.cc
system/MemoryControl.hh
system/MemoryControl.py
system/RubyPort.cc
system/RubyPort.hh
system/RubySystem.py
system/SConscript
system/Sequencer.cc
system/Sequencer.hh
system/Sequencer.py
system/System.cc
system/System.hh
6875:5eb6e323b595 29-Jan-2010 Steve Reinhardt <steve.reinhardt@amd.com>

ruby: get rid of obsolete, unused CustomTopology class.

6865:abfa00a2a23a 22-Jan-2010 Derek Hower <drh5@cs.wisc.edu>

Automated merge with ssh://hg@m5sim.org/m5

6863:21fbf0412e0d 19-Jan-2010 Derek Hower <drh5@cs.wisc.edu>

ruby: new atomics implementation

This patch changes the way that Ruby handles atomic RMW instructions. This implementation, unlike the prior one, is protocol independent. It works by locking an address from the sequencer immediately after the read portion of an RMW completes. When that address is locked, the coherence controller will only satisfy requests coming from one port (e.g., the mandatory queue) and will ignore all others. After the write portion completed, the line is unlocked. This should also work with multi-line atomics, as long as the blocks are always acquired in the same order.

6862:3d308cbd1657 19-Jan-2010 Derek Hower <drh5@cs.wisc.edu>

merge


/gem5/src/arch/isa_specific.hh
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/RubySlicc_ComponentMapping.sm
/gem5/src/mem/protocol/SConsopts
config/MI_example-homogeneous.rb
config/TwoLevel_SplitL1UnifiedL2.rb
config/cfg.rb
config/defaults.rb
libruby.cc
libruby.hh
slicc_interface/RubySlicc_ComponentMapping.hh
system/CacheMemory.cc
system/CacheMemory.hh
system/DirectoryMemory.cc
system/Sequencer.cc
system/Sequencer.hh
/gem5/src/mem/slicc/SConscript
/gem5/src/mem/slicc/ast/AST.cc
/gem5/src/mem/slicc/ast/AST.hh
/gem5/src/mem/slicc/ast/ASTs.hh
/gem5/src/mem/slicc/ast/ActionDeclAST.cc
/gem5/src/mem/slicc/ast/ActionDeclAST.hh
/gem5/src/mem/slicc/ast/AssignStatementAST.cc
/gem5/src/mem/slicc/ast/AssignStatementAST.hh
/gem5/src/mem/slicc/ast/CheckAllocateStatementAST.cc
/gem5/src/mem/slicc/ast/CheckAllocateStatementAST.hh
/gem5/src/mem/slicc/ast/CheckStopSlotsStatementAST.cc
/gem5/src/mem/slicc/ast/CheckStopSlotsStatementAST.hh
/gem5/src/mem/slicc/ast/ChipComponentAccessAST.cc
/gem5/src/mem/slicc/ast/ChipComponentAccessAST.hh
/gem5/src/mem/slicc/ast/CopyHeadStatementAST.cc
/gem5/src/mem/slicc/ast/CopyHeadStatementAST.hh
/gem5/src/mem/slicc/ast/DeclAST.cc
/gem5/src/mem/slicc/ast/DeclAST.hh
/gem5/src/mem/slicc/ast/DeclListAST.cc
/gem5/src/mem/slicc/ast/DeclListAST.hh
/gem5/src/mem/slicc/ast/EnqueueStatementAST.cc
/gem5/src/mem/slicc/ast/EnqueueStatementAST.hh
/gem5/src/mem/slicc/ast/EnumDeclAST.cc
/gem5/src/mem/slicc/ast/EnumDeclAST.hh
/gem5/src/mem/slicc/ast/EnumExprAST.cc
/gem5/src/mem/slicc/ast/EnumExprAST.hh
/gem5/src/mem/slicc/ast/ExprAST.cc
/gem5/src/mem/slicc/ast/ExprAST.hh
/gem5/src/mem/slicc/ast/ExprStatementAST.cc
/gem5/src/mem/slicc/ast/ExprStatementAST.hh
/gem5/src/mem/slicc/ast/FormalParamAST.cc
/gem5/src/mem/slicc/ast/FormalParamAST.hh
/gem5/src/mem/slicc/ast/FuncCallExprAST.cc
/gem5/src/mem/slicc/ast/FuncCallExprAST.hh
/gem5/src/mem/slicc/ast/FuncDeclAST.cc
/gem5/src/mem/slicc/ast/FuncDeclAST.hh
/gem5/src/mem/slicc/ast/IfStatementAST.cc
/gem5/src/mem/slicc/ast/IfStatementAST.hh
/gem5/src/mem/slicc/ast/InPortDeclAST.cc
/gem5/src/mem/slicc/ast/InPortDeclAST.hh
/gem5/src/mem/slicc/ast/InfixOperatorExprAST.cc
/gem5/src/mem/slicc/ast/InfixOperatorExprAST.hh
/gem5/src/mem/slicc/ast/LiteralExprAST.cc
/gem5/src/mem/slicc/ast/LiteralExprAST.hh
/gem5/src/mem/slicc/ast/Location.cc
/gem5/src/mem/slicc/ast/Location.hh
/gem5/src/mem/slicc/ast/MachineAST.cc
/gem5/src/mem/slicc/ast/MachineAST.hh
/gem5/src/mem/slicc/ast/MemberExprAST.cc
/gem5/src/mem/slicc/ast/MemberExprAST.hh
/gem5/src/mem/slicc/ast/MethodCallExprAST.cc
/gem5/src/mem/slicc/ast/MethodCallExprAST.hh
/gem5/src/mem/slicc/ast/NewExprAST.cc
/gem5/src/mem/slicc/ast/NewExprAST.hh
/gem5/src/mem/slicc/ast/ObjDeclAST.cc
/gem5/src/mem/slicc/ast/ObjDeclAST.hh
/gem5/src/mem/slicc/ast/OutPortDeclAST.cc
/gem5/src/mem/slicc/ast/OutPortDeclAST.hh
/gem5/src/mem/slicc/ast/PairAST.cc
/gem5/src/mem/slicc/ast/PairAST.hh
/gem5/src/mem/slicc/ast/PairListAST.cc
/gem5/src/mem/slicc/ast/PairListAST.hh
/gem5/src/mem/slicc/ast/PeekStatementAST.cc
/gem5/src/mem/slicc/ast/PeekStatementAST.hh
/gem5/src/mem/slicc/ast/ReturnStatementAST.cc
/gem5/src/mem/slicc/ast/ReturnStatementAST.hh
/gem5/src/mem/slicc/ast/StatementAST.cc
/gem5/src/mem/slicc/ast/StatementAST.hh
/gem5/src/mem/slicc/ast/StatementListAST.cc
/gem5/src/mem/slicc/ast/StatementListAST.hh
/gem5/src/mem/slicc/ast/TransitionDeclAST.cc
/gem5/src/mem/slicc/ast/TransitionDeclAST.hh
/gem5/src/mem/slicc/ast/TypeAST.cc
/gem5/src/mem/slicc/ast/TypeAST.hh
/gem5/src/mem/slicc/ast/TypeDeclAST.cc
/gem5/src/mem/slicc/ast/TypeDeclAST.hh
/gem5/src/mem/slicc/ast/TypeFieldAST.cc
/gem5/src/mem/slicc/ast/TypeFieldAST.hh
/gem5/src/mem/slicc/ast/TypeFieldEnumAST.cc
/gem5/src/mem/slicc/ast/TypeFieldEnumAST.hh
/gem5/src/mem/slicc/ast/TypeFieldMemberAST.cc
/gem5/src/mem/slicc/ast/TypeFieldMemberAST.hh
/gem5/src/mem/slicc/ast/TypeFieldMethodAST.cc
/gem5/src/mem/slicc/ast/TypeFieldMethodAST.hh
/gem5/src/mem/slicc/ast/VarExprAST.cc
/gem5/src/mem/slicc/ast/VarExprAST.hh
/gem5/src/mem/slicc/generator/fileio.cc
/gem5/src/mem/slicc/generator/fileio.hh
/gem5/src/mem/slicc/generator/html_gen.cc
/gem5/src/mem/slicc/generator/html_gen.hh
/gem5/src/mem/slicc/generator/mif_gen.cc
/gem5/src/mem/slicc/generator/mif_gen.hh
/gem5/src/mem/slicc/main.cc
/gem5/src/mem/slicc/main.hh
/gem5/src/mem/slicc/parser/lexer.ll
/gem5/src/mem/slicc/parser/parser.py
/gem5/src/mem/slicc/parser/parser.yy
/gem5/src/mem/slicc/slicc_global.hh
/gem5/src/mem/slicc/symbols/Action.hh
/gem5/src/mem/slicc/symbols/Event.hh
/gem5/src/mem/slicc/symbols/Func.cc
/gem5/src/mem/slicc/symbols/Func.hh
/gem5/src/mem/slicc/symbols/State.hh
/gem5/src/mem/slicc/symbols/StateMachine.cc
/gem5/src/mem/slicc/symbols/StateMachine.hh
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/mem/slicc/symbols/Symbol.cc
/gem5/src/mem/slicc/symbols/Symbol.hh
/gem5/src/mem/slicc/symbols/SymbolTable.cc
/gem5/src/mem/slicc/symbols/SymbolTable.hh
/gem5/src/mem/slicc/symbols/Transition.cc
/gem5/src/mem/slicc/symbols/Transition.hh
/gem5/src/mem/slicc/symbols/Type.cc
/gem5/src/mem/slicc/symbols/Type.hh
/gem5/src/mem/slicc/symbols/Type.py
/gem5/src/mem/slicc/symbols/Var.cc
/gem5/src/mem/slicc/symbols/Var.hh
/gem5/src/python/m5/convert.py
/gem5/src/python/m5/environment.py
/gem5/src/python/m5/smartdict.py
/gem5/src/python/m5/util/misc.py
/gem5/tests/configs/memtest-ruby.py
/gem5/tests/configs/ruby_config.py
6861:7561088131f9 04-Dec-2009 Derek Hower <drh5@cs.wisc.edu>

ruby: cleaned up ruby-lang configuration

6859:5de565c4b7bd 18-Nov-2009 Derek Hower <drh5@cs.wisc.edu>

ruby: added sequencer stats to track what requests are waiting on

6858:92135335e177 18-Nov-2009 Derek Hower <drh5@cs.wisc.edu>

ruby: turned off randomization by default, turned on memory controller random arbitrate

6857:14d7cd6f09a6 13-Nov-2009 Derek Hower <drh5@cs.wisc.edu>

ruby: added -A option to TwoLevel_SplitL1UnifiedL2 to set the L1 cache size

6856:f3caa1cd1d9a 13-Nov-2009 Derek Hower <drh5@cs.wisc.edu>

ruby: gave ALIASED_REQUEST priority over BUFFER_FULL in sequencer

6855:5a55833aede4 13-Nov-2009 Derek Hower <drh5@cs.wisc.edu>

ruby: reduce the memory usage of ruby by making memory vector page based

6854:575b029534f1 13-Nov-2009 Derek Hower <drh5@cs.wisc.edu>

ruby: cache memory bugfix

6853:971902a8740e 20-Oct-2009 Derek Hower <drh5@cs.wisc.edu>

ruby: removed obsolete configuration files

6852:e98ede05836c 16-Oct-2009 Derek Hower <drh5@cs.wisc.edu>

ruby: add parameter to config to set # of l2 banks

6850:d480ef5b9028 21-Sep-2009 Polina Dudnik <pdudnik@gmail.com>

Atomics bug fix

6848:1139f1e51da9 25-Sep-2009 Derek Hower <drh5@cs.wisc.edu>

ruby: more helpful config error message

6846:60e0df8086f0 17-Sep-2009 Polina Dudnik <pdudnik@cs.wisc.edu>

Functionality migrated to sequencer.

6845:9740ade45962 15-Sep-2009 Derek Hower <drh5@cs.wisc.edu>

ruby: improve libruby_issue_request feedback

6844:b8421af116e5 15-Sep-2009 Derek Hower <drh5@cs.wisc.edu>

removed isReady from the library interface

6843:de4b394c6792 15-Sep-2009 Derek Hower <drh5@cs.wisc.edu>

ruby: added broadcast mechanism

6842:346b8460b306 15-Sep-2009 Derek Hower <drh5@cs.wisc.edu>

ruby: added unified assert script

6841:be6ad0778565 15-Sep-2009 Derek Hower <drh5@cs.wisc.edu>

ruby: made configuration parameters uniform

6840:a78dc9a782b8 14-Sep-2009 Derek Hower <drh5@cs.wisc.edu>

ruby:removed unused code from CacheMemory

6839:0bf5c598c9c5 14-Sep-2009 Derek Hower <drh5@cs.wisc.edu>

ruby: configuration updates

6838:829892ec644c 14-Sep-2009 Derek Hower <drh5@cs.wisc.edu>

ruby: removed stray printf

6836:1a01f799bd76 11-Sep-2009 Derek Hower <drh5@cs.wisc.edu>

ruby: cleaned up unified MESI/MOESI configuration

6835:ec28f4e6df9e 11-Sep-2009 Derek Hower <drh5@cs.wisc.edu>

merge

6833:38da844de114 10-Sep-2009 Derek Hower <drh5@cs.wisc.edu>

ruby: removed SMT-related Sequencer assert

6832:576153b639d0 10-Sep-2009 Derek Hower <drh5@cs.wisc.edu>

ruby: made randomization true by default

6830:0173532b03f0 10-Sep-2009 Derek Hower <drh5@cs.wisc.edu>

ruby: made L2 request/response latency based on cache latency by default

6829:4169f24434ef 09-Sep-2009 Derek Hower <drh5@cs.wisc.edu>

ruby: made Locked read/write atomic requests within ruby

6827:2431d803c355 01-Sep-2009 Derek Hower <drh5@cs.wisc.edu>

ruby: fixed config assertion failure

6825:104115ebc206 21-Aug-2009 pdudnik@gmail.com

[mq]: first_patch

6823:c47323cc8f98 25-Aug-2009 Derek Hower <drh5@cs.wisc.edu>

ruby: CacheMemory tag lookup uses a hash instead of a loop

6822:79d81f0b6217 18-Aug-2009 Derek Hower <drh5@cs.wisc.edu>

ruby: added random seed option to config scripts

6797:7bf0a839c237 18-Nov-2009 Brad Beckmann <Brad.Beckmann@amd.com>

Resurrection of the CMP token protocol to GEM5

6795:394bc95d417b 18-Nov-2009 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: removed the chip pointer from MessageBuffer
The Chip object no longer exists and thus is removed from the MessageBuffer
constructor.

6791:71021368db4a 18-Nov-2009 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: The persistent table files from GEMS
These files are need by the MOESI_CMP_token protocol.

6790:14c356da6ed3 18-Nov-2009 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: MOESI hammer support for DMA reads and writes

6789:53caf4b9186d 18-Nov-2009 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Added a memory controller feature to MOESI hammer

6788:c43f6fdcc24c 18-Nov-2009 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Hammer ruby configuration support

6785:bb675ba62c79 18-Nov-2009 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: returns the number of LLC needed for broadcast
Added feature to CacheMemory to return the number of last level caches.
This count is need for broadcast protocols such as MOESI_hammer.

6784:13387a838449 18-Nov-2009 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: cache configuration fix to use bytes
Changed cache size to be in bytes instead of kb so that testers can use very
small caches and increase the chance of writeback races.

6783:c82047a62104 18-Nov-2009 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: fix CacheMemory destructor

6782:db88ebe2c9fc 18-Nov-2009 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: split CacheMemory.hh into a .hh and a .cc

6781:8da9d36fc14a 18-Nov-2009 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Added default names to message buffers
Added default names to message buffers created by the simple network.

6774:554d84a850d6 18-Nov-2009 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: fixed dma mi example to work with multiple dma ports

6770:5ea2e2b3b39f 18-Nov-2009 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Fixed Directory memory destructor

6765:b5101309174d 18-Nov-2009 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Support for merging ALPHA_FS and ruby
Connects M5 cpu and dma ports directly to ruby sequencers and dma
sequencers. Rubymem also includes a pio port so that pio requests
and be forwarded to a special pio bus connecting to device pio
ports.

6763:5a879a3513dc 18-Nov-2009 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Ruby 64-bit address output fixes.

6762:a22a47e60c21 18-Nov-2009 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Ruby destruction fix.

6761:81e9d83f87c0 18-Nov-2009 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Ruby debug print fixes.

6712:b95abe00dd9d 04-Nov-2009 Nathan Binkert <nate@binkert.org>

build: fix compile problems pointed out by gcc 4.4

6700:deb871e1fc27 28-Oct-2009 Nathan Binkert <nate@binkert.org>

license: Fix license on network model code

This mostly was a matter of changing the license owner to Princeton
which is as it should have been. The code was originally licensed
under the GPL but was relicensed as BSD by Li-Shiuan Peh on July 27,
2009. This relicensing was in an explicit e-mail to Nathan Binkert,
Brad Beckmann, Mark Hill, David Wood, and Steve Reinhardt.


network/Network.cc
network/garnet-fixed-pipeline/CreditLink_d.hh
network/garnet-fixed-pipeline/GarnetNetwork_d.cc
network/garnet-fixed-pipeline/GarnetNetwork_d.hh
network/garnet-fixed-pipeline/InputUnit_d.cc
network/garnet-fixed-pipeline/InputUnit_d.hh
network/garnet-fixed-pipeline/NetworkHeader.hh
network/garnet-fixed-pipeline/NetworkInterface_d.cc
network/garnet-fixed-pipeline/NetworkInterface_d.hh
network/garnet-fixed-pipeline/NetworkLink_d.cc
network/garnet-fixed-pipeline/NetworkLink_d.hh
network/garnet-fixed-pipeline/OutVcState_d.cc
network/garnet-fixed-pipeline/OutVcState_d.hh
network/garnet-fixed-pipeline/OutputUnit_d.cc
network/garnet-fixed-pipeline/OutputUnit_d.hh
network/garnet-fixed-pipeline/Router_d.cc
network/garnet-fixed-pipeline/Router_d.hh
network/garnet-fixed-pipeline/RoutingUnit_d.cc
network/garnet-fixed-pipeline/RoutingUnit_d.hh
network/garnet-fixed-pipeline/SWallocator_d.cc
network/garnet-fixed-pipeline/SWallocator_d.hh
network/garnet-fixed-pipeline/Switch_d.cc
network/garnet-fixed-pipeline/Switch_d.hh
network/garnet-fixed-pipeline/VCallocator_d.cc
network/garnet-fixed-pipeline/VCallocator_d.hh
network/garnet-fixed-pipeline/VirtualChannel_d.cc
network/garnet-fixed-pipeline/VirtualChannel_d.hh
network/garnet-fixed-pipeline/flitBuffer_d.cc
network/garnet-fixed-pipeline/flitBuffer_d.hh
network/garnet-fixed-pipeline/flit_d.cc
network/garnet-fixed-pipeline/flit_d.hh
network/garnet-flexible-pipeline/FlexibleConsumer.hh
network/garnet-flexible-pipeline/GarnetNetwork.cc
network/garnet-flexible-pipeline/GarnetNetwork.hh
network/garnet-flexible-pipeline/InVcState.cc
network/garnet-flexible-pipeline/InVcState.hh
network/garnet-flexible-pipeline/NetworkConfig.hh
network/garnet-flexible-pipeline/NetworkInterface.cc
network/garnet-flexible-pipeline/NetworkInterface.hh
network/garnet-flexible-pipeline/NetworkLink.cc
network/garnet-flexible-pipeline/NetworkLink.hh
network/garnet-flexible-pipeline/OutVcState.cc
network/garnet-flexible-pipeline/OutVcState.hh
network/garnet-flexible-pipeline/Router.cc
network/garnet-flexible-pipeline/Router.hh
network/garnet-flexible-pipeline/VCarbiter.cc
network/garnet-flexible-pipeline/VCarbiter.hh
network/garnet-flexible-pipeline/flit.cc
network/garnet-flexible-pipeline/flit.hh
network/garnet-flexible-pipeline/flitBuffer.cc
network/garnet-flexible-pipeline/flitBuffer.hh
6659:60e8bbcae401 23-Sep-2009 Nathan Binkert <nate@binkert.org>

ruby: Disable all debug output by default

6635:3b2d7fdff6b1 11-Sep-2009 pdudnik@gmail.com

Added new MESI files

6634:737662612eb7 11-Sep-2009 pdudnik@gmail.com

Config adjustments for MESI

6631:5437a0eeb822 11-Sep-2009 pdudnik@gmail.com

Object print bug fix

6510:336a194c8500 15-Aug-2009 pdudnik@gmail.com

Made servicing_atomic a counter and added started writes:
a function for setting the flag to indicate that
the rmw_writes started issuing

6506:e9e7ca667575 14-Aug-2009 pdudnik@gmail.com

Multi-line RMW handling

6505:a2306c563df2 14-Aug-2009 pdudnik@gmail.com

SMT atomics modifications:
don't allow enquing from other threads if servicing and atomic for a thread

6497:64bf776c5e70 13-Aug-2009 Derek Hower <drh5@cs.wisc.edu>

Automated merge with ssh://hg@m5sim.org/m5

6496:41bcaefab1a0 13-Aug-2009 Derek Hower <drh5@cs.wisc.edu>

ruby: config bugfix

6495:04a90b404da6 11-Aug-2009 Tushar Krishna <Tushar.Krishna@amd.com>

ruby/network data_msg_size bug fix with updated stats

6494:be123e27612f 11-Aug-2009 Brad Beckmann <Brad.Beckmann@amd.com>

merged Tushar's bug fix with public repository changes

6493:1fa51760a963 07-Aug-2009 Tushar Krishna <Tushar.Krishna@amd.com>

bug fix for data_msg_size in network/Network.cc

6488:692b62dfc8b0 06-Aug-2009 Derek Hower <drh5@cs.wisc.edu>

ruby: better configuration assert message

6470:e76348cb11de 05-Aug-2009 Derek Hower <drh5@cs.wisc.edu>

ruby: configuration supports multiple runs in same session

These changes allow to run Ruby-gems multiple times from the same
ruby-lang script with different configurations

6468:26abdfe2d980 05-Aug-2009 Derek Hower <drh5@cs.wisc.edu>

ruby: made mapAddressToRange based off a bit count

6467:5670eee2a866 04-Aug-2009 Derek Hower <drh5@cs.wisc.edu>

slicc: added MOESI_CMP_directory, DMA SequencerMsg, parameterized controllers

This changeset contains a lot of different changes that are too
mingled to separate. They are:

1. Added MOESI_CMP_directory

I made the changes necessary to bring back MOESI_CMP_directory,
including adding a DMA controller. I got rid of MOESI_CMP_directory_m
and made MOESI_CMP_directory use a memory controller. Added a new
configuration for two level protocols in general, and
MOESI_CMP_directory in particular.

2. DMA Sequencer uses a generic SequencerMsg

I will eventually make the cache Sequencer use this type as well. It
doesn't contain an offset field, just a physical address and a length.
MI_example has been updated to deal with this.

3. Parameterized Controllers

SLICC controllers can now take custom parameters to use for mapping,
latencies, etc. Currently, only int parameters are supported.


/gem5/src/mem/gems_common/Map.hh
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MI_example-dma.sm
/gem5/src/mem/protocol/MI_example-msg.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-msg.sm
/gem5/src/mem/protocol/MOESI_CMP_directory.slicc
/gem5/src/mem/protocol/MOESI_CMP_directory_m-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory_m.slicc
/gem5/src/mem/protocol/RubySlicc_ComponentMapping.sm
/gem5/src/mem/protocol/RubySlicc_Exports.sm
/gem5/src/mem/protocol/RubySlicc_Profiler.sm
/gem5/src/mem/protocol/RubySlicc_Types.sm
/gem5/src/mem/protocol/RubySlicc_Util.sm
config/MI_example-homogeneous.rb
config/MI_example.rb
config/MOESI_CMP_directory.rb
config/TwoLevel_SplitL1UnifiedL2.rb
config/cfg.rb
config/defaults.rb
slicc_interface/RubySlicc_ComponentMapping.hh
slicc_interface/RubySlicc_Util.hh
system/DMASequencer.cc
system/DirectoryMemory.cc
system/DirectoryMemory.hh
system/PerfectCacheMemory.hh
system/System.hh
system/TimerTable.cc
system/TimerTable.hh
/gem5/src/mem/slicc/ast/AST.hh
/gem5/src/mem/slicc/ast/ActionDeclAST.cc
/gem5/src/mem/slicc/ast/ActionDeclAST.hh
/gem5/src/mem/slicc/ast/EnqueueStatementAST.cc
/gem5/src/mem/slicc/ast/FormalParamAST.cc
/gem5/src/mem/slicc/ast/FormalParamAST.hh
/gem5/src/mem/slicc/ast/FuncDeclAST.cc
/gem5/src/mem/slicc/ast/FuncDeclAST.hh
/gem5/src/mem/slicc/ast/MachineAST.cc
/gem5/src/mem/slicc/ast/MachineAST.hh
/gem5/src/mem/slicc/parser/parser.py
/gem5/src/mem/slicc/parser/parser.yy
/gem5/src/mem/slicc/symbols/StateMachine.cc
/gem5/src/mem/slicc/symbols/StateMachine.hh
6434:a6e8795b73de 29-Jul-2009 Derek Hower <drh5@cs.wisc.edu>

ruby: fixed clearStats

6433:0f0f0fbef977 27-Jul-2009 Derek Hower <drh5@cs.wisc.edu>

ruby: removed unused/incorrect profiler state

6386:82ee4a597908 22-Jul-2009 Polina Dudnik <pdudnik@gmail.com>

Fixed the licences plus minor fixes for compilation

6381:fb39bf847dbe 21-Jul-2009 Derek Hower <drh5@cs.wisc.edu>

ruby: fixed sequencer RMW data bug

6380:6ed66f196c89 21-Jul-2009 Derek Hower <drh5@cs.wisc.edu>

ruby: libruby_init now takes parsed Ruby-lang config text

libruby_init now expects to get a file that contains the output of
running a ruby-lang configuration, opposed to the ruby-lang
configuration itself.

6374:11423b4639c0 20-Jul-2009 Derek Hower <drh5@cs.wisc.edu>

ruby: moved cache stats from Profiler to CacheMemory

Caches are now responsible for their own statistic gathering. This
requires a direct callback from the protocol on misses, and so all
future protocols need to take this into account.

6373:544d33334ee1 19-Jul-2009 Derek Hower <drh5@cs.wisc.edu>

scons: removed RubyConfig from scons

6372:f1a41ea3bbab 18-Jul-2009 Derek Hower <drh5@cs.wisc.edu>

ruby: removed all refs to old RubyConfig

6371:a1768b396928 18-Jul-2009 Derek Hower <drh5@cs.wisc.edu>

ruby: removed dead files

6370:ebfc37fa8615 18-Jul-2009 Derek Hower <drh5@cs.wisc.edu>

ruby: removed dead files

6369:82ac95f4d9f0 18-Jul-2009 Derek Hower <drh5@cs.wisc.edu>

merge

6368:cecc7019b458 18-Jul-2009 Derek Hower <drh5@cs.wisc.edu>

ruby: fixed dma sequencer bug

The DMASequencer was still using a parameter from the old RubyConfig,
causing an offset error when the requested data wasn't block aligned.
This changeset also includes a fix to MI_example for a similar bug.

6367:c4e91b8e3da3 18-Jul-2009 Derek Hower <drh5@cs.wisc.edu>

ruby: better debug print for DataBlock

6357:bd813379f121 15-Jul-2009 pdudnik@gmail.com

Tester update

6355:79464d8a4d2f 13-Jul-2009 pdudnik@gmail.com

1. Got rid of unused functions in DirectoryMemory
2. Reintroduced RMW_Read and RMW_Write
3. Defined -2 in the Sequencer as well as made a note about mandatory queue

Did not address the issues in the slicc because remaking the atomics altogether to allow
multiple processors to issue atomic requests at once

6354:390fefc98e2b 13-Jul-2009 pdudnik@gmail.com

Changes to add tracing and replaying command-line options
Trace is automatically ended upon a manual checkpoint

6353:979add6f6fb7 13-Jul-2009 pdudnik@gmail.com

Locked requests should actually be converted to ST rather than ATOMIC, because ATOMIC is for RMW.

6351:31d19bdd9d85 13-Jul-2009 pdudnik@gmail.com

Minor fixes for compiling

6350:accdf59eedd3 13-Jul-2009 pdudnik@gmail.com

Replaced RMW with Locked. RMW will be used for the coherence-aided atomics other than LLSC

6349:1b3d165d890d 13-Jul-2009 pdudnik@gmail.com

Moved the lock check and clearing the lock into makeRequest

6348:374e1d9b0660 13-Jul-2009 pdudnik@gmail.com

Forgot to replace one of the RubyRequest_RMW

6347:a532849ca78f 13-Jul-2009 Polina pdudnik@gmail.com

Reintegrated Derek's functional implementation of atomics with a minor change: don't clear lock on failure

6339:61f8eb04e96d 13-Jul-2009 Derek Hower <drh5@cs.wisc.edu>

regression: updated memtest-ruby stats

This also includes a change to the default Ruby random seed, which was
previously set using the wall clock. It is now set to 1234 so that
the stat files don't change for the regression tester.

6297:57650468aff1 08-Jul-2009 Derek Hower <drh5@cs.wisc.edu>

slicc: fixed MI_example bug. The directory wasn't deallocating the TBE, leading to a leak. Also increased the default max TBE size to 256 to allow memtest to pass the regression.

6296:553a34ccd03b 08-Jul-2009 Derek Hower <drh5@cs.wisc.edu>

ruby: set the default values of the debug object so that nothing is printed

6294:b42cea5e1625 08-Jul-2009 Derek Hower <drh5@cs.wisc.edu>

removed stray debug print

6289:a9e7d19871b5 06-Jul-2009 Nathan Binkert <nate@binkert.org>

ruby: Fix RubyMemory to work with the newer ruby.

6288:083a6806dd96 06-Jul-2009 Nathan Binkert <nate@binkert.org>

ruby: apply some fixes that were overwritten by the recent ruby import.

6286:40b142645016 06-Jul-2009 Nathan Binkert <nate@binkert.org>

scons: update SCons files for changes in ruby.

6285:ce086eca1ede 06-Jul-2009 Nathan Binkert <nate@binkert.org>

ruby: Import the latest ruby changes from gems.
This was done with an automated process, so there could be things that were
done in this tree in the past that didn't make it. One known regression
is that atomic memory operations do not seem to work properly anymore.


/gem5/src/mem/gems_common/std-includes.hh
/gem5/src/mem/gems_common/util.cc
/gem5/src/mem/gems_common/util.hh
/gem5/src/mem/protocol/MESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-mem.sm
/gem5/src/mem/protocol/MESI_CMP_directory-msg.sm
/gem5/src/mem/protocol/MESI_CMP_directory.slicc
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MI_example-dma.sm
/gem5/src/mem/protocol/MI_example-msg.sm
/gem5/src/mem/protocol/MI_example.slicc
/gem5/src/mem/protocol/RubySlicc_ComponentMapping.sm
/gem5/src/mem/protocol/RubySlicc_Exports.sm
/gem5/src/mem/protocol/RubySlicc_Types.sm
/gem5/src/mem/protocol/standard_1level_CMP-protocol.sm
buffers/MessageBuffer.cc
buffers/MessageBuffer.hh
common/Address.hh
common/Consumer.hh
common/DataBlock.cc
common/DataBlock.hh
common/Debug.cc
common/Debug.hh
common/Driver.hh
common/Global.hh
common/Set.cc
common/SubBlock.cc
common/SubBlock.hh
common/TypeDefines.hh
config/MI_example-homogeneous.rb
config/RubyConfig.cc
config/RubyConfig.hh
config/cfg.rb
config/config.hh
config/defaults.rb
config/libruby_cfg_test.cc
config/print_cfg.rb
config/rubyconfig.defaults
config/tester.defaults
eventqueue/RubyEventQueue.cc
filters/AbstractBloomFilter.hh
filters/BlockBloomFilter.cc
filters/BlockBloomFilter.hh
filters/BulkBloomFilter.cc
filters/BulkBloomFilter.hh
filters/GenericBloomFilter.cc
filters/GenericBloomFilter.hh
filters/H3BloomFilter.cc
filters/H3BloomFilter.hh
filters/LSB_CountingBloomFilter.cc
filters/LSB_CountingBloomFilter.hh
filters/MultiBitSelBloomFilter.cc
filters/MultiBitSelBloomFilter.hh
filters/MultiGrainBloomFilter.cc
filters/MultiGrainBloomFilter.hh
filters/NonCountingBloomFilter.cc
filters/NonCountingBloomFilter.hh
init.cc
init.hh
libruby.cc
libruby.hh
libruby_internal.hh
network/Network.cc
network/Network.hh
network/garnet-fixed-pipeline/CreditLink_d.hh
network/garnet-fixed-pipeline/GarnetNetwork_d.cc
network/garnet-fixed-pipeline/GarnetNetwork_d.hh
network/garnet-fixed-pipeline/NetworkInterface_d.cc
network/garnet-fixed-pipeline/NetworkLink_d.cc
network/garnet-fixed-pipeline/NetworkLink_d.hh
network/garnet-fixed-pipeline/OutVcState_d.cc
network/garnet-fixed-pipeline/OutVcState_d.hh
network/garnet-fixed-pipeline/OutputUnit_d.cc
network/garnet-fixed-pipeline/Router_d.cc
network/garnet-fixed-pipeline/SWallocator_d.cc
network/garnet-fixed-pipeline/VCallocator_d.cc
network/garnet-flexible-pipeline/GarnetNetwork.cc
network/garnet-flexible-pipeline/GarnetNetwork.hh
network/garnet-flexible-pipeline/NetworkConfig.hh
network/garnet-flexible-pipeline/NetworkInterface.cc
network/garnet-flexible-pipeline/NetworkLink.cc
network/garnet-flexible-pipeline/Router.cc
network/simple/CustomTopology.cc
network/simple/CustomTopology.hh
network/simple/HierarchicalSwitchTopology.cc
network/simple/HierarchicalSwitchTopology.hh
network/simple/PerfectSwitch.cc
network/simple/PtToPtTopology.cc
network/simple/PtToPtTopology.hh
network/simple/SimpleNetwork.cc
network/simple/SimpleNetwork.hh
network/simple/Switch.cc
network/simple/Switch.hh
network/simple/Throttle.cc
network/simple/Throttle.hh
network/simple/Topology.cc
network/simple/Topology.hh
network/simple/Torus2DTopology.cc
network/simple/Torus2DTopology.hh
profiler/AddressProfiler.cc
profiler/AddressProfiler.hh
profiler/Profiler.cc
profiler/Profiler.hh
recorder/CacheRecorder.cc
recorder/CacheRecorder.hh
recorder/TraceRecord.cc
recorder/TraceRecord.hh
recorder/Tracer.cc
recorder/Tracer.hh
slicc_interface/AbstractCacheEntry.cc
slicc_interface/AbstractCacheEntry.hh
slicc_interface/AbstractChip.cc
slicc_interface/AbstractChip.hh
slicc_interface/AbstractController.hh
slicc_interface/RubySlicc_ComponentMapping.hh
slicc_interface/RubySlicc_Profiler_interface.cc
slicc_interface/RubySlicc_Util.hh
storebuffer/hfa.hh
storebuffer/hfatypes.hh
storebuffer/interface.cc
storebuffer/interface.hh
storebuffer/stb_interface.cc
storebuffer/stb_interface.hh
storebuffer/storebuffer.cc
storebuffer/storebuffer.hh
system/AbstractMemOrCache.hh
system/CacheMemory.hh
system/DMASequencer.cc
system/DMASequencer.hh
system/DirectoryMemory.cc
system/DirectoryMemory.hh
system/MemoryControl.cc
system/MemoryControl.hh
system/MemoryVector.hh
system/NodePersistentTable.cc
system/NodePersistentTable.hh
system/PersistentArbiter.cc
system/PersistentArbiter.hh
system/PersistentTable.cc
system/PersistentTable.hh
system/ProcessorInterface.hh
system/RubyPort.cc
system/RubyPort.hh
system/Sequencer.cc
system/Sequencer.hh
system/StoreBuffer.cc
system/StoreBuffer.hh
system/StoreCache.cc
system/StoreCache.hh
system/System.cc
system/System.hh
system/TBETable.hh
tester/BarrierGenerator.cc
tester/BarrierGenerator.hh
tester/Check.cc
tester/Check.hh
tester/CheckTable.cc
tester/CheckTable.hh
tester/DetermGETXGenerator.cc
tester/DetermGETXGenerator.hh
tester/DetermInvGenerator.cc
tester/DetermInvGenerator.hh
tester/DetermSeriesGETSGenerator.cc
tester/DetermSeriesGETSGenerator.hh
tester/DeterministicDriver.cc
tester/DeterministicDriver.hh
tester/Driver_Tester.cc
tester/Driver_Tester.hh
tester/EventQueue_Tester.hh
tester/Global_Tester.hh
tester/Instruction.cc
tester/Instruction.hh
tester/RaceyDriver.cc
tester/RaceyDriver.hh
tester/RaceyPseudoThread.cc
tester/RaceyPseudoThread.hh
tester/RequestGenerator.cc
tester/RequestGenerator.hh
tester/SpecifiedGenerator.cc
tester/SpecifiedGenerator.hh
tester/SyntheticDriver.cc
tester/SyntheticDriver.hh
tester/Tester.cc
tester/Tester.hh
tester/main.cc
tester/main.hh
tester/test_framework.cc
tester/test_framework.hh
/gem5/src/mem/slicc/ast/ASTs.hh
/gem5/src/mem/slicc/ast/EnqueueStatementAST.cc
/gem5/src/mem/slicc/ast/MachineAST.cc
/gem5/src/mem/slicc/ast/MachineAST.hh
/gem5/src/mem/slicc/ast/MethodCallExprAST.cc
/gem5/src/mem/slicc/ast/NewExprAST.cc
/gem5/src/mem/slicc/ast/NewExprAST.hh
/gem5/src/mem/slicc/ast/ObjDeclAST.cc
/gem5/src/mem/slicc/parser/lexer.ll
/gem5/src/mem/slicc/parser/parser.yy
/gem5/src/mem/slicc/symbols/Func.cc
/gem5/src/mem/slicc/symbols/Func.hh
/gem5/src/mem/slicc/symbols/StateMachine.cc
/gem5/src/mem/slicc/symbols/StateMachine.hh
/gem5/src/mem/slicc/symbols/Symbol.hh
/gem5/src/mem/slicc/symbols/SymbolTable.cc
/gem5/src/mem/slicc/symbols/SymbolTable.hh
/gem5/src/mem/slicc/symbols/Type.cc
/gem5/src/mem/slicc/symbols/Type.hh
/gem5/src/mem/slicc/symbols/Var.hh
6284:a63d1dc4c820 06-Jul-2009 Nathan Binkert <nate@binkert.org>

ruby: replace strings that were missed in original ruby import.


/gem5/src/mem/gems_common/ioutil/attrlex.ll
/gem5/src/mem/gems_common/ioutil/attrparse.yy
common/Global.hh
common/NetDest.cc
common/NetDest.hh
common/Set.cc
common/Set.hh
config/RubyConfig.cc
config/RubyConfig.hh
eventqueue/RubyEventQueue.hh
init.cc
init.hh
network/Network.hh
network/garnet-fixed-pipeline/CreditLink_d.hh
network/garnet-fixed-pipeline/GarnetNetwork_d.cc
network/garnet-fixed-pipeline/GarnetNetwork_d.hh
network/garnet-fixed-pipeline/InputUnit_d.hh
network/garnet-fixed-pipeline/NetworkHeader.hh
network/garnet-fixed-pipeline/NetworkInterface_d.cc
network/garnet-fixed-pipeline/NetworkInterface_d.hh
network/garnet-fixed-pipeline/NetworkLink_d.cc
network/garnet-fixed-pipeline/NetworkLink_d.hh
network/garnet-fixed-pipeline/OutVcState_d.hh
network/garnet-fixed-pipeline/OutputUnit_d.hh
network/garnet-fixed-pipeline/Router_d.cc
network/garnet-fixed-pipeline/Router_d.hh
network/garnet-fixed-pipeline/RoutingUnit_d.hh
network/garnet-fixed-pipeline/SWallocator_d.cc
network/garnet-fixed-pipeline/SWallocator_d.hh
network/garnet-fixed-pipeline/Switch_d.hh
network/garnet-fixed-pipeline/VCallocator_d.cc
network/garnet-fixed-pipeline/VCallocator_d.hh
network/garnet-fixed-pipeline/VirtualChannel_d.hh
network/garnet-fixed-pipeline/flitBuffer_d.hh
network/garnet-fixed-pipeline/flit_d.hh
network/garnet-flexible-pipeline/FlexibleConsumer.hh
network/garnet-flexible-pipeline/GarnetNetwork.cc
network/garnet-flexible-pipeline/GarnetNetwork.hh
network/garnet-flexible-pipeline/InVcState.hh
network/garnet-flexible-pipeline/NetworkConfig.hh
network/garnet-flexible-pipeline/NetworkInterface.hh
network/garnet-flexible-pipeline/NetworkLink.cc
network/garnet-flexible-pipeline/NetworkLink.hh
network/garnet-flexible-pipeline/OutVcState.hh
network/garnet-flexible-pipeline/Router.cc
network/garnet-flexible-pipeline/Router.hh
network/garnet-flexible-pipeline/VCarbiter.hh
network/garnet-flexible-pipeline/flit.hh
network/garnet-flexible-pipeline/flitBuffer.hh
network/simple/PerfectSwitch.cc
network/simple/SimpleNetwork.cc
network/simple/SimpleNetwork.hh
network/simple/Switch.cc
network/simple/Throttle.cc
network/simple/Topology.cc
network/simple/Topology.hh
profiler/AddressProfiler.cc
profiler/AddressProfiler.hh
profiler/CacheProfiler.cc
profiler/CacheProfiler.hh
profiler/Profiler.cc
profiler/Profiler.hh
slicc_interface/AbstractCacheEntry.cc
slicc_interface/AbstractChip.cc
slicc_interface/NetworkMessage.hh
slicc_interface/RubySlicc_Profiler_interface.cc
slicc_interface/RubySlicc_Profiler_interface.hh
slicc_interface/RubySlicc_Util.hh
system/AbstractMemOrCache.hh
system/CacheMemory.hh
system/DirectoryMemory.cc
system/DirectoryMemory.hh
system/MachineID.hh
system/MemoryControl.cc
system/MemoryControl.hh
system/NodeID.hh
system/NodePersistentTable.hh
system/PerfectCacheMemory.hh
system/PersistentArbiter.hh
system/Sequencer.hh
system/System.cc
system/System.hh
system/TBETable.hh
system/TimerTable.hh
tester/Instruction.hh
tester/SpecifiedGenerator.cc
tester/SpecifiedGenerator.hh
/gem5/src/mem/slicc/ast/AST.cc
/gem5/src/mem/slicc/ast/AST.hh
/gem5/src/mem/slicc/ast/ActionDeclAST.cc
/gem5/src/mem/slicc/ast/ActionDeclAST.hh
/gem5/src/mem/slicc/ast/AssignStatementAST.cc
/gem5/src/mem/slicc/ast/AssignStatementAST.hh
/gem5/src/mem/slicc/ast/ChipComponentAccessAST.cc
/gem5/src/mem/slicc/ast/ChipComponentAccessAST.hh
/gem5/src/mem/slicc/ast/DeclAST.cc
/gem5/src/mem/slicc/ast/DeclAST.hh
/gem5/src/mem/slicc/ast/DeclListAST.cc
/gem5/src/mem/slicc/ast/DeclListAST.hh
/gem5/src/mem/slicc/ast/EnqueueStatementAST.hh
/gem5/src/mem/slicc/ast/EnumDeclAST.cc
/gem5/src/mem/slicc/ast/EnumDeclAST.hh
/gem5/src/mem/slicc/ast/EnumExprAST.cc
/gem5/src/mem/slicc/ast/EnumExprAST.hh
/gem5/src/mem/slicc/ast/ExprAST.cc
/gem5/src/mem/slicc/ast/ExprAST.hh
/gem5/src/mem/slicc/ast/ExprStatementAST.cc
/gem5/src/mem/slicc/ast/ExprStatementAST.hh
/gem5/src/mem/slicc/ast/FormalParamAST.cc
/gem5/src/mem/slicc/ast/FormalParamAST.hh
/gem5/src/mem/slicc/ast/FuncCallExprAST.cc
/gem5/src/mem/slicc/ast/FuncCallExprAST.hh
/gem5/src/mem/slicc/ast/FuncDeclAST.cc
/gem5/src/mem/slicc/ast/FuncDeclAST.hh
/gem5/src/mem/slicc/ast/IfStatementAST.cc
/gem5/src/mem/slicc/ast/IfStatementAST.hh
/gem5/src/mem/slicc/ast/InPortDeclAST.cc
/gem5/src/mem/slicc/ast/InPortDeclAST.hh
/gem5/src/mem/slicc/ast/InfixOperatorExprAST.cc
/gem5/src/mem/slicc/ast/InfixOperatorExprAST.hh
/gem5/src/mem/slicc/ast/LiteralExprAST.cc
/gem5/src/mem/slicc/ast/LiteralExprAST.hh
/gem5/src/mem/slicc/ast/Location.cc
/gem5/src/mem/slicc/ast/Location.hh
/gem5/src/mem/slicc/ast/MachineAST.cc
/gem5/src/mem/slicc/ast/MachineAST.hh
/gem5/src/mem/slicc/ast/MemberExprAST.cc
/gem5/src/mem/slicc/ast/MemberExprAST.hh
/gem5/src/mem/slicc/ast/MethodCallExprAST.cc
/gem5/src/mem/slicc/ast/MethodCallExprAST.hh
/gem5/src/mem/slicc/ast/ObjDeclAST.cc
/gem5/src/mem/slicc/ast/ObjDeclAST.hh
/gem5/src/mem/slicc/ast/OutPortDeclAST.cc
/gem5/src/mem/slicc/ast/OutPortDeclAST.hh
/gem5/src/mem/slicc/ast/PairAST.cc
/gem5/src/mem/slicc/ast/PairAST.hh
/gem5/src/mem/slicc/ast/PairListAST.cc
/gem5/src/mem/slicc/ast/PairListAST.hh
/gem5/src/mem/slicc/ast/PeekStatementAST.cc
/gem5/src/mem/slicc/ast/PeekStatementAST.hh
/gem5/src/mem/slicc/ast/ReturnStatementAST.cc
/gem5/src/mem/slicc/ast/ReturnStatementAST.hh
/gem5/src/mem/slicc/ast/StatementAST.cc
/gem5/src/mem/slicc/ast/StatementAST.hh
/gem5/src/mem/slicc/ast/StatementListAST.cc
/gem5/src/mem/slicc/ast/StatementListAST.hh
/gem5/src/mem/slicc/ast/TransitionDeclAST.cc
/gem5/src/mem/slicc/ast/TransitionDeclAST.hh
/gem5/src/mem/slicc/ast/TypeAST.cc
/gem5/src/mem/slicc/ast/TypeAST.hh
/gem5/src/mem/slicc/ast/TypeDeclAST.cc
/gem5/src/mem/slicc/ast/TypeDeclAST.hh
/gem5/src/mem/slicc/ast/TypeFieldAST.cc
/gem5/src/mem/slicc/ast/TypeFieldAST.hh
/gem5/src/mem/slicc/ast/TypeFieldEnumAST.cc
/gem5/src/mem/slicc/ast/TypeFieldEnumAST.hh
/gem5/src/mem/slicc/ast/TypeFieldMemberAST.cc
/gem5/src/mem/slicc/ast/TypeFieldMemberAST.hh
/gem5/src/mem/slicc/ast/TypeFieldMethodAST.cc
/gem5/src/mem/slicc/ast/TypeFieldMethodAST.hh
/gem5/src/mem/slicc/ast/VarExprAST.cc
/gem5/src/mem/slicc/ast/VarExprAST.hh
/gem5/src/mem/slicc/generator/fileio.cc
/gem5/src/mem/slicc/generator/fileio.hh
/gem5/src/mem/slicc/generator/html_gen.cc
/gem5/src/mem/slicc/generator/html_gen.hh
/gem5/src/mem/slicc/generator/mif_gen.hh
/gem5/src/mem/slicc/main.hh
/gem5/src/mem/slicc/symbols/Func.cc
/gem5/src/mem/slicc/symbols/Func.hh
/gem5/src/mem/slicc/symbols/SymbolTable.hh
/gem5/src/mem/slicc/symbols/Transition.hh
/gem5/src/mem/slicc/symbols/Type.cc
/gem5/src/mem/slicc/symbols/Type.hh
/gem5/src/mem/slicc/symbols/Var.hh
6239:0c808c6d4481 10-Jun-2009 Nathan Binkert <nate@binkert.org>

copyright: I missed some copyrights during ruby integration

6221:58a3c04e6344 26-May-2009 Nathan Binkert <nate@binkert.org>

types: add a type for thread IDs and try to use it everywhere


/gem5/src/arch/alpha/miscregfile.cc
/gem5/src/arch/alpha/miscregfile.hh
/gem5/src/arch/mips/mt.hh
/gem5/src/arch/mips/regfile.cc
/gem5/src/arch/mips/regfile/float_regfile.cc
/gem5/src/arch/mips/regfile/float_regfile.hh
/gem5/src/arch/mips/regfile/misc_regfile.cc
/gem5/src/arch/mips/regfile/misc_regfile.hh
/gem5/src/arch/mips/regfile/regfile.cc
/gem5/src/arch/mips/regfile/regfile.hh
/gem5/src/base/types.hh
/gem5/src/cpu/base.cc
/gem5/src/cpu/base.hh
/gem5/src/cpu/base_dyn_inst.hh
/gem5/src/cpu/btb.cc
/gem5/src/cpu/inorder/cpu.cc
/gem5/src/cpu/inorder/cpu.hh
/gem5/src/cpu/inorder/first_stage.cc
/gem5/src/cpu/inorder/first_stage.hh
/gem5/src/cpu/inorder/inorder_cpu_builder.cc
/gem5/src/cpu/inorder/inorder_dyn_inst.cc
/gem5/src/cpu/inorder/inorder_dyn_inst.hh
/gem5/src/cpu/inorder/pipeline_stage.cc
/gem5/src/cpu/inorder/pipeline_stage.hh
/gem5/src/cpu/inorder/resource.cc
/gem5/src/cpu/inorder/resource.hh
/gem5/src/cpu/inorder/resource_pool.9stage.cc
/gem5/src/cpu/inorder/resource_pool.cc
/gem5/src/cpu/inorder/resource_pool.hh
/gem5/src/cpu/inorder/resources/agen_unit.cc
/gem5/src/cpu/inorder/resources/bpred_unit.cc
/gem5/src/cpu/inorder/resources/bpred_unit.hh
/gem5/src/cpu/inorder/resources/branch_predictor.cc
/gem5/src/cpu/inorder/resources/branch_predictor.hh
/gem5/src/cpu/inorder/resources/cache_unit.cc
/gem5/src/cpu/inorder/resources/cache_unit.hh
/gem5/src/cpu/inorder/resources/decode_unit.cc
/gem5/src/cpu/inorder/resources/decode_unit.hh
/gem5/src/cpu/inorder/resources/execution_unit.cc
/gem5/src/cpu/inorder/resources/fetch_seq_unit.cc
/gem5/src/cpu/inorder/resources/fetch_seq_unit.hh
/gem5/src/cpu/inorder/resources/graduation_unit.cc
/gem5/src/cpu/inorder/resources/inst_buffer.cc
/gem5/src/cpu/inorder/resources/inst_buffer.hh
/gem5/src/cpu/inorder/resources/inst_buffer_new.cc
/gem5/src/cpu/inorder/resources/inst_buffer_new.hh
/gem5/src/cpu/inorder/resources/mult_div_unit.cc
/gem5/src/cpu/inorder/resources/tlb_unit.cc
/gem5/src/cpu/inorder/resources/tlb_unit.hh
/gem5/src/cpu/inorder/resources/use_def.cc
/gem5/src/cpu/inorder/resources/use_def.hh
/gem5/src/cpu/inorder/thread_context.cc
/gem5/src/cpu/inorder/thread_context.hh
/gem5/src/cpu/inorder/thread_state.hh
/gem5/src/cpu/o3/bpred_unit.hh
/gem5/src/cpu/o3/bpred_unit_impl.hh
/gem5/src/cpu/o3/btb.hh
/gem5/src/cpu/o3/commit.hh
/gem5/src/cpu/o3/commit_impl.hh
/gem5/src/cpu/o3/cpu.cc
/gem5/src/cpu/o3/cpu.hh
/gem5/src/cpu/o3/cpu_builder.cc
/gem5/src/cpu/o3/decode.hh
/gem5/src/cpu/o3/decode_impl.hh
/gem5/src/cpu/o3/fetch.hh
/gem5/src/cpu/o3/fetch_impl.hh
/gem5/src/cpu/o3/free_list.cc
/gem5/src/cpu/o3/free_list.hh
/gem5/src/cpu/o3/iew.hh
/gem5/src/cpu/o3/iew_impl.hh
/gem5/src/cpu/o3/inst_queue.hh
/gem5/src/cpu/o3/inst_queue_impl.hh
/gem5/src/cpu/o3/lsq.hh
/gem5/src/cpu/o3/lsq_impl.hh
/gem5/src/cpu/o3/lsq_unit.hh
/gem5/src/cpu/o3/lsq_unit_impl.hh
/gem5/src/cpu/o3/mem_dep_unit.hh
/gem5/src/cpu/o3/mem_dep_unit_impl.hh
/gem5/src/cpu/o3/regfile.hh
/gem5/src/cpu/o3/rename.hh
/gem5/src/cpu/o3/rename_impl.hh
/gem5/src/cpu/o3/rob.hh
/gem5/src/cpu/o3/rob_impl.hh
/gem5/src/cpu/o3/store_set.cc
/gem5/src/cpu/o3/store_set.hh
/gem5/src/cpu/o3/thread_context_impl.hh
/gem5/src/cpu/ozone/back_end_impl.hh
/gem5/src/cpu/ozone/cpu_builder.cc
/gem5/src/cpu/ozone/inst_queue.hh
/gem5/src/cpu/ozone/inst_queue_impl.hh
/gem5/src/cpu/ozone/lw_back_end_impl.hh
/gem5/src/cpu/ozone/null_predictor.hh
/gem5/src/cpu/ozone/simple_cpu_builder.cc
/gem5/src/cpu/simple/atomic.cc
/gem5/src/cpu/simple/base.cc
/gem5/src/cpu/simple/base.hh
/gem5/src/cpu/simple/timing.cc
/gem5/src/cpu/simple_thread.hh
/gem5/src/cpu/smt.hh
/gem5/src/cpu/thread_context.hh
/gem5/src/cpu/thread_state.cc
/gem5/src/cpu/thread_state.hh
/gem5/src/mem/cache/mshr.cc
/gem5/src/mem/cache/mshr.hh
/gem5/src/mem/request.hh
system/CacheMemory.hh
/gem5/src/sim/system.hh
6216:2f4020838149 17-May-2009 Nathan Binkert <nate@binkert.org>

includes: sort includes again


/gem5/src/arch/alpha/isa_traits.hh
/gem5/src/arch/alpha/predecoder.hh
/gem5/src/arch/arm/utility.hh
/gem5/src/arch/mips/dsp.hh
/gem5/src/arch/mips/isa_traits.hh
/gem5/src/arch/mips/utility.hh
/gem5/src/arch/sparc/isa_traits.hh
/gem5/src/arch/sparc/predecoder.hh
/gem5/src/arch/sparc/regfile.hh
/gem5/src/arch/x86/bios/acpi.hh
/gem5/src/arch/x86/bios/e820.hh
/gem5/src/arch/x86/bios/intelmp.cc
/gem5/src/arch/x86/bios/smbios.cc
/gem5/src/arch/x86/bios/smbios.hh
/gem5/src/arch/x86/intmessage.hh
/gem5/src/arch/x86/miscregfile.hh
/gem5/src/arch/x86/pagetable.hh
/gem5/src/arch/x86/pagetable_walker.hh
/gem5/src/arch/x86/predecoder.cc
/gem5/src/arch/x86/regfile.hh
/gem5/src/arch/x86/utility.hh
/gem5/src/arch/x86/x86_traits.hh
/gem5/src/base/cp_annotate.hh
/gem5/src/base/crc.cc
/gem5/src/base/inet.cc
/gem5/src/base/inet.hh
/gem5/src/base/intmath.hh
/gem5/src/base/misc.cc
/gem5/src/base/pollevent.cc
/gem5/src/base/res_list.hh
/gem5/src/base/statistics.hh
/gem5/src/base/stats/mysql.cc
/gem5/src/base/stats/output.cc
/gem5/src/cpu/exetrace.hh
/gem5/src/cpu/inorder/comm.hh
/gem5/src/cpu/inorder/inorder_trace.hh
/gem5/src/cpu/inteltrace.hh
/gem5/src/cpu/legiontrace.hh
/gem5/src/cpu/nativetrace.hh
/gem5/src/cpu/o3/2bit_local_pred.hh
/gem5/src/cpu/o3/bpred_unit.hh
/gem5/src/cpu/o3/comm.hh
/gem5/src/cpu/o3/fetch_impl.hh
/gem5/src/cpu/o3/inst_queue.hh
/gem5/src/cpu/o3/ras.hh
/gem5/src/cpu/o3/store_set.hh
/gem5/src/cpu/o3/tournament_pred.hh
/gem5/src/cpu/ozone/ea_list.hh
/gem5/src/cpu/ozone/inst_queue.hh
/gem5/src/cpu/ozone/null_predictor.hh
/gem5/src/cpu/simple/base.cc
/gem5/src/cpu/simple_thread.hh
/gem5/src/cpu/static_inst.hh
/gem5/src/cpu/thread_context.hh
/gem5/src/dev/alpha/backdoor.hh
/gem5/src/dev/etherlink.hh
/gem5/src/dev/etherpkt.hh
/gem5/src/dev/intel_8254_timer.hh
/gem5/src/dev/mips/backdoor.hh
/gem5/src/dev/ns_gige.cc
/gem5/src/dev/sinic.cc
/gem5/src/dev/x86/intdev.hh
/gem5/src/dev/x86/south_bridge.cc
/gem5/src/kern/tru64/dump_mbuf.cc
/gem5/src/kern/tru64/mbuf.hh
/gem5/src/mem/bus.hh
/gem5/src/mem/cache/cache_impl.hh
/gem5/src/mem/cache/mshr.cc
/gem5/src/mem/cache/tags/fa_lru.cc
/gem5/src/mem/cache/tags/fa_lru.hh
/gem5/src/mem/cache/tags/iic_repl/gen.cc
/gem5/src/mem/cache/tags/iic_repl/repl.hh
/gem5/src/mem/cache/tags/lru.hh
/gem5/src/mem/gems_common/util.cc
/gem5/src/mem/packet.hh
/gem5/src/mem/page_table.hh
/gem5/src/mem/physical.cc
common/Debug.hh
common/Global.hh
network/orion/power_ll.cc
network/orion/power_utils.cc
/gem5/src/mem/rubymem.cc
/gem5/src/mem/slicc/slicc_global.hh
/gem5/src/python/swig/core.i
/gem5/src/python/swig/event.i
/gem5/src/python/swig/pyobject.hh
/gem5/src/python/swig/sim_object.i
/gem5/src/sim/arguments.hh
/gem5/src/sim/eventq.hh
/gem5/src/sim/init.cc
/gem5/src/sim/insttracer.hh
/gem5/src/sim/sim_object.cc
/gem5/src/sim/simulate.cc
/gem5/src/sim/syscall_emul.hh
/gem5/src/unittest/rangemaptest.cc
/gem5/src/unittest/rangemultimaptest.cc
/gem5/util/statetrace/arch/tracechild_amd64.hh
/gem5/util/statetrace/arch/tracechild_i386.hh
/gem5/util/statetrace/arch/tracechild_sparc.hh
6205:39a0b4026bda 13-May-2009 Nathan Binkert <nate@binkert.org>

ruby: deal with printf warnings and convert some to cprintf

6204:b247610d8882 13-May-2009 Nathan Binkert <nate@binkert.org>

ruby: remove random uint typedef and use unsigned

6173:5a809dcfed1e 11-May-2009 Nathan Binkert <nate@binkert.org>

ruby: assert(false) should be panic.
This also fixes some compiler warnings

6168:ba6fe02228db 11-May-2009 Nathan Binkert <nate@binkert.org>

ruby: add RUBY sticky option that must be set to add ruby to the build
Default is false

6165:2d26c346f1be 11-May-2009 Daniel Sanchez <sanchezd@stanford.edu>

ruby: Working M5 interface and updated Ruby interface.
This changeset also includes a lot of work from Derek Hower <drh5@cs.wisc.edu>

RubyMemory is now both a driver for Ruby and a port for M5. Changed
makeRequest/hitCallback interface. Brought packets (superficially)
into the sequencer. Modified tester infrastructure to be packet based.
and Ruby can be used together through the example ruby_se.py
script. SPARC parallel applications work, and the timing *seems* right
from combined M5/Ruby debug traces. To run,
% build/ALPHA_SE/m5.debug configs/example/ruby_se.py -c
tests/test-progs/hello/bin/alpha/linux/hello -n 4 -t

6164:29b7b7aba911 11-May-2009 Steve Reinhardt <steve.reinhardt@amd.com>

ruby: Check stderr and not stdin before hanging on an assert.

6163:92318648212f 11-May-2009 Polina Dudnik <pdudnik@gmail.com>

ruby: decommission code

1. Set.* and BigSet.* are replaced with OptBigSet.* which was renamed Set.*
2. Decomissioned all bloom filters
3. Decomissioned ruby/simics directory

6162:cbd6debc4fd0 11-May-2009 Derek Hower <drh5@cs.wisc.edu>

ruby: removed dead functions from the sequencer

6161:8ad9be15d1e1 11-May-2009 Polina Dudnik <pdudnik@gmail.com>

ruby: Removed g_SIMULATING flag
1. removed checks from tester files
2. removed else clause in Sequencer and DirectoryMemory else clause is
needed by the tester, it is up to Derek to revive it elsewhere when he
gets to it

Also:
1. Changed m_entries in DirectoryMemory to a map
2. And replaced SIMICS_read_physical_memory with a call to now-dummy
Derek's-to-be readPhysMem function

6160:91e31308be1e 11-May-2009 Polina Dudnik <pdudnik@gmail.com>

ruby: Remove transactional access types (e.g. LD_XACT) from CacheRequestType

1. Modified enumeration
2. Also modified profiler
3. Remove transactions from Tester
4. Edited XACT_MEM out of Synthetic Driver

6159:25181e8dd68e 11-May-2009 Polina Dudnik <pdudnik@gmail.com>

ruby: reordered Debug and RubyConfig::init to fix segfault
due to uninitialized output file pointer.

6158:5e0a261d57b8 11-May-2009 Dan Gibson <gibson@cs.wisc.edu>

ruby: Disabled RubyEventQueue's deletion of its home-grown priority heap.
Temporarily to fix unusual memory problem.

6157:eaf2fd8f54c0 11-May-2009 Nathan Binkert <nate@binkert.org>

ruby: Migrate all of ruby and slicc to SCons.
Add the PROTOCOL sticky option sets the coherence protocol that slicc
will parse and therefore ruby will use. This whole process was made
difficult by the fact that the set of files that are output by slicc
are not easily known ahead of time. The easiest thing wound up being
to write a parser for slicc that would tell me. Incidentally this
means we now have a slicc grammar written in python.

6156:76de2027b8ad 11-May-2009 Nathan Binkert <nate@binkert.org>

ruby: clean up a few warnings

6155:2b8fec056712 11-May-2009 Dan Gibson <gibson@cs.wisc.edu>

ruby: Fixed some unresolved references.

6154:6bb54dcb940e 11-May-2009 Nathan Binkert <nate@binkert.org>

ruby: Make ruby #includes use full paths to the files they're including.
This basically means changing all #include statements and changing
autogenerated code so that it generates the correct paths. Because
slicc generates #includes, I had to hard code the include paths to
mem/protocol.


/gem5/src/mem/gems_common/Allocator.hh
/gem5/src/mem/gems_common/Map.hh
/gem5/src/mem/gems_common/PrioHeap.hh
/gem5/src/mem/gems_common/RefCnt_tester.cc
/gem5/src/mem/gems_common/RefCountable.hh
/gem5/src/mem/gems_common/Vector.hh
/gem5/src/mem/gems_common/ioutil/attrlex.ll
/gem5/src/mem/gems_common/ioutil/attrparse.yy
/gem5/src/mem/gems_common/ioutil/confio.cc
/gem5/src/mem/gems_common/ioutil/confio.hh
/gem5/src/mem/gems_common/ioutil/initvar.cc
/gem5/src/mem/gems_common/ioutil/vardecl.hh
/gem5/src/mem/gems_common/util.cc
/gem5/src/mem/gems_common/util.hh
buffers/MessageBuffer.cc
buffers/MessageBuffer.hh
buffers/MessageBufferNode.cc
buffers/MessageBufferNode.hh
common/Address.cc
common/Address.hh
common/BigSet.cc
common/BigSet.hh
common/Consumer.hh
common/DataBlock.cc
common/DataBlock.hh
common/Debug.cc
common/Driver.cc
common/Driver.hh
common/Global.cc
common/Global.hh
common/Histogram.cc
common/Histogram.hh
common/Message.cc
common/NetDest.cc
common/NetDest.hh
common/OptBigSet.cc
common/OptBigSet.hh
common/Set.cc
common/Set.hh
common/SubBlock.cc
common/SubBlock.hh
config/RubyConfig.cc
config/RubyConfig.hh
eventqueue/RubyEventQueue.cc
eventqueue/RubyEventQueue.hh
eventqueue/RubyEventQueueNode.cc
eventqueue/RubyEventQueueNode.hh
init.cc
network/Network.hh
network/garnet-fixed-pipeline/CreditLink_d.hh
network/garnet-fixed-pipeline/GarnetNetwork_d.cc
network/garnet-fixed-pipeline/GarnetNetwork_d.hh
network/garnet-fixed-pipeline/InputUnit_d.cc
network/garnet-fixed-pipeline/InputUnit_d.hh
network/garnet-fixed-pipeline/NetworkHeader.hh
network/garnet-fixed-pipeline/NetworkInterface_d.cc
network/garnet-fixed-pipeline/NetworkInterface_d.hh
network/garnet-fixed-pipeline/NetworkLink_d.cc
network/garnet-fixed-pipeline/NetworkLink_d.hh
network/garnet-fixed-pipeline/OutVcState_d.cc
network/garnet-fixed-pipeline/OutVcState_d.hh
network/garnet-fixed-pipeline/OutputUnit_d.cc
network/garnet-fixed-pipeline/OutputUnit_d.hh
network/garnet-fixed-pipeline/Router_d.cc
network/garnet-fixed-pipeline/Router_d.hh
network/garnet-fixed-pipeline/RoutingUnit_d.cc
network/garnet-fixed-pipeline/RoutingUnit_d.hh
network/garnet-fixed-pipeline/SWallocator_d.cc
network/garnet-fixed-pipeline/SWallocator_d.hh
network/garnet-fixed-pipeline/Switch_d.cc
network/garnet-fixed-pipeline/Switch_d.hh
network/garnet-fixed-pipeline/VCallocator_d.cc
network/garnet-fixed-pipeline/VCallocator_d.hh
network/garnet-fixed-pipeline/VirtualChannel_d.cc
network/garnet-fixed-pipeline/VirtualChannel_d.hh
network/garnet-fixed-pipeline/flitBuffer_d.cc
network/garnet-fixed-pipeline/flitBuffer_d.hh
network/garnet-fixed-pipeline/flit_d.cc
network/garnet-fixed-pipeline/flit_d.hh
network/garnet-flexible-pipeline/FlexibleConsumer.hh
network/garnet-flexible-pipeline/GarnetNetwork.cc
network/garnet-flexible-pipeline/GarnetNetwork.hh
network/garnet-flexible-pipeline/InVcState.cc
network/garnet-flexible-pipeline/InVcState.hh
network/garnet-flexible-pipeline/NetworkConfig.hh
network/garnet-flexible-pipeline/NetworkInterface.cc
network/garnet-flexible-pipeline/NetworkInterface.hh
network/garnet-flexible-pipeline/NetworkLink.cc
network/garnet-flexible-pipeline/NetworkLink.hh
network/garnet-flexible-pipeline/OutVcState.cc
network/garnet-flexible-pipeline/OutVcState.hh
network/garnet-flexible-pipeline/Router.cc
network/garnet-flexible-pipeline/Router.hh
network/garnet-flexible-pipeline/VCarbiter.cc
network/garnet-flexible-pipeline/VCarbiter.hh
network/garnet-flexible-pipeline/flit.cc
network/garnet-flexible-pipeline/flit.hh
network/garnet-flexible-pipeline/flitBuffer.cc
network/garnet-flexible-pipeline/flitBuffer.hh
network/orion/NetworkPower.cc
network/orion/SIM_power.hh
network/orion/power_arbiter.cc
network/orion/power_arbiter.hh
network/orion/power_array.cc
network/orion/power_bus.cc
network/orion/power_crossbar.cc
network/orion/power_ll.cc
network/orion/power_router_init.cc
network/orion/power_router_init.hh
network/orion/power_static.cc
network/orion/power_static.hh
network/orion/power_utils.cc
network/simple/PerfectSwitch.cc
network/simple/PerfectSwitch.hh
network/simple/SimpleNetwork.cc
network/simple/SimpleNetwork.hh
network/simple/Switch.cc
network/simple/Switch.hh
network/simple/Throttle.cc
network/simple/Throttle.hh
network/simple/Topology.cc
network/simple/Topology.hh
profiler/AccessTraceForAddress.cc
profiler/AccessTraceForAddress.hh
profiler/AddressProfiler.cc
profiler/AddressProfiler.hh
profiler/CacheProfiler.cc
profiler/CacheProfiler.hh
profiler/Profiler.cc
profiler/Profiler.hh
profiler/StoreTrace.cc
profiler/StoreTrace.hh
profiler/XactProfiler.cc
profiler/XactProfiler.hh
recorder/CacheRecorder.cc
recorder/CacheRecorder.hh
recorder/TraceRecord.cc
recorder/TraceRecord.hh
recorder/Tracer.cc
recorder/Tracer.hh
slicc_interface/AbstractCacheEntry.cc
slicc_interface/AbstractCacheEntry.hh
slicc_interface/AbstractChip.cc
slicc_interface/AbstractChip.hh
slicc_interface/Message.hh
slicc_interface/NetworkMessage.hh
slicc_interface/RubySlicc_ComponentMapping.hh
slicc_interface/RubySlicc_Profiler_interface.cc
slicc_interface/RubySlicc_Profiler_interface.hh
slicc_interface/RubySlicc_Util.hh
slicc_interface/RubySlicc_includes.hh
system/AbstractBloomFilter.hh
system/AbstractMemOrCache.hh
system/AbstractReplacementPolicy.hh
system/BlockBloomFilter.cc
system/BlockBloomFilter.hh
system/BulkBloomFilter.cc
system/BulkBloomFilter.hh
system/CacheMemory.hh
system/DirectoryMemory.cc
system/DirectoryMemory.hh
system/GenericBloomFilter.cc
system/GenericBloomFilter.hh
system/H3BloomFilter.cc
system/H3BloomFilter.hh
system/LRUPolicy.hh
system/LSB_CountingBloomFilter.cc
system/LSB_CountingBloomFilter.hh
system/MachineID.hh
system/MemoryControl.cc
system/MemoryControl.hh
system/MemoryNode.cc
system/MemoryNode.hh
system/MultiBitSelBloomFilter.cc
system/MultiBitSelBloomFilter.hh
system/MultiGrainBloomFilter.cc
system/MultiGrainBloomFilter.hh
system/NodeID.hh
system/NodePersistentTable.cc
system/NodePersistentTable.hh
system/NonCountingBloomFilter.cc
system/NonCountingBloomFilter.hh
system/PerfectCacheMemory.hh
system/PersistentArbiter.cc
system/PersistentArbiter.hh
system/PersistentTable.cc
system/PersistentTable.hh
system/PseudoLRUPolicy.hh
system/Sequencer.cc
system/Sequencer.hh
system/StoreBuffer.cc
system/StoreBuffer.hh
system/StoreCache.cc
system/StoreCache.hh
system/System.cc
system/System.hh
system/TBETable.hh
system/TimerTable.cc
system/TimerTable.hh
tester/BarrierGenerator.cc
tester/BarrierGenerator.hh
tester/Check.cc
tester/Check.hh
tester/CheckTable.cc
tester/CheckTable.hh
tester/DetermGETXGenerator.cc
tester/DetermGETXGenerator.hh
tester/DetermInvGenerator.cc
tester/DetermInvGenerator.hh
tester/DetermSeriesGETSGenerator.cc
tester/DetermSeriesGETSGenerator.hh
tester/DeterministicDriver.cc
tester/DeterministicDriver.hh
tester/Instruction.cc
tester/Instruction.hh
tester/RaceyDriver.cc
tester/RaceyDriver.hh
tester/RequestGenerator.cc
tester/RequestGenerator.hh
tester/SpecifiedGenerator.cc
tester/SpecifiedGenerator.hh
tester/SyntheticDriver.cc
tester/SyntheticDriver.hh
tester/Tester.cc
tester/Tester.hh
tester/XactAbortRequestGenerator.cc
tester/XactAbortRequestGenerator.hh
tester/XactRequestGenerator.cc
tester/XactRequestGenerator.hh
tester/main.cc
tester/main.hh
tester/test_framework.cc
tester/test_framework.hh
/gem5/src/mem/slicc/ast/AST.cc
/gem5/src/mem/slicc/ast/AST.hh
/gem5/src/mem/slicc/ast/ASTs.hh
/gem5/src/mem/slicc/ast/ActionDeclAST.cc
/gem5/src/mem/slicc/ast/ActionDeclAST.hh
/gem5/src/mem/slicc/ast/AssignStatementAST.cc
/gem5/src/mem/slicc/ast/AssignStatementAST.hh
/gem5/src/mem/slicc/ast/CheckAllocateStatementAST.cc
/gem5/src/mem/slicc/ast/CheckAllocateStatementAST.hh
/gem5/src/mem/slicc/ast/CheckStopSlotsStatementAST.cc
/gem5/src/mem/slicc/ast/CheckStopSlotsStatementAST.hh
/gem5/src/mem/slicc/ast/ChipComponentAccessAST.cc
/gem5/src/mem/slicc/ast/ChipComponentAccessAST.hh
/gem5/src/mem/slicc/ast/CopyHeadStatementAST.cc
/gem5/src/mem/slicc/ast/CopyHeadStatementAST.hh
/gem5/src/mem/slicc/ast/DeclAST.cc
/gem5/src/mem/slicc/ast/DeclAST.hh
/gem5/src/mem/slicc/ast/DeclListAST.cc
/gem5/src/mem/slicc/ast/DeclListAST.hh
/gem5/src/mem/slicc/ast/EnqueueStatementAST.cc
/gem5/src/mem/slicc/ast/EnqueueStatementAST.hh
/gem5/src/mem/slicc/ast/EnumDeclAST.cc
/gem5/src/mem/slicc/ast/EnumDeclAST.hh
/gem5/src/mem/slicc/ast/EnumExprAST.cc
/gem5/src/mem/slicc/ast/EnumExprAST.hh
/gem5/src/mem/slicc/ast/ExprAST.cc
/gem5/src/mem/slicc/ast/ExprAST.hh
/gem5/src/mem/slicc/ast/ExprStatementAST.cc
/gem5/src/mem/slicc/ast/ExprStatementAST.hh
/gem5/src/mem/slicc/ast/FormalParamAST.cc
/gem5/src/mem/slicc/ast/FormalParamAST.hh
/gem5/src/mem/slicc/ast/FuncCallExprAST.cc
/gem5/src/mem/slicc/ast/FuncCallExprAST.hh
/gem5/src/mem/slicc/ast/FuncDeclAST.cc
/gem5/src/mem/slicc/ast/FuncDeclAST.hh
/gem5/src/mem/slicc/ast/IfStatementAST.cc
/gem5/src/mem/slicc/ast/IfStatementAST.hh
/gem5/src/mem/slicc/ast/InPortDeclAST.cc
/gem5/src/mem/slicc/ast/InPortDeclAST.hh
/gem5/src/mem/slicc/ast/InfixOperatorExprAST.cc
/gem5/src/mem/slicc/ast/InfixOperatorExprAST.hh
/gem5/src/mem/slicc/ast/LiteralExprAST.cc
/gem5/src/mem/slicc/ast/LiteralExprAST.hh
/gem5/src/mem/slicc/ast/Location.cc
/gem5/src/mem/slicc/ast/Location.hh
/gem5/src/mem/slicc/ast/MachineAST.cc
/gem5/src/mem/slicc/ast/MachineAST.hh
/gem5/src/mem/slicc/ast/MemberExprAST.cc
/gem5/src/mem/slicc/ast/MemberExprAST.hh
/gem5/src/mem/slicc/ast/MethodCallExprAST.cc
/gem5/src/mem/slicc/ast/MethodCallExprAST.hh
/gem5/src/mem/slicc/ast/ObjDeclAST.cc
/gem5/src/mem/slicc/ast/ObjDeclAST.hh
/gem5/src/mem/slicc/ast/OutPortDeclAST.cc
/gem5/src/mem/slicc/ast/OutPortDeclAST.hh
/gem5/src/mem/slicc/ast/PairAST.cc
/gem5/src/mem/slicc/ast/PairAST.hh
/gem5/src/mem/slicc/ast/PairListAST.cc
/gem5/src/mem/slicc/ast/PairListAST.hh
/gem5/src/mem/slicc/ast/PeekStatementAST.cc
/gem5/src/mem/slicc/ast/PeekStatementAST.hh
/gem5/src/mem/slicc/ast/ReturnStatementAST.cc
/gem5/src/mem/slicc/ast/ReturnStatementAST.hh
/gem5/src/mem/slicc/ast/StatementAST.cc
/gem5/src/mem/slicc/ast/StatementAST.hh
/gem5/src/mem/slicc/ast/StatementListAST.cc
/gem5/src/mem/slicc/ast/StatementListAST.hh
/gem5/src/mem/slicc/ast/TransitionDeclAST.cc
/gem5/src/mem/slicc/ast/TransitionDeclAST.hh
/gem5/src/mem/slicc/ast/TypeAST.cc
/gem5/src/mem/slicc/ast/TypeAST.hh
/gem5/src/mem/slicc/ast/TypeDeclAST.cc
/gem5/src/mem/slicc/ast/TypeDeclAST.hh
/gem5/src/mem/slicc/ast/TypeFieldAST.cc
/gem5/src/mem/slicc/ast/TypeFieldAST.hh
/gem5/src/mem/slicc/ast/TypeFieldEnumAST.cc
/gem5/src/mem/slicc/ast/TypeFieldEnumAST.hh
/gem5/src/mem/slicc/ast/TypeFieldMemberAST.cc
/gem5/src/mem/slicc/ast/TypeFieldMemberAST.hh
/gem5/src/mem/slicc/ast/TypeFieldMethodAST.cc
/gem5/src/mem/slicc/ast/TypeFieldMethodAST.hh
/gem5/src/mem/slicc/ast/VarExprAST.cc
/gem5/src/mem/slicc/ast/VarExprAST.hh
/gem5/src/mem/slicc/generator/fileio.cc
/gem5/src/mem/slicc/generator/fileio.hh
/gem5/src/mem/slicc/generator/html_gen.cc
/gem5/src/mem/slicc/generator/html_gen.hh
/gem5/src/mem/slicc/generator/mif_gen.cc
/gem5/src/mem/slicc/generator/mif_gen.hh
/gem5/src/mem/slicc/main.cc
/gem5/src/mem/slicc/main.hh
/gem5/src/mem/slicc/parser/lexer.ll
/gem5/src/mem/slicc/parser/parser.yy
/gem5/src/mem/slicc/slicc_global.hh
/gem5/src/mem/slicc/symbols/Action.hh
/gem5/src/mem/slicc/symbols/Event.hh
/gem5/src/mem/slicc/symbols/Func.cc
/gem5/src/mem/slicc/symbols/Func.hh
/gem5/src/mem/slicc/symbols/State.hh
/gem5/src/mem/slicc/symbols/StateMachine.cc
/gem5/src/mem/slicc/symbols/StateMachine.hh
/gem5/src/mem/slicc/symbols/Symbol.cc
/gem5/src/mem/slicc/symbols/Symbol.hh
/gem5/src/mem/slicc/symbols/SymbolTable.cc
/gem5/src/mem/slicc/symbols/SymbolTable.hh
/gem5/src/mem/slicc/symbols/Transition.cc
/gem5/src/mem/slicc/symbols/Transition.hh
/gem5/src/mem/slicc/symbols/Type.cc
/gem5/src/mem/slicc/symbols/Type.hh
/gem5/src/mem/slicc/symbols/Var.cc
/gem5/src/mem/slicc/symbols/Var.hh
6153:0011560d49b0 11-May-2009 Dan Gibson <gibson@cs.wisc.edu>

ruby: remove unnecessary code.

1) Removing files from the ruby build left some unresovled
symbols. Those have been fixed.

2) Most of the dependencies on Simics data types and the simics
interface files have been removed.

3) Almost all mention of opal is gone.

4) Huge chunks of LogTM are now gone.

5) Handling 1-4 left ~hundreds of unresolved references, which were
fixed, yielding a snowball effect (and the massive size of this
delta).

6152:705b277e1141 11-May-2009 Derek Hower <drh5@cs.wisc.edu>

ruby: Cleaned up sequencer. Removed LogTM specific code.

6151:bc6b84108443 11-May-2009 Derek Hower <drh5@cs.wisc.edu>

ruby: added Packet interface to makeRequest and isReady.
Also pushed Packet usage into the Sequencer

6150:a2ebddfe1a37 11-May-2009 Nathan Binkert <nate@binkert.org>

ruby: fold the debugging options into Debug.cc

6149:ff34514cbf37 11-May-2009 Derek Hower <drh5@cs.wisc.edu>

ruby: Renamed Ruby's EventQueue to RubyEventQueue

6148:71a683318799 11-May-2009 Daniel Sanchez <sanchezd@stanford.edu>

ruby: Removed System name clash by renaming ruby's System to RubySystem

6147:e9a8bb75c3a8 11-May-2009 Nathan Binkert <nate@binkert.org>

ruby: rename config.include to config.hh and clean up the macro stuff.
I did the macro cleanup because I was worried that the SCons scanner
would get confused. This code will hopefully go away soon anyway.

6146:0390b60a0b51 11-May-2009 Nathan Binkert <nate@binkert.org>

ruby: strip out some unused defines

6145:15cca6ab723a 11-May-2009 Nathan Binkert <nate@binkert.org>

ruby: Import ruby and slicc from GEMS

We eventually plan to replace the m5 cache hierarchy with the GEMS
hierarchy, but for now we will make both live alongside eachother.


/gem5/src/mem/gems_common/Allocator.hh
/gem5/src/mem/gems_common/Map.hh
/gem5/src/mem/gems_common/PrioHeap.hh
/gem5/src/mem/gems_common/RefCnt.hh
/gem5/src/mem/gems_common/RefCnt_tester.cc
/gem5/src/mem/gems_common/RefCountable.hh
/gem5/src/mem/gems_common/Vector.hh
/gem5/src/mem/gems_common/calc_host.sh
/gem5/src/mem/gems_common/ioutil/attrlex.ll
/gem5/src/mem/gems_common/ioutil/attrparse.yy
/gem5/src/mem/gems_common/ioutil/confio.cc
/gem5/src/mem/gems_common/ioutil/confio.hh
/gem5/src/mem/gems_common/ioutil/embedtext.py
/gem5/src/mem/gems_common/ioutil/initvar.cc
/gem5/src/mem/gems_common/ioutil/initvar.hh
/gem5/src/mem/gems_common/ioutil/vardecl.hh
/gem5/src/mem/gems_common/std-includes.hh
/gem5/src/mem/gems_common/util.cc
/gem5/src/mem/gems_common/util.hh
/gem5/src/mem/protocol/LogTM.sm
/gem5/src/mem/protocol/MESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-mem.sm
/gem5/src/mem/protocol/MESI_CMP_directory-msg.sm
/gem5/src/mem/protocol/MESI_CMP_directory.slicc
/gem5/src/mem/protocol/MESI_CMP_filter_directory-L1cache.sm
/gem5/src/mem/protocol/MESI_CMP_filter_directory-L2cache.sm
/gem5/src/mem/protocol/MESI_CMP_filter_directory-mem.sm
/gem5/src/mem/protocol/MESI_CMP_filter_directory-msg.sm
/gem5/src/mem/protocol/MESI_CMP_filter_directory.slicc
/gem5/src/mem/protocol/MESI_CMP_filter_directory_m-mem.sm
/gem5/src/mem/protocol/MESI_CMP_filter_directory_m.slicc
/gem5/src/mem/protocol/MESI_SCMP_bankdirectory-L1cache.sm
/gem5/src/mem/protocol/MESI_SCMP_bankdirectory-L2cache.sm
/gem5/src/mem/protocol/MESI_SCMP_bankdirectory-mem.sm
/gem5/src/mem/protocol/MESI_SCMP_bankdirectory-msg.sm
/gem5/src/mem/protocol/MESI_SCMP_bankdirectory.slicc
/gem5/src/mem/protocol/MESI_SCMP_bankdirectory_m-mem.sm
/gem5/src/mem/protocol/MESI_SCMP_bankdirectory_m.slicc
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MI_example-msg.sm
/gem5/src/mem/protocol/MI_example.slicc
/gem5/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-msg.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-perfectDir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory.slicc
/gem5/src/mem/protocol/MOESI_CMP_directory_m-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory_m.slicc
/gem5/src/mem/protocol/MOESI_CMP_token-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_token-msg.sm
/gem5/src/mem/protocol/MOESI_CMP_token.slicc
/gem5/src/mem/protocol/MOESI_SMP_directory-cache.sm
/gem5/src/mem/protocol/MOESI_SMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_SMP_directory-msg.sm
/gem5/src/mem/protocol/MOESI_SMP_directory.slicc
/gem5/src/mem/protocol/MOESI_SMP_token-cache.sm
/gem5/src/mem/protocol/MOESI_SMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_SMP_token-msg.sm
/gem5/src/mem/protocol/MOESI_SMP_token.slicc
/gem5/src/mem/protocol/MOSI_SMP_bcast-cache.sm
/gem5/src/mem/protocol/MOSI_SMP_bcast-dir.sm
/gem5/src/mem/protocol/MOSI_SMP_bcast-msg.sm
/gem5/src/mem/protocol/MOSI_SMP_bcast.slicc
/gem5/src/mem/protocol/MOSI_SMP_bcast_1level-cache.sm
/gem5/src/mem/protocol/MOSI_SMP_bcast_1level.slicc
/gem5/src/mem/protocol/MOSI_SMP_bcast_m-dir.sm
/gem5/src/mem/protocol/MOSI_SMP_bcast_m.slicc
/gem5/src/mem/protocol/MOSI_SMP_directory_1level-cache.sm
/gem5/src/mem/protocol/MOSI_SMP_directory_1level-dir.sm
/gem5/src/mem/protocol/MOSI_SMP_directory_1level-msg.sm
/gem5/src/mem/protocol/MOSI_SMP_directory_1level.slicc
/gem5/src/mem/protocol/MSI_MOSI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MSI_MOSI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MSI_MOSI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MSI_MOSI_CMP_directory-msg.sm
/gem5/src/mem/protocol/MSI_MOSI_CMP_directory.slicc
/gem5/src/mem/protocol/RubySlicc_ComponentMapping.sm
/gem5/src/mem/protocol/RubySlicc_Defines.sm
/gem5/src/mem/protocol/RubySlicc_Exports.sm
/gem5/src/mem/protocol/RubySlicc_MemControl.sm
/gem5/src/mem/protocol/RubySlicc_Profiler.sm
/gem5/src/mem/protocol/RubySlicc_Types.sm
/gem5/src/mem/protocol/RubySlicc_Util.sm
/gem5/src/mem/protocol/RubySlicc_interfaces.slicc
/gem5/src/mem/protocol/doc/MSI_MOSI_CMP_directory_2level-protocol-description.txt
/gem5/src/mem/protocol/doc/MSI_dir_L1_MOSI_dir_L2_SNUCA_CMP-protocol-description.txt
/gem5/src/mem/protocol/standard_1level_SMP-protocol.sm
/gem5/src/mem/protocol/standard_CMP-protocol.sm
/gem5/src/mem/protocol/standard_SMP-protocol.sm
Decomissioning_note
FakeSimicsDataTypes.hh
README.debugging
buffers/MessageBuffer.cc
buffers/MessageBuffer.hh
buffers/MessageBufferNode.cc
buffers/MessageBufferNode.hh
common/Address.cc
common/Address.hh
common/BigSet.cc
common/BigSet.hh
common/Consumer.hh
common/DataBlock.cc
common/DataBlock.hh
common/Debug.cc
common/Debug.def
common/Debug.hh
common/Driver.cc
common/Driver.hh
common/Global.cc
common/Global.hh
common/Histogram.cc
common/Histogram.hh
common/Message.cc
common/NetDest.cc
common/NetDest.hh
common/OptBigSet.cc
common/OptBigSet.hh
common/Set.cc
common/Set.hh
common/SubBlock.cc
common/SubBlock.hh
config/RubyConfig.cc
config/RubyConfig.hh
config/config.include
config/rubyconfig.defaults
config/tester.defaults
eventqueue/EventQueue.cc
eventqueue/EventQueue.hh
eventqueue/EventQueueNode.cc
eventqueue/EventQueueNode.hh
eventqueue/EventQueue_tester.cc
init.cc
init.hh
interfaces/OpalInterface.cc
interfaces/OpalInterface.hh
interfaces/mf_api.hh
network/Network.hh
network/garnet-fixed-pipeline/CreditLink_d.hh
network/garnet-fixed-pipeline/GarnetNetwork_d.cc
network/garnet-fixed-pipeline/GarnetNetwork_d.hh
network/garnet-fixed-pipeline/InputUnit_d.cc
network/garnet-fixed-pipeline/InputUnit_d.hh
network/garnet-fixed-pipeline/NetworkHeader.hh
network/garnet-fixed-pipeline/NetworkInterface_d.cc
network/garnet-fixed-pipeline/NetworkInterface_d.hh
network/garnet-fixed-pipeline/NetworkLink_d.cc
network/garnet-fixed-pipeline/NetworkLink_d.hh
network/garnet-fixed-pipeline/OutVcState_d.cc
network/garnet-fixed-pipeline/OutVcState_d.hh
network/garnet-fixed-pipeline/OutputUnit_d.cc
network/garnet-fixed-pipeline/OutputUnit_d.hh
network/garnet-fixed-pipeline/Router_d.cc
network/garnet-fixed-pipeline/Router_d.hh
network/garnet-fixed-pipeline/RoutingUnit_d.cc
network/garnet-fixed-pipeline/RoutingUnit_d.hh
network/garnet-fixed-pipeline/SWallocator_d.cc
network/garnet-fixed-pipeline/SWallocator_d.hh
network/garnet-fixed-pipeline/Switch_d.cc
network/garnet-fixed-pipeline/Switch_d.hh
network/garnet-fixed-pipeline/VCallocator_d.cc
network/garnet-fixed-pipeline/VCallocator_d.hh
network/garnet-fixed-pipeline/VirtualChannel_d.cc
network/garnet-fixed-pipeline/VirtualChannel_d.hh
network/garnet-fixed-pipeline/flitBuffer_d.cc
network/garnet-fixed-pipeline/flitBuffer_d.hh
network/garnet-fixed-pipeline/flit_d.cc
network/garnet-fixed-pipeline/flit_d.hh
network/garnet-flexible-pipeline/FlexibleConsumer.hh
network/garnet-flexible-pipeline/GarnetNetwork.cc
network/garnet-flexible-pipeline/GarnetNetwork.hh
network/garnet-flexible-pipeline/InVcState.cc
network/garnet-flexible-pipeline/InVcState.hh
network/garnet-flexible-pipeline/NetworkConfig.hh
network/garnet-flexible-pipeline/NetworkInterface.cc
network/garnet-flexible-pipeline/NetworkInterface.hh
network/garnet-flexible-pipeline/NetworkLink.cc
network/garnet-flexible-pipeline/NetworkLink.hh
network/garnet-flexible-pipeline/OutVcState.cc
network/garnet-flexible-pipeline/OutVcState.hh
network/garnet-flexible-pipeline/Router.cc
network/garnet-flexible-pipeline/Router.hh
network/garnet-flexible-pipeline/VCarbiter.cc
network/garnet-flexible-pipeline/VCarbiter.hh
network/garnet-flexible-pipeline/flit.cc
network/garnet-flexible-pipeline/flit.hh
network/garnet-flexible-pipeline/flitBuffer.cc
network/garnet-flexible-pipeline/flitBuffer.hh
network/garnet-flexible-pipeline/netconfig.defaults
network/orion/NetworkPower.cc
network/orion/NetworkPower.hh
network/orion/SIM_port.hh
network/orion/SIM_power.hh
network/orion/SIM_power_test.hh
network/orion/parm_technology.hh
network/orion/power_arbiter.cc
network/orion/power_arbiter.hh
network/orion/power_array.cc
network/orion/power_array.hh
network/orion/power_bus.cc
network/orion/power_bus.hh
network/orion/power_crossbar.cc
network/orion/power_crossbar.hh
network/orion/power_ll.cc
network/orion/power_ll.hh
network/orion/power_router_init.cc
network/orion/power_router_init.hh
network/orion/power_static.cc
network/orion/power_static.hh
network/orion/power_utils.cc
network/orion/power_utils.hh
network/simple/Network_Files/GarnetFileMaker.py
network/simple/Network_Files/NUCA_Procs-16_ProcsPerChip-16_L2Banks-16_Memories-16.txt
network/simple/Network_Files/NUCA_Procs-16_ProcsPerChip-16_L2Banks-16_Memories-4.txt
network/simple/Network_Files/NUCA_Procs-16_ProcsPerChip-16_L2Banks-16_Memories-8.txt
network/simple/Network_Files/NUCA_Procs-16_ProcsPerChip-1_L2Banks-16_Memories-16.txt
network/simple/Network_Files/NUCA_Procs-16_ProcsPerChip-4_L2Banks-16_Memories-16.txt
network/simple/Network_Files/NUCA_Procs-16_ProcsPerChip-4_L2Banks-16_Memories-4.txt
network/simple/Network_Files/NUCA_Procs-16_ProcsPerChip-4_L2Banks-32_Memories-4.txt
network/simple/Network_Files/NUCA_Procs-16_ProcsPerChip-4_L2Banks-4_Memories-16.txt
network/simple/Network_Files/NUCA_Procs-16_ProcsPerChip-4_L2Banks-4_Memories-4.txt
network/simple/Network_Files/NUCA_Procs-1_ProcsPerChip-1_L2Banks-1_Memories-1.txt
network/simple/Network_Files/NUCA_Procs-1_ProcsPerChip-1_L2Banks-256_Memories-1.txt
network/simple/Network_Files/NUCA_Procs-1_ProcsPerChip-1_L2Banks-32_Memories-1.txt
network/simple/Network_Files/NUCA_Procs-1_ProcsPerChip-1_L2Banks-64_Memories-1.txt
network/simple/Network_Files/NUCA_Procs-2_ProcsPerChip-1_L2Banks-2_Memories-2.txt
network/simple/Network_Files/NUCA_Procs-2_ProcsPerChip-2_L2Banks-2_Memories-2.txt
network/simple/Network_Files/NUCA_Procs-32_ProcsPerChip-32_L2Banks-32_Memories-16.txt
network/simple/Network_Files/NUCA_Procs-32_ProcsPerChip-32_L2Banks-32_Memories-4.txt
network/simple/Network_Files/NUCA_Procs-4_ProcsPerChip-1_L2Banks-4_Memories-4.txt
network/simple/Network_Files/NUCA_Procs-4_ProcsPerChip-4_L2Banks-4_Memories-4.txt
network/simple/Network_Files/NUCA_Procs-7_ProcsPerChip-7_L2Banks-7_Memories-7.txt
network/simple/Network_Files/NUCA_Procs-8_ProcsPerChip-1_L2Banks-8_Memories-8.txt
network/simple/Network_Files/NUCA_Procs-8_ProcsPerChip-4_L2Banks-8_Memories-8.txt
network/simple/Network_Files/NUCA_Procs-8_ProcsPerChip-8_L2Banks-256_Memories-8.txt
network/simple/Network_Files/NUCA_Procs-8_ProcsPerChip-8_L2Banks-8_Memories-8.txt
network/simple/Network_Files/NetworkFileMaker.py
network/simple/Network_Files/TLC_Procs-8_ProcsPerChip-8_L2Banks-256_Memories-8.txt
network/simple/Network_Files/TOKEN_CMP_Procs-16_ProcsPerChip-16_L2Banks-16_Memories-16.txt
network/simple/Network_Files/TOKEN_CMP_Procs-16_ProcsPerChip-4_L2Banks-16_Memories-16.txt
network/simple/PerfectSwitch.cc
network/simple/PerfectSwitch.hh
network/simple/SimpleNetwork.cc
network/simple/SimpleNetwork.hh
network/simple/Switch.cc
network/simple/Switch.hh
network/simple/Throttle.cc
network/simple/Throttle.hh
network/simple/Topology.cc
network/simple/Topology.hh
profiler/AccessTraceForAddress.cc
profiler/AccessTraceForAddress.hh
profiler/AddressProfiler.cc
profiler/AddressProfiler.hh
profiler/CacheProfiler.cc
profiler/CacheProfiler.hh
profiler/Profiler.cc
profiler/Profiler.hh
profiler/StoreTrace.cc
profiler/StoreTrace.hh
profiler/XactProfiler.cc
profiler/XactProfiler.hh
recorder/CacheRecorder.cc
recorder/CacheRecorder.hh
recorder/TraceRecord.cc
recorder/TraceRecord.hh
recorder/Tracer.cc
recorder/Tracer.hh
simics/commands.cc
simics/commands.hh
simics/interface.cc
simics/interface.hh
simics/simics_api_dummy.c
slicc_interface/AbstractCacheEntry.cc
slicc_interface/AbstractCacheEntry.hh
slicc_interface/AbstractChip.cc
slicc_interface/AbstractChip.hh
slicc_interface/AbstractProtocol.hh
slicc_interface/Message.hh
slicc_interface/NetworkMessage.hh
slicc_interface/RubySlicc_ComponentMapping.hh
slicc_interface/RubySlicc_Profiler_interface.cc
slicc_interface/RubySlicc_Profiler_interface.hh
slicc_interface/RubySlicc_Util.hh
slicc_interface/RubySlicc_includes.hh
system/AbstractBloomFilter.hh
system/AbstractMemOrCache.hh
system/AbstractReplacementPolicy.hh
system/BlockBloomFilter.cc
system/BlockBloomFilter.hh
system/BulkBloomFilter.cc
system/BulkBloomFilter.hh
system/CacheMemory.hh
system/DirectoryMemory.cc
system/DirectoryMemory.hh
system/GenericBloomFilter.cc
system/GenericBloomFilter.hh
system/H3BloomFilter.cc
system/H3BloomFilter.hh
system/LRUPolicy.hh
system/LSB_CountingBloomFilter.cc
system/LSB_CountingBloomFilter.hh
system/MachineID.hh
system/MemoryControl.cc
system/MemoryControl.hh
system/MemoryNode.cc
system/MemoryNode.hh
system/MultiBitSelBloomFilter.cc
system/MultiBitSelBloomFilter.hh
system/MultiGrainBloomFilter.cc
system/MultiGrainBloomFilter.hh
system/NodeID.hh
system/NodePersistentTable.cc
system/NodePersistentTable.hh
system/NonCountingBloomFilter.cc
system/NonCountingBloomFilter.hh
system/PerfectCacheMemory.hh
system/PersistentArbiter.cc
system/PersistentArbiter.hh
system/PersistentTable.cc
system/PersistentTable.hh
system/PseudoLRUPolicy.hh
system/Sequencer.cc
system/Sequencer.hh
system/StoreBuffer.cc
system/StoreBuffer.hh
system/StoreCache.cc
system/StoreCache.hh
system/System.cc
system/System.hh
system/TBETable.hh
system/TimerTable.cc
system/TimerTable.hh
tester/BarrierGenerator.cc
tester/BarrierGenerator.hh
tester/Check.cc
tester/Check.hh
tester/CheckTable.cc
tester/CheckTable.hh
tester/DetermGETXGenerator.cc
tester/DetermGETXGenerator.hh
tester/DetermInvGenerator.cc
tester/DetermInvGenerator.hh
tester/DetermSeriesGETSGenerator.cc
tester/DetermSeriesGETSGenerator.hh
tester/DeterministicDriver.cc
tester/DeterministicDriver.hh
tester/Instruction.cc
tester/Instruction.hh
tester/RaceyDriver.cc
tester/RaceyDriver.hh
tester/RequestGenerator.cc
tester/RequestGenerator.hh
tester/SpecifiedGenerator.cc
tester/SpecifiedGenerator.hh
tester/SyntheticDriver.cc
tester/SyntheticDriver.hh
tester/Tester.cc
tester/Tester.hh
tester/XactAbortRequestGenerator.cc
tester/XactAbortRequestGenerator.hh
tester/XactRequestGenerator.cc
tester/XactRequestGenerator.hh
tester/main.cc
tester/main.hh
tester/test_framework.cc
tester/test_framework.hh
/gem5/src/mem/slicc/README
/gem5/src/mem/slicc/ast/AST.cc
/gem5/src/mem/slicc/ast/AST.hh
/gem5/src/mem/slicc/ast/ASTs.hh
/gem5/src/mem/slicc/ast/ActionDeclAST.cc
/gem5/src/mem/slicc/ast/ActionDeclAST.hh
/gem5/src/mem/slicc/ast/AssignStatementAST.cc
/gem5/src/mem/slicc/ast/AssignStatementAST.hh
/gem5/src/mem/slicc/ast/CheckAllocateStatementAST.cc
/gem5/src/mem/slicc/ast/CheckAllocateStatementAST.hh
/gem5/src/mem/slicc/ast/CheckStopSlotsStatementAST.cc
/gem5/src/mem/slicc/ast/CheckStopSlotsStatementAST.hh
/gem5/src/mem/slicc/ast/ChipComponentAccessAST.cc
/gem5/src/mem/slicc/ast/ChipComponentAccessAST.hh
/gem5/src/mem/slicc/ast/CopyHeadStatementAST.cc
/gem5/src/mem/slicc/ast/CopyHeadStatementAST.hh
/gem5/src/mem/slicc/ast/DeclAST.cc
/gem5/src/mem/slicc/ast/DeclAST.hh
/gem5/src/mem/slicc/ast/DeclListAST.cc
/gem5/src/mem/slicc/ast/DeclListAST.hh
/gem5/src/mem/slicc/ast/EnqueueStatementAST.cc
/gem5/src/mem/slicc/ast/EnqueueStatementAST.hh
/gem5/src/mem/slicc/ast/EnumDeclAST.cc
/gem5/src/mem/slicc/ast/EnumDeclAST.hh
/gem5/src/mem/slicc/ast/EnumExprAST.cc
/gem5/src/mem/slicc/ast/EnumExprAST.hh
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/gem5/src/mem/slicc/doc/SLICC_V03.txt
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