History log of /gem5/src/mem/qos/
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13892:0182a0601f66 22-Apr-2019 Gabe Black <gabeblack@google.com>

mem: Minimize the use of MemObject.

MemObject doesn't provide anything beyond its base ClockedObject any
more, so this change removes it from most inheritance hierarchies.
Occasionally MemObject is replaced with SimObject when I was fairly
confident that the extra functionality of ClockedObject wasn't needed.

Change-Id: Ic014ab61e56402e62548e8c831eb16e26523fdce
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18289
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>


/gem5/src/arch/arm/ArmTLB.py
/gem5/src/arch/arm/table_walker.cc
/gem5/src/arch/arm/table_walker.hh
/gem5/src/arch/generic/BaseTLB.py
/gem5/src/arch/generic/tlb.hh
/gem5/src/arch/x86/X86TLB.py
/gem5/src/arch/x86/pagetable_walker.cc
/gem5/src/arch/x86/pagetable_walker.hh
/gem5/src/cpu/BaseCPU.py
/gem5/src/cpu/base.cc
/gem5/src/cpu/base.hh
/gem5/src/cpu/o3/checker.cc
/gem5/src/cpu/o3/cpu.hh
/gem5/src/cpu/simple/base.cc
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.cc
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.hh
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.py
/gem5/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc
/gem5/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh
/gem5/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.py
/gem5/src/cpu/testers/memtest/MemTest.py
/gem5/src/cpu/testers/memtest/memtest.cc
/gem5/src/cpu/testers/memtest/memtest.hh
/gem5/src/cpu/testers/rubytest/RubyTester.cc
/gem5/src/cpu/testers/rubytest/RubyTester.hh
/gem5/src/cpu/testers/rubytest/RubyTester.py
/gem5/src/cpu/testers/traffic_gen/BaseTrafficGen.py
/gem5/src/cpu/testers/traffic_gen/base.cc
/gem5/src/cpu/testers/traffic_gen/base.hh
/gem5/src/cpu/thread_state.hh
/gem5/src/dev/Device.py
/gem5/src/dev/dma_device.cc
/gem5/src/dev/dma_device.hh
/gem5/src/dev/io_device.cc
/gem5/src/dev/io_device.hh
/gem5/src/dev/x86/intdev.hh
/gem5/src/doc/memory_system.doxygen
/gem5/src/gpu-compute/GPU.py
/gem5/src/gpu-compute/LdsState.py
/gem5/src/gpu-compute/X86GPUTLB.py
/gem5/src/gpu-compute/compute_unit.cc
/gem5/src/gpu-compute/compute_unit.hh
/gem5/src/gpu-compute/gpu_tlb.cc
/gem5/src/gpu-compute/gpu_tlb.hh
/gem5/src/gpu-compute/lds_state.cc
/gem5/src/gpu-compute/lds_state.hh
/gem5/src/gpu-compute/tlb_coalescer.cc
/gem5/src/gpu-compute/tlb_coalescer.hh
/gem5/src/mem/AbstractMemory.py
/gem5/src/mem/AddrMapper.py
/gem5/src/mem/Bridge.py
/gem5/src/mem/CommMonitor.py
/gem5/src/mem/ExternalMaster.py
/gem5/src/mem/ExternalSlave.py
/gem5/src/mem/MemChecker.py
/gem5/src/mem/MemDelay.py
/gem5/src/mem/SerialLink.py
/gem5/src/mem/XBar.py
/gem5/src/mem/abstract_mem.cc
/gem5/src/mem/abstract_mem.hh
/gem5/src/mem/addr_mapper.cc
/gem5/src/mem/addr_mapper.hh
/gem5/src/mem/bridge.cc
/gem5/src/mem/bridge.hh
/gem5/src/mem/cache/Cache.py
/gem5/src/mem/cache/base.cc
/gem5/src/mem/cache/base.hh
/gem5/src/mem/comm_monitor.cc
/gem5/src/mem/comm_monitor.hh
/gem5/src/mem/dram_ctrl.cc
/gem5/src/mem/dramsim2.cc
/gem5/src/mem/external_master.cc
/gem5/src/mem/external_master.hh
/gem5/src/mem/external_slave.cc
/gem5/src/mem/external_slave.hh
/gem5/src/mem/mem_checker_monitor.cc
/gem5/src/mem/mem_checker_monitor.hh
/gem5/src/mem/mem_delay.cc
/gem5/src/mem/mem_delay.hh
/gem5/src/mem/mport.hh
/gem5/src/mem/packet.hh
/gem5/src/mem/port.cc
/gem5/src/mem/port.hh
mem_sink.cc
/gem5/src/mem/qport.hh
/gem5/src/mem/ruby/network/dummy_port.hh
/gem5/src/mem/ruby/slicc_interface/AbstractController.cc
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/slicc_interface/Controller.py
/gem5/src/mem/ruby/system/RubyPort.cc
/gem5/src/mem/ruby/system/RubyPort.hh
/gem5/src/mem/ruby/system/Sequencer.py
/gem5/src/mem/ruby/system/WeightedLRUReplacementPolicy.py
/gem5/src/mem/serial_link.cc
/gem5/src/mem/serial_link.hh
/gem5/src/mem/simple_mem.cc
/gem5/src/mem/tport.cc
/gem5/src/mem/tport.hh
/gem5/src/mem/xbar.cc
/gem5/src/mem/xbar.hh
/gem5/src/python/m5/SimObject.py
/gem5/src/sim/System.py
/gem5/src/sim/cxx_manager.cc
/gem5/src/sim/system.cc
/gem5/src/sim/system.hh
13784:1941dc118243 07-Mar-2019 Gabe Black <gabeblack@google.com>

arch, cpu, dev, gpu, mem, sim, python: start using getPort.

Replace the getMasterPort, getSlavePort, and getEthPort functions
with getPort, and remove extraneous mechanisms that are no longer
necessary.

Change-Id: Iab7e3c02d2f3a0cf33e7e824e18c28646b5bc318
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17040
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>


/gem5/src/arch/arm/table_walker.cc
/gem5/src/arch/arm/table_walker.hh
/gem5/src/arch/arm/tlb.cc
/gem5/src/arch/arm/tlb.hh
/gem5/src/arch/generic/tlb.hh
/gem5/src/arch/x86/interrupts.hh
/gem5/src/arch/x86/pagetable_walker.cc
/gem5/src/arch/x86/pagetable_walker.hh
/gem5/src/arch/x86/tlb.cc
/gem5/src/arch/x86/tlb.hh
/gem5/src/cpu/base.cc
/gem5/src/cpu/base.hh
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.cc
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.hh
/gem5/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc
/gem5/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh
/gem5/src/cpu/testers/memtest/memtest.cc
/gem5/src/cpu/testers/memtest/memtest.hh
/gem5/src/cpu/testers/rubytest/RubyTester.cc
/gem5/src/cpu/testers/rubytest/RubyTester.hh
/gem5/src/cpu/testers/traffic_gen/base.cc
/gem5/src/cpu/testers/traffic_gen/base.hh
/gem5/src/cpu/trace/trace_cpu.cc
/gem5/src/dev/dma_device.cc
/gem5/src/dev/dma_device.hh
/gem5/src/dev/io_device.cc
/gem5/src/dev/io_device.hh
/gem5/src/dev/net/Ethernet.py
/gem5/src/dev/net/SConscript
/gem5/src/dev/net/dist_etherlink.cc
/gem5/src/dev/net/dist_etherlink.hh
/gem5/src/dev/net/etherbus.cc
/gem5/src/dev/net/etherbus.hh
/gem5/src/dev/net/etherdevice.hh
/gem5/src/dev/net/etherlink.cc
/gem5/src/dev/net/etherlink.hh
/gem5/src/dev/net/etherobject.hh
/gem5/src/dev/net/etherswitch.cc
/gem5/src/dev/net/etherswitch.hh
/gem5/src/dev/net/ethertap.cc
/gem5/src/dev/net/ethertap.hh
/gem5/src/dev/net/i8254xGBe.cc
/gem5/src/dev/net/i8254xGBe.hh
/gem5/src/dev/net/ns_gige.cc
/gem5/src/dev/net/ns_gige.hh
/gem5/src/dev/net/python.cc
/gem5/src/dev/net/sinic.cc
/gem5/src/dev/net/sinic.hh
/gem5/src/dev/pci/copy_engine.cc
/gem5/src/dev/pci/copy_engine.hh
/gem5/src/dev/x86/i82094aa.cc
/gem5/src/dev/x86/i82094aa.hh
/gem5/src/gpu-compute/compute_unit.hh
/gem5/src/gpu-compute/dispatcher.cc
/gem5/src/gpu-compute/dispatcher.hh
/gem5/src/gpu-compute/gpu_tlb.cc
/gem5/src/gpu-compute/gpu_tlb.hh
/gem5/src/gpu-compute/lds_state.hh
/gem5/src/gpu-compute/tlb_coalescer.cc
/gem5/src/gpu-compute/tlb_coalescer.hh
/gem5/src/learning_gem5/part2/simple_cache.cc
/gem5/src/learning_gem5/part2/simple_cache.hh
/gem5/src/learning_gem5/part2/simple_memobj.cc
/gem5/src/learning_gem5/part2/simple_memobj.hh
/gem5/src/mem/addr_mapper.cc
/gem5/src/mem/addr_mapper.hh
/gem5/src/mem/bridge.cc
/gem5/src/mem/bridge.hh
/gem5/src/mem/cache/base.cc
/gem5/src/mem/cache/base.hh
/gem5/src/mem/comm_monitor.cc
/gem5/src/mem/comm_monitor.hh
/gem5/src/mem/dram_ctrl.cc
/gem5/src/mem/dram_ctrl.hh
/gem5/src/mem/dramsim2.cc
/gem5/src/mem/dramsim2.hh
/gem5/src/mem/external_master.cc
/gem5/src/mem/external_master.hh
/gem5/src/mem/external_slave.cc
/gem5/src/mem/external_slave.hh
/gem5/src/mem/mem_checker_monitor.cc
/gem5/src/mem/mem_checker_monitor.hh
/gem5/src/mem/mem_delay.cc
/gem5/src/mem/mem_delay.hh
/gem5/src/mem/mem_object.cc
/gem5/src/mem/mem_object.hh
mem_sink.cc
mem_sink.hh
/gem5/src/mem/ruby/network/MessageBuffer.hh
/gem5/src/mem/ruby/network/Network.hh
/gem5/src/mem/ruby/network/dummy_port.hh
/gem5/src/mem/ruby/slicc_interface/AbstractController.cc
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/system/RubyPort.cc
/gem5/src/mem/ruby/system/RubyPort.hh
/gem5/src/mem/serial_link.cc
/gem5/src/mem/serial_link.hh
/gem5/src/mem/simple_mem.cc
/gem5/src/mem/simple_mem.hh
/gem5/src/mem/xbar.cc
/gem5/src/mem/xbar.hh
/gem5/src/python/SConscript
/gem5/src/python/pybind11/pybind.hh
/gem5/src/python/pybind11/pyobject.cc
/gem5/src/sim/SConscript
/gem5/src/sim/cxx_manager.cc
/gem5/src/sim/init.cc
/gem5/src/sim/python.cc
/gem5/src/sim/system.cc
/gem5/src/sim/system.hh
13720:18f5d3990ac9 26-Jan-2019 Andreas Sandberg <andreas.sandberg@arm.com>

python: Stop using basestring to test for strings

The base class basestring doesn't exist in Python 3. Use string_types
from six instead.

Change-Id: I7e84903fb7dd4a0af7ae4e9f4ec2e54338f212bb
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15998
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Juha Jäykkä <juha.jaykka@arm.com>

13665:9c7fe3811b88 25-Jan-2019 Andreas Sandberg <andreas.sandberg@arm.com>

python: Don't assume SimObjects live in the global namespace

The importer in Python 3 doesn't like the way we import SimObjects
from the global namespace. Convert the existing SimObject declarations
to import from m5.objects. As a side-effect, this makes these files
consistent with configuration files.

Change-Id: I11153502b430822130722839e1fa767b82a027aa
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15981
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>


/gem5/src/arch/alpha/AlphaSystem.py
/gem5/src/arch/alpha/AlphaTLB.py
/gem5/src/arch/arm/ArmISA.py
/gem5/src/arch/arm/ArmNativeTrace.py
/gem5/src/arch/arm/ArmPMU.py
/gem5/src/arch/arm/ArmSemihosting.py
/gem5/src/arch/arm/ArmSystem.py
/gem5/src/arch/arm/ArmTLB.py
/gem5/src/arch/arm/tracers/TarmacTrace.py
/gem5/src/arch/mips/MipsSystem.py
/gem5/src/arch/mips/MipsTLB.py
/gem5/src/arch/power/PowerTLB.py
/gem5/src/arch/riscv/RiscvSystem.py
/gem5/src/arch/riscv/RiscvTLB.py
/gem5/src/arch/sparc/SparcNativeTrace.py
/gem5/src/arch/sparc/SparcSystem.py
/gem5/src/arch/sparc/SparcTLB.py
/gem5/src/arch/x86/X86LocalApic.py
/gem5/src/arch/x86/X86NativeTrace.py
/gem5/src/arch/x86/X86System.py
/gem5/src/arch/x86/X86TLB.py
/gem5/src/base/vnc/Vnc.py
/gem5/src/cpu/BaseCPU.py
/gem5/src/cpu/CPUTracers.py
/gem5/src/cpu/CheckerCPU.py
/gem5/src/cpu/DummyChecker.py
/gem5/src/cpu/InstPBTrace.py
/gem5/src/cpu/kvm/BaseKvmCPU.py
/gem5/src/cpu/kvm/X86KvmCPU.py
/gem5/src/cpu/minor/MinorCPU.py
/gem5/src/cpu/o3/FUPool.py
/gem5/src/cpu/o3/FuncUnitConfig.py
/gem5/src/cpu/o3/O3CPU.py
/gem5/src/cpu/o3/O3Checker.py
/gem5/src/cpu/o3/probe/ElasticTrace.py
/gem5/src/cpu/o3/probe/SimpleTrace.py
/gem5/src/cpu/simple/AtomicSimpleCPU.py
/gem5/src/cpu/simple/BaseSimpleCPU.py
/gem5/src/cpu/simple/NonCachingSimpleCPU.py
/gem5/src/cpu/simple/TimingSimpleCPU.py
/gem5/src/cpu/simple/probes/SimPoint.py
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.py
/gem5/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.py
/gem5/src/cpu/testers/memtest/MemTest.py
/gem5/src/cpu/testers/rubytest/RubyTester.py
/gem5/src/cpu/testers/traffic_gen/BaseTrafficGen.py
/gem5/src/cpu/testers/traffic_gen/PyTrafficGen.py
/gem5/src/cpu/testers/traffic_gen/TrafficGen.py
/gem5/src/cpu/trace/TraceCPU.py
/gem5/src/dev/BadDevice.py
/gem5/src/dev/Device.py
/gem5/src/dev/Platform.py
/gem5/src/dev/alpha/AlphaBackdoor.py
/gem5/src/dev/alpha/Tsunami.py
/gem5/src/dev/arm/EnergyCtrl.py
/gem5/src/dev/arm/FlashDevice.py
/gem5/src/dev/arm/Gic.py
/gem5/src/dev/arm/NoMali.py
/gem5/src/dev/arm/RealView.py
/gem5/src/dev/arm/UFSHostDevice.py
/gem5/src/dev/arm/VirtIOMMIO.py
/gem5/src/dev/i2c/I2C.py
/gem5/src/dev/mips/Malta.py
/gem5/src/dev/net/Ethernet.py
/gem5/src/dev/pci/CopyEngine.py
/gem5/src/dev/pci/PciDevice.py
/gem5/src/dev/pci/PciHost.py
/gem5/src/dev/serial/Terminal.py
/gem5/src/dev/serial/Uart.py
/gem5/src/dev/sparc/T1000.py
/gem5/src/dev/storage/Ide.py
/gem5/src/dev/virtio/VirtIO.py
/gem5/src/dev/virtio/VirtIO9P.py
/gem5/src/dev/virtio/VirtIOBlock.py
/gem5/src/dev/virtio/VirtIOConsole.py
/gem5/src/dev/x86/Cmos.py
/gem5/src/dev/x86/I8042.py
/gem5/src/dev/x86/I82094AA.py
/gem5/src/dev/x86/I8237.py
/gem5/src/dev/x86/I8254.py
/gem5/src/dev/x86/I8259.py
/gem5/src/dev/x86/Pc.py
/gem5/src/dev/x86/PcSpeaker.py
/gem5/src/dev/x86/SouthBridge.py
/gem5/src/gpu-compute/GPU.py
/gem5/src/gpu-compute/LdsState.py
/gem5/src/learning_gem5/part2/SimpleCache.py
/gem5/src/learning_gem5/part2/SimpleMemobj.py
/gem5/src/mem/AbstractMemory.py
/gem5/src/mem/AddrMapper.py
/gem5/src/mem/Bridge.py
/gem5/src/mem/CommMonitor.py
/gem5/src/mem/DRAMCtrl.py
/gem5/src/mem/ExternalMaster.py
/gem5/src/mem/ExternalSlave.py
/gem5/src/mem/HMCController.py
/gem5/src/mem/MemChecker.py
/gem5/src/mem/MemDelay.py
/gem5/src/mem/MemObject.py
/gem5/src/mem/SerialLink.py
/gem5/src/mem/SimpleMemory.py
/gem5/src/mem/XBar.py
/gem5/src/mem/cache/Cache.py
/gem5/src/mem/cache/prefetch/Prefetcher.py
/gem5/src/mem/cache/tags/Tags.py
/gem5/src/mem/probes/MemFootprintProbe.py
/gem5/src/mem/probes/MemTraceProbe.py
/gem5/src/mem/probes/StackDistProbe.py
QoSMemCtrl.py
QoSMemSinkCtrl.py
/gem5/src/mem/ruby/network/BasicRouter.py
/gem5/src/mem/ruby/network/Network.py
/gem5/src/mem/ruby/network/garnet2.0/GarnetLink.py
/gem5/src/mem/ruby/network/garnet2.0/GarnetNetwork.py
/gem5/src/mem/ruby/network/simple/SimpleLink.py
/gem5/src/mem/ruby/network/simple/SimpleNetwork.py
/gem5/src/mem/ruby/slicc_interface/Controller.py
/gem5/src/mem/ruby/structures/LRUReplacementPolicy.py
/gem5/src/mem/ruby/structures/PseudoLRUReplacementPolicy.py
/gem5/src/mem/ruby/structures/RubyCache.py
/gem5/src/mem/ruby/structures/RubyPrefetcher.py
/gem5/src/mem/ruby/system/GPUCoalescer.py
/gem5/src/mem/ruby/system/RubySystem.py
/gem5/src/mem/ruby/system/Sequencer.py
/gem5/src/mem/ruby/system/VIPERCoalescer.py
/gem5/src/mem/ruby/system/WeightedLRUReplacementPolicy.py
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/sim/System.py
/gem5/src/sim/TickedObject.py
/gem5/src/sim/power/MathExprPowerModel.py
/gem5/src/sim/power/ThermalModel.py
13564:9bbd53a77887 27-Nov-2018 Nikos Nikoleris <nikos.nikoleris@arm.com>

mem: Determine if a packet queue forces ordering at construction

A packet queue is typically used to hold on to packets that are
schedules to be sent in the future or when they need to queue behind
younger packets that have been sent out yet. Due to memory order
requirements, some MemObjects need to maintain the order for packet
(mostly responses) that reference the same cache block.

Prior to this patch the ordering requirements where determined when
the packet was scheduled to be sent. This patch moves the parameter to
the constructor.

Change-Id: Ieb4d94e86bc7514f5036b313ec23ea47dd653164
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15555
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

13475:5189e2334f1a 28-Nov-2018 Nikos Nikoleris <nikos.nikoleris@arm.com>

base, sim: Add missing destructors

Derived classes with virtual functions need to define a virtual
destructor or a protected destructor otherwise calling the base class
destructor has undefined behavior. This change adds a virtual
distructor in the base class.

Change-Id: I1c855aa56dff6585ff99b9147bdb4eb9729a0a53
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14815
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

13430:4b0a26035e4b 07-Sep-2016 Matteo Andreozzi <Matteo.Andreozzi@arm.com>

mem: avoid calling regStat twice on a QoSPolicy

Change-Id: I216c57073fabe29c3f898a5d89cee41efd4277d5
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13696
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

13023:a379876f2244 17-Aug-2018 Giacomo Travaglini <giacomo.travaglini@arm.com>

mem: Implement QoS Proportional Fair policy

Providing a configurable fair scheduling policy based on utilization;
utilization is directly proportional to a score which is inversely
proportional to the QoS priority. It is meant to avoid starvation of low
priority packets.

Users can tune the policy by adjusting the weight parameter (weight of
the following formula)

new_score = ((1.0 - weight) * old_score) + (weight * served_bytes)

Change-Id: I7679e234b916c57ebed06cec0ff3cff3cf2aef22
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12359
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

12968:1c2b8dd9241f 10-May-2018 Giacomo Travaglini <giacomo.travaglini@arm.com>

mem: Implement base QoS Policies.

This patch implements a base fixed priority policy and an ideal
turnaround policy for the QoS memory controller.

Change-Id: I38ce16f845fc0ec86d6fc4cc5dc5406f213a465e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11972
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

12967:16c791dd6ee6 10-May-2018 Matteo Andreozzi <matteo.andreozzi@arm.com>

mem: Add a simple QoS-aware Memory Controller

This patch implements QoSMemorySink: a simple generic QoS-aware memory
controller which inherits from QoS::MemCtrl.

Change-Id: I537a4e2d4cb8f54fa0002eb088b2c6957afb9973
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11971
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Matthew Poremba <porembam@gmail.com>

12966:3b20a7f755d5 10-Jan-2018 Matteo Andreozzi <Matteo.Andreozzi@arm.com>

mem: Add a QoS-aware Memory Controller type

This is the implementation of QoS algorithms support for gem5 memory
objects. This change-list provides a framework for specifying QoS
algorithm which can be used to prioritise service to specific masters in
the memory controller.
The QoS support implemented here is designed to be extendable so that
new QoS algorithms can be easily plugged into the memory controller as
"QoS Policies".

Change-Id: I0b611f13fce54dd1dd444eb806f8e98afd248bd5
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11970
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>