13892:0182a0601f66 |
22-Apr-2019 |
Gabe Black <gabeblack@google.com> |
mem: Minimize the use of MemObject.
MemObject doesn't provide anything beyond its base ClockedObject any more, so this change removes it from most inheritance hierarchies. Occasionally MemObject is replaced with SimObject when I was fairly confident that the extra functionality of ClockedObject wasn't needed.
Change-Id: Ic014ab61e56402e62548e8c831eb16e26523fdce Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18289 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Gabe Black <gabeblack@google.com> |
13784:1941dc118243 |
07-Mar-2019 |
Gabe Black <gabeblack@google.com> |
arch, cpu, dev, gpu, mem, sim, python: start using getPort.
Replace the getMasterPort, getSlavePort, and getEthPort functions with getPort, and remove extraneous mechanisms that are no longer necessary.
Change-Id: Iab7e3c02d2f3a0cf33e7e824e18c28646b5bc318 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17040 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
13720:18f5d3990ac9 |
26-Jan-2019 |
Andreas Sandberg <andreas.sandberg@arm.com> |
python: Stop using basestring to test for strings
The base class basestring doesn't exist in Python 3. Use string_types from six instead.
Change-Id: I7e84903fb7dd4a0af7ae4e9f4ec2e54338f212bb Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15998 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Juha Jäykkä <juha.jaykka@arm.com> |
13665:9c7fe3811b88 |
25-Jan-2019 |
Andreas Sandberg <andreas.sandberg@arm.com> |
python: Don't assume SimObjects live in the global namespace
The importer in Python 3 doesn't like the way we import SimObjects from the global namespace. Convert the existing SimObject declarations to import from m5.objects. As a side-effect, this makes these files consistent with configuration files.
Change-Id: I11153502b430822130722839e1fa767b82a027aa Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15981 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
13564:9bbd53a77887 |
27-Nov-2018 |
Nikos Nikoleris <nikos.nikoleris@arm.com> |
mem: Determine if a packet queue forces ordering at construction
A packet queue is typically used to hold on to packets that are schedules to be sent in the future or when they need to queue behind younger packets that have been sent out yet. Due to memory order requirements, some MemObjects need to maintain the order for packet (mostly responses) that reference the same cache block.
Prior to this patch the ordering requirements where determined when the packet was scheduled to be sent. This patch moves the parameter to the constructor.
Change-Id: Ieb4d94e86bc7514f5036b313ec23ea47dd653164 Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15555 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
13475:5189e2334f1a |
28-Nov-2018 |
Nikos Nikoleris <nikos.nikoleris@arm.com> |
base, sim: Add missing destructors
Derived classes with virtual functions need to define a virtual destructor or a protected destructor otherwise calling the base class destructor has undefined behavior. This change adds a virtual distructor in the base class.
Change-Id: I1c855aa56dff6585ff99b9147bdb4eb9729a0a53 Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/14815 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
13430:4b0a26035e4b |
07-Sep-2016 |
Matteo Andreozzi <Matteo.Andreozzi@arm.com> |
mem: avoid calling regStat twice on a QoSPolicy
Change-Id: I216c57073fabe29c3f898a5d89cee41efd4277d5 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13696 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> |
13023:a379876f2244 |
17-Aug-2018 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
mem: Implement QoS Proportional Fair policy
Providing a configurable fair scheduling policy based on utilization; utilization is directly proportional to a score which is inversely proportional to the QoS priority. It is meant to avoid starvation of low priority packets.
Users can tune the policy by adjusting the weight parameter (weight of the following formula)
new_score = ((1.0 - weight) * old_score) + (weight * served_bytes)
Change-Id: I7679e234b916c57ebed06cec0ff3cff3cf2aef22 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12359 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com> |
12968:1c2b8dd9241f |
10-May-2018 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
mem: Implement base QoS Policies.
This patch implements a base fixed priority policy and an ideal turnaround policy for the QoS memory controller.
Change-Id: I38ce16f845fc0ec86d6fc4cc5dc5406f213a465e Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11972 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> |
12967:16c791dd6ee6 |
10-May-2018 |
Matteo Andreozzi <matteo.andreozzi@arm.com> |
mem: Add a simple QoS-aware Memory Controller
This patch implements QoSMemorySink: a simple generic QoS-aware memory controller which inherits from QoS::MemCtrl.
Change-Id: I537a4e2d4cb8f54fa0002eb088b2c6957afb9973 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11971 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Matthew Poremba <porembam@gmail.com> |
12966:3b20a7f755d5 |
10-Jan-2018 |
Matteo Andreozzi <Matteo.Andreozzi@arm.com> |
mem: Add a QoS-aware Memory Controller type
This is the implementation of QoS algorithms support for gem5 memory objects. This change-list provides a framework for specifying QoS algorithm which can be used to prioritise service to specific masters in the memory controller. The QoS support implemented here is designed to be extendable so that new QoS algorithms can be easily plugged into the memory controller as "QoS Policies".
Change-Id: I0b611f13fce54dd1dd444eb806f8e98afd248bd5 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11970 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> |