mem-cache: Fix set and way of sub-entries

Set and way of sub-entries were not being set previously.
They must be set after the sub-blocks have been assigned
to the main block.

Change-Id: I7b6921b8437b29c472d691cd78cf20f2bb6c7e07
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19669
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Handle data expansion

When a block in compressed form is overwriten, it may change
its size. If the new compressed size is bigger, and the total
size becomes bigger than the block size, one or more blocks
will have to be evicted. This is called data expansion, or
fat writes.

This change assumes that a first level cache cannot have a
compressor, since otherwise data expansion should have been
handled for atomic operations and writes. As such, data
expansions should only be seen on writebacks. As writebacks
are forwarded to the next level when failed, there should
be no data expansions when servicing misses either.

This patch adds the functionality to handle data expansions
by evicting the co-allocated blocks to make room for an
expanded block.

Change-Id: I0bd77bf6446bfae336889940b2f75d6f0c87e533
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12087
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Add co-allocation function to compressed tags

Implement a co-allocation function in compressed tags, so
that compressed blocks can be co-allocated in a superblock.
Co-allocation is possible when compression ratio (CR) blocks
that share a superblock tag can be compressed to up to (100/CR)%
of their size.

Change-Id: I937cc1fcbb488e70309cb5478c12db65f1b4b23f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11411
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Add compression and decompression calls

Add a compressor to the base cache class and compress within
block allocation and decompress on writebacks.

This change does not implement data expansion (fat writes) yet,
nor it adds the compression latency to the block write time.

Change-Id: Ie36db65f7487c9b05ec4aedebc2c7651b4cb4821
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11410
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Add block size to findVictim

Add block size to findVictim. For standard caches it
will not be used. Compressed caches, however, need to
know the size of the compressed block to decide whether
a block is co-allocatable or not.

Change-Id: Id07f79763687b29f75d707c080fa9bd978a408aa
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11198
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Mohammad Seyedzadeh <sm.seyedzade@gmail.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Add compression data to CompressionBlk

Add a compression bit, decompression latency and compressed
block size and their respective getters and setters.

Change-Id: Ia9d8656552d60e8d4e85fe5379dd75fc5adb0abe
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11102
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Stub compression framework

Create a stub of a compression framework where we can have
multiple data blocks per tag entry. Only consecutive blocks
can share a tag as of now.

For each tag entry there can be multiple data blocks. We have
the same number of tags a conventional cache would have, but
we instantiate the maximum number of data blocks (according to
the compression ratio) per tag, to virtually implement
compression without increasing the complexity of the simulator.

Change-Id: I549940c7afb2f744ab293ff8bb283967e7551a11
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/10763
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Revert "mem-cache: Remove Packet dependency in Tags"

Reverting patch due to polymorphism limitations.

This reverts commit 86a54d91936b524c0ef0f282959f0fc29bafe7eb.

Change-Id: Ie032dcc5176448c62118c89732b3cc6b8efd5a13
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17049
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

python: Don't assume SimObjects live in the global namespace

The importer in Python 3 doesn't like the way we import SimObjects
from the global namespace. Convert the existing SimObject declarations
to import from m5.objects. As a side-effect, this makes these files
consistent with configuration files.

Change-Id: I11153502b430822130722839e1fa767b82a027aa
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15981
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

mem-cache: Optimize sector valid and secure check

Previously a loop was being done to check whether the
block was valid/secure or not. Variables have been
added to skip this loop and save and update sector
block state when sub-blocks are validated, invalidated
and secured.

Change-Id: Ie1734f7dfda9698c7bf22a1fcbfc47ffb9239cea
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/14363
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem-cache: Add setters to validate and secure block

In order to allow polymorphism of the block these two
functions have been added, and all direct status
assignments to these bits have been substituted.

We also assert that the block has been invalidated
before insertion. Then the block is validated in
the insertion.

Change-Id: Ie7be42408721ad4c2c9dc880f82a62cb594f8668
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/14362
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Remove Cache dependency from Tags

Tags do not need to be aware of caches.

Change-Id: Ib6a082b74dcd9b2f10852651634b59512732fb2a
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/14296
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Move access latency calculation to Cache

Access latency was not being calculated properly, as it was
always assuming that for hits reads take as long as writes,
and that parallel accesses would produce the same latency
for read and write misses.

By moving the calculation to the Cache we can use the write/
read information, reduce latency variables duplication and
remove Cache dependency from Tags.

The tag lookup latency is still calculated by the Tags.

Change-Id: I71bc68fb5c3515b372c3bf002d61b6f048a45540
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/13697
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Rename the tag class init function to tagsInit.

Since the tag classes are subclasses of SimObject, they inherit an
init function which does generic initialization at simulation startup
and which doesn't take any parameters. A new function was added which
does take a parameter, and which is just for doing tag specific
initialization as triggered by the base cache. These two names clashed,
and clang complained that the tag local name was hiding the SimObject
name (which it was).

Change-Id: I399775aceaf8f1a8e2646d434facef22e6d3e7d0
Reviewed-on: https://gem5-review.googlesource.com/c/13875
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Fix unused variable warning in FALRU:invalidate()

Change-Id: I3b902045433ca56b3e62c251158e784b5fa9e4d7
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13600
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

mem-cache: Factor ReplaceableEntry out

ReplaceableEntry is referenced by many classes that do
not necessarily need access to the replacement policies.
Therefore, in order to allow better compilation units,
we factor it out to a new file.

Change-Id: I0823567bf1ca336ffcdf783682ef473e8878d7fd
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/13418
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Move sector_blks to tags folder

Move sector_blks.hh and sector_blks.cc to the tags folder,
as its usage scope is restricted to the tags, and caches
should not be aware of them.

Change-Id: Ia7a71f51ec251d827872daf108c87da543a0ba57
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/13417
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Rename blk.cc/hh to cache_blk.cc/hh

Rename the files blk.cc and blk.hh to cache_blk.cc and cache_blk.hh
to comply with the usual file-class naming rules.

Change-Id: I8af45df3e4b8dd934fd9929ec914fb230cb2cb09
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/13416
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Virtualize block print

Encapsulate and virtualize block print, so that relevant
information can be easily printed anywhere.

Change-Id: I91109c29c126755183a0fd2b4446f5335e64076b
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/13415
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Remove CacheSet.hh

Replacement policies aren't aware of cache sets and do not
organize blocks based on replacement data. Block search is
independent of block placement.

Besides, indexing policies have their own way of addressing
the sets, therefore there is no need to use this class anymore.

BlkType has been removed, as it wasn't being used.

Change-Id: Ia79c2a491e59f295c8d60a0466c317eb0e2bdab9
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/9782
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Split Tags for indexing policies

Split indexing functionality from tags, so that code duplication
is reduced when adding new classes that use different indexing
policies, such as set associative, skewed associative or other
hash-based policies.

An indexing policy defines the mapping between an address' set
and its physical location. For example, a conventional set assoc
cache maps an address to all ways in a set using an immutable
function, that is, a set x is always mapped to set x. However,
skewed assoc caches map an address to a different set for each way,
using a skewing function.

FALRU has been left unmodified as it is a specialization with its
own complexity.

Change-Id: I0838b41663f21eba0aeab7aeb7839e3703ca3324
Reviewed-on: https://gem5-review.googlesource.com/c/8885
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem-cache: Use set and way for ReplaceableEntry

Replaceable entries belong to table-like structures, and therefore
they should be indexable by combining a row and a column. These,
using conventional cache nomenclature translate to sets and ways.

Make these entries aware of their sets and ways. The idea is to
make indexing policies usable by other table-like structures. In
order to do so we move sets and ways to ReplaceableEntry, which
will be the common base among table entries.

Change-Id: If0e3dacf9ea2f523af9cface067469ccecf82648
Reviewed-on: https://gem5-review.googlesource.com/c/12764
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem-cache: Use possible locations to find block

Use possible locations to find block to make it placement policy
independent.

Change-Id: I4c9d9e1e1ff91ce12e85ca1970f927d8f4f5a93b
Reviewed-on: https://gem5-review.googlesource.com/c/8884
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem-cache: Create tags initialization function

Having the blocks initialized in the constructor makes it harder
to apply inheritance in the tags classes. This patch decouples
the block initialization functionality from the constructor by
using an init() function. It also sets the parent cache.

Change-Id: I0da7fdaae492b1177c7cc3bda8639f79921fbbeb
Reviewed-on: https://gem5-review.googlesource.com/c/11509
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem-cache: Remove Packet dependency in Tags

Decouple Tags from Packets, only extracting the necessary
functionality for block insertion. As a side effect, create
a new function to update common insertion statistics.

Change-Id: I5c58f7c17de3255beee531f72a3fd25a30d74c90
Reviewed-on: https://gem5-review.googlesource.com/c/11098
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem-cache: Fix FALRU hash invalidation

The block was being invalidated before the hash could erase
its entry, therefore it was using invalid values (tag was
being assigned MaxAddr and the secure bit was reset).

This change reorders the calls, so that the appropriate hash
entry is erased.

Change-Id: I161463df0f8f5220179bc68d7be12051e5390d01
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/13210
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Make checking function const in FALRU

The checking function should not be able to modify either
the head and tail pointers nor should it modify its class.

Change-Id: I2ad495f0c8c6b778d48512143e94b4c9a353f22e
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/13209
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Make boundaries in FALRU an STL container

Turn the dynamically allocated array of pointers "boundaries"
into a STL vector.

Change-Id: I3409898473b155f69b4c6e038eba2dffb5b09380
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/13208
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem-cache: Fix FALRU inCachesMask initialization

inCachesMask is not being initialized, which triggers an assertion
on insertion. Fix this by implementing a default constructor for
the FALRUBlk.

Change-Id: I587cf5e0191c4587d938e6ab6036ec1b32f37793
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/13207
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem-cache: Fix non-bijective function in Skewed caches

The hash() function must be bijective for the skewed caches to work,
however when the hashing is done on top of a one-bit address, the
MSB and LSB refer to the same bit, and therefore their xor will
always be zero.

This patch adds a fatal error to not allow the user to set an invalid
value for the number of sets that would generate that bug.

As a side note, the missing header for the bitfields functions has
been added.

Change-Id: I35a03ac5fdc4debb091f7f2db5db33568d0b0021
Reviewed-on: https://gem5-review.googlesource.com/12724
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Create Skewed Assoc placement policy

Create a class that implements the skewed associative placement
policy. It uses the hash function and expansions of the skewing
functions described in "Skewed-Associative caches", by Seznec.

Only 8 skewing functions are implemented, and therefore if more
are needed a hash function will be recursively applied on top
of the output of one of these functions to generate different
values. This is not optimal, and if more functions are needed
it might be more effective to implement them.

Change-Id: Ibc77edffd8128114a8b200cec5d8deedfb5105cb
Reviewed-on: https://gem5-review.googlesource.com/8886
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Fix support for secure blocks in the FALRU cache

Fully associative caches use an unordered map to enable efficient
lookups of existing blocks. Previously this map was indexed using the
tag of the block. Security extentions allow secure and non secure
versions of a block with the same tag to co-exist in the cache. This
patch amends the block map to allow correct lookups for FALRU caches.

Change-Id: Iccf07464deab56d1d270bae14bb3b154047e3556
Reviewed-on: https://gem5-review.googlesource.com/11309
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Forward declare ReplaceableEntry

Forward declare ReplaceableEntry where in classes where pointers
to it are used.

Change-Id: I49c08d36442a563d7a6b4c9bcd7eba3591d29b60
Reviewed-on: https://gem5-review.googlesource.com/11096
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Remove unnecessary cast in SectorTags::findVictim

Removes an uneccessary cast that also caused an unused variable
error (due to -Werror) when compiling .fast targets.

Change-Id: Ic043f462925e7eaa7b691455f1d9e08a1c101980
Reviewed-on: https://gem5-review.googlesource.com/11119
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Make packet const in insertBlock

The packet should not be modified within insertBlock.

Change-Id: If7d2b01fe131f9923194efd155c9e85eeab24d5a
Reviewed-on: https://gem5-review.googlesource.com/10811
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Create Sector Cache

Implementation of Sector Caches, i.e., a cache with multiple
sequential data entries per tag entry for Set Associtive
placement policies.

Change-Id: I8e1e9448fa44ba308ccb16cd5bcc5fd36c988feb
Reviewed-on: https://gem5-review.googlesource.com/9741
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Use secure bit in findVictim

Sector caches must know if there was a sector hit in order
to decide whether a victim's sector must be fully evicted
to give place to a new sector or not.

In order to do so it needs the tag and secure information.

Change-Id: Ib554169e25fa131d6bf986561f7970b787c56874
Reviewed-on: https://gem5-review.googlesource.com/10722
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Move tagsInUse to children

Move tagsInUse to children, as sector caches have different
tag invalidation and insertion, and thus they must handle
updating this variable.

Change-Id: I875c9b7364a909c76daf610d1e226c4e82063870
Reviewed-on: https://gem5-review.googlesource.com/10721
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Return evictions along with victims

For both sector and compressed caches multiple blocks may need
to be evicted in order to make room for a new block.

For example, when replacing a sector, all the blocks in this
sector must be evicted. A replacement, however, does not always
need to evict multiple blocks, as it is in the case of an
insertion of a block whose sector is already present in the cache
(i.e., its corresponding entry in the sector had not been brought
in yet, so it was invalid).

This patch creates the cache framework for that to happen.

Change-Id: I77bedf69637cf899fef4d9432eb6da8529ea398b
Reviewed-on: https://gem5-review.googlesource.com/10142
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Use ReplaceableEntry in findBlockBySetAndWay

With a sector cache you can't find a block using only its set
and way, as there is the sector offset to take into account. As
all of these blocks inherit from ReplaceableEntry, the return
type of this function has been updated.

This function has also been declared closer to findBlock() due
to their similar functionality.

Change-Id: I4730a2b4ebb5738f7fc118201e208a1b9c3ba8e8
Reviewed-on: https://gem5-review.googlesource.com/10141
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Privatize extractSet

Only BaseSetAssoc uses extractSet(). Besides, skewed caches need
the way information to know which set an address is located at.

Change-Id: Id222e907dc550d053018561bb2683cfc415471ec
Reviewed-on: https://gem5-review.googlesource.com/9962
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Replace block visitor with std::function

This change modifies forEachBlk tags function to accept std::function
as parameter. It also adds an anyBlk tags function that given a
condition, it iterates through the blocks and returns whether the
condition is met.

Finally, it uses forEachBlk to implement the print, computeStats and
cleanupRefs functions that also work for the FALRU class.

Change-Id: I2f75f4baa1fdd5a1d343a63ecace3eb9458fbf03
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10621
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Fix include directives in the cache related classes

Change-Id: I111b0f662897c43974aadb08da1ed85c7542585c
Reviewed-on: https://gem5-review.googlesource.com/10433
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Delegate block invalidation to block allocation

For a block replacement we first select a victim block, we invalidate
it and then populate it with the new information. Prior to this change
BaseTags::insertBlock() did the invalidation and filled in the block
with the new information. Now that the replacements stat is moved to
the BaseCache, insertBlock does not need to perform the invalidation
and as a result we can unify the block eviction code in BaseCache.

Change-Id: I5bdf00b2dab2752ed2137ab7201ed1dc451333b3
Reviewed-on: https://gem5-review.googlesource.com/10429
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

mem-cache: Move reference count stats update to blk invalidation

The tags in the cache keep track of the number of references to the
blocks as well as the average number of references between an
insertion and the next invalidation. Previously the stats where
updated only on block insertion and invalidations were ignored. This
changes moves the update of the counters to the block invalidation
function.

Change-Id: Ie7672c13813ec278a65232694024d2e5e17c4612
Reviewed-on: https://gem5-review.googlesource.com/10428
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

mem-cache: Remove isTouched field from the CacheBlk

At the moment isTouched is used in the warm-up detection mechanism but
it keeps track of the same information as isValid(). This change
removes it and substitutes its use by isValid().

Change-Id: I611ddf2fa4562ae3b3b2ed2fb74d26abd2e5ec62
Reviewed-on: https://gem5-review.googlesource.com/10427
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

mem-cache: Move replacements stat to the base cache class

Change-Id: I25dbcfcddfe1c422a76eb1af3f726c1360d8d110
Reviewed-on: https://gem5-review.googlesource.com/10426
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

mem-cache: Create block insertion function

Create a block insertion function to be used when inserting
blocks. This resets the number of references to 1 (the
insertion is taken into account), sets the insertion tick,
and set secure state.

Change-Id: Ifc34cbbd1c125207ce47912d188809221c7a157e
Reviewed-on: https://gem5-review.googlesource.com/9824
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: ReplacementPolicy specific replacement data

Replacement data is specific for each replacement policy, and thus
should be instantiated differently by each policy.

Touch() and reset() do not need to be aware of CacheBlk, as they
only update its ReplacementData.

Invalidate() makes replacement policies independent of cache blocks,
by removing the awareness of the valid state.

An inheritable base ReplaceableEntry class was created to allow usage
of replacement policies with any table-like structure.

Change-Id: I998917d800fa48504ed95abffa2f1b7bfd68522b
Reviewed-on: https://gem5-review.googlesource.com/9421
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Use block iteration in BaseSetAssoc

Use block iteration instead of numSets and assoc in print(),
cleanupRefs() and computeStats().

This makes these functions rely solely on what they are used for:
printing and calculating stats of blocks. With the addition of
Sectors an extra indirection level is added, and thus these
functions would be skipping blocks.

Change-Id: I0006f82736cce02ba3e501ffafe9236f748daf32
Reviewed-on: https://gem5-review.googlesource.com/10143
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Use findBlock in FALRU's block access

An access must perform a block search, which is done by findBlock.

The tagHash is indexed by tags, so use extractTag instead of re-
implementing its functionality.

Change-Id: Ib5abacbc65cddf0f2d7e4440eb5355b56998a585
Reviewed-on: https://gem5-review.googlesource.com/10082
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem-cache: Use secure flag in FALRU's findBlock

FALRU's findBlock() must use the secure flag to assure proper
functionality.

Change-Id: I54e9fbd3c9093b3e8043c4c6c850b74a8f1f5ec0
Reviewed-on: https://gem5-review.googlesource.com/10081
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Revamp multiple size tracking for FALRU caches

This change fixes a few bugs and refactors the mechanism by which
caches that use the FALRU tags can output statistics for multiple
cache sizes ranging from the minimum cache of interest up to the
actual configured cache size.

Change-Id: Ibea029cf275a8c068c26eceeb06c761fc53aede2
Reviewed-on: https://gem5-review.googlesource.com/9826
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Add MoveToTail to FALRU

FALRU was missing MoveToTail functionality within its invalidate
function, and MoveToHead was doing unnecessary passes when the
moved block was the head already.

Besides, added some comments to make the code understandable.

Change-Id: I2430d82b5d53c88b102a62610ea38b46d6e03a55
Reviewed-on: https://gem5-review.googlesource.com/9541
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem: Remove unused 'using namespace'

Removal of unused/barely used 'using namespace' from C++ files.

Change-Id: I66dc548c04506db2e41180b9ea7ab5abd7d5375a
Reviewed-on: https://gem5-review.googlesource.com/9601
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Move insertBlock functionality in FALRU

Block insertion is being done in the getCandidates function, while the
insertBlock function does not do anything.

Besides, BaseTags' stats weren't being updated.

Change-Id: Iadab9c1ea61519214f66fa24c4b91c4fc95604c0
Reviewed-on: https://gem5-review.googlesource.com/8882
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Fix FALRU data block seg fault

FALRU didn't initialize the blocks' data, causing seg faults.
This patch does not make FALRU functional yet.

Change-Id: I10cbcf5afc3f8bc357eeb8b7cb46789dec47ba8b
Reviewed-on: https://gem5-review.googlesource.com/9302
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Split array indexing and replacement policies.

Replacement policies (LRU, Random) are currently considered as array
indexing methods, but have completely different functionalities:

- Array indexers determine the possible locations for block allocation.
This information is used to generate replacement candidates when
conflicts happen.
- Replacement policies determine which of the replacement candidates
should be evicted to make room for new allocations.

For this reason, they were split into different classes. Advantages:

- Easier and more straightforward to implement other replacement
policies (RRIP, LFU, ARC, ...)
- Allow easier future implementation of cache organization schemes

As now we can't assure the use of sets, the previous way to create a
true LRU is not viable. Now a timestamp_bits parameter controls how
many bits are dedicated for the timestamp, and a true LRU can be
achieved through an infinite number of bits (although a few bits suffice
in practice).

Change-Id: I23750db121f1474d17831137e6ff618beb2b3eda
Reviewed-on: https://gem5-review.googlesource.com/8501
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Use CacheBlk parameter on address regeneration

Skewed caches need to know the way to regenerate a block address.

Change-Id: I62c61ac9509eff2f37bad36862751956db7a6e40
Reviewed-on: https://gem5-review.googlesource.com/8782
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Fix missing overrides

clang doesn't like inconsistent overrides. Add override to all overidden
functions in lru.hh

Change-Id: I100ff4a7d90757439afee879ff9838c15f5c0b1d
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/8861
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Make invalidate a common function between tag classes

invalidate was defined as a separate function in the base associative
and fully-associative tags classes although both functions should
implement identical functionality. This patch moves the invalidate
function in the base tags class.

Change-Id: I206ee969b00ab9e05873c6d87531474fcd712907
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8286
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Fix bug generated by 8282

Merge 1ae7fced4d32898531a6875a339ef00e43e20e66 generated
a bug in tagsInUse calculation.

Change-Id: I079e327a0a26a7968f2ed8e433dd6e790c80998b
Reviewed-on: https://gem5-review.googlesource.com/8781
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Use findBlock() in accessBlock()

Use placement policy specific block search within generic access.

Change-Id: I6070035e6e00595bcf073d4011f78a55ba7e7a8a
Reviewed-on: https://gem5-review.googlesource.com/8721
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Remove redundant block initialization on allocation

Change-Id: I7496e12e6a517529316c480d5f6e2ade601f0e2d
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8282
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Remove mumBlock redundant initialiation from FALRU

Change-Id: Id3afec0a62446d6d0f44ccb655032343037637e0
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8281
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Remove extra block init in BaseSetAssoc

Removed extra initialization of cache block just after they have been
created and organized the comments.

Change-Id: I75c1beaf0489e3e530fd8cbff2739dc7593e3e6f
Reviewed-on: https://gem5-review.googlesource.com/8661
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Vectorize C arrays in BaseSetAssoc.

Transform BaseSetAssoc's arrays into C++ vectors to avoid unnecessary
resource management.

Change-Id: I656f42f29e5f9589eba491b410ca1df5a64f2f34
Reviewed-on: https://gem5-review.googlesource.com/8621
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem-cache: Fix CacheSet memory leak

CacheSet blocks were being allocated but never freed.
Used vector to avoid using pure C array.

Change-Id: I6f32fa5a305ff4e1d7602535026c1396764102ed
Reviewed-on: https://gem5-review.googlesource.com/8603
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Make cache warmup percentage a parameter.

The warmupPercentage is the percentage of different tags (based on the
cache size) that need to be touched in order to warm up the cache.
If Warmup failed (i.e., not enough tags were touched), warmup_cycle = 0.

The warmup is not being taken into account to calculate the stats (i.e.,
stats acquisition starts before cache is warmed up). Maybe in the future
this functionality should be added.

Change-Id: I2b93a99c19fddb99a4c60e6d4293fa355744d05e
Reviewed-on: https://gem5-review.googlesource.com/8061
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Remove extra numSets zero check.

numSets is unsigned, so it cannot be lower than 0. Besides, isPowerOf2(0)
is false by definition (and implemmentation*), so there is no need for the
double check.

* As presented in base/intmath.hh

Change-Id: I3f6296694a937434feddc7ed21f11c2a6fdfc5a9
Reviewed-on: https://gem5-review.googlesource.com/7901
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

mem: Standardize mem folder header guards

Standardize all header guards in the mem directory according to the most
frequent patterns. In general they have the form:
mem: __FOLDER_TREE_FILE_NAME_HH__
ruby: __FOLDER_TREE_FILENAME_HH__

Change-Id: I983853e292deb302becf151bf0e970057dc24774
Reviewed-on: https://gem5-review.googlesource.com/7881
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

misc: Rename misc.(hh|cc) to logging.(hh|cc)

These files aren't a collection of miscellaneous stuff, they're the
definition of the Logger interface, and a few utility macros for
calling into that interface (panic, warn, etc.).

Change-Id: I84267ac3f45896a83c0ef027f8f19c5e9a5667d1
Reviewed-on: https://gem5-review.googlesource.com/6226
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>

mem: Make blkAlign a common function between all tag classes

blkAlign was defined as a separate function in the base associative
and fully-associative tags classes although both functions implemented
identical functionality. This patch moves the blkAlign in the base
tags class.

Change-Id: I3d415d0e62bddeec7ce0d559667e40a8c5fdc2d4
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>

mem: Remove unused size field from the CacheBlk class

Change-Id: I6149290d6d2ac1a4bd6165871c93d7b7d6a980ad
Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>

mem: Remove unused arguments (asid/contex_id) from accessBlock

Change-Id: I79c2662fc81630ab321db8a75be6cd15fa07d372
Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>

mem: Remove unused type BlkList from the cache and the tags

Change-Id: If9ebb8488e8db587482ecfa99d2c12cfe5734fb9
Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>

mem: Remove unused functions from the tag classes

Change-Id: I4f3c2c027b1acaaf791a4c71086f34a9b9fbf4df
Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>

mem: Split the hit_latency into tag_latency and data_latency

If the cache access mode is parallel, i.e. "sequential_access" parameter
is set to "False", tags and data are accessed in parallel. Therefore,
the hit_latency is the maximum latency between tag_latency and
data_latency. On the other hand, if the cache access mode is
sequential, i.e. "sequential_access" parameter is set to "True",
tags and data are accessed sequentially. Therefore, the hit_latency
is the sum of tag_latency plus data_latency.

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>

sim: Call regStats of base-class as well

We want to extend the stats of objects hierarchically and thus it is necessary
to register the statistics of the base-class(es), as well. For now, these are
empty, but generic stats will be added there.

Patch originally provided by Akash Bagdia at ARM Ltd.

mem: fix headers include order in the cache related classes

Change-Id: Ia57cc104978861ab342720654e408dbbfcbe4b69
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

mem: change NULL to nullptr in the cache related classes

Change-Id: I5042410be54935650b7d05c84d8d9efbfcc06e70
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

mem: fix the line length in the cache related classes

Change-Id: I6d1feb164a958dde0da87a1cd2698096112c4a82
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

misc: Appease clang static analyzer

A few minor fixes to issues identified by the clang static analyzer.

misc: Add explicit overrides and fix other clang >= 3.5 issues

This patch adds explicit overrides as this is now required when using
"-Wall" with clang >= 3.5, the latter now part of the most recent
XCode. The patch consequently removes "virtual" for those methods
where "override" is added. The latter should be enough of an
indication.

As part of this patch, a few minor issues that clang >= 3.5 complains
about are also resolved (unused methods and variables).

misc: Remove redundant compiler-specific defines

This patch moves away from using M5_ATTR_OVERRIDE and the m5::hashmap
(and similar) abstractions, as these are no longer needed with gcc 4.7
and clang 3.1 as minimum compiler versions.

mem: Tidy up CacheSet

Minor tweaks and house keeping.

arm, mem: Remove unused CLEAR_LL request flag

Cleaning up dead code. The CLREX stores zero directly to
MISCREG_LOCKFLAG and so the request flag is no longer needed. The
corresponding functionality in the cache tags is also removed.

mem: Make caches way aware

This patch makes cache sets aware of the way number. This enables
some nice features such as the ablity to restrict way allocation. The
implemented mechanism allows to set a maximum way number to be
allocated 'k' which must fulfill 0 < k <= N (where N is the number of
ways). In the future more sophisticated mechasims can be implemented.

mem: Remove templates in cache model

This patch changes the cache implementation to rely on virtual methods
rather than using the replacement policy as a template argument.

There is no impact on the simulation performance, and overall the
changes make it easier to modify (and subclass) the cache and/or
replacement policy.

mem: Clarify usage of latency in the cache

This patch adds some much-needed clarity in the specification of the
cache timing. For now, hit_latency and response_latency are kept as
top-level parameters, but the cache itself has a number of local
variables to better map the individual timing variables to different
behaviours (and sub-components).

The introduced variables are:
- lookupLatency: latency of tag lookup, occuring on any access
- forwardLatency: latency that occurs in case of outbound miss
- fillLatency: latency to fill a cache block
We keep the existing responseLatency

The forwardLatency is used by allocateInternalBuffer() for:
- MSHR allocateWriteBuffer (unchached write forwarded to WriteBuffer);
- MSHR allocateMissBuffer (cacheable miss in MSHR queue);
- MSHR allocateUncachedReadBuffer (unchached read allocated in MSHR
queue)
It is our assumption that the time for the above three buffers is the
same. Similarly, for snoop responses passing through the cache we use
forwardLatency.

mem: Dynamically determine page bytes in memory components

This patch takes a step towards an ISA-agnostic memory
system by enabling the components to establish the page size after
instantiation. The swap operation in the memory is now also allowing
any granularity to avoid depending on the IntReg of the ISA.

misc: Remove assertions ensuring unsigned values >= 0

misc: Fix a number of unitialised variables and members

Static analysis unearther a bunch of uninitialised variables and
members, and this patch addresses the problem. In all cases these
omissions seem benign in the end, but at least fixing them means less
false positives next time round.

mem: Properly set cache block status fields on writebacks

When a cacheline is written back to a lower-level cache,
tags->insertBlock() sets various status parameters. However these
status bits were cleared immediately after calling. This patch makes
it so that these status fields are not cleared by moving them outside
of the tags->insertBlock() call.

mem: refactor LRU cache tags and add random replacement tags

this patch implements a new tags class that uses a random replacement policy.
these tags prefer to evict invalid blocks first, if none are available a
replacement candidate is chosen at random.

this patch factors out the common code in the LRU class and creates a new
abstract class: the BaseSetAssoc class. any set associative tag class must
implement the functionality related to the actual replacement policy in the
following methods:

accessBlock()
findVictim()
insertBlock()
invalidate()

mem: Remove redundant findVictim() input argument
The patch
(1) removes the redundant writeback argument from findVictim()
(2) fixes the description of access() function

Committed by: Nilay Vaish <nilay@cs.wisc.edu>

mem: Add support for a security bit in the memory system

This patch adds the basic building blocks required to support e.g. ARM
TrustZone by discerning secure and non-secure memory accesses.

Cache: Collect very basic stats on tag and data accesses

Adds very basic statistics on the number of tag and data accesses within the
cache, which is important for power modelling. For the tags, simply count
the associativity of the cache each time. For the data, this depends on
whether tags and data are accessed sequentially, which is given by a new
parameter. In the parallel case, all data blocks are accessed each time, but
with sequential accesses, a single data block is accessed only on a hit.

mem: per-thread cache occupancy and per-block ages

This patch enables tracking of cache occupancy per thread along with
ages (in buckets) per cache blocks. Cache occupancy stats are
recalculated on each stat dump.

arch: Resurrect the NOISA build target and rename it NULL

This patch makes it possible to once again build gem5 without any
ISA. The main purpose is to enable work around the interconnect and
memory system without having to build any CPU models or device models.

The regress script is updated to include the NULL ISA target. Currently
no regressions make use of it, but all the testers could (and perhaps
should) transition to it.

mem: Set the cache line size on a system level

This patch removes the notion of a peer block size and instead sets
the cache line size on the system level.

Previously the size was set per cache, and communicated through the
interconnect. There were plenty checks to ensure that everyone had the
same size specified, and these checks are now removed. Another benefit
that is not yet harnessed is that the cache line size is now known at
construction time, rather than after the port binding. Hence, the
block size can be locally stored and does not have to be queried every
time it is used.

A follow-on patch updates the configuration scripts accordingly.

mem: Reorganize cache tags and make them a SimObject

This patch reorganizes the cache tags to allow more flexibility to
implement new replacement policies. The base tags class is now a
clocked object so that derived classes can use a clock if they need
one. Also having deriving from SimObject allows specialized Tag
classes to be swapped in/out in .py files.

The cache set is now templatized to allow it to contain customized
cache blocks with additional informaiton. This involved moving code to
the .hh file and removing cacheset.cc.

The statistics belonging to the cache tags are now including ".tags"
in their name. Hence, the stats need an update to reflect the change
in naming.

mem: Adding verbose debug output in the memory system

This patch provides useful printouts throughut the memory system. This
includes pretty-printed cache tags and function call messages
(call-stack like).

scons: Fix up numerous warnings about name shadowing

This patch address the most important name shadowing warnings (as
produced when using gcc/clang with -Wshadow). There are many
locations where constructor parameters and function parameters shadow
local variables, but these are left unchanged.

mem: Remove the IIC replacement policy

The IIC replacement policy seems to be unused and has probably
gathered too much bit rot to be useful. This patch removes the IIC and
its associated cache parameters.

mem: Add support for writing back and flushing caches

This patch adds support for the following optional drain methods in
the classical memory system's cache model:

memWriteback() - Write back all dirty cache lines to memory using
functional accesses.

memInvalidate() - Invalidate all cache lines. Dirty cache lines
are lost unless a writeback is requested.

Since memWriteback() is called when checkpointing systems, this patch
adds support for checkpointing systems with caches. The serialization
code now checks whether there are any dirty lines in the cache. If
there are dirty lines in the cache, the checkpoint is flagged as bad
and a warning is printed.

sim: Include object header files in SWIG interfaces

When casting objects in the generated SWIG interfaces, SWIG uses
classical C-style casts ( (Foo *)bar; ). In some cases, this can
degenerate into the equivalent of a reinterpret_cast (mainly if only a
forward declaration of the type is available). This usually works for
most compilers, but it is known to break if multiple inheritance is
used anywhere in the object hierarchy.

This patch introduces the cxx_header attribute to Python SimObject
definitions, which should be used to specify a header to include in
the SWIG interface. The header should include the declaration of the
wrapped object. We currently don't enforce header the use of the
header attribute, but a warning will be generated for objects that do
not use it.

Fix: Address a few minor issues identified by cppcheck

This patch addresses a number of smaller issues identified by the code
inspection utility cppcheck. There are a number of identified leaks in
the arm/linux/system.cc (although the function only get's called once
so it is not a major problem), a few deletes in dev/x86/i8042.cc that
were not array deletes, and sprintfs where the character array had one
element less than needed. In the IIC tags there was a function
allocating an array of longs which is in fact never used.

Mem: Use cycles to express cache-related latencies

This patch changes the cache-related latencies from an absolute time
expressed in Ticks, to a number of cycles that can be scaled with the
clock period of the caches. Ultimately this patch serves to enable
future work that involves dynamic frequency scaling. As an immediate
benefit it also makes it more convenient to specify cache performance
without implicitly assuming a specific CPU core operating frequency.

The stat blocked_cycles that actually counter in ticks is now updated
to count in cycles.

As the timing is now rounded to the clock edges of the cache, there
are some regressions that change. Plenty of them have very minor
changes, whereas some regressions with a short run-time are perturbed
quite significantly. A follow-on patch updates all the statistics for
the regressions.

MEM: Put memory system document into doxygen

clang: Fix issues identified by the clang static analyzer

This patch addresses a few minor issues reported by the clang static
analyzer.

The analysis was run with:

scan-build -disable-checker deadcode \
-enable-checker experimental.core \
-disable-checker experimental.core.CastToStruct \
-enable-checker experimental.cpluscplus

Cache: Split invalidateBlk up to seperate block vs. tags

This seperates the functionality to clear the state in a block into
blk.hh and the functionality to udpate the tag information into the
tags. This gets rid of the case where calling invalidateBlk on an
already-invalid block does something different than calling it on a
valid block, which was confusing.

Param: Transition to Cycles for relevant parameters

This patch is a first step to using Cycles as a parameter type. The
main affected modules are the CPUs and the Ruby caches. There are
definitely plenty more places that are affected, but this patch serves
as a starting point to making the transition.

An important part of this patch is to actually enable parameters to be
specified as Param.Cycles which involves some changes to params.py.

Fix: Address a few benign memory leaks

This patch is the result of static analysis identifying a number of
memory leaks. The leaks are all benign as they are a result of not
deallocating memory in the desctructor. The fix still has value as it
removes false positives in the static analysis.

Cache: Fix the LRU policy for classic memory hierarchy

The LRU policy always evicted the least recently touched way, even if it
contained valid data and another way was invalid, as can happen if a block has
been invalidated by coherance. This can result in caches never warming up even
though they are replacing blocks. This modifies the LRU policy to move blocks
to LRU position on invalidation.

MEM: Remove the Broadcast destination from the packet

This patch simplifies the packet by removing the broadcast flag and
instead more firmly relying on (and enforcing) the semantics of
transactions in the classic memory system, i.e. request packets are
routed from a master to a slave based on the address, and when they
are created they have neither a valid source, nor destination. On
their way to the slave, the request packet is updated with a source
field for all modules that multiplex packets from multiple master
(e.g. a bus). When a request packet is turned into a response packet
(at the final slave), it moves the potentially populated source field
to the destination field, and the response packet is routed through
any multiplexing components back to the master based on the
destination field.

Modules that connect multiplexing components, such as caches and
bridges store any existing source and destination field in the sender
state as a stack (just as before).

The packet constructor is simplified in that there is no longer a need
to pass the Packet::Broadcast as the destination (this was always the
case for the classic memory system). In the case of Ruby, rather than
using the parameter to the constructor we now rely on setDest, as
there is already another three-argument constructor in the packet
class.

In many places where the packet information was printed as part of
DPRINTFs, request packets would be printed with a numeric "dest" that
would always be -1 (Broadcast) and that field is now removed from the
printing.

mem: fix cache stats to use request ids correctly

This patch fixes the cache stats to use the new request ids.
Cache stats also display the requestor names in the vector subnames.
Most cache stats now include "nozero" and "nonan" flags to reduce the
amount of excessive cache stat dump. Also, simplified
incMissCount()/incHitCount() functions.

mem: Add a master ID to each request object.

This change adds a master id to each request object which can be
used identify every device in the system that is capable of issuing a request.
This is part of the way to removing the numCpus+1 stats in the cache and
replacing them with the master ids. This is one of a series of changes
that make way for the stats output to be changed to python.

clang: Enable compiling gem5 using clang 2.9 and 3.0

This patch adds the necessary flags to the SConstruct and SConscript
files for compiling using clang 2.9 and later (on Ubuntu et al and OSX
XCode 4.2), and also cleans up a bunch of compiler warnings found by
clang. Most of the warnings are related to hidden virtual functions,
comparisons with unsigneds >= 0, and if-statements with empty
bodies. A number of mismatches between struct and class are also
fixed. clang 2.8 is not working as it has problems with class names
that occur in multiple namespaces (e.g. Statistics in
kernel_stats.hh).

clang has a bug (http://llvm.org/bugs/show_bug.cgi?id=7247) which
causes confusion between the container std::set and the function
Packet::set, and this is currently addressed by not including the
entire namespace std, but rather selecting e.g. "using std::vector" in
the appropriate places.

GCC: Get everything working with gcc 4.6.1.

And by "everything" I mean all the quick regressions.

scons: rename TraceFlags to DebugFlags

stats: rename stats so they can be used as python expressions

trace: reimplement the DTRACE function so it doesn't use a vector
At the same time, rename the trace flags to debug flags since they
have broader usage than simply tracing. This means that
--trace-flags is now --debug-flags and --trace-help is now --debug-help

includes: sort all includes

Replace curTick global variable with accessor functions.
This step makes it easy to replace the accessor functions
(which still access a global variable) with ones that access
per-thread curTick values.

SCons: Support building without an ISA