mem-cache: Fix BDI size calculation

The bitmask field indicates to which base a delta refers, and in
the original paper it is fixed and proportional to the highest
number of bases allowed in the compressed data.

Change-Id: I271bf2e19e0765de52b933eaf6d4fcc2ce25d185
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19748
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Use SatCounter for RRPV

Use SatCounter in RRIP's RRPV. As such, move validation functionality
to a proper variable.

Change-Id: I142db2b7f6cd518ac3a2b68c9ed48005402b3464
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20452
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem: Eliminate the Base(Slave|Master)Port classes.

The Port class has assumed all the duties of the less generic
Base*Port classes, making them unnecessary. Since they don't add
anything but make the code more complex, this change eliminates them.

Change-Id: Ibb9c56def04465f353362595c1f1c5ac5083e5e9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20236
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

mem-cache: Fix non-virtual base destructor of Repl Entry

ReplaceableEntry contains a virtual method, yet its destructor
was not virtual, causing errors in some compilers.

Change-Id: I13deec843f4007d9deb924882a8d98ff6a89c84f
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19808
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: mark block as dirty when handling SW prefetch

This addresses the issue described in
64687ee mem-cache: Mark block as dirty after a SWPrefetchEXResp.

Previous patch misses cases when the prefetch response is ReadExResp or
UpgradeResp. Also, marking the block as dirty in serviceMSHRTargets
instead of in handleFill covers cases when the prefetch is coalesced with
other requests.

Change-Id: I2b377fdd240eb0f09e720b6bb284dee6545925ce
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19688
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Fix set and way of sub-entries

Set and way of sub-entries were not being set previously.
They must be set after the sub-blocks have been assigned
to the main block.

Change-Id: I7b6921b8437b29c472d691cd78cf20f2bb6c7e07
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19669
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Create CPack compressor

Implementation of C-Pack, as described in "C-Pack: A High-
Performance Microprocessor Cache Compression Algorithm".

C-Pack uses pattern matching schemes to detect and compress
frequently appearing data patterns. As in the original paper,
it divides the input in 32-bit words, and uses 6 patterns to
match with its dictionary.

For the patterns, each letter represents a byte: Z is a null
byte, M is a dictionary match, X is a new value. The patterns
are ZZZZ, XXXX, MMMM, MMXX, ZZZX, MMMX.

Change-Id: I2efc9db2c862620dcc1155300e39be558f9017e0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11105
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

Revert "mem-cache: Remove writebacks packet list"

This reverts commit bf0a722acdd8247602e83720a5f81a0b69c76250.

Reason for revert: This patch introduces a bug:

The problem here is that the insertion of block A may cause the
eviction of block B, which on the lower level may cause the
eviction of block A. Since A is not marked as present yet, A is
"safely" removed from the snoop filter

However, by reverting it, using atomic and a Tags sub-class that
can generate multiple evictions at once becomes broken when using
Atomic mode and shall be fixed in a future patch.

Change-Id: I5b27e54b54ae5b50255588835c1a2ebf3015f002
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19088
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Accuracy-based rate control for prefetchers

Added a mechanism to control the number of prefetches generated
based in the effectiveness of the prefetches generated so far.

Change-Id: I33af82546f74a5b5ab372c28574b76dd9a1bd46a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18808
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Support for page crossing prefetches

Prefetchers can now issue hardware prefetch requests that go beyond
the boundaries of the system page. Page crossing references will need
to look up the TLBs to be able to compute the physical address to be
prefetched.

Change-Id: Ib56374097e3b7dc87414139d210ea9272f96b06b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/14620
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Add multi-prefetcher adaptor

This patch adds a meta-prefetcher that enables gem5's cache models to
connect to multiple prefetchers. Sub-prefetchers still use the
probes-based interface and training can be controlled
independently. However, when the cache requests a prefetch packet, the
adaptor traverses the priority list of prefetchers and uses the first
prefetcher that is able to generate a prefetch.

Kudos to Mitch Hayenga for the original version of this patch.

Change-Id: I25569a834997e5404c7183ec995d212912c5dcdf
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18868
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch, base, cpu, dev, mem, sim: Remove #if 0-ed out code.

This code will be preserved through version control, but otherwise
creates clutter and will rot in place since it's never compiled.

Change-Id: Id265f6deac445116843956ea5cf1210d8127274e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18608
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Use SatCounter for prefetchers

Many prefetchers re-implement saturating counters with ints. Make
them use SatCounters instead.

Added missing operators and constructors to SatCounter for that to
be possible and their respective tests.

Change-Id: I36f10c89c27c9b3d1bf461e9ea546920f6ebb888
Signed-off-by: Daniel <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17995
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Javier Bueno Hedo <javier.bueno@metempsy.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

cpu,mem: Add support for partial loads/stores and wide mem. accesses

This changeset adds support for partial (or masked) loads/stores, i.e.
loads/stores that can disable accesses to individual bytes within the
target address range. In addition, this changeset extends the code to
crack memory accesses across most CPU models (TimingSimpleCPU still
TBD), so that arbitrarily wide memory accesses are supported. These
changes are required for supporting ISAs with wide vectors.

Additional authors:
- Gabor Dozsa <gabor.dozsa@arm.com>
- Tiago Muck <tiago.muck@arm.com>

Change-Id: Ibad33541c258ad72925c0b1d5abc3e5e8bf92d92
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13518
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Remove writebacks packet list

Previously all atomic writebacks concerned a single block,
therefore, when a block was evicted, no other block would be
pending eviction. With sector tags (and compression),
however, a single replacement can generate many evictions.

This can cause problems, since a writeback that evicts a block
may evict blocks in the lower cache. If one of these conflict
with one of the blocks pending eviction in the higher level, the
snoop must inform it to the lower level. Since atomic mode does
not have a writebuffer, this kind of conflict wouldn't be noticed.

Therefore, instead of evicting multiple blocks at once, we
do it one by one.

Change-Id: I2fc2f9eb0f26248ddf91adbe987d158f5a2e592b
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18209
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Handle data expansion

When a block in compressed form is overwriten, it may change
its size. If the new compressed size is bigger, and the total
size becomes bigger than the block size, one or more blocks
will have to be evicted. This is called data expansion, or
fat writes.

This change assumes that a first level cache cannot have a
compressor, since otherwise data expansion should have been
handled for atomic operations and writes. As such, data
expansions should only be seen on writebacks. As writebacks
are forwarded to the next level when failed, there should
be no data expansions when servicing misses either.

This patch adds the functionality to handle data expansions
by evicting the co-allocated blocks to make room for an
expanded block.

Change-Id: I0bd77bf6446bfae336889940b2f75d6f0c87e533
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12087
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Add co-allocation function to compressed tags

Implement a co-allocation function in compressed tags, so
that compressed blocks can be co-allocated in a superblock.
Co-allocation is possible when compression ratio (CR) blocks
that share a superblock tag can be compressed to up to (100/CR)%
of their size.

Change-Id: I937cc1fcbb488e70309cb5478c12db65f1b4b23f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11411
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Add compression and decompression calls

Add a compressor to the base cache class and compress within
block allocation and decompress on writebacks.

This change does not implement data expansion (fat writes) yet,
nor it adds the compression latency to the block write time.

Change-Id: Ie36db65f7487c9b05ec4aedebc2c7651b4cb4821
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11410
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Create BDI Compressor

Implement Base-Delta-Immediate compression, as described in
'Base-Delta-Immediate Compression: Practical Data Compression
for On-Chip Caches'

Change-Id: I7980c340ab53a086b748f4b2108de4adc775fac8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11412
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Add compression stats

Add compression statistics to the compressors. It tracks
the number of blocks that can fit into a certain power
of two size, and the number of decompressions.

For example, if a block is compressed to 100 bits, it will
belong to the 128-bits compression size. Although it could
also fit bigger sizes, they are not taken into account for
the stats (i.e., the 100-bit compression will fit only the
128-bits size, not 256 or higher).

We save stats for compressions that fail (i.e., compressed
size is bigger than original cache line size).

Change-Id: Idab71a40a660e33259908ccd880e42a880b5ee06
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11103
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Create cache compressor

Create basic template for cache compressors. A basic compressor
must implement a compression and a decompression method.

Change-Id: I83dc4d2b8d2bc5ed9f760c938edfa4ebdd6b8583
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11100
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Add block size to findVictim

Add block size to findVictim. For standard caches it
will not be used. Compressed caches, however, need to
know the size of the compressed block to decide whether
a block is co-allocatable or not.

Change-Id: Id07f79763687b29f75d707c080fa9bd978a408aa
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11198
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Mohammad Seyedzadeh <sm.seyedzade@gmail.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Add compression data to CompressionBlk

Add a compression bit, decompression latency and compressed
block size and their respective getters and setters.

Change-Id: Ia9d8656552d60e8d4e85fe5379dd75fc5adb0abe
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11102
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Create CacheComp debug flag

Create a debug flag for cache compression.

Change-Id: Id4b8e86d658d3aa550906ee0f8da3b54f4cdab7d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11104
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem-cache: Stub compression framework

Create a stub of a compression framework where we can have
multiple data blocks per tag entry. Only consecutive blocks
can share a tag as of now.

For each tag entry there can be multiple data blocks. We have
the same number of tags a conventional cache would have, but
we instantiate the maximum number of data blocks (according to
the compression ratio) per tag, to virtually implement
compression without increasing the complexity of the simulator.

Change-Id: I549940c7afb2f744ab293ff8bb283967e7551a11
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/10763
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Mark block as dirty after a SWPrefetchEXResp

This is a workaround for a bug introduced from the change:
59e3585a8 arch-arm: We add PRFM PST instruction for arm
which can cause deadlocks in the memory system.

The design of the classic memory system in gem5 makes the folloing two
assumptions:
* A cache that fetches a block with an intention to modify it, becomes
the point of ordering and therefore commits to respond to any snoop
requests [1].
* A cache that fetches an exclusive copy of the block, does so with
the intention to modify it [2]. Immediately after it receives the
block, it will write to it and mark it as dirty. As the point of
ordering, it responds to any outstanding snoops.

The current implementation of prefetch exclusive request breaks the
second assumption. A cache can fetch an exclusive block without an
immediate intention to modify it. If the block is not modified, it
will not be marked as dirty. However, the cache has committed to
respond to outstanding snoops, and if the block is clean it
won't. This can result in deadlocks where a snoop gets stuck waiting
for responses.

One solution (implemented by this patch) is to unconditionally mark
the block dirty when filling due to a prefetch exclusive request.
This makes the PrefetchExReq behave like a WriteReq. However, as it
may mark as dirty a clean block, it creates the requirement for an
uncessary WritebackDirty in the future. In practice, this shouldn't be
a big problem unless the application is unnecessarily using prefetch
exclusive instructions.

Other solutions, would require deeper changes to the design of the
memory system to handle this properly.

[1]: When a cache commits to respond, it "informs" the xbar/PoC (point
of coherence) and the other caches of its intention to respond. As a
result the request will not be send to the main memory.
[2]: In fact the assumption is that in the needsWritable MSHR there is
at least one WriteReq before any snoops from other caches.

Change-Id: I378d3c0dadf25fc52e430b67102347b44d2f18ea
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17729
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>

mem: Minimize the use of MemObject.

MemObject doesn't provide anything beyond its base ClockedObject any
more, so this change removes it from most inheritance hierarchies.
Occasionally MemObject is replaced with SimObject when I was fairly
confident that the extra functionality of ClockedObject wasn't needed.

Change-Id: Ic014ab61e56402e62548e8c831eb16e26523fdce
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18289
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>

cpu,mem: missing override specifier

Change-Id: I731d3ef021596450ac307461f215760a148bb28a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18348
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Fix fix of replacement count

Commit 7976b561de61b7523ca9a860154ad7ba701d12a7 tried fixing
replacement update when a single location can be associated to
multiple blocks.

Although the comment of the correct action was added, the proper
validation check was forgotten. This change adds that check and
moves doing the eviction to when there is a valid block.

Change-Id: I31d8bb914ccfd1849e9d97464d70a58a62f59533
Signed-off-by: Daniel <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18210
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Fix increasing replacement count

Replacements should be increased when there is any evicted
block, which does not necessarily have to be the victim.

For example, assume a superblock contains 4 blocks, and both
A and C are stored compressed (belonging to SB_1). Then F,
from SB2 needs to make room by replacing SB1. If F map to
location 2, the number of replacements should be increased,
even though 2 had no valid blocks:

Tag Data Tag Data
|SB_1|--|A|X|C|X| --> |SB_2| |X|F|X|X|
1 2 3 4 1 2 3 4

Change-Id: I7b3735d28a35faa8d8fa613a1555bb258da65859
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18208
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem-cache: Remove blk_addr from Queue::trySatisfyFunctional

The blk_addr is pkt->getBlockAddr(), and therefore can be
acquired internally, when needed, as long as the pkt is
provided.

Change-Id: I2780445d2a0cb9e27257961efc4f438cc19550e5
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17537
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Add match functions to QueueEntry

Having the caller decide the matching logic is error-prone, and
frequently ends up with the secure bit being forgotten. This
change adds matching functions to the QueueEntry to avoid this
problem.

As a side effect the signature of findPending has been changed.

Change-Id: I6e494a821c1e6e841ab103ec69632c0e1b269a08
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17530
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem: Add packet matching functions

Add both block and non-block-aligned packet matching functions,
so that both address and secure bits are checked when checking
whether a packet matches a request.

Change-Id: Id0069befb925d112e06f250741cb47d9dfa249cc
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17533
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Move Target to QueueEntry

WriteQueueEntry's target has 100% functionality overlap with MSHR's,
therefore make it base to MSHR::Target.

Change-Id: I48614e78179d708bd91bbe75a752e5a05146e8eb
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17534
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Assert Entry inherits from QueueEntry in Queue

Queue has several assumptions regarding its template parameter,
so make sure they are fulfilled by forcing Entry to be derived
from QueueEntry.

Change-Id: I0203a62aec00c04ac89e9674d86a44a07f9f13ab
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17529
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Fix RRPV for RRIP

The RRPV values for RRIP and NRU replacment policies.
Long re-rereference interval was used instead of
distant re-rereference interval and vice-versa.
The btp value permit to choose beetwen distant and
long insertion ratio. A btp value of 0 force the
policy to always insert at a distant re-reference
interval and a btp value of 100 force the policy to
always insert at a long (intermediate) re-rereference
interval.

Change-Id: I516098f73942b769dcc31fe0edfe07c3e9c3effd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17851
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Fix MSHR handling of cache clean requests

Previously satisfied clean requests would not snoop in-service
MSHRs. This is a problem when a clean request is also invalidating, in
which case we have to post-invalidate or post-downgrade outstanding
requests. This changes fixes this bug.

Change-Id: I31e42aa94dd3637b2818e00fbaae68c810145eaf
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17728
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

mem-cache: ambiguous use of abs function

std::abs doesn't accept unsigned long long, generating the error:

error: call to 'abs' is ambiguous

Use instead a compare-and-subtract idiom.

Also, Changed return type of distanceFromTrigger from unsigned int to Addr to
prevent overflow problems.

Change-Id: Ia7752c1c7a838f98e8c7ed6ade9f586f31bbcf7d
Signed-off-by: Ryan Gambord <gambordr@oregonstate.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17788
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: AMPM Prefetcher fails when restoring from a checkpoint

The preriodic event triggers an assertion due to an incorrect tick value to
schedule when restoring from a checkpoint.

Change-Id: I9454dd0c97d5a098f8a409886e63f7a7e990947c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17732
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Fix PIF prefetcher compilation error with NULL ISA

Referencing BaseCPU is causing a compilation error when using the NULL ISA.
This patch changes the reference to a SimObject, which fixes the problem.

Change-Id: I2530486cab65974f5b83e54a733c4b0e98730d26
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17731
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: ISB prefetcher was triggering an assertion

An assertion ignored the case when an entry of the SP table had been invalidated.

Change-Id: I5bf04e7a0979300b0f41f680c371f6397d4cbf3f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17734
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Fix panic in Indirect Memory prefetcher

Memory requests with a size non-power-of-two and less than 8 values were causing
a panic, but there these should be allowed and ignored by the prefetcher.

Change-Id: I86baa60058cc8a7f232d6ba5748d4c24a463c840
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17733
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Proactive Instruction Fetch Implementation

Ferdman, M., Kaynak, C., & Falsafi, B. (2011, December).
Proactive instruction fetch. In Proceedings of the 44th Annual IEEE/ACM
International Symposium on Microarchitecture (pp. 152-162). ACM.

Change-Id: I38c3ab30a94ab279f03e3d5936ce8ed118310c0e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16968
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Remove extra cache header from AMAP

The cache header was being included in the AMAP, although not
used, which resulted in slightly longer compilation time.

Change-Id: I3654bc719c6b5f558af116addae159301602a3cf
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17711
Reviewed-by: Javier Bueno Hedo <javier.bueno@metempsy.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Added the STeMS prefetcher

Reference:
Stephen Somogyi, Thomas F. Wenisch, Anastasia Ailamaki, and
Babak Falsafi. 2009. Spatio-temporal memory streaming.
In Proceedings of the 36th annual international symposium on
Computer architecture (ISCA '09). ACM, New York, NY, USA, 69-80.

Change-Id: I58cea1a7faa9391f8aa4469eb4973feabd31097a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16423
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

arch, cpu, dev, gpu, mem, sim, python: start using getPort.

Replace the getMasterPort, getSlavePort, and getEthPort functions
with getPort, and remove extraneous mechanisms that are no longer
necessary.

Change-Id: Iab7e3c02d2f3a0cf33e7e824e18c28646b5bc318
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17040
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

mem-cache: tautological comparison of byteOrder

Error:
build/X86/mem/cache/prefetch/indirect_memory.cc:56:24:
error: result of comparison of constant -1 with expression
of type 'const ByteOrder' is always false
[-Werror,-Wtautological-constant-out-of-range-compare]
fatal_if(byteOrder == -1, "This prefetcher requires a defined ISA\n");
~~~~~~~~~ ^ ~~
build/X86/base/logging.hh:205:14: note: expanded from macro 'fatal_if'
if ((cond)) { \
^~~~
1 error generated.

Fix:
cast of constant (-1) used in comparison

Change-Id: I3deb154c2fe5b92c4ddf499176cb185c4ec7cf64
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17388
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Added the Indirect Memory Prefetcher

Reference:
Xiangyao Yu, Christopher J. Hughes, Nadathur Satish, and Srinivas Devadas.
2015. IMP: indirect memory prefetcher. In Proceedings of the 48th
International Symposium on Microarchitecture (MICRO-48). ACM,
New York, NY, USA, 178-190. DOI: https://doi.org/10.1145/2830772.2830807

Change-Id: I52790f69c13ec55b8c1c8b9396ef9a1fb1be9797
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16223
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Fix write hit latency calculation order

Patch 6d8694a5fb5cfb905186249581cc6a3fde6cc38a changes the order
at which the access latency is calculated for hits. This order
is incorrect, since the calculations must use the blk's whenReady
value before the access is satisfied.

Change-Id: I30dae5435f54200cc8fdf71fd0dbd2cf9c6f8b17
Signed-off-by: Daniel <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17190
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Removed default arg from get() in prefetch/base.hh

commit b0d1643 caused building against NULL to break due to
NULLIsa::GuestByteOrder not being defined.

Removal of default argument in src/mem/cache/prefetch/base.hh fixes
this.

Change-Id: I99a4abb4be1418fadec145481164f7caa3334ca0
Signed-off-by: Ryan Gambord
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17070
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Revert "mem-cache: Remove Packet dependency in Tags"

Reverting patch due to polymorphism limitations.

This reverts commit 86a54d91936b524c0ef0f282959f0fc29bafe7eb.

Change-Id: Ie032dcc5176448c62118c89732b3cc6b8efd5a13
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17049
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Added extra information to PrefetchInfo

Added additional information to the PrefetchInfo data structure
- Whether the event is triggered by a cache miss
- Whether the event is a write or a read
- Size of the data accessed
- Data accessed by the request

Change-Id: I070f3ffe837ea960a357388e7f2b8a61d7b2196c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16583
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Add header delay to handleFill whenReady

A prefetch response will have a header delay, which was not being
taken into account.

Change-Id: I66a071bc81ef41b8c0de37aa2df75171d1979a6f
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/14895
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Allow tag-only accesses on latency calculation

Some accesses only need to search for a tag in the tag array, with
no need to touch the data array. This is the case for CleanEvicts,
evicts that don't find a corresponding block entry (since a write
cannot be done in parallel with tag lookup), and maintenance
operations.

Change-Id: I7365a915500b5d7ab636d49a9acc627072a7f58e
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/14878
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Add lookup latency to access' whenReady

When dealing with writebacks, as soon as the packet metadata arrives
there will be a tag lookup, done sequentially because a write can't
be done in parallel. While the tag lookup is being done, the payload
will arrive. When both the payload are present and the tag is correct
block entry is determined the fill happens.

Change-Id: If1a0085d742458b675bfc012b6d908d9d9a25e32
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/14877
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Fix recvTimingReq doWritebacks tick

Before being sent to the writebuffer, the evicted blocks
must be selected for replacement, and therefore the
access latency must be applied. The forward latency is
then applied on top of that delay.

Change-Id: I16a25a8bf6051f63eb7a02fe66acb6af26d434fc
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/14736
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Use header delay on latency calculation

Previously the bus delay was being ignored for the access latency
calculation, and then applied on top of the access latency. This
patch fixes the order, as first the packet must arrive before the
access starts.

Change-Id: I6d55299a911d54625c147814dd423bfc63ef1b65
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/14876
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Remove old todo about latency in hit function

The header and payload delay have already been accounted and
zeroed previous to calling this function. The probe is not
allowed to modify the packet, therefore no extra delays are
added, and it is safe to remove the todo note.

Change-Id: I8ddf7e189fbe609cdec34364f3c013427930daf7
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/14875
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Sandbox Based Optimal Offset Implementation

Brown, N. T., & Sendag, R. Sandbox Based Optimal Offset Estimation.

Change-Id: Ieb693b6b2c3d8bdfb6948389ca10e92c85454862
Reviewed-on: https://gem5-review.googlesource.com/c/15095
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Copy over flags to forwarded response

A cache that forwards a request to the memory below does not fill and
forwards the response with the data to cache above. This change
ensures that the flags of the original response are also preserved.

Change-Id: I244b20b073c31b976358816c5b14bba413b8271f
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/16182
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

mem-cache: added missing override specifier in BoP

Added missing specifier for various virtual functions.

Change-Id: I41aebb3b76bce6dd3bee21ac0e2b0e52cb90fc80
Reviewed-on: https://gem5-review.googlesource.com/c/16728
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: A Best-Offset Prefetcher

Michaud, P. (2015, June). A best-offset prefetcher.
In 2nd Data Prefetching Championship.

Change-Id: I61bb89ca5639356d54aeb04e856d5bf6e8805c22
Reviewed-on: https://gem5-review.googlesource.com/c/14820
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Add a mechanism to iterate all entries of an AssociativeSet

Added functions to obtain an iterator to access all entries of
an AssociativeSet container.

Change-Id: I1ec555bd97d97e3edaced2b8f61287e922279c26
Reviewed-on: https://gem5-review.googlesource.com/c/16582
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Added the Slim AMPM Prefetcher

Reference:
Towards Bandwidth-Efficient Prefetching with Slim AMPM.
Young, V., & Krishna, A. (2015). The 2nd Data Prefetching Championship.

Slim AMPM is composed of two prefetchers, the DPCT and the AMPM (both already
in gem5).

Change-Id: I6e868faf216e3e75231cf181d59884ed6f0d382a
Reviewed-on: https://gem5-review.googlesource.com/c/16383
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Irregular Stream Buffer Prefetcher

Based in the description of the following publication:
Akanksha Jain and Calvin Lin. 2013. Linearizing irregular memory accesses
for improved correlated prefetching. In Proceedings of the 46th Annual
IEEE/ACM International Symposium on Microarchitecture (MICRO-46). ACM,
New York, NY, USA, 247-259.

Change-Id: Ibeb6abc93ca40ad634df6ed5cf8becb0a49d1165
Reviewed-on: https://gem5-review.googlesource.com/c/15215
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

mem-cache: Added the Delta Correlating Prediction Tables Prefetcher

Reference:
Multi-level hardware prefetching using low complexity delta correlating
prediction tables with partial matching.
Marius Grannaes, Magnus Jahre, and Lasse Natvig. 2010.
In Proceedings of the 5th international conference on High Performance
Embedded Architectures and Compilers (HiPEAC'10)
Change-Id: I7b5d7ede9284862a427cfd5693a47652a69ed49d
Reviewed-on: https://gem5-review.googlesource.com/c/16062
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

python: Don't assume SimObjects live in the global namespace

The importer in Python 3 doesn't like the way we import SimObjects
from the global namespace. Convert the existing SimObject declarations
to import from m5.objects. As a side-effect, this makes these files
consistent with configuration files.

Change-Id: I11153502b430822130722839e1fa767b82a027aa
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15981
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

mem-cache: Updated version of the Signature Path Prefetcher

This implementation is based in the description available in:
Jinchun Kim, Seth H. Pugsley, Paul V. Gratz, A. L. Narasimha Reddy,
Chris Wilkerson, and Zeshan Chishti. 2016.
Path confidence based lookahead prefetching.
In The 49th Annual IEEE/ACM International Symposium on Microarchitecture
(MICRO-49). IEEE Press, Piscataway, NJ, USA, Article 60, 12 pages.

Change-Id: I4b8b54efef48ced7044bd535de9a69bca68d47d9
Reviewed-on: https://gem5-review.googlesource.com/c/14819
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem: Determine if a packet queue forces ordering at construction

A packet queue is typically used to hold on to packets that are
schedules to be sent in the future or when they need to queue behind
younger packets that have been sent out yet. Due to memory order
requirements, some MemObjects need to maintain the order for packet
(mostly responses) that reference the same cache block.

Prior to this patch the ordering requirements where determined when
the packet was scheduled to be sent. This patch moves the parameter to
the constructor.

Change-Id: Ieb4d94e86bc7514f5036b313ec23ea47dd653164
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15555
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem-cache: Access Map Pattern Matching Prefetcher

Implementation of the Access Map Pattern Matching prefetcher
Based in the description of the following paper:
Access map pattern matching for high performance data cache prefetch.
Ishii, Y., Inaba, M., & Hiraki, K. (2011).
Journal of Instruction-Level Parallelism, 13, 1-24.

Change-Id: I0d4b7f7afc2ab4938bdd8755bfed26e26a28530c
Reviewed-on: https://gem5-review.googlesource.com/c/15096
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Signature Path Prefetcher

Related paper:
Lookahead Prefetching with Signature Path
J Kim, PV Gratz, ALN Reddy
The 2nd Data Prefetching Championship (DPC2), 2015

Change-Id: I2319be2fa409f955f65e1bf1e1bb2d6d9a4fea11
Reviewed-on: https://gem5-review.googlesource.com/c/14737
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: allow prefetchers to emit page crossing references

QueuedPrefetcher takes the responsability to check for page
crossing references.

Change-Id: I0ae6bf8be465118990d9ea1cac0da8f70e69aeb1
Reviewed-on: https://gem5-review.googlesource.com/c/14735
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: virtual address support for prefetchers

Prefetchers can be configured to operate with virtual or physical addreses.
The option can be configured through the "use_virtual_addresses" parameter
of the Prefetcher object.

Change-Id: I4f8c3687988afecc8a91c3c5b2d44cc0580f72aa
Reviewed-on: https://gem5-review.googlesource.com/c/14416
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Workaround for setWhenReady assertion

Change 174da8e2da6a896d2e97bc264f9c827a0f4c35ac added an assert that
is not satisfiable with current implementation, breaking some
regression tests.

Change-Id: Ibafaf0c51906384364f0b2a4b931f8ec6126d858
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/14955
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Remove writebacks parameter from serviceMSHRTargets

Change 8ba77ae8fc98a355082da2bd9fdc6ecf4928f725 introduced the
writebacks parameter, but it was never used.

Change-Id: I225e5b399de42d77c72fc0012d3dc93ef39b8853
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/14896
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Add getter and setter to CacheBlk::whenReady

Add a getter and a setter function to access CacheBlk::whenReady
to encapsulate the variable and allow error checking. This error
checking consists on verifying that writes to a block after it
has been inserted follow a chronological order.

As a side effect, tickInserted retain its value until updated,
that is, it is not reset in invalidate().

Change-Id: Idc3c5a99c3f002ee9acc2424f00e554877fd3a69
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/14715
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Optimize sector valid and secure check

Previously a loop was being done to check whether the
block was valid/secure or not. Variables have been
added to skip this loop and save and update sector
block state when sub-blocks are validated, invalidated
and secured.

Change-Id: Ie1734f7dfda9698c7bf22a1fcbfc47ffb9239cea
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/14363
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

arch, base, cpu, gpu, mem: Replace assert(0 or false with panic.

Neither assert(0) nor assert(false) give any hint as to why control
getting to them is bad, and their more descriptive versions,
assert(0 && "description") and assert(false && "description"), jury
rig assert to add an error message when the utility function panic()
already does that directly with better formatting options.

This change replaces that flavor of call to assert with panic, except
in the actual code which processes the formatting that panic uses (to
avoid infinitely recurring error handling), and in some *.sm files
since I don't know what rules those have to follow and don't want to
accidentaly break them.

Change-Id: I8addfbfaf77eaed94ec8191f2ae4efb477cefdd0
Reviewed-on: https://gem5-review.googlesource.com/c/14636
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem-cache: Add setters to validate and secure block

In order to allow polymorphism of the block these two
functions have been added, and all direct status
assignments to these bits have been substituted.

We also assert that the block has been invalidated
before insertion. Then the block is validated in
the insertion.

Change-Id: Ie7be42408721ad4c2c9dc880f82a62cb594f8668
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/14362
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: a missing cast was truncating addresses

High bits were truncated when computing the block address

Change-Id: Iab2a4c6063ece2d1d4c24ce5686045a6d6d35434
Reviewed-on: https://gem5-review.googlesource.com/c/14415
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: fix invalid iterator access

An iterator was assigned end() and then it was used to access
its corresponding element.

Change-Id: I87246cf56cbc694dd6b4e2cabbe84a08429d2ac3
Reviewed-on: https://gem5-review.googlesource.com/c/14361
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Make StridePrefetcher use Replacement Policies

Previously StridePrefetcher was only able to use random
replacement policy. This change allows all replacement
policies to be applied to the pc table.

Change-Id: I8714e71a6a4c9c31fbca49a07a456dcacd3e402c
Signed-off-by: Daniel <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/14360
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Add invalidation function to StrideEntry

Add invalidation function to StrideEntry so that every
entry can be invalidated appropriately.

Change-Id: I38c42b7d7c93d839f797d116f1d2c88572123c0e
Signed-off-by: Daniel <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/14359
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Make PCTable context independent

Move the unordered_map outside of the PCTable, as it
belongs to the StridePrefetcher. By doing so we are
moving towards a table that ressembles the ones of
the Tags classes.

Some functions have been moved from the prefetcher to
the PCTable, as they didn't belong there. As such, they
have been renamed to remove the unnecessary prefix.

Change-Id: I3e54bc7dee65e1f78d96b0d548ac8345b7bd4364
Signed-off-by: Daniel <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/14358
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Vectorize StridePrefetcher's entries.

Turn StridePrefetcher::PCTable::entries into a vector of vectors.

Change-Id: I2a4589a76eb205910c43723638b7989eddd5ca24
Reviewed-on: https://gem5-review.googlesource.com/c/14357
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Return entry in StridePrefetcher::pcTableHit()

Return a pointer to the entry instead of returning a
boolean and passing a pointer reference. As a side
effect, change the name of the function to be more
descriptive of the functionality.

Change-Id: Iad44979e98031754c1d0857b1790c0eaf77e9765
Signed-off-by: Daniel <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/14356
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Cleanup prefetchers

Prefetcher code had extra variables, dependencies
that could be removed, code duplication, and missing
overrides.

Change-Id: I6e9fbf67a0bdab7eb591893039e088261f52d31a
Signed-off-by: Daniel <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/14355
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Remove Cache dependency from Tags

Tags do not need to be aware of caches.

Change-Id: Ib6a082b74dcd9b2f10852651634b59512732fb2a
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/14296
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Move access latency calculation to Cache

Access latency was not being calculated properly, as it was
always assuming that for hits reads take as long as writes,
and that parallel accesses would produce the same latency
for read and write misses.

By moving the calculation to the Cache we can use the write/
read information, reduce latency variables duplication and
remove Cache dependency from Tags.

The tag lookup latency is still calculated by the Tags.

Change-Id: I71bc68fb5c3515b372c3bf002d61b6f048a45540
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/13697
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: implement a probe-based interface

The HW Prefetcher of a cache can now listen events
from their associated CPUs and from its own cache.

Change-Id: I28aecd8faf8ed44be94464d84485bd1cea2efae3
Reviewed-on: https://gem5-review.googlesource.com/c/14155
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Align how we handle requests in atomic with timing

Requests, for which a cache has already committed to respond do not
perform any lookups. Previously in atomic mode the packet would pay
the lookup latency while in timing it wouldn't. This patch aligns
recvAtomic with recvTimingReq and removes the lookup latency from the
the handling of such requests.

Change-Id: I50a0631f8058e5086d94d55af0e1788a60e2883f
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14175
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

mem-cache: Rename the tag class init function to tagsInit.

Since the tag classes are subclasses of SimObject, they inherit an
init function which does generic initialization at simulation startup
and which doesn't take any parameters. A new function was added which
does take a parameter, and which is just for doing tag specific
initialization as triggered by the base cache. These two names clashed,
and clang complained that the tag local name was hiding the SimObject
name (which it was).

Change-Id: I399775aceaf8f1a8e2646d434facef22e6d3e7d0
Reviewed-on: https://gem5-review.googlesource.com/c/13875
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem: Use Packet writing functions instead of memcpy

Classes were using memcpy instead of the Packet functions
created for writing to/from the packet. This allows these
writes to be better checked and tracked.

This also fixes a bug in MemCheckerMonitor, which was using
the incorrect type for the packet pointer.

Change-Id: I5bbc8a24e59464e8219bb6d54af8209e6d4ee1af
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/13695
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Fix double block invalidation

Block was being invalidated twice when not a tempBlock.
Make explicit that the else case is only to be applied
when handling the tempBlock, as otherwise the Tags
should be taking care of the invalidation.

Change-Id: Ie7603fdbe156c54e94bbdc83541b55e66f8d250f
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/13895
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

arch-arm: We add PRFM PST instruction for arm

Note current PRFM supports only PLD, but PST (prefetch for store) is
also important for latency hiding. We also bug fix in disassembler to
display prfop correctly.

Change-Id: I9144e7233900aa2d555e1c1a6a2c2e41d837aa13
Signed-off-by: Yuetsu Kodama <yuetsu.kodama@riken.jp>
Reviewed-on: https://gem5-review.googlesource.com/c/13675
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

mem-cache: Move evictBlock(CacheBlk*, PacketList&) to base

Move evictBlock(CacheBlk*, PacketList&) to base cache,
as it is both sub-classes implementations are equal.

Change-Id: I80fbd16813bfcc4938fb01ed76abe29b3f8b3018
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/13656
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Fix unused variable warning in FALRU:invalidate()

Change-Id: I3b902045433ca56b3e62c251158e784b5fa9e4d7
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13600
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

mem: Add write coalescing and write-no-allocate to the caches

Enable the cache to detect contiguous writes and hold on to the MSHR
long enough to allow the entire line to be written. If the whole line
is written, the MSHR will be sent out as an invalidation requests, as
it is part of a whole-line write, i.e. no-fetch-on-write.

The cache is also able to switch to a write-no-allocate policy on the
actual completion of the writes, and instead use the tempBlock and
turn the write operation into a writeback.

These policies are all well-known, and described in works such as
Jouppi, Cache Write Policies and Performance, vol 21, no 2, ACM, 1993.

Change-Id: I19792f2970b3c6798c9b2b493acdd156897284ae
Reviewed-on: https://gem5-review.googlesource.com/c/12907
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem: Delay servicing an MSHR after its allocation

An MSHR is allocated and the computed latency determines when the MSHR
will be ready and can be serviced by the cache. This patch adds a
function that allows changing the time that an MSHR is ready and
adjusts the queue such that other MSHRs can be serviced first if they
are ready.

Change-Id: Ie908191fcb3c2d84d4c6f855c8b1e41ca5881bff
Reviewed-on: https://gem5-review.googlesource.com/c/12906
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem: Restructure whole-line writes to simplify write merging

This patch changes how we deal with whole-line writes their
responses. With these changes, we use the MSHR tracking to determine
if a whole-line is written, and on a fill we simply handle the
invalidation response, with the actual writes taking place as part of
satisfying the CPU-side hit.

Change-Id: I9a18e41a95db3c20b97f8bca7d95ff33d35a578b
Reviewed-on: https://gem5-review.googlesource.com/c/12905
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem: Determine if an MSHR does a whole-line write

This patch adds support for determining whether the targets in an MSHR
are 1) only writes and 2) whether these writes are effectively a
whole-line write. This patch adds the necessary functions in the MSHR
to allow for write coalescing in the cache.

Change-Id: I2c9a9a83d2d9b506a491ba5b0b9ac1054bdb31b4
Reviewed-on: https://gem5-review.googlesource.com/c/12904
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Add missing includes in TreePLRU

Add missing includes to TreePLRU files.

Change-Id: Ia1e7b2aa91eec8a30b6dccf513cca37a3058b350
Reviewed-on: https://gem5-review.googlesource.com/c/13477
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Factor ReplaceableEntry out

ReplaceableEntry is referenced by many classes that do
not necessarily need access to the replacement policies.
Therefore, in order to allow better compilation units,
we factor it out to a new file.

Change-Id: I0823567bf1ca336ffcdf783682ef473e8878d7fd
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/13418
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Move sector_blks to tags folder

Move sector_blks.hh and sector_blks.cc to the tags folder,
as its usage scope is restricted to the tags, and caches
should not be aware of them.

Change-Id: Ia7a71f51ec251d827872daf108c87da543a0ba57
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/13417
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Rename blk.cc/hh to cache_blk.cc/hh

Rename the files blk.cc and blk.hh to cache_blk.cc and cache_blk.hh
to comply with the usual file-class naming rules.

Change-Id: I8af45df3e4b8dd934fd9929ec914fb230cb2cb09
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/13416
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Virtualize block print

Encapsulate and virtualize block print, so that relevant
information can be easily printed anywhere.

Change-Id: I91109c29c126755183a0fd2b4446f5335e64076b
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/13415
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Create Tree-PLRU replacement policy

Implementation of a Tree-PLRU replacement policy. It is based on
the assumption that a set associative cache is used.

Change-Id: I74b227e88fd6c93aab5bb2cd0e8730376db28f52
Reviewed-on: https://gem5-review.googlesource.com/c/11106
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem-cache: Remove CacheSet.hh

Replacement policies aren't aware of cache sets and do not
organize blocks based on replacement data. Block search is
independent of block placement.

Besides, indexing policies have their own way of addressing
the sets, therefore there is no need to use this class anymore.

BlkType has been removed, as it wasn't being used.

Change-Id: Ia79c2a491e59f295c8d60a0466c317eb0e2bdab9
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/9782
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Split Tags for indexing policies

Split indexing functionality from tags, so that code duplication
is reduced when adding new classes that use different indexing
policies, such as set associative, skewed associative or other
hash-based policies.

An indexing policy defines the mapping between an address' set
and its physical location. For example, a conventional set assoc
cache maps an address to all ways in a set using an immutable
function, that is, a set x is always mapped to set x. However,
skewed assoc caches map an address to a different set for each way,
using a skewing function.

FALRU has been left unmodified as it is a specialization with its
own complexity.

Change-Id: I0838b41663f21eba0aeab7aeb7839e3703ca3324
Reviewed-on: https://gem5-review.googlesource.com/c/8885
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem-cache: Use set and way for ReplaceableEntry

Replaceable entries belong to table-like structures, and therefore
they should be indexable by combining a row and a column. These,
using conventional cache nomenclature translate to sets and ways.

Make these entries aware of their sets and ways. The idea is to
make indexing policies usable by other table-like structures. In
order to do so we move sets and ways to ReplaceableEntry, which
will be the common base among table entries.

Change-Id: If0e3dacf9ea2f523af9cface067469ccecf82648
Reviewed-on: https://gem5-review.googlesource.com/c/12764
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem-cache: Use possible locations to find block

Use possible locations to find block to make it placement policy
independent.

Change-Id: I4c9d9e1e1ff91ce12e85ca1970f927d8f4f5a93b
Reviewed-on: https://gem5-review.googlesource.com/c/8884
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem-cache: Create tags initialization function

Having the blocks initialized in the constructor makes it harder
to apply inheritance in the tags classes. This patch decouples
the block initialization functionality from the constructor by
using an init() function. It also sets the parent cache.

Change-Id: I0da7fdaae492b1177c7cc3bda8639f79921fbbeb
Reviewed-on: https://gem5-review.googlesource.com/c/11509
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem-cache: Remove Packet dependency in Tags

Decouple Tags from Packets, only extracting the necessary
functionality for block insertion. As a side effect, create
a new function to update common insertion statistics.

Change-Id: I5c58f7c17de3255beee531f72a3fd25a30d74c90
Reviewed-on: https://gem5-review.googlesource.com/c/11098
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem-cache: Fix FALRU hash invalidation

The block was being invalidated before the hash could erase
its entry, therefore it was using invalid values (tag was
being assigned MaxAddr and the secure bit was reset).

This change reorders the calls, so that the appropriate hash
entry is erased.

Change-Id: I161463df0f8f5220179bc68d7be12051e5390d01
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/13210
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Make checking function const in FALRU

The checking function should not be able to modify either
the head and tail pointers nor should it modify its class.

Change-Id: I2ad495f0c8c6b778d48512143e94b4c9a353f22e
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/13209
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Make boundaries in FALRU an STL container

Turn the dynamically allocated array of pointers "boundaries"
into a STL vector.

Change-Id: I3409898473b155f69b4c6e038eba2dffb5b09380
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/13208
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem-cache: Fix FALRU inCachesMask initialization

inCachesMask is not being initialized, which triggers an assertion
on insertion. Fix this by implementing a default constructor for
the FALRUBlk.

Change-Id: I587cf5e0191c4587d938e6ab6036ec1b32f37793
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/13207
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem-cache: Fix non-bijective function in Skewed caches

The hash() function must be bijective for the skewed caches to work,
however when the hashing is done on top of a one-bit address, the
MSB and LSB refer to the same bit, and therefore their xor will
always be zero.

This patch adds a fatal error to not allow the user to set an invalid
value for the number of sets that would generate that bug.

As a side note, the missing header for the bitfields functions has
been added.

Change-Id: I35a03ac5fdc4debb091f7f2db5db33568d0b0021
Reviewed-on: https://gem5-review.googlesource.com/12724
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Fix bug in handleAtomicReqMiss

"4976ff5 mem-cache: Refactor the recvAtomic function" introduced a bug
where if an atomic request that fills in using the tempBlock it will
not evict it when it finishes handling the request as it should. This
triggers an assertion. This change fixes this bug.

Change-Id: I73c808a7e15237eddb36b5448ef6728f7bcf7fd9
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12644
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Create Skewed Assoc placement policy

Create a class that implements the skewed associative placement
policy. It uses the hash function and expansions of the skewing
functions described in "Skewed-Associative caches", by Seznec.

Only 8 skewing functions are implemented, and therefore if more
are needed a hash function will be recursively applied on top
of the output of one of these functions to generate different
values. This is not optimal, and if more functions are needed
it might be more effective to implement them.

Change-Id: Ibc77edffd8128114a8b200cec5d8deedfb5105cb
Reviewed-on: https://gem5-review.googlesource.com/8886
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: TempCacheBlk allocates and destroys its own data

This change is because I want to make CacheBlk::data private, so that
I can track all the places which write to it. But to keep that commit
smaller (it is pretty big, because of all the places which might
change it), I have split this into a commit of its own.

Change-Id: I15a2fc1752085ff3681f5c74ec90be3828a559ea
Reviewed-on: https://gem5-review.googlesource.com/11829
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem: Rename Packet::checkFunctional to trySatisfyFunctional

Packet::checkFunctional also wrote data to/from the packet depending
on if it was read/write, respectively, which the 'check' in the name
would suggest otherwise. This renames it to doFunctional, which is
more suggestive. It also renames any function called checkFunctional
which calls Packet::checkFunctional. These are

- Bridge::BridgeMasterPort::checkFunctional
- calls Packet::checkFunctional
- MSHR::checkFunctional
- calls Packet::checkFunctional
- MSHR::TargetList::checkFunctional
- calls Packet::checkFunctional
- Queue<>::checkFunctional
(of src/mem/cache/queue.hh, not src/cpu/minor/buffers.h)
- Instantiated with Queue<WriteQueueEntry> and Queue<MSHR>
- WriteQueueEntry
- calls Packet::checkFunctional
- WriteQueueEntry::TargetList
- calls Packet::checkFunctional
- MemDelay::checkFunctional
- calls QueuedSlavePort/QueuedMasterPort::checkFunctional
- Packet::checkFunctional
- PacketQueue::checkFunctional
- calls Packet::checkFunctional
- QueuedSlavePort::checkFunctional
- calls PacketQueue::doFunctional
- QueuedMasterPort::checkFunctional
- calls PacketQueue::doFunctional
- SerialLink::SerialLinkMasterPort::checkFunctional
- calls Packet::doFunctional

Change-Id: Ieca2579c020c329040da053ba8e25820801b62c5
Reviewed-on: https://gem5-review.googlesource.com/11810
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem-cache: Typo in comment: 'proceed' -> 'precede'

The writebacks happen before anything below, not after.

Change-Id: I7eaefbbf33aa17c496255dedd964a56118a28741
Reviewed-on: https://gem5-review.googlesource.com/11749
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem-cache: Promote deferred targets on cache clean responses

While a cache clean operation is pending, all requests to the
corresponding block get deferred. When the response of a cache clean
operation is received, if the block is present and the response is not
invalidating, we can service all deferred targets that didn't require
writable. This change implements this functionality.

Change-Id: Ief47e74d07749a6a9736ab450eb46eefa53464a2
Reviewed-on: https://gem5-review.googlesource.com/11018
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem-cache: Promote targets that don't require writable

Until now, all deferred targets of an MSHR would be promoted together
as soon as the targets were serviced. Due to the way we handle cache
clean operations we might need to promote only deferred targets that
don't require writable, leaving some targets as deferred. This change
adds support for this selective promotion.

Change-Id: I502e523dc9adbaf394955cbacea8286ab6a9b6bc
Reviewed-on: https://gem5-review.googlesource.com/11017
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem-cache: Fix promoting of targets that need writable

There are cases where a request which does not need a writable copy
gets an response upgraded reponse and fills in a writable copy. When
this happens, we promote deferred MSHR targets that were deferred
because they needed a writable copy to service them immediately.

Previously, we would uncoditionally promote deferred targets. Since
the deferred targets might contain a cache invalidation operation, we
have to make sure that any targets following the cache invalidation is
not promoted.

Change-Id: I1f7b28f7d35f84329e065c8f63117db21852365a
Reviewed-on: https://gem5-review.googlesource.com/11016
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem-cache: Selectively clear downstream pending

Until now, all deferred targets of an MSHR would be promoted together
as soon as the targets were serviced. When we promote deferred targets
we also clear the downstreamPending flag.

Due to the way we handle cache clean operations we might need to
promote only deferred targets that don't require writable, leaving
some targets as deferred. To allow for partial target promotion, this
change adds support for clearing the downstreamPending only for a
subset of a TargetsList.

Change-Id: Id06953643ba9a975ebacc76ac10215441e264e74
Reviewed-on: https://gem5-review.googlesource.com/11015
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem-cache: Fix TempCacheBlock insert

TempCacheBlock insert() had a different signature than the parent class
which caused an error on clang. This matches the signature with default
zero values.

Change-Id: Ic096914497f3d17e88295c9e65a04d76fdddf365
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/11349
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Fix support for secure blocks in the FALRU cache

Fully associative caches use an unordered map to enable efficient
lookups of existing blocks. Previously this map was indexed using the
tag of the block. Security extentions allow secure and non secure
versions of a block with the same tag to co-exist in the cache. This
patch amends the block map to allow correct lookups for FALRU caches.

Change-Id: Iccf07464deab56d1d270bae14bb3b154047e3556
Reviewed-on: https://gem5-review.googlesource.com/11309
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Initialize CacheBlk data pointer

Initialize CacheBlk's data pointer as a nullptr.

Change-Id: Ice85b4b11495cad4b0a160ccb9efe1be673e57e2
Reviewed-on: https://gem5-review.googlesource.com/11097
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Forward declare ReplaceableEntry

Forward declare ReplaceableEntry where in classes where pointers
to it are used.

Change-Id: I49c08d36442a563d7a6b4c9bcd7eba3591d29b60
Reviewed-on: https://gem5-review.googlesource.com/11096
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

base,mem: Support AtomicOpFunctor in the classic memory system

AtomicOpFunctor can be used to implement atomic memory operations.
AtomicOpFunctor is captured inside a memory request and executed directly
in the memory hierarchy in a single step.

This patch enables AtomicOpFunctor pointers to be included in a memory
request and executed in a single step in the classic cache system.

This patch also makes the copy constructor of Request class do a deep
copy of AtomicOpFunctor object. This prevents a copy of a Request object
from accessing a deleted AtomicOpFunctor object.

Change-Id: I6649532b37f711e55f4552ad26893efeb300dd37
Reviewed-on: https://gem5-review.googlesource.com/8185
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Remove unnecessary cast in SectorTags::findVictim

Removes an uneccessary cast that also caused an unused variable
error (due to -Werror) when compiling .fast targets.

Change-Id: Ic043f462925e7eaa7b691455f1d9e08a1c101980
Reviewed-on: https://gem5-review.googlesource.com/11119
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Insert on block allocation

When a block is being replaced in an allocation, if successfull,
the block will be inserted. Therefore we move the insertion
functionality to allocateBlock().

allocateBlock's signature has been modified to allow this
modification.

Change-Id: I60d17a83ff4f3021fdc976378868ccde6c7507bc
Reviewed-on: https://gem5-review.googlesource.com/10812
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Make packet const in insertBlock

The packet should not be modified within insertBlock.

Change-Id: If7d2b01fe131f9923194efd155c9e85eeab24d5a
Reviewed-on: https://gem5-review.googlesource.com/10811
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Create Sector Cache

Implementation of Sector Caches, i.e., a cache with multiple
sequential data entries per tag entry for Set Associtive
placement policies.

Change-Id: I8e1e9448fa44ba308ccb16cd5bcc5fd36c988feb
Reviewed-on: https://gem5-review.googlesource.com/9741
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

misc: Using smart pointers for memory Requests

This patch is changing the underlying type for RequestPtr from Request*
to shared_ptr<Request>. Having memory requests being managed by smart
pointers will simplify the code; it will also prevent memory leakage and
dangling pointers.

Change-Id: I7749af38a11ac8eb4d53d8df1252951e0890fde3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10996
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

misc: Substitute pointer to Request with aliased RequestPtr

Every usage of Request* in the code has been replaced with the
RequestPtr alias. This is a preparing patch for when RequestPtr will be
the typdefed to a smart pointer to Request rather then a raw pointer to
Request.

Change-Id: I73cbaf2d96ea9313a590cdc731a25662950cd51a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10995
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

mem-cache: Change Cache block tag check

Change tag to address check for compatibility with sector design.
Cache should not use tag, as sector sub-blocks share them, and
it could lead to wrong accesses.

Change-Id: Id1fa26f417595f475c5b5c07ae1f02f5fa0684ba
Reviewed-on: https://gem5-review.googlesource.com/10723
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Use secure bit in findVictim

Sector caches must know if there was a sector hit in order
to decide whether a victim's sector must be fully evicted
to give place to a new sector or not.

In order to do so it needs the tag and secure information.

Change-Id: Ib554169e25fa131d6bf986561f7970b787c56874
Reviewed-on: https://gem5-review.googlesource.com/10722
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Move tagsInUse to children

Move tagsInUse to children, as sector caches have different
tag invalidation and insertion, and thus they must handle
updating this variable.

Change-Id: I875c9b7364a909c76daf610d1e226c4e82063870
Reviewed-on: https://gem5-review.googlesource.com/10721
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Return evictions along with victims

For both sector and compressed caches multiple blocks may need
to be evicted in order to make room for a new block.

For example, when replacing a sector, all the blocks in this
sector must be evicted. A replacement, however, does not always
need to evict multiple blocks, as it is in the case of an
insertion of a block whose sector is already present in the cache
(i.e., its corresponding entry in the sector had not been brought
in yet, so it was invalid).

This patch creates the cache framework for that to happen.

Change-Id: I77bedf69637cf899fef4d9432eb6da8529ea398b
Reviewed-on: https://gem5-review.googlesource.com/10142
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Use ReplaceableEntry in findBlockBySetAndWay

With a sector cache you can't find a block using only its set
and way, as there is the sector offset to take into account. As
all of these blocks inherit from ReplaceableEntry, the return
type of this function has been updated.

This function has also been declared closer to findBlock() due
to their similar functionality.

Change-Id: I4730a2b4ebb5738f7fc118201e208a1b9c3ba8e8
Reviewed-on: https://gem5-review.googlesource.com/10141
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Privatize extractSet

Only BaseSetAssoc uses extractSet(). Besides, skewed caches need
the way information to know which set an address is located at.

Change-Id: Id222e907dc550d053018561bb2683cfc415471ec
Reviewed-on: https://gem5-review.googlesource.com/9962
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Create an address aware TempCacheBlk

tempBlock has its member variables manually set in order to allow
it to be used in the block address regeneration function. This is
not necessary, and ti can be simply given the address, so it does
not need to be aware of set and tag. This will simplify
implementation of sector and skewed caches.

Change-Id: Iaffb10c323509722cd5589fe1030b818d43336d6
Reviewed-on: https://gem5-review.googlesource.com/9961
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Fix secure bit modification

Secure bit was being updated outside insertion.

Change-Id: I83d9b010e8cf64013bbea9bae3ea68b0c414a189
Reviewed-on: https://gem5-review.googlesource.com/10622
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Replace block visitor with std::function

This change modifies forEachBlk tags function to accept std::function
as parameter. It also adds an anyBlk tags function that given a
condition, it iterates through the blocks and returns whether the
condition is met.

Finally, it uses forEachBlk to implement the print, computeStats and
cleanupRefs functions that also work for the FALRU class.

Change-Id: I2f75f4baa1fdd5a1d343a63ecace3eb9458fbf03
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10621
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Fix include directives in the cache related classes

Change-Id: I111b0f662897c43974aadb08da1ed85c7542585c
Reviewed-on: https://gem5-review.googlesource.com/10433
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Add a non-coherent cache

The class re-uses the existing MSHR and write queue. At the moment
every single access is handled by the cache, even uncacheable
accesses, and nothing is forwarded.

This is a modified version of a changeset put together by Andreas
Hansson <andreas.hansson@arm.com>

Change-Id: I41f7f9c2b8c7fa5ec23712a4446e8adb1c9a336a
Reviewed-on: https://gem5-review.googlesource.com/8291
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

mem-cache: Move cache bypass mechanism to the ports

Cache bypass is necessary for cpu models like the KvmCPU. Previously
the bypass would happen at the cache classes. With this change the
bypassing happens directly at the ports.

Change-Id: I34de9fc63383aee8590643e169501ea6060d2d62
Reviewed-on: https://gem5-review.googlesource.com/10432
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

mem-cache: Adopt a more sensible cache class hierarchy

This patch changes what goes into the BaseCache and what goes into the
Cache, to make it easier to add a NoncoherentCache with as much re-use
as possible. A number of redundant members and definitions are also
removed in the process.

This is a modified version of a changeset put together by Andreas
Hansson <andreas.hansson@arm.com>

Change-Id: Ie9dd73c4ec07732e778e7416b712dad8b4bd5d4b
Reviewed-on: https://gem5-review.googlesource.com/10431
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Add helper function to perform evictions

Change-Id: I2df24eb1a8516220bec9b685c8c09bf55be18681
Reviewed-on: https://gem5-review.googlesource.com/10430
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

mem-cache: Delegate block invalidation to block allocation

For a block replacement we first select a victim block, we invalidate
it and then populate it with the new information. Prior to this change
BaseTags::insertBlock() did the invalidation and filled in the block
with the new information. Now that the replacements stat is moved to
the BaseCache, insertBlock does not need to perform the invalidation
and as a result we can unify the block eviction code in BaseCache.

Change-Id: I5bdf00b2dab2752ed2137ab7201ed1dc451333b3
Reviewed-on: https://gem5-review.googlesource.com/10429
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

mem-cache: Refactor the recvAtomic function

The recvAtomic function in the cache handles atomic requests. Over
time, recvAtomic has grown in complexity and code size. This change
factors out some of its functionality in a separate functiona. The new
functions handles atomic requests that miss.

Change-Id: If77d2de1e3e802e1da37f889f68910e700c59209
Reviewed-on: https://gem5-review.googlesource.com/10425
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Refactor the cache recvTimingReq function

The recvTimingReq function in the cache handles timing requests. Over
time, recvTimingReq has grown in complexity and code size. This change
factors out some of its functionality in two separate functions. The
new functions handle timing requests that hit and timing requests that
miss separately.

Change-Id: I09902d648d7272f0f9ec2851fa6376f7305ba418
Reviewed-on: https://gem5-review.googlesource.com/10424
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Refactor the cache recvTimingResp function

The recvTimingResp function in the cache handles timing
responses. Over time, recvTimingResp has grown in complexity and code
size. This change factors out some of its functionality to a separate
function. The new function iterates through the in-service targets and
handles them accordingly.

Change-Id: I0ef28288640f6be1b30452b0664d32432e692ea6
Reviewed-on: https://gem5-review.googlesource.com/10423
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Fix RandomReplData

Random replacement policy's data was being instantiated with
the incorrect class.

Change-Id: Ib573a6b5a63868d6069997c6279bec3b10c6b9b9
Reviewed-on: https://gem5-review.googlesource.com/10623
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Determine if an MSHR has requests from another cache

To decide whether we allocate upon receiving a response we need to
determine if any of the currently serviced requests (non-deferred
targets) is comming from another cache. This change adds support for
tracking this information in the MSHR.

Change-Id: If1db93c12b6af5813b91b9d6b6e5e196d327f038
Reviewed-on: https://gem5-review.googlesource.com/10422
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Move reference count stats update to blk invalidation

The tags in the cache keep track of the number of references to the
blocks as well as the average number of references between an
insertion and the next invalidation. Previously the stats where
updated only on block insertion and invalidations were ignored. This
changes moves the update of the counters to the block invalidation
function.

Change-Id: Ie7672c13813ec278a65232694024d2e5e17c4612
Reviewed-on: https://gem5-review.googlesource.com/10428
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

mem-cache: Remove isTouched field from the CacheBlk

At the moment isTouched is used in the warm-up detection mechanism but
it keeps track of the same information as isValid(). This change
removes it and substitutes its use by isValid().

Change-Id: I611ddf2fa4562ae3b3b2ed2fb74d26abd2e5ec62
Reviewed-on: https://gem5-review.googlesource.com/10427
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

mem-cache: Move replacements stat to the base cache class

Change-Id: I25dbcfcddfe1c422a76eb1af3f726c1360d8d110
Reviewed-on: https://gem5-review.googlesource.com/10426
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

mem-cache: Simplify writeback for the tempBlock in recvTimingResp

When we use the tempBlock to fill-in, we have to write it back and
invalidate it at the end of current transaction. This patch simplifies
the writeback flow by treating it as a regular writeback.

Change-Id: I257be7bbff211e2832ad001a4e991daf67704485
Reviewed-on: https://gem5-review.googlesource.com/10421
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Create block insertion function

Create a block insertion function to be used when inserting
blocks. This resets the number of references to 1 (the
insertion is taken into account), sets the insertion tick,
and set secure state.

Change-Id: Ifc34cbbd1c125207ce47912d188809221c7a157e
Reviewed-on: https://gem5-review.googlesource.com/9824
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Create Second-Chance replacement policy

Implementation of a Second-Chance replacement policy. Similar to FIFO,
but every block is given a second chance if it has been touched.

Change-Id: Id4d52b698d0045a4914a4d848fdf9c3c00a28508
Reviewed-on: https://gem5-review.googlesource.com/9441
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: ReplacementPolicy specific replacement data

Replacement data is specific for each replacement policy, and thus
should be instantiated differently by each policy.

Touch() and reset() do not need to be aware of CacheBlk, as they
only update its ReplacementData.

Invalidate() makes replacement policies independent of cache blocks,
by removing the awareness of the valid state.

An inheritable base ReplaceableEntry class was created to allow usage
of replacement policies with any table-like structure.

Change-Id: I998917d800fa48504ed95abffa2f1b7bfd68522b
Reviewed-on: https://gem5-review.googlesource.com/9421
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

sim,cpu,mem,arch: Introduced MasterInfo data structure

With this patch a gem5 System will store more info about its Masters.
While it was previously keeping track of the Master name and Master ID
only, it is now adding a per-Master pointer to the SimObject related to
the Master.
This will make it possible for a client to query a System for a Master
using either the master's name or the master's pointer.

Change-Id: I8b97d328a65cd06f329e2cdd3679451c17d2b8f6
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9781
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Use block iteration in BaseSetAssoc

Use block iteration instead of numSets and assoc in print(),
cleanupRefs() and computeStats().

This makes these functions rely solely on what they are used for:
printing and calculating stats of blocks. With the addition of
Sectors an extra indirection level is added, and thus these
functions would be skipping blocks.

Change-Id: I0006f82736cce02ba3e501ffafe9236f748daf32
Reviewed-on: https://gem5-review.googlesource.com/10143
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Use findBlock in FALRU's block access

An access must perform a block search, which is done by findBlock.

The tagHash is indexed by tags, so use extractTag instead of re-
implementing its functionality.

Change-Id: Ib5abacbc65cddf0f2d7e4440eb5355b56998a585
Reviewed-on: https://gem5-review.googlesource.com/10082
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem-cache: Use secure flag in FALRU's findBlock

FALRU's findBlock() must use the secure flag to assure proper
functionality.

Change-Id: I54e9fbd3c9093b3e8043c4c6c850b74a8f1f5ec0
Reviewed-on: https://gem5-review.googlesource.com/10081
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Create NRU Replacement Policy

Implementation of a Not Recently Used replacement policy.

Change-Id: I24ab3a6f1db6dcb756b869cfebb5c4bc544170e8
Reviewed-on: https://gem5-review.googlesource.com/9001
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Revamp multiple size tracking for FALRU caches

This change fixes a few bugs and refactors the mechanism by which
caches that use the FALRU tags can output statistics for multiple
cache sizes ranging from the minimum cache of interest up to the
actual configured cache size.

Change-Id: Ibea029cf275a8c068c26eceeb06c761fc53aede2
Reviewed-on: https://gem5-review.googlesource.com/9826
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Add MoveToTail to FALRU

FALRU was missing MoveToTail functionality within its invalidate
function, and MoveToHead was doing unnecessary passes when the
moved block was the head already.

Besides, added some comments to make the code understandable.

Change-Id: I2430d82b5d53c88b102a62610ea38b46d6e03a55
Reviewed-on: https://gem5-review.googlesource.com/9541
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem: Remove unused 'using namespace'

Removal of unused/barely used 'using namespace' from C++ files.

Change-Id: I66dc548c04506db2e41180b9ea7ab5abd7d5375a
Reviewed-on: https://gem5-review.googlesource.com/9601
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Move insertBlock functionality in FALRU

Block insertion is being done in the getCandidates function, while the
insertBlock function does not do anything.

Besides, BaseTags' stats weren't being updated.

Change-Id: Iadab9c1ea61519214f66fa24c4b91c4fc95604c0
Reviewed-on: https://gem5-review.googlesource.com/8882
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Create LIP Replacement Policy

Implementation of a LRU Insertion Policy replacement policy.

Change-Id: I1a9aa0091ff2cdc1b1652c1d5ec7a3b33fba5b44
Reviewed-on: https://gem5-review.googlesource.com/9002
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Create BIP Replacement Policy

Implementation of a Bimodal Insertion Policy replacement policy.

Change-Id: Ife058d0d4310dbcb35858348006189f0b2bf7c37
Reviewed-on: https://gem5-review.googlesource.com/9003
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Use Packet functions to write data blocks

Instead of using raw memcpy, use the proper writer functions
from the Packet class in Cache.

Fixed typos in comments of these functions.

Change-Id: I156a00989c6cbaa73763349006a37a18243d6ed4
Reviewed-on: https://gem5-review.googlesource.com/9661
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Remove unused return value from the recvTimingReq func

The recvTimingReq function in the cache always returns true. This
changeset removes the return value.

Change-Id: I00dddca65ee7224ecfa579ea5195c841dac02972
Reviewed-on: https://gem5-review.googlesource.com/8289
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

mem-cache: Fix FALRU data block seg fault

FALRU didn't initialize the blocks' data, causing seg faults.
This patch does not make FALRU functional yet.

Change-Id: I10cbcf5afc3f8bc357eeb8b7cb46789dec47ba8b
Reviewed-on: https://gem5-review.googlesource.com/9302
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Create LFU replacement policy

Implementation of a Least Frequently Used replacement policy.

Change-Id: I772afccd3a7955777e53d59341e922718db44e5c
Reviewed-on: https://gem5-review.googlesource.com/8890
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Create RRIP Replacement Policy

Implementation of a Re-Reference Interval Prediction replacement
policy.

Change-Id: Iba716eb5df2bf2be156e765f889d94f6ad00c91b
Reviewed-on: https://gem5-review.googlesource.com/8981
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

mem-cache: Create BRRIP replacement policy

Implementation of a Bimodal Re-Reference Interval Prediction
replacement policy.

Change-Id: I25d4a59a60ef7ac496c66852e394fd6cbaf50912
Reviewed-on: https://gem5-review.googlesource.com/8891
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: fix missing overrides in repl policies

Change-Id: I67759a4532e8a46c1643d4c3a9c546ad6b565b81
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/9321
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Create FIFO replacement policy

Implementation of a First-In, First-Out replacement policy.

Change-Id: Id234ec9d29c092dd4516e609da14b8a75a96b5e4
Reviewed-on: https://gem5-review.googlesource.com/8888
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Fix MRU rebase

Rebase of MRU missed a const qualifier, introducing a compilation
error.

Change-Id: Ia25aa30523613a1a87593a353abe439946656f63
Reviewed-on: https://gem5-review.googlesource.com/9301
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Create MRU replacement policy

Implementation of a Most Recently Used replacement policy.

Change-Id: Id52cb247ca25d4523dcc53490d113695dac6a3f1
Reviewed-on: https://gem5-review.googlesource.com/8889
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Split array indexing and replacement policies.

Replacement policies (LRU, Random) are currently considered as array
indexing methods, but have completely different functionalities:

- Array indexers determine the possible locations for block allocation.
This information is used to generate replacement candidates when
conflicts happen.
- Replacement policies determine which of the replacement candidates
should be evicted to make room for new allocations.

For this reason, they were split into different classes. Advantages:

- Easier and more straightforward to implement other replacement
policies (RRIP, LFU, ARC, ...)
- Allow easier future implementation of cache organization schemes

As now we can't assure the use of sets, the previous way to create a
true LRU is not viable. Now a timestamp_bits parameter controls how
many bits are dedicated for the timestamp, and a true LRU can be
achieved through an infinite number of bits (although a few bits suffice
in practice).

Change-Id: I23750db121f1474d17831137e6ff618beb2b3eda
Reviewed-on: https://gem5-review.googlesource.com/8501
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Allow clean operations when block allocation fails

Block allocation can fail when there is an in-service MSHR that
operates on the victim block. This can happed due to:
* an upgrade operation: a request that needs a writable copy of the
block finds a shared (non-writable) copy of the block in the cache
and has allocates an MSHR for the pending upgrade operation, or
* a clean operation: a clean request finds a dirty copy of the block
and allocates an MSHR for the pending clean operation.
This changes relaxes an assertion to allow for the 2nd case (cache
clean operations).

Change-Id: Ib51482160b5f2b3702ed744b0eac2029d34bc9d4
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9021
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

mem-cache: Use CacheBlk parameter on address regeneration

Skewed caches need to know the way to regenerate a block address.

Change-Id: I62c61ac9509eff2f37bad36862751956db7a6e40
Reviewed-on: https://gem5-review.googlesource.com/8782
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Fix missing overrides

clang doesn't like inconsistent overrides. Add override to all overidden
functions in lru.hh

Change-Id: I100ff4a7d90757439afee879ff9838c15f5c0b1d
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/8861
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Make the block invalidate functions virtual

This change makes the cache block invalidation function in the
BaseTags and CacheBlk class virtual to enable derived classes.

Change-Id: I2e64b01c6ca637f16d10474fc8b08eeec3f23453
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8287
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

mem-cache: Make invalidate a common function between tag classes

invalidate was defined as a separate function in the base associative
and fully-associative tags classes although both functions should
implement identical functionality. This patch moves the invalidate
function in the base tags class.

Change-Id: I206ee969b00ab9e05873c6d87531474fcd712907
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8286
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Allow prefetchers to override setCache.

This lets them hook setCache, perhaps to set up additional state based
on the set cache.

Change-Id: Ic3b34fa43d052c71e8ef733a57fe47c70899cd27
Reviewed-on: https://gem5-review.googlesource.com/8701
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

mem-cache: Fix bug generated by 8282

Merge 1ae7fced4d32898531a6875a339ef00e43e20e66 generated
a bug in tagsInUse calculation.

Change-Id: I079e327a0a26a7968f2ed8e433dd6e790c80998b
Reviewed-on: https://gem5-review.googlesource.com/8781
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Populate whenReady for blocks filled from writebacks

Writebacks write data to either an existing block or a newly allocated
block. In either case we need to populate the whenReady field of the
block which will determine when the new value can be used.

Change-Id: I5788fad0b8086a1be96714639bf6a9470b334926
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8285
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Use findBlock() in accessBlock()

Use placement policy specific block search within generic access.

Change-Id: I6070035e6e00595bcf073d4011f78a55ba7e7a8a
Reviewed-on: https://gem5-review.googlesource.com/8721
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Remove redundant block initialization on allocation

Change-Id: I7496e12e6a517529316c480d5f6e2ade601f0e2d
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8282
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Remove mumBlock redundant initialiation from FALRU

Change-Id: Id3afec0a62446d6d0f44ccb655032343037637e0
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8281
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Populate the secure bit when the temp block is filled

The secure bit should be set when we fill a block with data from a
secure location, as indicated by the packet that triggers the fill.
This patch fixes a bug in which the cache wouldn't populate the secure
bit when filling the temp block.

Change-Id: I95c706146449804ff42b205b25dd79750f3e882a
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8284
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

mem-cache: Remove unnecessary block initialization on writeback

Change-Id: Ia9b825bcbb8d326705f74c15a93a88703153ba5a
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8283
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

mem-cache: Remove extra block init in BaseSetAssoc

Removed extra initialization of cache block just after they have been
created and organized the comments.

Change-Id: I75c1beaf0489e3e530fd8cbff2739dc7593e3e6f
Reviewed-on: https://gem5-review.googlesource.com/8661
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Vectorize C arrays in BaseSetAssoc.

Transform BaseSetAssoc's arrays into C++ vectors to avoid unnecessary
resource management.

Change-Id: I656f42f29e5f9589eba491b410ca1df5a64f2f34
Reviewed-on: https://gem5-review.googlesource.com/8621
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem-cache: Fix CacheSet memory leak

CacheSet blocks were being allocated but never freed.
Used vector to avoid using pure C array.

Change-Id: I6f32fa5a305ff4e1d7602535026c1396764102ed
Reviewed-on: https://gem5-review.googlesource.com/8603
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Make cache warmup percentage a parameter.

The warmupPercentage is the percentage of different tags (based on the
cache size) that need to be touched in order to warm up the cache.
If Warmup failed (i.e., not enough tags were touched), warmup_cycle = 0.

The warmup is not being taken into account to calculate the stats (i.e.,
stats acquisition starts before cache is warmed up). Maybe in the future
this functionality should be added.

Change-Id: I2b93a99c19fddb99a4c60e6d4293fa355744d05e
Reviewed-on: https://gem5-review.googlesource.com/8061
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Only pendingModified MSHRs can satisfy CMO snoops

We set the satisfied flag when a cache clean request encounters:
1) a block with the dirty bit set, or
2) a pending modified MSHR which means that the cache will get copy of
the block that will be soon modified.

This changeset fixes a previous bug that set the satisfied flag on
snooping MSHR hits even the pendingModified flags was not set.

Change-Id: I4968c4820997be5cc1238148eea12a1ba39837d4
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/7822
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem-cache: Cleaned blocks should be marked as not writable

A writeclean packet writes a dirty block to the memory below and
therefore sets the dirty flag for the block when the memory below is a
cache. If the block was also marked as writable it can satisfy future
write requests without further requests/snoops. This can lead to
multiple copies of the same block marked as dirty which is not
allowed. This changeset clears the writable flag from the cleaned
block to prevent the cache from satisfying future write requests
without sending a downstream request.

Change-Id: I14d3c62fd33f81b1a8ba62374c8565ccab00a6fe
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/7821
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

mem-cache: Remove extra numSets zero check.

numSets is unsigned, so it cannot be lower than 0. Besides, isPowerOf2(0)
is false by definition (and implemmentation*), so there is no need for the
double check.

* As presented in base/intmath.hh

Change-Id: I3f6296694a937434feddc7ed21f11c2a6fdfc5a9
Reviewed-on: https://gem5-review.googlesource.com/7901
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

mem: Standardize mem folder header guards

Standardize all header guards in the mem directory according to the most
frequent patterns. In general they have the form:
mem: __FOLDER_TREE_FILE_NAME_HH__
ruby: __FOLDER_TREE_FILENAME_HH__

Change-Id: I983853e292deb302becf151bf0e970057dc24774
Reviewed-on: https://gem5-review.googlesource.com/7881
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Prune unnecessary writebacks in exclusive caches

Exclusive caches use the tempBlock to fill for responses from a
downstream cache. The reason for this is that they only pass the block
to the cache above without keeping a copy. When all requests are
serviced the block is immediately invalidated unless it is dirty, in
which case it has to be written back to the memory below.

To avoid unnecessary writebacks, this changeset forces mostly
exclusive caches to issuse requests that can only fetch clean data
when possible.

Reported-by: Quereshi Muhammad Avais <avais@kaist.ac.kr>

Change-Id: I01b377563f5aa3e12d22f425a04db7c023071849
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5061
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem: Co-ordination of CMOs in the xbar

A clean packet request serving a cache maintenance operation (CMO)
visits all memories down to the specified xbar. The visited caches
invalidate their copy (if the CMO is invalidating) and if a dirty copy
is found a write packet writes the dirty data to the memory level
below the specified xbar. A response is send back when all the caches
are clean and/or invalidated and the specified xbar has seen the write
packet.

This patch adds the following functionality in the xbar:
1) Accounts for the cache clean requests that go through the xbar
2) Generates the cache clean response when both the cache clean
request and the corresponding writeclean packet has crossed the
destination xbar.

Previously transactions in the xbar were identified using the pointer
of the original request. Cache clean transactions comprise of two
different packets, the clean request and the writeclean, and therefore
have different request pointers. This patch adds support for custom
transaction IDs that by default take the value of the request pointer
but can be overriden by the contructor. This allows the clean request
and writeclean share the same id which the coherent xbar uses to
co-ordinate them and send the response in a timely manner.

Change-Id: I80db76386a1caded38dc66e6e18f930c3bb800ff
Reviewed-by: Stephan Diestelhorst <stephan.diestelhorst@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5051
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

mem: Add support for handling CMOs in the MSHRs

To add support for cache maintenance operations (CMOs) in the MSHRs,
this change adds the following functionality:
- If a CMO request hits in the MSHRs, we deferred as we can't
coalesce it with any other requests.
- When we promote any deferred targets, we promote them in order and
stop if we encounter a CMO request. If the CMO request is at the
beginning of the deferred targets list it will be the only promoted
target.

Change-Id: I10d1f7e16bd6d522d917279c5d408a3f0cee4286
Reviewed-by: Stephan Diestelhorst <stephan.diestelhorst@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5050
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

mem: Add support for CMOs in the cache

This change adds support for maintenance operations (CMOs) in the
cache. The supported memory operations clean and/or invalidate a cache
block as specified by its VA to the specified xbar (PoU, PoC).

A cache maintenance packet visits all memories down to the specified
xbar. Caches need to invalidate their copy if it is an invalidating
CMO. If it is (additionally) a cleaning CMO and a dirty copy exists,
the cache cleans it with a WriteClean request.

Change-Id: Ibf31daa7213925898f3408738b11b1dd76c90b79
Reviewed-by: Stephan Diestelhorst <stephan.diestelhorst@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5049
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

mem: Promote deferred targets only when the block is valid

When a response indicates that there are no other sharers of the
block, the cache can promote its copy of the block to writable and
potential service deferred targets even if the request didn't ask for
a writable copy.

Previously, a response would guarantee the presence of the block in
the cache. A response could either be filling, upgrading or a response
to an invalidation due to a pending whole line write. Responses to
cache maintenance invalidations break this assumption. This change
adds an extra check to make sure that the block was already valid or
that the response is filling before promoting the block.

Change-Id: I6839f683a05d4dad4205c23f365a925b7b05e366
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5048
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

mem: Support for specifying the destination of a WriteClean

Previously, WriteClean packets would always write to the first memory
below unless the memory was unable to allocate in which case it would
be forwarded further below.

This change adds support for specifying the destination of a
WriteClean packet. The cache annotates the request with the specified
destination and marks the packet as write-through upon its
creation. The coherent xbar checks packets for their destination and
resets the write-through flag when necessary e.g., the coherent xbar
that is set as the PoC will reset the write-through flag for packets
to the PoC.

Change-Id: I84b653f5cb6e46e97e09508649a3725d72d94606
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5046
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

mem: Add support for WriteClean packets in the memory system

This change adds support for creating and handling WriteClean
packets. The WriteClean operation is almost identical to a
WritebackDirty with the exception that the cache generating a
WriteClean retains a copy of the block.

Change-Id: I63c8de62919fad0f9547d412f8266aa4292ebecd
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5045
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Add support for checking whether a cache is busy

This changeset adds support for checking whether the cache is
currently busy and a timing request would be rejected.

Change-Id: I5e37b011b2387b1fa1c9e687b9be545f06ffb5f5
Reviewed-on: https://gem5-review.googlesource.com/5042
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

misc: Rename misc.(hh|cc) to logging.(hh|cc)

These files aren't a collection of miscellaneous stuff, they're the
definition of the Logger interface, and a few utility macros for
calling into that interface (panic, warn, etc.).

Change-Id: I84267ac3f45896a83c0ef027f8f19c5e9a5667d1
Reviewed-on: https://gem5-review.googlesource.com/6226
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>