History log of /gem5/src/learning_gem5/part2/
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14252:1659a606447f 06-Sep-2019 Gabe Black <gabeblack@google.com>

dev: Scrub out some lingering uses of MemObject.

MemObject doesn't do anything any more, and is basically just an alias
for ClockedObject.

Change-Id: Ic0e1658609e4e1d7f4b829fbc421f222e4869dee
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20719
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

13841:8772d37d4bf6 05-Apr-2019 Jason Lowe-Power <jason@lowepower.com>

learning_gem5: Fix vector port panic in SimpleCache

Change-Id: I0f3b71fdbed77690c533d9d14e774ab2cc08c053
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17870
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>

13784:1941dc118243 07-Mar-2019 Gabe Black <gabeblack@google.com>

arch, cpu, dev, gpu, mem, sim, python: start using getPort.

Replace the getMasterPort, getSlavePort, and getEthPort functions
with getPort, and remove extraneous mechanisms that are no longer
necessary.

Change-Id: Iab7e3c02d2f3a0cf33e7e824e18c28646b5bc318
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17040
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>


/gem5/src/arch/arm/table_walker.cc
/gem5/src/arch/arm/table_walker.hh
/gem5/src/arch/arm/tlb.cc
/gem5/src/arch/arm/tlb.hh
/gem5/src/arch/generic/tlb.hh
/gem5/src/arch/x86/interrupts.hh
/gem5/src/arch/x86/pagetable_walker.cc
/gem5/src/arch/x86/pagetable_walker.hh
/gem5/src/arch/x86/tlb.cc
/gem5/src/arch/x86/tlb.hh
/gem5/src/cpu/base.cc
/gem5/src/cpu/base.hh
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.cc
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.hh
/gem5/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc
/gem5/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh
/gem5/src/cpu/testers/memtest/memtest.cc
/gem5/src/cpu/testers/memtest/memtest.hh
/gem5/src/cpu/testers/rubytest/RubyTester.cc
/gem5/src/cpu/testers/rubytest/RubyTester.hh
/gem5/src/cpu/testers/traffic_gen/base.cc
/gem5/src/cpu/testers/traffic_gen/base.hh
/gem5/src/cpu/trace/trace_cpu.cc
/gem5/src/dev/dma_device.cc
/gem5/src/dev/dma_device.hh
/gem5/src/dev/io_device.cc
/gem5/src/dev/io_device.hh
/gem5/src/dev/net/Ethernet.py
/gem5/src/dev/net/SConscript
/gem5/src/dev/net/dist_etherlink.cc
/gem5/src/dev/net/dist_etherlink.hh
/gem5/src/dev/net/etherbus.cc
/gem5/src/dev/net/etherbus.hh
/gem5/src/dev/net/etherdevice.hh
/gem5/src/dev/net/etherlink.cc
/gem5/src/dev/net/etherlink.hh
/gem5/src/dev/net/etherobject.hh
/gem5/src/dev/net/etherswitch.cc
/gem5/src/dev/net/etherswitch.hh
/gem5/src/dev/net/ethertap.cc
/gem5/src/dev/net/ethertap.hh
/gem5/src/dev/net/i8254xGBe.cc
/gem5/src/dev/net/i8254xGBe.hh
/gem5/src/dev/net/ns_gige.cc
/gem5/src/dev/net/ns_gige.hh
/gem5/src/dev/net/python.cc
/gem5/src/dev/net/sinic.cc
/gem5/src/dev/net/sinic.hh
/gem5/src/dev/pci/copy_engine.cc
/gem5/src/dev/pci/copy_engine.hh
/gem5/src/dev/x86/i82094aa.cc
/gem5/src/dev/x86/i82094aa.hh
/gem5/src/gpu-compute/compute_unit.hh
/gem5/src/gpu-compute/dispatcher.cc
/gem5/src/gpu-compute/dispatcher.hh
/gem5/src/gpu-compute/gpu_tlb.cc
/gem5/src/gpu-compute/gpu_tlb.hh
/gem5/src/gpu-compute/lds_state.hh
/gem5/src/gpu-compute/tlb_coalescer.cc
/gem5/src/gpu-compute/tlb_coalescer.hh
simple_cache.cc
simple_cache.hh
simple_memobj.cc
simple_memobj.hh
/gem5/src/mem/addr_mapper.cc
/gem5/src/mem/addr_mapper.hh
/gem5/src/mem/bridge.cc
/gem5/src/mem/bridge.hh
/gem5/src/mem/cache/base.cc
/gem5/src/mem/cache/base.hh
/gem5/src/mem/comm_monitor.cc
/gem5/src/mem/comm_monitor.hh
/gem5/src/mem/dram_ctrl.cc
/gem5/src/mem/dram_ctrl.hh
/gem5/src/mem/dramsim2.cc
/gem5/src/mem/dramsim2.hh
/gem5/src/mem/external_master.cc
/gem5/src/mem/external_master.hh
/gem5/src/mem/external_slave.cc
/gem5/src/mem/external_slave.hh
/gem5/src/mem/mem_checker_monitor.cc
/gem5/src/mem/mem_checker_monitor.hh
/gem5/src/mem/mem_delay.cc
/gem5/src/mem/mem_delay.hh
/gem5/src/mem/mem_object.cc
/gem5/src/mem/mem_object.hh
/gem5/src/mem/qos/mem_sink.cc
/gem5/src/mem/qos/mem_sink.hh
/gem5/src/mem/ruby/network/MessageBuffer.hh
/gem5/src/mem/ruby/network/Network.hh
/gem5/src/mem/ruby/network/dummy_port.hh
/gem5/src/mem/ruby/slicc_interface/AbstractController.cc
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/system/RubyPort.cc
/gem5/src/mem/ruby/system/RubyPort.hh
/gem5/src/mem/serial_link.cc
/gem5/src/mem/serial_link.hh
/gem5/src/mem/simple_mem.cc
/gem5/src/mem/simple_mem.hh
/gem5/src/mem/xbar.cc
/gem5/src/mem/xbar.hh
/gem5/src/python/SConscript
/gem5/src/python/pybind11/pybind.hh
/gem5/src/python/pybind11/pyobject.cc
/gem5/src/sim/SConscript
/gem5/src/sim/cxx_manager.cc
/gem5/src/sim/init.cc
/gem5/src/sim/python.cc
/gem5/src/sim/system.cc
/gem5/src/sim/system.hh
13665:9c7fe3811b88 25-Jan-2019 Andreas Sandberg <andreas.sandberg@arm.com>

python: Don't assume SimObjects live in the global namespace

The importer in Python 3 doesn't like the way we import SimObjects
from the global namespace. Convert the existing SimObject declarations
to import from m5.objects. As a side-effect, this makes these files
consistent with configuration files.

Change-Id: I11153502b430822130722839e1fa767b82a027aa
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15981
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>


/gem5/src/arch/alpha/AlphaSystem.py
/gem5/src/arch/alpha/AlphaTLB.py
/gem5/src/arch/arm/ArmISA.py
/gem5/src/arch/arm/ArmNativeTrace.py
/gem5/src/arch/arm/ArmPMU.py
/gem5/src/arch/arm/ArmSemihosting.py
/gem5/src/arch/arm/ArmSystem.py
/gem5/src/arch/arm/ArmTLB.py
/gem5/src/arch/arm/tracers/TarmacTrace.py
/gem5/src/arch/mips/MipsSystem.py
/gem5/src/arch/mips/MipsTLB.py
/gem5/src/arch/power/PowerTLB.py
/gem5/src/arch/riscv/RiscvSystem.py
/gem5/src/arch/riscv/RiscvTLB.py
/gem5/src/arch/sparc/SparcNativeTrace.py
/gem5/src/arch/sparc/SparcSystem.py
/gem5/src/arch/sparc/SparcTLB.py
/gem5/src/arch/x86/X86LocalApic.py
/gem5/src/arch/x86/X86NativeTrace.py
/gem5/src/arch/x86/X86System.py
/gem5/src/arch/x86/X86TLB.py
/gem5/src/base/vnc/Vnc.py
/gem5/src/cpu/BaseCPU.py
/gem5/src/cpu/CPUTracers.py
/gem5/src/cpu/CheckerCPU.py
/gem5/src/cpu/DummyChecker.py
/gem5/src/cpu/InstPBTrace.py
/gem5/src/cpu/kvm/BaseKvmCPU.py
/gem5/src/cpu/kvm/X86KvmCPU.py
/gem5/src/cpu/minor/MinorCPU.py
/gem5/src/cpu/o3/FUPool.py
/gem5/src/cpu/o3/FuncUnitConfig.py
/gem5/src/cpu/o3/O3CPU.py
/gem5/src/cpu/o3/O3Checker.py
/gem5/src/cpu/o3/probe/ElasticTrace.py
/gem5/src/cpu/o3/probe/SimpleTrace.py
/gem5/src/cpu/simple/AtomicSimpleCPU.py
/gem5/src/cpu/simple/BaseSimpleCPU.py
/gem5/src/cpu/simple/NonCachingSimpleCPU.py
/gem5/src/cpu/simple/TimingSimpleCPU.py
/gem5/src/cpu/simple/probes/SimPoint.py
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.py
/gem5/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.py
/gem5/src/cpu/testers/memtest/MemTest.py
/gem5/src/cpu/testers/rubytest/RubyTester.py
/gem5/src/cpu/testers/traffic_gen/BaseTrafficGen.py
/gem5/src/cpu/testers/traffic_gen/PyTrafficGen.py
/gem5/src/cpu/testers/traffic_gen/TrafficGen.py
/gem5/src/cpu/trace/TraceCPU.py
/gem5/src/dev/BadDevice.py
/gem5/src/dev/Device.py
/gem5/src/dev/Platform.py
/gem5/src/dev/alpha/AlphaBackdoor.py
/gem5/src/dev/alpha/Tsunami.py
/gem5/src/dev/arm/EnergyCtrl.py
/gem5/src/dev/arm/FlashDevice.py
/gem5/src/dev/arm/Gic.py
/gem5/src/dev/arm/NoMali.py
/gem5/src/dev/arm/RealView.py
/gem5/src/dev/arm/UFSHostDevice.py
/gem5/src/dev/arm/VirtIOMMIO.py
/gem5/src/dev/i2c/I2C.py
/gem5/src/dev/mips/Malta.py
/gem5/src/dev/net/Ethernet.py
/gem5/src/dev/pci/CopyEngine.py
/gem5/src/dev/pci/PciDevice.py
/gem5/src/dev/pci/PciHost.py
/gem5/src/dev/serial/Terminal.py
/gem5/src/dev/serial/Uart.py
/gem5/src/dev/sparc/T1000.py
/gem5/src/dev/storage/Ide.py
/gem5/src/dev/virtio/VirtIO.py
/gem5/src/dev/virtio/VirtIO9P.py
/gem5/src/dev/virtio/VirtIOBlock.py
/gem5/src/dev/virtio/VirtIOConsole.py
/gem5/src/dev/x86/Cmos.py
/gem5/src/dev/x86/I8042.py
/gem5/src/dev/x86/I82094AA.py
/gem5/src/dev/x86/I8237.py
/gem5/src/dev/x86/I8254.py
/gem5/src/dev/x86/I8259.py
/gem5/src/dev/x86/Pc.py
/gem5/src/dev/x86/PcSpeaker.py
/gem5/src/dev/x86/SouthBridge.py
/gem5/src/gpu-compute/GPU.py
/gem5/src/gpu-compute/LdsState.py
SimpleCache.py
SimpleMemobj.py
/gem5/src/mem/AbstractMemory.py
/gem5/src/mem/AddrMapper.py
/gem5/src/mem/Bridge.py
/gem5/src/mem/CommMonitor.py
/gem5/src/mem/DRAMCtrl.py
/gem5/src/mem/ExternalMaster.py
/gem5/src/mem/ExternalSlave.py
/gem5/src/mem/HMCController.py
/gem5/src/mem/MemChecker.py
/gem5/src/mem/MemDelay.py
/gem5/src/mem/MemObject.py
/gem5/src/mem/SerialLink.py
/gem5/src/mem/SimpleMemory.py
/gem5/src/mem/XBar.py
/gem5/src/mem/cache/Cache.py
/gem5/src/mem/cache/prefetch/Prefetcher.py
/gem5/src/mem/cache/tags/Tags.py
/gem5/src/mem/probes/MemFootprintProbe.py
/gem5/src/mem/probes/MemTraceProbe.py
/gem5/src/mem/probes/StackDistProbe.py
/gem5/src/mem/qos/QoSMemCtrl.py
/gem5/src/mem/qos/QoSMemSinkCtrl.py
/gem5/src/mem/ruby/network/BasicRouter.py
/gem5/src/mem/ruby/network/Network.py
/gem5/src/mem/ruby/network/garnet2.0/GarnetLink.py
/gem5/src/mem/ruby/network/garnet2.0/GarnetNetwork.py
/gem5/src/mem/ruby/network/simple/SimpleLink.py
/gem5/src/mem/ruby/network/simple/SimpleNetwork.py
/gem5/src/mem/ruby/slicc_interface/Controller.py
/gem5/src/mem/ruby/structures/LRUReplacementPolicy.py
/gem5/src/mem/ruby/structures/PseudoLRUReplacementPolicy.py
/gem5/src/mem/ruby/structures/RubyCache.py
/gem5/src/mem/ruby/structures/RubyPrefetcher.py
/gem5/src/mem/ruby/system/GPUCoalescer.py
/gem5/src/mem/ruby/system/RubySystem.py
/gem5/src/mem/ruby/system/Sequencer.py
/gem5/src/mem/ruby/system/VIPERCoalescer.py
/gem5/src/mem/ruby/system/WeightedLRUReplacementPolicy.py
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/sim/System.py
/gem5/src/sim/TickedObject.py
/gem5/src/sim/power/MathExprPowerModel.py
/gem5/src/sim/power/ThermalModel.py
12749:223c83ed9979 04-Jun-2018 Giacomo Travaglini <giacomo.travaglini@arm.com>

misc: Using smart pointers for memory Requests

This patch is changing the underlying type for RequestPtr from Request*
to shared_ptr<Request>. Having memory requests being managed by smart
pointers will simplify the code; it will also prevent memory leakage and
dangling pointers.

Change-Id: I7749af38a11ac8eb4d53d8df1252951e0890fde3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10996
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>


/gem5/ext/sst/ExtMaster.cc
/gem5/ext/sst/ExtSlave.cc
/gem5/src/arch/alpha/locked_mem.hh
/gem5/src/arch/alpha/tlb.cc
/gem5/src/arch/alpha/tlb.hh
/gem5/src/arch/arm/isa.cc
/gem5/src/arch/arm/locked_mem.hh
/gem5/src/arch/arm/stage2_lookup.cc
/gem5/src/arch/arm/stage2_lookup.hh
/gem5/src/arch/arm/stage2_mmu.cc
/gem5/src/arch/arm/stage2_mmu.hh
/gem5/src/arch/arm/table_walker.cc
/gem5/src/arch/arm/table_walker.hh
/gem5/src/arch/arm/tlb.cc
/gem5/src/arch/arm/tlb.hh
/gem5/src/arch/arm/tracers/tarmac_parser.cc
/gem5/src/arch/arm/tracers/tarmac_parser.hh
/gem5/src/arch/arm/vtophys.cc
/gem5/src/arch/generic/locked_mem.hh
/gem5/src/arch/generic/tlb.cc
/gem5/src/arch/generic/tlb.hh
/gem5/src/arch/hsail/insts/mem.hh
/gem5/src/arch/mips/locked_mem.hh
/gem5/src/arch/mips/tlb.cc
/gem5/src/arch/mips/tlb.hh
/gem5/src/arch/power/tlb.cc
/gem5/src/arch/power/tlb.hh
/gem5/src/arch/riscv/locked_mem.hh
/gem5/src/arch/riscv/tlb.cc
/gem5/src/arch/riscv/tlb.hh
/gem5/src/arch/sparc/tlb.cc
/gem5/src/arch/sparc/tlb.hh
/gem5/src/arch/x86/intmessage.hh
/gem5/src/arch/x86/pagetable_walker.cc
/gem5/src/arch/x86/pagetable_walker.hh
/gem5/src/arch/x86/tlb.cc
/gem5/src/arch/x86/tlb.hh
/gem5/src/cpu/base.cc
/gem5/src/cpu/base_dyn_inst.hh
/gem5/src/cpu/base_dyn_inst_impl.hh
/gem5/src/cpu/checker/cpu.cc
/gem5/src/cpu/checker/cpu.hh
/gem5/src/cpu/checker/cpu_impl.hh
/gem5/src/cpu/kvm/base.cc
/gem5/src/cpu/kvm/x86_cpu.cc
/gem5/src/cpu/minor/fetch1.cc
/gem5/src/cpu/minor/fetch1.hh
/gem5/src/cpu/minor/lsq.cc
/gem5/src/cpu/minor/lsq.hh
/gem5/src/cpu/o3/cpu.hh
/gem5/src/cpu/o3/fetch.hh
/gem5/src/cpu/o3/fetch_impl.hh
/gem5/src/cpu/o3/lsq.hh
/gem5/src/cpu/o3/lsq_impl.hh
/gem5/src/cpu/o3/lsq_unit.hh
/gem5/src/cpu/o3/lsq_unit_impl.hh
/gem5/src/cpu/simple/atomic.cc
/gem5/src/cpu/simple/atomic.hh
/gem5/src/cpu/simple/base.cc
/gem5/src/cpu/simple/base.hh
/gem5/src/cpu/simple/timing.cc
/gem5/src/cpu/simple/timing.hh
/gem5/src/cpu/testers/directedtest/InvalidateGenerator.cc
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.cc
/gem5/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
/gem5/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc
/gem5/src/cpu/testers/memtest/memtest.cc
/gem5/src/cpu/testers/rubytest/Check.cc
/gem5/src/cpu/testers/rubytest/RubyTester.cc
/gem5/src/cpu/testers/traffic_gen/base_gen.cc
/gem5/src/cpu/testers/traffic_gen/traffic_gen.cc
/gem5/src/cpu/trace/trace_cpu.cc
/gem5/src/cpu/translation.hh
/gem5/src/dev/dma_device.cc
/gem5/src/dev/x86/i82094aa.cc
/gem5/src/gpu-compute/compute_unit.cc
/gem5/src/gpu-compute/fetch_unit.cc
/gem5/src/gpu-compute/gpu_tlb.cc
/gem5/src/gpu-compute/gpu_tlb.hh
/gem5/src/gpu-compute/shader.cc
/gem5/src/gpu-compute/shader.hh
simple_cache.cc
/gem5/src/mem/abstract_mem.cc
/gem5/src/mem/abstract_mem.hh
/gem5/src/mem/cache/base.cc
/gem5/src/mem/cache/blk.hh
/gem5/src/mem/cache/cache.cc
/gem5/src/mem/cache/mshr.cc
/gem5/src/mem/cache/noncoherent_cache.cc
/gem5/src/mem/cache/prefetch/queued.cc
/gem5/src/mem/packet.hh
/gem5/src/mem/page_table.cc
/gem5/src/mem/page_table.hh
/gem5/src/mem/port.cc
/gem5/src/mem/port_proxy.cc
/gem5/src/mem/request.hh
/gem5/src/mem/ruby/slicc_interface/AbstractController.cc
/gem5/src/mem/ruby/system/CacheRecorder.cc
/gem5/src/mem/ruby/system/GPUCoalescer.cc
/gem5/src/mem/ruby/system/GPUCoalescer.hh
/gem5/src/mem/ruby/system/RubyPort.cc
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/util/tlm/src/sc_master_port.cc
12360:a3c5434d3c4f 05-Dec-2017 Hanhwi Jang <jang.hanhwi@gmail.com>

learning-gem5: Fix missing misc.hh in hello_object.cc

misc.hh has been renamed in
commit 1088f0c4ac3999fc3c363cc51daef4cfb360a2bd

Change-Id: Ic4f8c6423e6a5466f8d924e793a24f62bb4eca9c
Reviewed-on: https://gem5-review.googlesource.com/6361
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

12339:1141f798a210 06-Oct-2017 Jason Lowe-Power <jason@lowepower.com>

learning_gem5: Adding code for SimpleCache

This is the rest of the code for part 2.

See http://learning.gem5.org/book/part2/simplecache.html

Change-Id: I5db099266a1196914656be3858fdd5fb4f8eab48
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/5023
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

12338:ae907b0a57c2 06-Oct-2017 Jason Lowe-Power <jason@lowepower.com>

learning_gem5: Adds the simple MemObject code

Adding more code from Learning gem5 Part II

See http://learning.gem5.org/book/part2/memoryobject.html

Change-Id: Iaa9480c5cdbe4090364f02e81dc1d0a0ddac392a
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/5022
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

12337:97857a19fb72 06-Oct-2017 Jason Lowe-Power <jason@lowepower.com>

learning_gem5: Add code for hello-goodbye example

Adding more code from Learning gem5 Part II

See http://learning.gem5.org/book/part2/parameters.html

Change-Id: I9fe5655239e011c718c5cf5fd62bebcda66ea966
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/5021
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

12336:9ead840035df 06-Oct-2017 Jason Lowe-Power <jason@lowepower.com>

learning_gem5: Add code for simple SimObject

This adds code from Learning gem5 Part II.

See http://learning.gem5.org/book/part2/helloobject.html

Change-Id: Ic2caa07876ca57f937729c27ce29b2cd8bf2380c
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/5020
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>