14021:d23e5577e8f5 |
02-May-2019 |
Gabe Black <gabeblack@google.com> |
kern: Replace an explicitly instantiated port proxy with one from the tc.
That avoids having to know what type of proxy to create.
Change-Id: I311e770ab720061b52f29df0dcc2273e028aa34a Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18578 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
13994:a18a6bb72a49 |
18-Apr-2018 |
Tony Gutierrez <anthony.gutierrez@amd.com> |
sim-se: remove /sys from special paths
Currently, the open system call implementation in SE mode treats /sys/ as a special path that is opened using a special open handler. The ROC runtime, however, reads several files in /sys/ that are supported via path redirection. Here we remove /sys/ from the special files so that the necessary files may be read via path redirection.
Change-Id: Ifdab38ea1e6cc486ad43aec96b6e032fe63f137d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12127 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com> Tested-by: kokoro <noreply+kokoro@google.com> |
13981:577196ddd040 |
02-May-2019 |
Gabe Black <gabeblack@google.com> |
arch, base, cpu, dev, mem, sim: Remove #if 0-ed out code.
This code will be preserved through version control, but otherwise creates clutter and will rot in place since it's never compiled.
Change-Id: Id265f6deac445116843956ea5cf1210d8127274e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18608 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com> |
13905:5cf30883255c |
27-Apr-2019 |
Gabe Black <gabeblack@google.com> |
arch: cpu: Track kernel stats using the base ISA agnostic type.
Then cast to the ISA specific type when necessary. This removes (mostly) an ISA specific aspect to some of the interfaces. The ISA specific version of the kernel stats still needs to be constructed and stored in a few places which means that kernel_stats.hh still needs to be a switching arch header, for instance.
In the future, I'd like to make the kernel its own object like the Process objects in SE mode, and then it would be able to instantiate and maintain its own stats.
Change-Id: I8309d49019124f6bea1482aaea5b5b34e8c97433 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18429 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
13893:0e863b6c441a |
24-Apr-2019 |
Gabe Black <gabeblack@google.com> |
mem: Remove the ISA specialized versions of port proxy's read/write.
These selected their behavior based on ifdefs and had to be disabled when on the NULL ISA. The versions which take an explicit endianness have been renamed to just read/write instead of readGtoH and writeHtoG since the direction of the translation is obvious from context.
Change-Id: I6cfbfda6c4481962d442d3370534e50532d41814 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18372 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com> |
13883:f44e21d3aaa7 |
18-Apr-2018 |
David Hashe <david.hashe@amd.com> |
sim-se: add a faux-filesystem
This change introduces the concept of a faux-filesystem. The faux-filesystem creates a directory structure in m5out (or whatever output dir the user specifies) where system calls may be redirected.
This is useful to avoid non-determinism when reading files with varying path names (e.g., variations from run-to-run if the simulation is scheduled on a cluster where paths may change).
Also, this changeset allows circumventing host pseudofiles which have information specific to the host processor (such as cache hierarchy or processor information). Bypassing host pseudofiles can be useful when executing runtimes in the absence of an operating system kernel since runtimes may try to query standard files (i.e. /proc or /sys) which are not relevant to an application executing in syscall emulation mode.
Change-Id: I90821b3b403168b904a662fa98b85def1628621c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12119 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com> |
13651:b33db942f760 |
02-Apr-2018 |
Moyang Wang <mw828@cornell.edu> |
kern,sim: implement FUTEX_WAKE_OP
This patch implements FUTEX_WAKE_OP operation in the futex syscall. Below is its description:
int futex(int *uaddr, int futex_op, int val, const struct timespec *timeout, int *uaddr2, int val3);
This operation was added to support some user-space use cases where more than one futex must be handled at the same time. The most notable example is the implementation of pthread_cond_signal(3), which requires operations on two futexes, the one used to implement the mutex and the one used in the implementation of the wait queue associated with the condition variable. FUTEX_WAKE_OP allows such cases to be implemented without leading to high rates of contention and context switching.
Reference: http://man7.org/linux/man-pages/man2/futex.2.html
Change-Id: I215f3c2a7bdc6374e5dfe06ee721c76933a10f2d Reviewed-on: https://gem5-review.googlesource.com/c/9630 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
13650:93efc0143eb7 |
02-Apr-2018 |
Moyang Wang <mw828@cornell.edu> |
sim, kern: support FUTEX_CMP_REQUEUE
This patch supports FUTEX_CMP_REQUEUE operation. Below is its description from Linux man page:
futex syscall: int futex(int *uaddr, int futex_op, int val, const struct timespec *timeout, int *uaddr2, int val3);
This operation first checks whether the location uaddr still contains the value val3. If not, the operation fails with the error EAGAIN. Otherwise, the operation wakes up a maximum of val waiters that are waiting on the futex at uaddr. If there are more than val waiters, then the remaining waiters are removed from the wait queue of the source futex at uaddr and added to the wait queue of the target futex at uaddr2. The val2 argument specifies an upper limit on the number of waiters that are requeued to the futex at uaddr2.
Reference: http://man7.org/linux/man-pages/man2/futex.2.html
Change-Id: I6d2ebd19a935b656d19d8342f7ab450c0d2031f4 Reviewed-on: https://gem5-review.googlesource.com/c/9629 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com> |
13642:253cda14088e |
02-Apr-2018 |
Tuan Ta <qtt2@cornell.edu> |
sim,kern: support FUTEX_WAIT_BITSET and FUTEX_WAKE_BITSET ops
This patch adds support for two operations in futex system call: FUTEX_WAIT_BITSET and FUTEX_WAKE_BITSET. The two operations are used to selectively wake up a certain thread waiting on a futex variable.
Basically each thread waiting on a futex variable is associated with a bitset that is checked when another thread tries to wake up all threads waiting on the futex variable.
Change-Id: I2300e53b144d8fae226423fa2efb0238c1d93ef9 Reviewed-on: https://gem5-review.googlesource.com/c/9621 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com> |
13570:b6484720c6a9 |
18-Apr-2018 |
Brandon Potter <brandon.potter@amd.com> |
sim-se: add syscalls related to polling
Fix poll so that it will use the syscall retry capability instead of causing a blocking call.
Add the accept and wait4 system calls.
Add polling to read to remove deadlocks that occur in the event queue that are caused by blocking system calls.
Modify the write system call to return an error number in case of error.
Change-Id: I0b4091a2e41e4187ebf69d63e0088f988f37d5da Reviewed-on: https://gem5-review.googlesource.com/c/12115 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com> |
12591:48dfacae20ba |
25-Jul-2017 |
Jason Lowe-Power <jason@lowepower.com> |
sim-se: Add /sys/devices/system/cpu/online file
Add the special file /sys/devices/system/cpu/online to the files that gem5 knows how to handle in SE mode. This file lists the CPUs that are active. For instance, in an 8 CPU system it is the following: 0-7
This implementation simply returns a file that is 0-%d where %d is the current number of thread contexts.
This file is required for C++11 threads with gcc 4.8 and above.
Change-Id: I0b566f77e75e9eca480509814d0fd038a231b940 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/8902 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com> |
12392:e0dbdf30a2a5 |
13-Dec-2017 |
Jason Lowe-Power <jason@lowepower.com> |
misc: Updates for gcc7.2 for x86
GCC 7.2 is much stricter than previous GCC versions. The following changes are needed:
* There is now a warning if there is an implicit fallthrough between two case statments. C++17 adds the [[fallthrough]]; declaration. However, to support non C++17 standards (i.e., C++11), we use M5_FALLTHROUGH. M5_FALLTHROUGH checks for [[fallthrough]] compliant C++17 compiler and if that doesn't exist, it defaults to nothing (no older compilers generate warnings). * The above resulted in a couple of bugs that were found. This is noted in the review request on gerrit. * throw() for dynamic exception specification is deprecated * There were a couple of new uninitialized variable warnings * Can no longer perform bitwise operations on a bool. * Must now include <functional> for std::function * Compiler bug for void* lambda. Changed to auto as work around. See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82878
Change-Id: I5d4c782a4e133fa4cdb119e35d9aff68c6e2958e Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/5802 Reviewed-by: Gabe Black <gabeblack@google.com> |
12334:e0ab29a34764 |
30-Nov-2017 |
Gabe Black <gabeblack@google.com> |
misc: Rename misc.(hh|cc) to logging.(hh|cc)
These files aren't a collection of miscellaneous stuff, they're the definition of the Logger interface, and a few utility macros for calling into that interface (panic, warn, etc.).
Change-Id: I84267ac3f45896a83c0ef027f8f19c5e9a5667d1 Reviewed-on: https://gem5-review.googlesource.com/6226 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Gabe Black <gabeblack@google.com> |
12182:acde8d31d970 |
25-Aug-2017 |
Gabe Black <gabeblack@google.com> |
stats: Move the swpipl function into the Alpha kernel stats.
This stat is only incremented by Alpha. Also move the _hwrei into the Alpha stats object since it's the class that actually sets up and maintains that value and it probably should have been there all along.
Change-Id: Ibd038a33230c01432c160490926d8e1e55f8ccb0 Reviewed-on: https://gem5-review.googlesource.com/4601 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
12181:2150eff234c1 |
25-Aug-2017 |
Gabe Black <gabeblack@google.com> |
stats: Get rid of some kernel stats related cruft.
The kernel stat mechanism should really be refactored and moved somewhere else, but in the mean time there's some old cruft that can be cleared away.
Change-Id: I21e725de590dda0d20bf3bc675bbe976c7b1bd86 Reviewed-on: https://gem5-review.googlesource.com/4600 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
11907:48a3d32da9d8 |
01-Mar-2017 |
Brandon Potter <Brandon.Potter@amd.com> |
syscall-emul: Add functionality to open syscalls
This changeset adds refactors the existing open system call, adds the openat variant (enabled for x86 builds), and adds additional "special file" test cases for /proc/meminfo and /etc/passwd.
Change-Id: I6f429db65bbf2a28ffa3fd12df518c2d0de49663 Reviewed-on: https://gem5-review.googlesource.com/2265 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Michael LeBeane <Michael.Lebeane@amd.com> |
11851:824055fe6b30 |
09-Nov-2016 |
Brandon Potter <brandon.potter@amd.com> |
syscall_emul: [patch 5/22] remove LiveProcess class and use Process instead
The EIOProcess class was removed recently and it was the only other class which derived from Process. Since every Process invocation is also a LiveProcess invocation, it makes sense to simplify the organization by combining the fields from LiveProcess into Process. |
11800:54436a1784dc |
09-Nov-2016 |
Brandon Potter <brandon.potter@amd.com> |
style: [patch 3/22] reduce include dependencies in some headers
Used cppclean to help identify useless includes and removed them. This involved erroneously included headers, but also cases where forward declarations could have been used rather than a full include. |
11793:ef606668d247 |
09-Nov-2016 |
Brandon Potter <brandon.potter@amd.com> |
style: [patch 1/22] use /r/3648/ to reorganize includes |
11705:d40bdd3c5778 |
17-Nov-2016 |
Andreas Hansson <andreas.hansson@arm.com> |
alpha: Remove ALPHA tru64 support and associated tests
No one appears to be using it, and it is causing build issues and increases the development and maintenance effort. |
11538:55014a40512c |
20-Jun-2016 |
Andreas Sandberg <andreas.sandberg@arm.com> |
kern, arm: Dump dmesg on kernel panic/oops
Add helper functions to dump the guest kernel's dmesg buffer to a text file in m5out. This functionality is split into two parts. First, a dmesg dump function that can be used in other places:
void Linux::dumpDmesg(ThreadContext *, std::ostream &)
This function is used to implement two PCEvents: DmesgDumpEvent and KernelPanic event. The only difference between the two is that the latter produces a gem5 panic instead of a warning in addition to dumping the kernel log.
Change-Id: I6d2af1d666ace57124089648ea906f6c787ac63c Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com> |
11414:cfad34a15729 |
01-Apr-2016 |
Steve Reinhardt <steve.reinhardt@amd.com> |
syscall_emul: remove mmapFlagTable
After all this it turns out we don't even use it. |
11413:3d47d83a48eb |
01-Apr-2016 |
Steve Reinhardt <steve.reinhardt@amd.com> |
syscall_emul: factor out flag tables into common file
The openFlagTable and mmapFlagTables for emulated Linux platforms are basically identical, but are specified repetitively for every platform. Use a common file that gets included for each platform so that we only have one copy, making them more consistent and simplifying changes (like adding #ifdefs).
In the process, made some minor fixes that slipped through due to previous inconsistencies, and added more #ifdefs to try to fix building on alternative hosts. |
11386:94c09b607a84 |
17-Mar-2016 |
Steve Reinhardt <steve.reinhardt@amd.com> |
syscall_emul: move mmapGrowsDown() to LiveProcess
The mmapGrowsDown() method was a static method on the OperatingSystem class (and derived classes), which worked OK for the templated syscall emulation methods, but made it hard to access elsewhere. This patch moves the method to be a virtual function on the LiveProcess method, where it can be overridden for specific platforms (for now, Alpha).
This patch also changes the value of mmapGrowsDown() from being false by default and true only on X86Linux32 to being true by default and false only on Alpha, which seems closer to reality (though in reality most people use ASLR and this doesn't really matter anymore).
In the process, also got rid of the unused mmap_start field on LiveProcess and OperatingSystem mmapGrowsUp variable. |
11382:654272b82e94 |
17-Mar-2016 |
Brandon Potter <brandon.potter@amd.com> |
syscall_emul: add many Linux kernel flags |
11381:516213d2f0cf |
17-Mar-2016 |
Brandon Potter <brandon.potter@amd.com> |
syscall_emul: rename OpenFlagTransTable struct
The structure definition only had the open system call flag set in mind when it was named, so we rename it here with the intention of using it to define additional tables to translate flags for other system calls in the future. |
11168:f98eb2da15a4 |
12-Oct-2015 |
Andreas Hansson <andreas.hansson@arm.com> |
misc: Remove redundant compiler-specific defines
This patch moves away from using M5_ATTR_OVERRIDE and the m5::hashmap (and similar) abstractions, as these are no longer needed with gcc 4.7 and clang 3.1 as minimum compiler versions. |
11166:9818190de72e |
10-Oct-2015 |
Joel Hestness <jthestness@gmail.com> |
sim: Don't quiesce UDelayEvents with 0 latency
ARM uses UDelayEvents to emulate kernel __*udelay functions and speed up simulation. UDelayEvents call Pseudoinst::quiesceNs to quiesce the system for a specified delay. Changeset 10341:0b4d10f53c2d introduced the requirement that any quiesce process that is started must also be completed by scheduling an EndQuiesceEvent. This change causes the CPU to hang if an IsQuiesce instruction is executed, but the corresponding EndQuiesceEvent is not scheduled.
Changeset 11058:d0934b57735a introduces a fix for uses of PseudoInst::quiesce* that would conditionally execute the EndQuiesceEvent. ARM UDelayEvents specify quiesce period of 0 ns (src/arch/arm/linux/system.cc), so changeset 11058 causes these events to now execute full quiesce processes, greatly increasing the total instructions executed in kernel delay loops and slowing simulation.
This patch updates the UDelayEvent to conditionally execute PseudoInst::quiesceNs (**a quiesce operation**) only if the specified delay is >0 ns. The result is ARM delay loops no longer execute instructions for quiesce handling, and regression time returns to normal. |
10932:cafae9abd4e4 |
24-Jul-2015 |
Brandon Potter <brandon.potter@amd.com> |
style: change Process function calls to use camelCase
The Process class methods were using an improper style and this subsequently bled into the system call code. The following regular expressions should be helpful if someone transitions private system call patches on top of these changesets:
s/alloc_fd/allocFD/ s/sim_fd(/simFD(/ s/sim_fd_obj/getFDEntry/ s/fix_file_offsets/fixFileOffsets/ s/find_file_offsets/findFileOffsets/ |
10905:a6ca6831e775 |
07-Jul-2015 |
Andreas Sandberg <andreas.sandberg@arm.com> |
sim: Refactor the serialization base class
Objects that are can be serialized are supposed to inherit from the Serializable class. This class is meant to provide a unified API for such objects. However, so far it has mainly been used by SimObjects due to some fundamental design limitations. This changeset redesigns to the serialization interface to make it more generic and hide the underlying checkpoint storage. Specifically:
* Add a set of APIs to serialize into a subsection of the current object. Previously, objects that needed this functionality would use ad-hoc solutions using nameOut() and section name generation. In the new world, an object that implements the interface has the methods serializeSection() and unserializeSection() that serialize into a named /subsection/ of the current object. Calling serialize() serializes an object into the current section.
* Move the name() method from Serializable to SimObject as it is no longer needed for serialization. The fully qualified section name is generated by the main serialization code on the fly as objects serialize sub-objects.
* Add a scoped ScopedCheckpointSection helper class. Some objects need to serialize data structures, that are not deriving from Serializable, into subsections. Previously, this was done using nameOut() and manual section name generation. To simplify this, this changeset introduces a ScopedCheckpointSection() helper class. When this class is instantiated, it adds a new /subsection/ and subsequent serialization calls during the lifetime of this helper class happen inside this section (or a subsection in case of nested sections).
* The serialize() call is now const which prevents accidental state manipulation during serialization. Objects that rely on modifying state can use the serializeOld() call instead. The default implementation simply calls serialize(). Note: The old-style calls need to be explicitly called using the serializeOld()/serializeSectionOld() style APIs. These are used by default when serializing SimObjects.
* Both the input and output checkpoints now use their own named types. This hides underlying checkpoint implementation from objects that need checkpointing and makes it easier to change the underlying checkpoint storage code. |
10810:683ab55819fd |
29-Apr-2015 |
Ruslan Bukin <br@bsdpad.com> |
arch, base, dev, kern, sym: FreeBSD support
This adds support for FreeBSD/aarch64 FS and SE mode (basic set of syscalls only)
Committed by: Nilay Vaish <nilay@cs.wisc.edu> |
10796:5bcba8001c7e |
22-Apr-2015 |
Brandon Potter <brandon.potter@amd.com> |
syscall_emul: implement clock_gettime system call |
10481:59fb5779ec6e |
16-Oct-2014 |
Andreas Hansson <andreas.hansson@arm.com> |
misc: Move AddrRangeList from port.hh to addr_range.hh
The new location seems like a better fit. The iterator typedefs are removed in favour of using C++11 auto. |
10468:8c1b836edc92 |
16-Oct-2014 |
Andreas Hansson <andreas.hansson@arm.com> |
dev: Use shared_ptr for Arguments::Data
This patch takes a first few steps in transitioning from the ad-hoc RefCountingPtr to the c++11 shared_ptr. There are no changes in behaviour, and the code modifications are mainly introducing the use of make_shared.
Note that the class could use unique_ptr rather than shared_ptr, was it not for the postfix increment and decrement operators. |
10318:98771a936b61 |
03-Sep-2014 |
Andreas Hansson <andreas.hansson@arm.com> |
arch: Cleanup unused ISA traits constants
This patch prunes unused values, and also unifies how the values are defined (not using an enum for ALPHA), aligning the use of int vs Addr etc.
The patch also removes the duplication of PageBytes/PageShift and VMPageSize/LogVMPageSize. For all ISAs the two pairs had identical values and the latter has been removed. |
10254:f2de979b7bb3 |
19-Jul-2014 |
Steve Reinhardt <steve.reinhardt@amd.com> |
kern: get rid of unused linux syscall files |
10027:532929273927 |
24-Jan-2014 |
Chris Adeniyi-Jones <Chris.Adeniyi-Jones@arm.com> |
sim: Add openat/fstatat syscalls and fix mremap
This patch adds support for the openat and fstatat syscalls and broadens the support for mremap to make it work on OS X. |
9850:87d6b41749e9 |
04-Sep-2013 |
Andreas Hansson <andreas.hansson@arm.com> |
arch: Resurrect the NOISA build target and rename it NULL
This patch makes it possible to once again build gem5 without any ISA. The main purpose is to enable work around the interconnect and memory system without having to build any CPU models or device models.
The regress script is updated to include the NULL ISA target. Currently no regressions make use of it, but all the testers could (and perhaps should) transition to it. |
9848:a733a8eb6363 |
04-Sep-2013 |
Andreas Hansson <andreas.hansson@arm.com> |
arch: Header clean up for NOISA resurrection
This patch is a first step to getting NOISA working again. A number of redundant includes make life more difficult than it has to be and this patch simply removes them. There are also some redundant forward declarations removed. |
9554:406fbcf60223 |
19-Feb-2013 |
Andreas Hansson <andreas.hansson@arm.com> |
scons: Add warning for missing declarations
This patch enables warnings for missing declarations. To avoid issues with SWIG-generated code, the warning is only applied to non-SWIG code. |
9550:e0e2c8f83d08 |
19-Feb-2013 |
Andreas Hansson <andreas.hansson@arm.com> |
scons: Fix up numerous warnings about name shadowing
This patch address the most important name shadowing warnings (as produced when using gcc/clang with -Wshadow). There are many locations where constructor parameters and function parameters shadow local variables, but these are left unchanged. |
9405:c0a0593510db |
07-Jan-2013 |
Andreas Hansson <andreas.hansson@arm.com> |
base: Encapsulate the underlying fields in AddrRange
This patch makes the start and end address private in a move to prevent direct manipulation and matching of ranges based on these fields. This is done so that a transition to ranges with interleaving support is possible.
As a result of hiding the start and end, a number of member functions are needed to perform the comparisons and manipulations that previously took place directly on the members. An accessor function is provided for the start address, and a function is added to test if an address is within a range. As a result of the latter the != and == operator is also removed in favour of the member function. A member function that returns a string representation is also created to allow debug printing.
In general, this patch does not add any functionality, but it does take us closer to a situation where interleaving (and more cleverness) can be added under the bonnet without exposing it to the user. More on that in a later patch. |
9238:9fa13250abd8 |
21-Sep-2012 |
Lluc Alvarez <lluc.alvarez@bsc.es> |
SE: Ignore FUTEX_PRIVATE_FLAG of sys_futex
This patch ignores the FUTEX_PRIVATE_FLAG of the sys_futex system call in SE mode.
With this patch, when sys_futex with the options FUTEX_WAIT_PRIVATE or FUTEX_WAKE_PRIVATE is emulated, the FUTEX_PRIVATE_FLAG is ignored and so their behaviours are the regular FUTEX_WAIT and FUTEX_WAKE.
Emulating FUTEX_WAIT_PRIVATE and FUTEX_WAKE_PRIVATE as if they were non-private is safe from a functional point of view. The FUTEX_PRIVATE_FLAG does not change the semantics of the futex, it's just a mechanism to improve performance under certain circunstances that can be ignored in SE mode. |
9146:a61fdbbc1d45 |
06-Aug-2012 |
Marc Orr <marc.orr@gmail.com> |
syscall emulation: Enabled getrlimit and getrusage for x86. Added/moved rlimit constants to base linux header file.
This patch is a revised version of Vince Weaver's earlier patch. |
9143:db55c4b5136e |
06-Aug-2012 |
Steve Reinhardt <steve.reinhardt@amd.com> |
syscall_emul: clean up open() code a bit. |
9141:593fe25c86a6 |
06-Aug-2012 |
Marc Orr <marc.orr@gmail.com> |
syscall emulation: Clean up ioctl handling, and implement for x86.
Enable different whitelists for different OS/arch combinations, since some use the generic Linux definitions only, and others use definitions inherited from earlier Unix flavors on those architectures.
Also update x86 function pointers so ioctl is no longer unimplemented on that platform.
This patch is a revised version of Vince Weaver's earlier patch. |
9112:6e854ea87bab |
11-Jul-2012 |
Marc Orr <marc.orr@gmail.com> |
syscall emulation: Add the futex system call. |
9089:da918cb3462e |
09-Jul-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
Port: Add getAddrRanges to master port (asking slave port)
This patch adds getAddrRanges to the master port, and thus avoids going through getSlavePort to be able to ask the slave. Similar to the previous patch that added isSnooping to the SlavePort, this patch aims to introduce an additional level of hierarchy in the ports (base port being protocol-agnostic) and getSlave/MasterPort will return port pointers to these base classes.
The function is named getAddrRanges also on the master port, but does nothing besides asking the connected slave port. The slave port, as before, has to provide an implementation and actually produce a list of address ranges. The initial design used the name getSlaveAddrRanges for the new function, but the more verbose name was later changed. |
9085:5f0321c03a26 |
02-Jul-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
gcc: Fix warnings for gcc 4.7 and clang 3.1
This patch fixes two warnings, one related to a narrowing conversion (int to MachInst), and one due to the cast operator for arguments and a mismatch in const-ness (const void* and void*). |
9034:8b9f227b64d8 |
30-May-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
gcc: Small fixes to compile with gcc 4.7
This patch makes two very minor changes to please gcc 4.7. The CopyData function no longer exists and this has been replaced. For some reason previous versions of gcc did not complain on the const char casting not having an implementation, but this is now addressed. |
8922:17f037ad8918 |
30-Mar-2012 |
William Wang <william.wang@arm.com> |
MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++ code, thus bringing the previous classification from the Python classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add assumptions and enfore compliance, also simplifying the two interfaces. As a starting point, isSnooping is confined to a master port, and getAddrRanges to slave ports. More of these specilisations are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and returns a port reference rather than a pointer as NULL would never be a valid return value. The default implementation of these two functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some code duplication, e.g. QueuedPort becomes QueuedMasterPort and QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort (avoiding multiple inheritance). With the later introduction of the port interfaces, moving the functionality outside the port itself, a lot of the duplicated code will disappear again. |
8852:c744483edfcf |
24-Feb-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
MEM: Make port proxies use references rather than pointers
This patch is adding a clearer design intent to all objects that would not be complete without a port proxy by making the proxies members rathen than dynamically allocated. In essence, if NULL would not be a valid value for the proxy, then we avoid using a pointer to make this clear.
The same approach is used for the methods using these proxies, such as loadSections, that now use references rather than pointers to better reflect the fact that NULL would not be an acceptable value (in fact the code would break and that is how this patch started out).
Overall the concept of "using a reference to express unconditional composition where a NULL pointer is never valid" could be done on a much broader scale throughout the code base, but for now it is only done in the locations affected by the proxies. |
8850:ed91b534ed04 |
24-Feb-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
CPU: Round-two unifying instr/data CPU ports across models
This patch continues the unification of how the different CPU models create and share their instruction and data ports. Most importantly, it forces every CPU to have an instruction and a data port, and gives these ports explicit getters in the BaseCPU (getDataPort and getInstPort). The patch helps in simplifying the code, make assumptions more explicit, andfurther ease future patches related to the CPU ports.
The biggest changes are in the in-order model (that was not modified in the previous unification patch), which now moves the ports from the CacheUnit to the CPU. It also distinguishes the instruction fetch and load-store unit from the rest of the resources, and avoids the use of indices and casting in favour of keeping track of these two units explicitly (since they are always there anyways). The atomic, timing and O3 model simply return references to their already existing ports. |
8808:8af87554ad7e |
31-Jan-2012 |
Gabe Black <gblack@eecs.umich.edu> |
Merge with main repository. |
8799:dac1e33e07b0 |
28-Jan-2012 |
Gabe Black <gblack@eecs.umich.edu> |
Merge with the main repo. |
8795:0909f8ed7aa0 |
07-Jan-2012 |
Gabe Black <gblack@eecs.umich.edu> |
Merge with main repository. |
8794:e2ac2b7164dd |
18-Nov-2011 |
Gabe Black <gblack@eecs.umich.edu> |
SE/FS: Get rid of includes of config/full_system.hh. |
8788:2d403a6d7078 |
13-Nov-2011 |
Gabe Black <gblack@eecs.umich.edu> |
SE/FS: Get rid of FULL_SYSTEM in kern. |
8780:89e0822462a1 |
01-Nov-2011 |
Gabe Black <gblack@eecs.umich.edu> |
SE/FS: Get rid of uses of FULL_SYSTEM in Alpha. |
8777:dd43f1c9fa0a |
31-Oct-2011 |
Gabe Black <gblack@eecs.umich.edu> |
SE/FS: Make the functions available from the TC consistent between SE and FS. |
8776:17efd86a39d3 |
30-Oct-2011 |
Gabe Black <gblack@eecs.umich.edu> |
SE/FS: Build the solaris object in both SE and FS. |
8774:232b5574d9c3 |
30-Oct-2011 |
Gabe Black <gblack@eecs.umich.edu> |
SE/FS: Compile in system events in SE mode. |
8770:81354d3836d4 |
30-Oct-2011 |
Gabe Black <gblack@eecs.umich.edu> |
SE/FS: Build syscall_emul.cc in FS mode. |
8767:e575781f71b8 |
30-Oct-2011 |
Gabe Black <gblack@eecs.umich.edu> |
SE/FS: Make getProcessPtr available in both modes, and get rid of FULL_SYSTEMs. |
8730:0a742249f76b |
30-Jan-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
MEM: Clean-up of Functional/Virtual/TranslatingPort remnants
This patch cleans up forward declarations and a member-function prototype that still referred to the old FunctionalPort, VirtualPort and TranslatingPort. There is no change in functionality. |
8711:c7e14f52c682 |
17-Jan-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
MEM: Separate queries for snooping and address ranges
This patch simplifies the address-range determination mechanism and also unifies the naming across ports and devices. It further splits the queries for determining if a port is snooping and what address ranges it responds to (aiming towards a separation of cache-maintenance ports and pure memory-mapped ports). Default behaviours are such that most ports do not have to define isSnooping, and master ports need not implement getAddrRanges. |
8706:b1838faf3bcc |
17-Jan-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
MEM: Add port proxies instead of non-structural ports
Port proxies are used to replace non-structural ports, and thus enable all ports in the system to correspond to a structural entity. This has the advantage of accessing memory through the normal memory subsystem and thus allowing any constellation of distributed memories, address maps, etc. Most accesses are done through the "system port" that is used for loading binaries, debugging etc. For the entities that belong to the CPU, e.g. threads and thread contexts, they wrap the CPU data port in a port proxy.
The following replacements are made: FunctionalPort > PortProxy TranslatingPort > SETranslatingPortProxy VirtualPort > FSTranslatingPortProxy |
8601:af28085882dc |
23-Oct-2011 |
Steve Reinhardt <steve.reinhardt@amd.com> |
SE: move page allocation from PageTable to Process
PageTable supported an allocate() call that called back through the Process to allocate memory, but did not have a method to map addresses without allocating new pages. It makes more sense for Process to do the allocation, so this method was renamed allocateMem() and moved to Process, and uses a new map() call on PageTable.
The remaining uses of the process pointer in PageTable were only to get the name and the PID, so by passing these in directly in the constructor, we can make PageTable completely independent of Process. |
8335:9228e00459d4 |
02-Jun-2011 |
Nathan Binkert <nate@binkert.org> |
scons: rename TraceFlags to DebugFlags |
8232:b28d06a175be |
15-Apr-2011 |
Nathan Binkert <nate@binkert.org> |
trace: reimplement the DTRACE function so it doesn't use a vector At the same time, rename the trace flags to debug flags since they have broader usage than simply tracing. This means that --trace-flags is now --debug-flags and --trace-help is now --debug-help |
8229:78bf55f23338 |
15-Apr-2011 |
Nathan Binkert <nate@binkert.org> |
includes: sort all includes |
8195:c6302ef82244 |
04-Apr-2011 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Fix multiplication error in udelay |
8143:b0b94a7b7c1f |
17-Mar-2011 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Detect and skip udelay() functions in linux kernel.
This change speeds up booting, especially in MP cases, by not executing udelay() on the core but instead skipping ahead tha amount of time that is being delayed. |
8138:f08692f2932e |
17-Mar-2011 |
Ali Saidi <Ali.Saidi@ARM.com> |
O3: Send instruction back to fetch on squash to seed predecoder correctly. |
7823:dac01f14f20f |
08-Jan-2011 |
Steve Reinhardt <steve.reinhardt@amd.com> |
Replace curTick global variable with accessor functions. This step makes it easy to replace the accessor functions (which still access a global variable) with ones that access per-thread curTick values. |
7811:a8fc35183c10 |
03-Jan-2011 |
Steve Reinhardt <steve.reinhardt@amd.com> |
Make commenting on close namespace brackets consistent.
Ran all the source files through 'perl -pi' with this script:
s|\s*(};?\s*)?/\*\s*(end\s*)?namespace\s*(\S+)\s*\*/(\s*})?|} // namespace $3|; s|\s*};?\s*//\s*(end\s*)?namespace\s*(\S+)\s*|} // namespace $2\n|; s|\s*};?\s*//\s*(\S+)\s*namespace\s*|} // namespace $1\n|;
Also did a little manual editing on some of the arch/*/isa_traits.hh files and src/SConscript. |
7768:cdb18c1b51ea |
19-Nov-2010 |
Ali Saidi <Ali.Saidi@ARM.com> |
SCons: Support building without an ISA |
7720:65d338a8dba4 |
31-Oct-2010 |
Gabe Black <gblack@eecs.umich.edu> |
ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.
This change is a low level and pervasive reorganization of how PCs are managed in M5. Back when Alpha was the only ISA, there were only 2 PCs to worry about, the PC and the NPC, and the lsb of the PC signaled whether or not you were in PAL mode. As other ISAs were added, we had to add an NNPC, micro PC and next micropc, x86 and ARM introduced variable length instruction sets, and ARM started to keep track of mode bits in the PC. Each CPU model handled PCs in its own custom way that needed to be updated individually to handle the new dimensions of variability, or, in the case of ARMs mode-bit-in-the-pc hack, the complexity could be hidden in the ISA at the ISA implementation's expense. Areas like the branch predictor hadn't been updated to handle branch delay slots or micropcs, and it turns out that had introduced a significant (10s of percent) performance bug in SPARC and to a lesser extend MIPS. Rather than perpetuate the problem by reworking O3 again to handle the PC features needed by x86, this change was introduced to rework PC handling in a more modular, transparent, and hopefully efficient way.
PC type:
Rather than having the superset of all possible elements of PC state declared in each of the CPU models, each ISA defines its own PCState type which has exactly the elements it needs. A cross product of canned PCState classes are defined in the new "generic" ISA directory for ISAs with/without delay slots and microcode. These are either typedef-ed or subclassed by each ISA. To read or write this structure through a *Context, you use the new pcState() accessor which reads or writes depending on whether it has an argument. If you just want the address of the current or next instruction or the current micro PC, you can get those through read-only accessors on either the PCState type or the *Contexts. These are instAddr(), nextInstAddr(), and microPC(). Note the move away from readPC. That name is ambiguous since it's not clear whether or not it should be the actual address to fetch from, or if it should have extra bits in it like the PAL mode bit. Each class is free to define its own functions to get at whatever values it needs however it needs to to be used in ISA specific code. Eventually Alpha's PAL mode bit could be moved out of the PC and into a separate field like ARM.
These types can be reset to a particular pc (where npc = pc + sizeof(MachInst), nnpc = npc + sizeof(MachInst), upc = 0, nupc = 1 as appropriate), printed, serialized, and compared. There is a branching() function which encapsulates code in the CPU models that checked if an instruction branched or not. Exactly what that means in the context of branch delay slots which can skip an instruction when not taken is ambiguous, and ideally this function and its uses can be eliminated. PCStates also generally know how to advance themselves in various ways depending on if they point at an instruction, a microop, or the last microop of a macroop. More on that later.
Ideally, accessing all the PCs at once when setting them will improve performance of M5 even though more data needs to be moved around. This is because often all the PCs need to be manipulated together, and by getting them all at once you avoid multiple function calls. Also, the PCs of a particular thread will have spatial locality in the cache. Previously they were grouped by element in arrays which spread out accesses.
Advancing the PC:
The PCs were previously managed entirely by the CPU which had to know about PC semantics, try to figure out which dimension to increment the PC in, what to set NPC/NNPC, etc. These decisions are best left to the ISA in conjunction with the PC type itself. Because most of the information about how to increment the PC (mainly what type of instruction it refers to) is contained in the instruction object, a new advancePC virtual function was added to the StaticInst class. Subclasses provide an implementation that moves around the right element of the PC with a minimal amount of decision making. In ISAs like Alpha, the instructions always simply assign NPC to PC without having to worry about micropcs, nnpcs, etc. The added cost of a virtual function call should be outweighed by not having to figure out as much about what to do with the PCs and mucking around with the extra elements.
One drawback of making the StaticInsts advance the PC is that you have to actually have one to advance the PC. This would, superficially, seem to require decoding an instruction before fetch could advance. This is, as far as I can tell, realistic. fetch would advance through memory addresses, not PCs, perhaps predicting new memory addresses using existing ones. More sophisticated decisions about control flow would be made later on, after the instruction was decoded, and handed back to fetch. If branching needs to happen, some amount of decoding needs to happen to see that it's a branch, what the target is, etc. This could get a little more complicated if that gets done by the predecoder, but I'm choosing to ignore that for now.
Variable length instructions:
To handle variable length instructions in x86 and ARM, the predecoder now takes in the current PC by reference to the getExtMachInst function. It can modify the PC however it needs to (by setting NPC to be the PC + instruction length, for instance). This could be improved since the CPU doesn't know if the PC was modified and always has to write it back.
ISA parser:
To support the new API, all PC related operand types were removed from the parser and replaced with a PCState type. There are two warts on this implementation. First, as with all the other operand types, the PCState still has to have a valid operand type even though it doesn't use it. Second, using syntax like PCS.npc(target) doesn't work for two reasons, this looks like the syntax for operand type overriding, and the parser can't figure out if you're reading or writing. Instructions that use the PCS operand (which I've consistently called it) need to first read it into a local variable, manipulate it, and then write it back out.
Return address stack:
The return address stack needed a little extra help because, in the presence of branch delay slots, it has to merge together elements of the return PC and the call PC. To handle that, a buildRetPC utility function was added. There are basically only two versions in all the ISAs, but it didn't seem short enough to put into the generic ISA directory. Also, the branch predictor code in O3 and InOrder were adjusted so that they always store the PC of the actual call instruction in the RAS, not the next PC. If the call instruction is a microop, the next PC refers to the next microop in the same macroop which is probably not desirable. The buildRetPC function advances the PC intelligently to the next macroop (in an ISA specific way) so that that case works.
Change in stats:
There were no change in stats except in MIPS and SPARC in the O3 model. MIPS runs in about 9% fewer ticks. SPARC runs with 30%-50% fewer ticks, which could likely be improved further by setting call/return instruction flags and taking advantage of the RAS.
TODO:
Add != operators to the PCState classes, defined trivially to be !(a==b). Smooth out places where PCs are split apart, passed around, and put back together later. I think this might happen in SPARC's fault code. Add ISA specific constructors that allow setting PC elements without calling a bunch of accessors. Try to eliminate the need for the branching() function. Factor out Alpha's PAL mode pc bit into a separate flag field, and eliminate places where it's blindly masked out or tested in the PC. |
7693:f1db1000d957 |
01-Oct-2010 |
Ali Saidi <Ali.Saidi@ARM.com> |
Debug: Implement getArgument() and function skipping for ARM.
In the process make add skipFuction() to handle isa specific function skipping instead of ifdefs and other ugliness. For almost all ABIs, 64 bit arguments can only start in even registers. Size is now passed to getArgument() so that 32 bit systems can make decisions about register selection for 64 bit arguments. The number argument is now passed by reference because getArgument() will need to change it based on the size of the argument and the current argument number.
For ARM, if the argument number is odd and a 64-bit register is requested the number must first be incremented to because all 64 bit arguments are passed in an even argument register. Then the number will be incremented again to access both halves of the argument. |
7678:f19b6a3a8cec |
13-Sep-2010 |
Gabe Black <gblack@eecs.umich.edu> |
Faults: Pass the StaticInst involved, if any, to a Fault's invoke method.
Also move the "Fault" reference counted pointer type into a separate file, sim/fault.hh. It would be better to name this less similarly to sim/faults.hh to reduce confusion, but fault.hh matches the name of the type. We could change Fault to FaultPtr to match other pointer types, and then changing the name of the file would make more sense. |
7676:92274350b953 |
10-Sep-2010 |
Nathan Binkert <nate@binkert.org> |
style: fix sorting of includes and whitespace in some files |
7076:88f29ad4fd08 |
06-May-2010 |
Nathan Binkert <nate@binkert.org> |
macos: MacOS has deprecated getdirentries, so just disable the code. Hopefully it isn't used much |
6744:408673e38566 |
14-Nov-2009 |
Ali Saidi <Ali.Saidi@arm.com> |
SE: Fix SE mode OS X compilation. |
6712:b95abe00dd9d |
04-Nov-2009 |
Nathan Binkert <nate@binkert.org> |
build: fix compile problems pointed out by gcc 4.4 |
6701:4842482e1bd1 |
30-Oct-2009 |
Gabe Black <gblack@eecs.umich.edu> |
Syscalls: Make system calls access arguments like a stack, not an array.
When accessing arguments for a syscall, the position of an argument depends on the policies of the ISA, how much space preceding arguments took up, and the "alignment" of the index for this particular argument into the number of possible storate locations. This change adjusts getSyscallArg to take its index parameter by reference instead of value and to adjust it to point to the possible location of the next argument on the stack, basically just after the current one. This way, the rules for the new argument can be applied locally without knowing about other arguments since those have already been taken into account implicitly.
All system calls have also been changed to reflect the new interface. In a number of cases this made the implementation clearer since it encourages arguments to be collected in one place in order and then used as necessary later, as opposed to scattering them throughout the function or using them in place in long expressions. It also discourages using getSyscallArg over and over to retrieve the same value when a temporary would do the job. |
6684:04cba5a03e2e |
24-Oct-2009 |
Timothy M. Jones <tjones1@inf.ed.ac.uk> |
syscall: Implementation of the time system call. |
6683:5e0fcc528fe5 |
24-Oct-2009 |
Timothy M. Jones <tjones1@inf.ed.ac.uk> |
syscall: Implementation of the times system call |
6672:b636411c118e |
02-Oct-2009 |
Gabe Black <gblack@eecs.umich.edu> |
SE mode: Make the direction anonymous mmaps move through memory configurable. |
6658:f4de76601762 |
23-Sep-2009 |
Nathan Binkert <nate@binkert.org> |
arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh |
6330:786136379872 |
09-Jul-2009 |
Gabe Black <gblack@eecs.umich.edu> |
Alpha: Pull the MiscRegFile fully into the ISA object. |
6326:008930a4ace5 |
09-Jul-2009 |
Gabe Black <gblack@eecs.umich.edu> |
Registers: Eliminate the ISA defined RegFile class. |
6313:95f69a436c82 |
09-Jul-2009 |
Gabe Black <gblack@eecs.umich.edu> |
Registers: Add an ISA object which replaces the MiscRegFile. This object encapsulates (or will eventually) the identity and characteristics of the ISA in the CPU. |
6227:a17798f2a52c |
05-Jun-2009 |
Nathan Binkert <nate@binkert.org> |
types: clean up types, especially signed vs unsigned |
6216:2f4020838149 |
17-May-2009 |
Nathan Binkert <nate@binkert.org> |
includes: sort includes again |
6215:9aed64c9f10f |
17-May-2009 |
Nathan Binkert <nate@binkert.org> |
includes: use base/types.hh not inttypes.h or stdint.h |
6214:1ec0ec8933ae |
17-May-2009 |
Nathan Binkert <nate@binkert.org> |
types: Move stuff for global types into src/base/types.hh |
6029:007c36616f47 |
15-Apr-2009 |
Steve Reinhardt <steve.reinhardt@amd.com> |
Get rid of the Unallocated thread context state. Basically merge it in with Halted. Also had to get rid of a few other functions that called ThreadContext::deallocate(), including: - InOrderCPU's setThreadRescheduleCondition. - ThreadContext::exit(). This function was there to avoid terminating simulation when one thread out of a multi-thread workload exits, but we need to find a better (non-cpu-centric) way. |
5999:3cf8e71257e0 |
05-Mar-2009 |
Nathan Binkert <nate@binkert.org> |
stats: Fix all stats usages to deal with template fixes |
5958:2d9737bf3c2f |
27-Feb-2009 |
Gabe Black <gblack@eecs.umich.edu> |
Processes: Make getting and setting system call arguments part of a process object. |
5795:72ce7502dc71 |
17-Jan-2009 |
Ali Saidi <saidi@eecs.umich.edu> |
Fix issue 326: glibc non-deterministic because it reads /proc |
5793:321f79ddb500 |
13-Jan-2009 |
Nathan Binkert <nate@binkert.org> |
SCons: centralize the Dir() workaround for newer versions of scons. Scons bug id: 2006 M5 Bug id: 308 |
5713:993c7952b930 |
02-Nov-2008 |
Lisa Hsu <hsul@eecs.umich.edu> |
Make it so that all thread contexts are registered with the System, even in SE. Process still keeps track of the tc's it owns, but registration occurs with the System, this eases the way for system-wide context Ids based on registration. |
5569:baeee670d4ce |
28-Sep-2008 |
Nathan Binkert <nate@binkert.org> |
style: Make a style pass over the whole arch/alpha directory. |
5566:3440c9ad49b4 |
28-Sep-2008 |
Nathan Binkert <nate@binkert.org> |
alpha: Get rid fo the namespace called EV5. We're never going to do an alpha platform other than the one we've got. |
5561:eb5664be6075 |
26-Sep-2008 |
Nathan Binkert <nate@binkert.org> |
Use logical operator instead of bitwise operator for correctness. |
5543:3af77710f397 |
10-Sep-2008 |
Ali Saidi <saidi@eecs.umich.edu> |
style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs |
5406:fc680749b40e |
11-Jun-2008 |
Ali Saidi <saidi@eecs.umich.edu> |
SCons: Fix more SCons version issues |
5403:92d376c98a41 |
20-May-2008 |
Stephen Hines <hines@cs.fsu.edu> |
SCons: Fixing SCons bug 2006 issues for non-alpha ISAs |
5401:40a49dafc572 |
06-May-2008 |
Ali Saidi <saidi@eecs.umich.edu> |
SCons: More scons fixing for SCons bug 2006 |
5202:ff56fa8c2091 |
31-Oct-2007 |
Steve Reinhardt <stever@gmail.com> |
String constant const-ness changes to placate g++ 4.2. Also some bug fixes in MIPS ISA uncovered by g++ warnings (Python string compares don't work in C++!). |
5192:582e583f8e7e |
31-Oct-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
Traceflags: Add SCons function to created a traceflag instead of having one file with them all. |
5191:bebbfea0baf3 |
31-Oct-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
Linux Support: Finally update vptr for new memory system. |
4826:259b996a6da6 |
01-Aug-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
Arguments: Get rid of duplicate code for the Arguments class in each architecture. Move the argument files to src/sim and add a utility.cc file with a function getArguments() that returns the given argument in the architecture specific fashion. getArguments() was getArg() is the architecture specific Argument class and has had all magic numbers replaced with meaningful constants. Also add a function to the Argument class for testing if an argument is NULL. |
4772:f08370a81812 |
27-Jul-2007 |
Gabe Black <gblack@eecs.umich.edu> |
X86: Fix argument register indexing. Code was assuming that all argument registers followed in order from ArgumentReg0. There is now an ArgumentReg array which is indexed to find the right index. There is a constant, NumArgumentRegs, which can be used to protect against using an invalid ArgumentReg. |
4475:fb185cc1c845 |
22-May-2007 |
Steve Reinhardt <stever@eecs.umich.edu> |
Change getDeviceAddressRanges to use bool for snoop arg. |
4429:74351f86f49a |
01-May-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
change the way dprintf works so the cache accesses required to fulfill the dprintf aren't show in between the Cycle: name: printing and the actual formatted string being printed |
4424:9034cc0615be |
30-Apr-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
always skip the debugprintf function (DebugPrintf traceflag shouldn't matter). Otherwise, when you turn on debugprintf alters the execution |
4400:619191b2f011 |
16-Apr-2007 |
Ron Dreslinski <rdreslin@umich.edu> |
Fixes for splash, may conflict with Korey's SMT work and doesn't support 03cpu yet.
src/cpu/simple/base.cc: Cpu's should start as unallocated, not suspended src/cpu/simple_thread.cc: Wait for a thread to be assigned to activate the cpu src/kern/tru64/tru64.hh: When looking for a open cpu to assign threads, look for an unallocated one, not a suspended one. |
4202:f7a05daec670 |
11-Mar-2007 |
Nathan Binkert <binkertn@umich.edu> |
Rework the way SCons recurses into subdirectories, making it automatic. The point is that now a subdirectory can be added to the build process just by creating a SConscript file in it. The process has two passes. On the first pass, all subdirs of the root of the tree are searched for SConsopts files. These files contain any command line options that ought to be added for a particular subdirectory. On the second pass, all subdirs of the src directory are searched for SConscript files. These files describe how to build any given subdirectory. I have added a Source() function. Any file (relative to the directory in which the SConscript resides) passed to that function is added to the build. Clean up everything to take advantage of Source(). function is added to the list of files to be built. |
4172:141705d83494 |
07-Mar-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
*MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg |
4167:ce5d0f62f13b |
06-Mar-2007 |
Nathan Binkert <binkertn@umich.edu> |
Move all of the parameters of the Root SimObject so they are directly configured by python. Move stuff from root.(cc|hh) to core.(cc|hh) since it really belogs there now. In the process, simplify how ticks are used in the python code. |
4046:ef34b290091e |
10-Feb-2007 |
Nathan Binkert <binkertn@umich.edu> |
Clean up tracing stuff more, get rid of the trace log since its not all that useful. Fix a few bugs with python/C++ integration. |
3594:e401993e0cbb |
10-Nov-2006 |
Kevin Lim <ktlim@umich.edu> |
Merge ktlim@zizzer:/bk/newmem into zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem |
3586:c5cc95fc5a61 |
09-Nov-2006 |
Gabe Black <gblack@eecs.umich.edu> |
Moved the Alpha MiscRegFile into it's own file, and got rid of the Alpha specific DepTag constants. |
3566:d2b4eef635f5 |
07-Nov-2006 |
Gabe Black <gblack@eecs.umich.edu> |
Fixed to account for branch delay slots. |
3565:6ad587fb7dfd |
07-Nov-2006 |
Gabe Black <gblack@eecs.umich.edu> |
Put kernel_stats back into arch. |
3563:3eccd8d56bb0 |
07-Nov-2006 |
Gabe Black <gblack@eecs.umich.edu> |
A cleaner hack. |
3561:97b0f2462948 |
07-Nov-2006 |
Gabe Black <gblack@eecs.umich.edu> |
Definition of stub kernel_stats object. This just uses the base object. |
3560:a9d12d67627b |
07-Nov-2006 |
Gabe Black <gblack@eecs.umich.edu> |
Alpha derived classes for kernel_stats. |
3549:91fdf097156a |
07-Nov-2006 |
Gabe Black <gblack@eecs.umich.edu> |
Moved the idle event out of system_events.hh. The skipFuncEvent can be made ISA independent by making it use the #define for branch delay slots (and NNPC) |
3548:85e64c82c522 |
07-Nov-2006 |
Gabe Black <gblack@eecs.umich.edu> |
Moved the switched version of kernel_stats.hh back to kern, and moved the base kernel_stats to base_kernel_stats |
3546:c4074658f1e1 |
07-Nov-2006 |
Gabe Black <gblack@eecs.umich.edu> |
Made kern a switching header file directory.
SConstruct: Put the code to make a switching header directory into a function so they are easy to make. src/arch/SConscript: Replace switching header code with the new function call. src/kern/SConscript: Created a new switching header directory in kern, and moved the declaration of some source files here. |
3544:3db423e3b41d |
06-Nov-2006 |
Gabe Black <gblack@eecs.umich.edu> |
Got rid of the ivlb and ivle kernel stats. |
3535:af201ccd2e51 |
06-Nov-2006 |
Gabe Black <gblack@eecs.umich.edu> |
Took the Alpha prefix off of AlphaArguments, and made sure it was being used from TheISA:: rather than AlphaISA:: |
3390:937865e2c08e |
23-Oct-2006 |
Gabe Black <gblack@eecs.umich.edu> |
Merge zizzer.eecs.umich.edu:/bk/newmem into zeep.eecs.umich.edu:/home/gblack/m5/newmem |
3363:8ed27e349b3d |
21-Oct-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
Tweak a few things for better page fault debugging.
src/sim/faults.cc: Fix fault message. src/kern/tru64/tru64.hh: Add DPRINTF to see where new thread stacks are allocated. src/arch/alpha/faults.cc: Add print statement so we know what the faulting address is in SE mode. |
3267:d3db53c60988 |
12-Oct-2006 |
Gabe Black <gblack@eecs.umich.edu> |
Merge zizzer.eecs.umich.edu:/bk/newmem into zeep.eecs.umich.edu:/home/gblack/m5/newmem |
3165:b765183ff697 |
08-Oct-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
Allocate new thread stacks and shared mem region via Process page table for Tru64 thread library emulation. |
3122:f6d56fc0a12d |
30-Sep-2006 |
Gabe Black <gblack@eecs.umich.edu> |
Some code cleanup.
src/kern/linux/linux.hh: src/kern/solaris/solaris.hh: Some code cleanup. Uncommented some typedefs. src/kern/tru64/tru64.hh: Some code cleanup. Deleted an obsoleted function. |
3114:7a4771b9b720 |
17-Sep-2006 |
Gabe Black <gblack@eecs.umich.edu> |
Finished changing how stat structures are translated, fixed the handling of various ids as LiveProcess parameters.
src/arch/alpha/linux/process.cc: src/arch/alpha/linux/process.hh: src/arch/alpha/process.cc: src/arch/alpha/process.hh: src/arch/alpha/tru64/process.cc: src/arch/alpha/tru64/process.hh: src/arch/mips/linux/process.cc: src/arch/mips/linux/process.hh: src/arch/mips/process.cc: src/arch/mips/process.hh: src/arch/sparc/linux/process.cc: src/arch/sparc/linux/process.hh: src/arch/sparc/process.cc: src/arch/sparc/process.hh: src/arch/sparc/solaris/process.cc: src/arch/sparc/solaris/process.hh: src/sim/process.cc: src/sim/process.hh: src/sim/syscall_emul.cc: src/sim/syscall_emul.hh: Changed Process to LiveProcess in syscall handlers and fixed the implementation of uid, euid, gid, egid, pid and ppid as LiveProcess parameters. src/kern/tru64/tru64.hh: Changed Process to LiveProcess in syscall handlers and fixed the implementation of uid, euid, gid, egid, pid and ppid as LiveProcess parameters. Also fit tru64 in with the new way to handle stat calls. |
3113:a6811aaea654 |
15-Sep-2006 |
Gabe Black <gblack@eecs.umich.edu> |
Changes to correct stat behavior |
2764:e6fea7527b3c |
17-Jun-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
Fixes to compile under Cygwin.
src/kern/linux/linux.hh: src/kern/solaris/solaris.hh: Rename BSD_HOST to the more specific NO_STAT64. src/sim/byteswap.hh: Replace set of swap_byte functions with a single templated version. Hope this fixes compiler issues with e.g. int32_t vs int disambiguation. src/sim/syscall_emul.hh: Rename BSD_HOST to the more specific NO_STAT64. Set this for __CYGWIN__. |
2760:4dbf498165ac |
17-Jun-2006 |
Nathan Binkert <binkertn@umich.edu> |
Add myself to list of authors |
2716:b9114064d77a |
11-Jun-2006 |
Nathan Binkert <binkertn@umich.edu> |
Merge iceaxe.:/Volumes/work/research/m5/head into iceaxe.:/Volumes/work/research/m5/merge
src/cpu/simple/base.cc: src/kern/kernel_stats.cc: src/kern/kernel_stats.hh: src/kern/system_events.cc: src/kern/system_events.hh: src/python/m5/objects/System.py: src/sim/system.cc: src/sim/system.hh: hand merge |
2683:d6b72bb2ed97 |
07-Jun-2006 |
Kevin Lim <ktlim@umich.edu> |
Reorganization/renaming of CPUExecContext. Now it is called SimpleThread in order to clear up the confusion due to the many ExecContexts. It also derives from a common ThreadState object, which holds various state common to threads across CPU models.
Following with the previous check-in, ExecContext now refers only to the interface provided to the ISA in order to access CPU state. ThreadContext refers to the interface provided to all objects outside the CPU in order to access thread state. SimpleThread provides all thread state and the interface to access it, and is suitable for simple execution models such as the SimpleCPU.
src/SConscript: Include thread state file. src/arch/alpha/ev5.cc: src/cpu/checker/cpu.cc: src/cpu/checker/cpu.hh: src/cpu/checker/thread_context.hh: src/cpu/memtest/memtest.cc: src/cpu/memtest/memtest.hh: src/cpu/o3/cpu.cc: src/cpu/ozone/cpu_impl.hh: src/cpu/simple/atomic.cc: src/cpu/simple/base.cc: src/cpu/simple/base.hh: src/cpu/simple/timing.cc: Rename CPUExecContext to SimpleThread. src/cpu/base_dyn_inst.hh: Make thread member variables protected.. src/cpu/o3/alpha_cpu.hh: src/cpu/o3/cpu.hh: Make various members of ThreadState protected. src/cpu/o3/alpha_cpu_impl.hh: Push generation of TranslatingPort into the CPU itself. Make various members of ThreadState protected. src/cpu/o3/thread_state.hh: Pull a lot of common code into the base ThreadState class. src/cpu/ozone/thread_state.hh: Rename CPUExecContext to SimpleThread, move a lot of common code into base ThreadState class. src/cpu/thread_state.hh: Push a lot of common code into base ThreadState class. This goes along with renaming CPUExecContext to SimpleThread, and making it derive from ThreadState. src/cpu/simple_thread.cc: Rename CPUExecContext to SimpleThread, make it derive from ThreadState. This helps push a lot of common code/state into a single class that can be used by all CPUs. src/cpu/simple_thread.hh: Rename CPUExecContext to SimpleThread, make it derive from ThreadState. src/kern/system_events.cc: Rename cpu_exec_context to thread_context. src/sim/process.hh: Remove unused forward declaration. |
2680:246e7104f744 |
06-Jun-2006 |
Kevin Lim <ktlim@umich.edu> |
Change ExecContext to ThreadContext. This is being renamed to differentiate between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh.
Further renames/reorganization will be coming shortly; what is currently CPUExecContext (the old ExecContext from m5) will be renamed to SimpleThread or something similar.
src/arch/alpha/arguments.cc: src/arch/alpha/arguments.hh: src/arch/alpha/ev5.cc: src/arch/alpha/faults.cc: src/arch/alpha/faults.hh: src/arch/alpha/freebsd/system.cc: src/arch/alpha/freebsd/system.hh: src/arch/alpha/isa/branch.isa: src/arch/alpha/isa/decoder.isa: src/arch/alpha/isa/main.isa: src/arch/alpha/linux/process.cc: src/arch/alpha/linux/system.cc: src/arch/alpha/linux/system.hh: src/arch/alpha/linux/threadinfo.hh: src/arch/alpha/process.cc: src/arch/alpha/regfile.hh: src/arch/alpha/stacktrace.cc: src/arch/alpha/stacktrace.hh: src/arch/alpha/tlb.cc: src/arch/alpha/tlb.hh: src/arch/alpha/tru64/process.cc: src/arch/alpha/tru64/system.cc: src/arch/alpha/tru64/system.hh: src/arch/alpha/utility.hh: src/arch/alpha/vtophys.cc: src/arch/alpha/vtophys.hh: src/arch/mips/faults.cc: src/arch/mips/faults.hh: src/arch/mips/isa_traits.cc: src/arch/mips/isa_traits.hh: src/arch/mips/linux/process.cc: src/arch/mips/process.cc: src/arch/mips/regfile/float_regfile.hh: src/arch/mips/regfile/int_regfile.hh: src/arch/mips/regfile/misc_regfile.hh: src/arch/mips/regfile/regfile.hh: src/arch/mips/stacktrace.hh: src/arch/sparc/faults.cc: src/arch/sparc/faults.hh: src/arch/sparc/isa_traits.hh: src/arch/sparc/linux/process.cc: src/arch/sparc/linux/process.hh: src/arch/sparc/process.cc: src/arch/sparc/regfile.hh: src/arch/sparc/solaris/process.cc: src/arch/sparc/stacktrace.hh: src/arch/sparc/ua2005.cc: src/arch/sparc/utility.hh: src/arch/sparc/vtophys.cc: src/arch/sparc/vtophys.hh: src/base/remote_gdb.cc: src/base/remote_gdb.hh: src/cpu/base.cc: src/cpu/base.hh: src/cpu/base_dyn_inst.hh: src/cpu/checker/cpu.cc: src/cpu/checker/cpu.hh: src/cpu/checker/exec_context.hh: src/cpu/cpu_exec_context.cc: src/cpu/cpu_exec_context.hh: src/cpu/cpuevent.cc: src/cpu/cpuevent.hh: src/cpu/exetrace.hh: src/cpu/intr_control.cc: src/cpu/memtest/memtest.hh: src/cpu/o3/alpha_cpu.hh: src/cpu/o3/alpha_cpu_impl.hh: src/cpu/o3/alpha_dyn_inst_impl.hh: src/cpu/o3/commit.hh: src/cpu/o3/commit_impl.hh: src/cpu/o3/cpu.cc: src/cpu/o3/cpu.hh: src/cpu/o3/fetch_impl.hh: src/cpu/o3/regfile.hh: src/cpu/o3/thread_state.hh: src/cpu/ozone/back_end.hh: src/cpu/ozone/cpu.hh: src/cpu/ozone/cpu_impl.hh: src/cpu/ozone/front_end.hh: src/cpu/ozone/front_end_impl.hh: src/cpu/ozone/inorder_back_end.hh: src/cpu/ozone/lw_back_end.hh: src/cpu/ozone/lw_back_end_impl.hh: src/cpu/ozone/lw_lsq.hh: src/cpu/ozone/lw_lsq_impl.hh: src/cpu/ozone/thread_state.hh: src/cpu/pc_event.cc: src/cpu/pc_event.hh: src/cpu/profile.cc: src/cpu/profile.hh: src/cpu/quiesce_event.cc: src/cpu/quiesce_event.hh: src/cpu/simple/atomic.cc: src/cpu/simple/base.cc: src/cpu/simple/base.hh: src/cpu/simple/timing.cc: src/cpu/static_inst.cc: src/cpu/static_inst.hh: src/cpu/thread_state.hh: src/dev/alpha_console.cc: src/dev/ns_gige.cc: src/dev/sinic.cc: src/dev/tsunami_cchip.cc: src/kern/kernel_stats.cc: src/kern/kernel_stats.hh: src/kern/linux/events.cc: src/kern/linux/events.hh: src/kern/system_events.cc: src/kern/system_events.hh: src/kern/tru64/dump_mbuf.cc: src/kern/tru64/tru64.hh: src/kern/tru64/tru64_events.cc: src/kern/tru64/tru64_events.hh: src/mem/vport.cc: src/mem/vport.hh: src/sim/faults.cc: src/sim/faults.hh: src/sim/process.cc: src/sim/process.hh: src/sim/pseudo_inst.cc: src/sim/pseudo_inst.hh: src/sim/syscall_emul.cc: src/sim/syscall_emul.hh: src/sim/system.cc: src/cpu/thread_context.hh: src/sim/system.hh: src/sim/vptr.hh: Change ExecContext to ThreadContext. |
2670:9107b8bd08cd |
02-Jun-2006 |
Kevin Lim <ktlim@umich.edu> |
Merge ktlim@zizzer:/bk/newmem into zizzer.eecs.umich.edu:/.automount/zamp/z/ktlim2/clean/newmem |
2665:a124942bacb8 |
31-May-2006 |
Ali Saidi <saidi@eecs.umich.edu> |
Updated Authors from bk prs info |
2654:9559cfa91b9d |
30-May-2006 |
Kevin Lim <ktlim@umich.edu> |
Merge ktlim@zizzer:/bk/m5 into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem
SConstruct: src/SConscript: src/arch/SConscript: src/arch/alpha/faults.cc: src/arch/alpha/tlb.cc: src/base/traceflags.py: src/cpu/SConscript: src/cpu/base.cc: src/cpu/base.hh: src/cpu/base_dyn_inst.cc: src/cpu/cpu_exec_context.cc: src/cpu/cpu_exec_context.hh: src/cpu/exec_context.hh: src/cpu/o3/alpha_cpu.hh: src/cpu/o3/alpha_cpu_impl.hh: src/cpu/o3/alpha_dyn_inst.hh: src/cpu/o3/cpu.cc: src/cpu/o3/cpu.hh: src/cpu/o3/regfile.hh: src/cpu/ozone/cpu.hh: src/cpu/simple/base.cc: src/cpu/base_dyn_inst.hh: src/cpu/o3/2bit_local_pred.cc: src/cpu/o3/2bit_local_pred.hh: src/cpu/o3/alpha_cpu.cc: src/cpu/o3/alpha_cpu_builder.cc: src/cpu/o3/alpha_dyn_inst.cc: src/cpu/o3/alpha_dyn_inst_impl.hh: src/cpu/o3/alpha_impl.hh: src/cpu/o3/alpha_params.hh: src/cpu/o3/bpred_unit.cc: src/cpu/o3/bpred_unit.hh: src/cpu/o3/bpred_unit_impl.hh: src/cpu/o3/btb.cc: src/cpu/o3/btb.hh: src/cpu/o3/comm.hh: src/cpu/o3/commit.cc: src/cpu/o3/commit.hh: src/cpu/o3/commit_impl.hh: src/cpu/o3/cpu_policy.hh: src/cpu/o3/decode.cc: src/cpu/o3/decode.hh: src/cpu/o3/decode_impl.hh: src/cpu/o3/fetch.cc: src/cpu/o3/fetch.hh: src/cpu/o3/fetch_impl.hh: src/cpu/o3/free_list.cc: src/cpu/o3/free_list.hh: src/cpu/o3/iew.cc: src/cpu/o3/iew.hh: src/cpu/o3/iew_impl.hh: src/cpu/o3/inst_queue.cc: src/cpu/o3/inst_queue.hh: src/cpu/o3/inst_queue_impl.hh: src/cpu/o3/mem_dep_unit.cc: src/cpu/o3/mem_dep_unit.hh: src/cpu/o3/mem_dep_unit_impl.hh: src/cpu/o3/ras.cc: src/cpu/o3/ras.hh: src/cpu/o3/rename.cc: src/cpu/o3/rename.hh: src/cpu/o3/rename_impl.hh: src/cpu/o3/rename_map.cc: src/cpu/o3/rename_map.hh: src/cpu/o3/rob.cc: src/cpu/o3/rob.hh: src/cpu/o3/rob_impl.hh: src/cpu/o3/sat_counter.cc: src/cpu/o3/sat_counter.hh: src/cpu/o3/store_set.cc: src/cpu/o3/store_set.hh: src/cpu/o3/tournament_pred.cc: src/cpu/o3/tournament_pred.hh: Hand merges. |
2632:1bb2f91485ea |
22-May-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
New directory structure: - simulator source now in 'src' subdirectory - imported files from 'ext' repository - support building in arbitrary places, including outside of the source tree. See comment at top of SConstruct file for more details. Regression tests are temporarily disabled; that syetem needs more extensive revisions.
SConstruct: Update for new directory structure. Modify to support build trees that are not subdirectories of the source tree. See comment at top of file for more details. Regression tests are temporarily disabled. src/arch/SConscript: src/arch/isa_parser.py: src/python/SConscript: Update for new directory structure. |