History log of /gem5/src/base/
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14297:b4519e586f5e 10-Sep-2019 Jordi Vaquero <jordi.vaquero@metempsy.com>

cpu, mem: Changing AtomicOpFunctor* for unique_ptr<AtomicOpFunctor>

This change is based on modify the way we move the AtomicOpFunctor*
through gem5 in order to mantain proper ownership of the object and
ensuring its destruction when it is no longer used.

Doing that we fix at the same time a memory leak in Request.hh
where we were assigning a new AtomicOpFunctor* without destroying the
previous one.

This change creates a new type AtomicOpFunctor_ptr as a
std::unique_ptr<AtomicOpFunctor> and move its ownership as needed. Except
for its only usage when AtomicOpFunc() is called.

Change-Id: Ic516f9d8217cb1ae1f0a19500e5da0336da9fd4f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20919
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

14268:3012cd98980d 12-May-2019 Daniel R. Carvalho <odanrc@yahoo.com.br>

base: Add a perfect bloom filter

Add a bloom filter that keeps track of all observed entries, and
thus has no false negatives nor false positives.

Change-Id: Iba784e617a99c77554c688470d9b9e12c260f23b
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18879
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

14267:148c62c7f0a3 10-Sep-2019 Tommaso Marinelli <tommarin@ucm.es>

stats: Add M5_VAR_USED to variable

Fixes compile error for gem5.fast due to unused variable.

Change-Id: Ib1664b100e95a741174610f8cdbdebaff9635f66
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20759
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

14266:711b485a4bf8 06-Sep-2019 Andreas Sandberg <andreas.sandberg@arm.com>

stats: Fix incorrect name conflict panic with grouped stats

Info::setName() performs a sanity check to ensure that the same stat
name isn't used twice. This doesn't work for new-style stats with a
parent group since the name is only unique within the group. Disable
the check for new-style stats since these usually use names generated
from member variable names.

Change-Id: I590abe6040407c6a4fe582c0782a418165ff5588
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20760
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

14264:f150b10dd048 14-May-2019 Daniel R. Carvalho <odanrc@yahoo.com.br>

base: Make Bloom Filter counting by default

Since a boolean bool filter is a saturating bloom filter with a
single bit per entry, generalize them by using SatCounter instead
of int for the filter entries.

Change-Id: I7f54e28d54de5671e0770b02ed9161735e6bd339
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18877
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

14263:4a6d5c4a0813 12-May-2019 Daniel R. Carvalho <odanrc@yahoo.com.br>

base: Make Bulk inherit from MultiBitSel Bloom Filter

Cleanup bulk's code and make it inherit from MultiBitSel.

Change-Id: I83154feb30bb3dac3d02743bcafbdcb57489c2fd
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18876
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

14262:991410960fdb 11-May-2019 Daniel R. Carvalho <odanrc@yahoo.com.br>

mem-ruby: Move Bloom Filters to base

All Bloom Filters are completely independent of Ruby, and
therefore can be used everywhere.

As a side effect, Ruby was not using the filters, so
their dependency was removed.

Change-Id: Ic5f430610c33c0791fb81c79101ebe737189497e
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18875
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

14215:fd07f1a146fd 30-Aug-2019 Andreas Sandberg <andreas.sandberg@arm.com>

stats: Create HDF5 stat files relative to simout

When using the HDF5 stats backend, we currently pass the filename from
the command line straight to the HDF5 library. This behaviour is
different from the expected behaviour when using plain text stat files
where relative paths are resolved relative to simout. This change adds
support for resolving hdf5 paths relative to simout.

Change-Id: I09cb0b7468735e697125eda7f04c5a85725ca8d0
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20508
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

14214:2282d56a0b8b 30-Aug-2019 Doğukan Korkmaztürk <d.korkmazturk@gmail.com>

stats: Catch exceptions by const reference

Catching exceptions by value causes -Werror=catch-value= to be
triggered during a build process. This change replaces the values
with const references in the catch blocks.

Change-Id: Iddabb595c5916d8120dcdb08e2c2f36ff21c3c9b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20528
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

14210:8f7626532f4d 29-May-2019 Daniel R. Carvalho <odanrc@yahoo.com.br>

base: Add function to saturate SatCounter

Create a saturation function for the SatCounter that makes its
internal counter reach its maximum value.

Change-Id: Ibd30fa27c4ae2714dd48e3eba85addd035fb737c
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20451
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

14209:7efe1c187149 22-Apr-2016 Andreas Sandberg <andreas.sandberg@arm.com>

stats: Add beta support for HDF5 stat dumps

This changeset add support for stat dumps in the HDF5 file
format. HDF5 is a binary data format that represents data in a
file-system-like balanced tree. It has native support for
N-dimensional arrays and binary data (e.g., frame buffers).

It has the following benefits over traditional text stat files:

* Efficient storage of time series (multiple stat dumps)

* Fast lookup of stats

* Plenty of existing tooling (e.g., Python libraries and graphical
viewers)

* File format can be used to store frame buffers together with
normal stats.

Drawbacks:

* Large startup cost (single stat dump larger than text equivalent)

* Stat dumps are slower than text

Known limitations:

* Distributions and histograms aren't supported.

HDF5 stat output can be enabled using the 'h5' URL scheme when
overriding the stat file name on gem5's command line. The following
parameters are supported:

* chunking (unsigned): Number of time steps to pre-allocate
(default: 10)

* desc (bool): Output stat descriptions (default: True)

* formulas (bool): Output derived stats (default: True)

Example gem5 command line:

./build/ARM/gem5.opt \
--stats-file="h5://stats.h5?desc=False;formulas=False" \
configs/example/fs.py

Example Python stat consumer that computes IPC:
import h5py

f = h5py.File('stats.h5', 'r')
group = f['/system/cpu']
for i, c in zip(group['committedInsts'], group['numCycles']):
print i, c, i / c

Change-Id: I351c6cbff2fb7bef9012f47876ba227ed288975b
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/8121
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>

14205:197360deaa20 26-Jun-2019 Andreas Sandberg <andreas.sandberg@arm.com>

stats: Add support for hierarchical stats

This change makes the stat system aware of the hierarchical nature of
stats. The aim is to achieve the following goals:

* Make the SimObject hierarchy explicit in the stat system (i.e.,
get rid of name() + ".foo"). This makes stat naming less fragile
and makes it possible to implement hierarchical formats like
XML/HDF5/JSON in a clean way.

* Make it more convenient to split stats into a separate
struct/class that can be bound to a SimObject. This makes the
namespace cleaner and makes stat accesses a bit more obvious.

* Make it possible to build groups of stats in C++ that can be used
in subcomponents in a SimObject (similar to what we do for
checkpoint sections). This makes it easier to structure large
components.

* Enable partial stat dumps. Some of our internal users have been
asking for this since a full stat dump can be large.

* Enable better stat access from Python.

This changeset implements solves the first three points by introducing
a class (Stats::Group) that owns statistics belonging to the same
object. SimObjects inherit from Stats::Group since they typically have
statistics.

New-style statistics need to be associated with a parent group at
instantiation time. Instantiation typically sets the name and the
description, other parameters need to be set by overriding
Group::regStats() just like with legacy stats. Simple objects with
scalar stats can typically avoid implementing regStats() altogether
since the stat name and description are both specified in the
constructor.

For convenience reasons, statistics groups can be merged into other
groups. This means that a SimObject can create a stat struct that
inherits from Stats::Group and merge it into the parent group
(SimObject). This can make the code cleaner since statistics tracking
gets grouped into a single object.

Stat visitors have a new API to expose the group structure. The
Output::beginGroup(name) method is called at the beginning of a group
and the Output::endGroup() method is called when all stats, and
sub-groups, have been visited. Flat formats (e.g., the text format)
typically need to maintain a stack to track the full path to a stat.

Legacy, flat, statistics are still supported after applying this
change. These stats don't belong to any group and stat visitors will
not see a Output::beginGroup(name) call before their corresponding
Output::visit() methods are called.

Change-Id: I9025d61dfadeabcc8ecf30813ab2060def455648
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19368
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

14175:8cf7610e44f8 06-Aug-2019 Ciro Santilli <ciro.santilli@arm.com>

base: assert that stats bucket size is greater than 0

Change-Id: I9a2264e9ee74acea1f09f01ea8f5004567ba1ea8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20049
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

14067:2c3667b32607 30-Aug-2018 Michiel W. van Tol <Michiel.VanTol@arm.com>

base: Add argument to Coroutine class to not run on creation

In some cases, the point where you create a Coroutine is not the same as
where you want to start running it (and want it to switch back to). This
leads to the unnecessary overhead of switching in and out of the
Coroutine. This change adds an optional boolean argument to the
constructor for the Coroutine class to allow for overriding the default
behavior of running the Coroutine upon creation, which in specific cases
can be used to avoid the unnecessary overhead and improve simulator
performance.

Change-Id: I044698f85e81ee4144208aee30d133bcb462d35d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18588
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

14056:d8e21ca49871 17-May-2019 Tiago Muck <tiago.muck@arm.com>

base: AddrRange does not merge single interleaved ranges

AddrRange does not attempt to merge interleaved address ranges if it
has only one of the ranges.

This is needed to allow XBars to accept request targeting only one
part of a interleaved address range. A use case for this would be
modeling distributed LLCs in which a XBar is used solely to
encapsulate the snoop filter of a single LLC slice.

Change-Id: If71c9cf1444ee11916611afb51eab3a4f1d93985
Signed-off-by: Tiago Muck <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18788
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

14048:9fca1b5cea8b 26-May-2019 Nikos Nikoleris <nikos.nikoleris@arm.com>

base: Extend unit tests for AddrRange

Change-Id: Ia154c3a17c3c8254a0e3d622568ac34f0d62fc9e
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19131
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

14047:91279ed7ec5e 26-May-2019 Nikos Nikoleris <nikos.nikoleris@arm.com>

base: Extend AddrRange to support more flexible addressing

Previously an AddrRange could express interleaving using a number of
consecutive bits and in additional optionally a second number of
consecutive bits. The two sets of consecutive bits would be xored and
matched against a value to determine if an address is in the
AddrRange. For example:

sel[0] = a[8] ^ a[12]
sel[1] = a[9] ^ a[13]
where sel == intlvMatch

This change extends AddrRange to allow more flexible interleavings
with an abritary number of set of bits which do not need be
consecutive. For example:

sel[0] = a[8] ^ a[11] ^ a[13]
sel[1] = a[15] ^ a[17] ^ a[19]
where sel == intlvMatch

Change-Id: I42220a6d5011a31f0560535762a25bfc823c3ebb
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19130
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

14046:9eecb7504759 28-May-2019 Nikos Nikoleris <nikos.nikoleris@arm.com>

base: Fix ctz32 for systems where unsigned int is not 32bit

The implementation of ctz32 uses __builtin_ctz to count the number of
trailing zeros and therefore makes the assumption that an unsigned int
is 32bit. This change checks whether that's the case and if not it
uses __builtin_ctzl instead.

Change-Id: Ic3ed3ada25fd0a93c7eb91d75b954e9924bdbb77
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19129
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

14045:219770957562 26-May-2019 Nikos Nikoleris <nikos.nikoleris@arm.com>

base: Add function to count trailing zeros in a 64-bit integer

Change-Id: Iaad0679b403bc5015ffeacbf7284313e41a36cd0
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19128
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

14042:7c548eb5c4c1 03-May-2019 Giacomo Travaglini <giacomo.travaglini@arm.com>

base: Provide a getter for Fiber::started boolean variable

This can be used to check if the fiber has started its execution.

Change-Id: Ie9222b8076756363c9f82c1333c76a352bcaf817
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18648
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

14041:ade853f97d68 07-Jun-2019 Giacomo Travaglini <giacomo.travaglini@arm.com>

base: Rename TestFiber into SwitchingFiber

This is done since TestFiber is too generic and it is not the only
Fiber's testing subclass in the unit test

Change-Id: Idc386f487091ae9bdadae865090a6719a25583da
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19153
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

14036:64006596f613 31-May-2019 Daniel R. Carvalho <odanrc@yahoo.com.br>

base: Fix missing headers to CircularQueue

CircularQueue is currently throwing compilation errors when creating
a derived class.

assert() needs <cassert>
ptrdiff_t needs <cstddef>
(u)intX_t need <cstdint>
random_access_iterator_tag needs <iterator>
is_same, enable_if and others need <type_traits>

Change-Id: I77a78e7b13f7a8b8e7e8b2b872065d78d1ab815a
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19089
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

14024:abe47b13653d 02-May-2019 Gabe Black <gabeblack@google.com>

arch, base, cpu, gpu, sim: Merge getMemProxy and getVirtProxy.

These two functions were performing the same function but had two
different names for historical reasons. This change merges them
together, keeping the getVirtProxy name to be consistent with the
getPhysProxy method used to get a non-translating proxy port.

Change-Id: Idd83c6b899f9343795075b030ccbc723a79e52a4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18581
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

14020:c9bf7a011602 02-May-2019 Gabe Black <gabeblack@google.com>

arch, base, sim: Demote (SE|FS)TranslatingPortProxy &s to PortProxy &s.

Al(most) all of the interesting differences between the two classes
have been removed. There are some control methods which are still
specific to each type which may require treating them as their true
type, but most code that consumes them doesn't need to worry about
which is which.

Change-Id: Ie592676f1e496c7940605b66e55cd7fae18e59d6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18577
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

14018:9d2153431f44 02-May-2019 Gabe Black <gabeblack@google.com>

arch, base, sim: Replace Copy(String)?(In|Out) with equivalent code.

This expands those functions into code which extracts the virt proxy
and then uses the appropriate method on it. This has two benefits.
First, the Copy* functions where mostly redundant wrappers around the
methods the proxy port already had. Second, using them forced a
particular port which might not actually be what the user wanted.

Change-Id: I62084631dd080061e3c74997125164f40da2d77c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18575
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

14017:815c925b777d 28-Aug-2018 Brandon Potter <brandon.potter@amd.com>

sim-se: const for loader's loadSection param

The port proxy can be declared as a reference to a const proxy
rather than just a reference to a proxy.

Change-Id: I4640b0c5f33e2334c1e7630131f78607ced40a34
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12301
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

14010:0e1e887507c0 01-May-2019 Gabe Black <gabeblack@google.com>

arch, base, dev, sim: Remove now unnecessary casts from PortProxy methods.

Change-Id: Ia73b2d86a10d02fa09c924a4571477bb5f200eb7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18572
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

14004:2fc669c4af85 24-Jan-2019 Tiago Muck <tiago.muck@arm.com>

base: Add warn_if_once macro

Change-Id: Ie68f3b07a35ed2e6b0eee20b3b34050542fcdc6c
Signed-off-by: Tiago Muck <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18420
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

13982:175e05a8ee6a 03-May-2019 Gabe Black <gabeblack@google.com>

base: Add a type for keeping track of object file loaders.

This avoids having a big pile of #if-s in sim/process.cc and allows
dynamically adding new types of object file loaders which might
recognize new arch/OS combinations.

Change-Id: Ie3b9c1aa2974d30a61afc4fcc529ffd6a74d43e0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18583
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

13981:577196ddd040 02-May-2019 Gabe Black <gabeblack@google.com>

arch, base, cpu, dev, mem, sim: Remove #if 0-ed out code.

This code will be preserved through version control, but otherwise
creates clutter and will rot in place since it's never compiled.

Change-Id: Id265f6deac445116843956ea5cf1210d8127274e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18608
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

13962:9c1c64414fb7 13-Apr-2019 Daniel <odanrc@yahoo.com.br>

base: Add operators to SatCounter

Add shift, add and subtract assignment operators, as well as
copy and move constructor and assignments to SatCounter, so
that it they can be used by the prefetchers.

Also add extra useful functions to calculate saturation
oercentile so that the instantiator does not need to be aware
of the counter's maximum value.

Change-Id: I61d0cb28c8375b9d2774a39011e4a0aa6fe9ccb7
Signed-off-by: Daniel <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17996
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

13961:3139b24cd76d 10-Apr-2019 Daniel <odanrc@yahoo.com.br>

base: Add GTest to SatCounter

Add a GTest to the SatCounter class.

Change-Id: Iaf1b18db9fe8d7fe32e0e40c7947dcd1fd6cc33b
Signed-off-by: Daniel <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17994
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

13960:e1ab93677110 10-Apr-2019 Daniel <odanrc@yahoo.com.br>

base: Move SatCounter to base directory

Saturating counters are used by many objects, not only
the cpu predictors. Therefore, move the class to the
base folder so that it can be more easily used.

Change-Id: I26f799324bdd8720ab8834c72a2002149cee777c
Signed-off-by: Daniel <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17993
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

13824:54e92033cf67 14-Mar-2019 Andrea Mondelli <Andrea.Mondelli@ucf.edu>

dev-arm: Correct cast of template parameter

Clang with -Wconstant-conversion is _very_ restrictive on casting.
The shift operator results in an incorrect promotion.

This patch add a compile-time static cast that remove the error
when clang is used.

Change-Id: I3aa1e77da2565799feadc32317d5faa111b2de86
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17308
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

13807:66bd3025e9cc 21-Mar-2019 Gabe Black <gabeblack@google.com>

base: Make AddrRangeMap able to return non-const iterators.

The erase() method only accepts regular iterators which is consistent
with the normal STL map, but the existing find() only returns const
iterators. The STL container can return either depending on if "this"
is const.

Unfortunately there isn't a great way to have only one find
implementation which returns the right type of iterator under the right
conditions. Also, it's not possible to turn a const_iterator into an
iterator, but it is possible to go the other way. This change
duplicates very short functions which return iterators, and for find
does the only thing I could find which avoids having to copy that
whole large function.

Change-Id: I2f789b5d0881feb9adff9978bd40e31731c6a688
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17588
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

13804:f53a9c35b287 20-Mar-2019 Isaac Sánchez Barrera <isaac.sanchez@bsc.es>

base,python: Fix to allow multiple --debug-ignore values.

When adding multiple SimObjects to --debug-ignore, either separating the values with
a colon or adding multiple --debug-ignore flags, the previous code only ignored the
last SimObject in the list. This changeset adds and uses new `ObjectMatch::add` and
`Logger::addIgnore` methods to make the functionality of the flag consistent with
its description.

Change-Id: Ib6967a48611ea59a211f81af2a970c4de429b1be
Signed-off-by: Isaac Sánchez Barrera <isaac.sanchez@bsc.es>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17488
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

13797:1969bb477391 21-Mar-2019 Giacomo Travaglini <giacomo.travaglini@arm.com>

base: Fix CircularQueue's operator-= when negative subtraction

Using operator-= when the rhs is a negative value is equivalent
to using += on -rhs. This is fixing rounding in that scenario.

Change-Id: Ia22e51f81a6805d27fd6b2115d288bb23421d00f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17528
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

13796:ca1eed45ebe5 08-Mar-2019 Giacomo Travaglini <giacomo.travaglini@arm.com>

base: Fix CircularQueue when diffing iterators

This patch is fixing CircularQueue iterators' subtraction, in particular
the behaviour when head and tail round multiple times.

Change-Id: Ie79ac8accd30a10cf039cf4def87675b01375d6b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17188
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

13689:0aa17326eef9 07-Feb-2019 Giacomo Travaglini <giacomo.travaglini@arm.com>

base: Fix enums checkpointing

Creating an extra version of string to number converters (__to_number)
in base/str.hh; it will be used by enums only when unserializing
them. The reason not to have a single helper for both enums and
integers is that std::numeric_limits trait is not specialized for enums.
We fix this by using the std::underlying_type trait.

Change-Id: I819e35c0df8c094de7b7a6390152964fa47d513d
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/16382
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

13665:9c7fe3811b88 25-Jan-2019 Andreas Sandberg <andreas.sandberg@arm.com>

python: Don't assume SimObjects live in the global namespace

The importer in Python 3 doesn't like the way we import SimObjects
from the global namespace. Convert the existing SimObject declarations
to import from m5.objects. As a side-effect, this makes these files
consistent with configuration files.

Change-Id: I11153502b430822130722839e1fa767b82a027aa
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15981
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>


/gem5/src/arch/alpha/AlphaSystem.py
/gem5/src/arch/alpha/AlphaTLB.py
/gem5/src/arch/arm/ArmISA.py
/gem5/src/arch/arm/ArmNativeTrace.py
/gem5/src/arch/arm/ArmPMU.py
/gem5/src/arch/arm/ArmSemihosting.py
/gem5/src/arch/arm/ArmSystem.py
/gem5/src/arch/arm/ArmTLB.py
/gem5/src/arch/arm/tracers/TarmacTrace.py
/gem5/src/arch/mips/MipsSystem.py
/gem5/src/arch/mips/MipsTLB.py
/gem5/src/arch/power/PowerTLB.py
/gem5/src/arch/riscv/RiscvSystem.py
/gem5/src/arch/riscv/RiscvTLB.py
/gem5/src/arch/sparc/SparcNativeTrace.py
/gem5/src/arch/sparc/SparcSystem.py
/gem5/src/arch/sparc/SparcTLB.py
/gem5/src/arch/x86/X86LocalApic.py
/gem5/src/arch/x86/X86NativeTrace.py
/gem5/src/arch/x86/X86System.py
/gem5/src/arch/x86/X86TLB.py
vnc/Vnc.py
/gem5/src/cpu/BaseCPU.py
/gem5/src/cpu/CPUTracers.py
/gem5/src/cpu/CheckerCPU.py
/gem5/src/cpu/DummyChecker.py
/gem5/src/cpu/InstPBTrace.py
/gem5/src/cpu/kvm/BaseKvmCPU.py
/gem5/src/cpu/kvm/X86KvmCPU.py
/gem5/src/cpu/minor/MinorCPU.py
/gem5/src/cpu/o3/FUPool.py
/gem5/src/cpu/o3/FuncUnitConfig.py
/gem5/src/cpu/o3/O3CPU.py
/gem5/src/cpu/o3/O3Checker.py
/gem5/src/cpu/o3/probe/ElasticTrace.py
/gem5/src/cpu/o3/probe/SimpleTrace.py
/gem5/src/cpu/simple/AtomicSimpleCPU.py
/gem5/src/cpu/simple/BaseSimpleCPU.py
/gem5/src/cpu/simple/NonCachingSimpleCPU.py
/gem5/src/cpu/simple/TimingSimpleCPU.py
/gem5/src/cpu/simple/probes/SimPoint.py
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.py
/gem5/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.py
/gem5/src/cpu/testers/memtest/MemTest.py
/gem5/src/cpu/testers/rubytest/RubyTester.py
/gem5/src/cpu/testers/traffic_gen/BaseTrafficGen.py
/gem5/src/cpu/testers/traffic_gen/PyTrafficGen.py
/gem5/src/cpu/testers/traffic_gen/TrafficGen.py
/gem5/src/cpu/trace/TraceCPU.py
/gem5/src/dev/BadDevice.py
/gem5/src/dev/Device.py
/gem5/src/dev/Platform.py
/gem5/src/dev/alpha/AlphaBackdoor.py
/gem5/src/dev/alpha/Tsunami.py
/gem5/src/dev/arm/EnergyCtrl.py
/gem5/src/dev/arm/FlashDevice.py
/gem5/src/dev/arm/Gic.py
/gem5/src/dev/arm/NoMali.py
/gem5/src/dev/arm/RealView.py
/gem5/src/dev/arm/UFSHostDevice.py
/gem5/src/dev/arm/VirtIOMMIO.py
/gem5/src/dev/i2c/I2C.py
/gem5/src/dev/mips/Malta.py
/gem5/src/dev/net/Ethernet.py
/gem5/src/dev/pci/CopyEngine.py
/gem5/src/dev/pci/PciDevice.py
/gem5/src/dev/pci/PciHost.py
/gem5/src/dev/serial/Terminal.py
/gem5/src/dev/serial/Uart.py
/gem5/src/dev/sparc/T1000.py
/gem5/src/dev/storage/Ide.py
/gem5/src/dev/virtio/VirtIO.py
/gem5/src/dev/virtio/VirtIO9P.py
/gem5/src/dev/virtio/VirtIOBlock.py
/gem5/src/dev/virtio/VirtIOConsole.py
/gem5/src/dev/x86/Cmos.py
/gem5/src/dev/x86/I8042.py
/gem5/src/dev/x86/I82094AA.py
/gem5/src/dev/x86/I8237.py
/gem5/src/dev/x86/I8254.py
/gem5/src/dev/x86/I8259.py
/gem5/src/dev/x86/Pc.py
/gem5/src/dev/x86/PcSpeaker.py
/gem5/src/dev/x86/SouthBridge.py
/gem5/src/gpu-compute/GPU.py
/gem5/src/gpu-compute/LdsState.py
/gem5/src/learning_gem5/part2/SimpleCache.py
/gem5/src/learning_gem5/part2/SimpleMemobj.py
/gem5/src/mem/AbstractMemory.py
/gem5/src/mem/AddrMapper.py
/gem5/src/mem/Bridge.py
/gem5/src/mem/CommMonitor.py
/gem5/src/mem/DRAMCtrl.py
/gem5/src/mem/ExternalMaster.py
/gem5/src/mem/ExternalSlave.py
/gem5/src/mem/HMCController.py
/gem5/src/mem/MemChecker.py
/gem5/src/mem/MemDelay.py
/gem5/src/mem/MemObject.py
/gem5/src/mem/SerialLink.py
/gem5/src/mem/SimpleMemory.py
/gem5/src/mem/XBar.py
/gem5/src/mem/cache/Cache.py
/gem5/src/mem/cache/prefetch/Prefetcher.py
/gem5/src/mem/cache/tags/Tags.py
/gem5/src/mem/probes/MemFootprintProbe.py
/gem5/src/mem/probes/MemTraceProbe.py
/gem5/src/mem/probes/StackDistProbe.py
/gem5/src/mem/qos/QoSMemCtrl.py
/gem5/src/mem/qos/QoSMemSinkCtrl.py
/gem5/src/mem/ruby/network/BasicRouter.py
/gem5/src/mem/ruby/network/Network.py
/gem5/src/mem/ruby/network/garnet2.0/GarnetLink.py
/gem5/src/mem/ruby/network/garnet2.0/GarnetNetwork.py
/gem5/src/mem/ruby/network/simple/SimpleLink.py
/gem5/src/mem/ruby/network/simple/SimpleNetwork.py
/gem5/src/mem/ruby/slicc_interface/Controller.py
/gem5/src/mem/ruby/structures/LRUReplacementPolicy.py
/gem5/src/mem/ruby/structures/PseudoLRUReplacementPolicy.py
/gem5/src/mem/ruby/structures/RubyCache.py
/gem5/src/mem/ruby/structures/RubyPrefetcher.py
/gem5/src/mem/ruby/system/GPUCoalescer.py
/gem5/src/mem/ruby/system/RubySystem.py
/gem5/src/mem/ruby/system/Sequencer.py
/gem5/src/mem/ruby/system/VIPERCoalescer.py
/gem5/src/mem/ruby/system/WeightedLRUReplacementPolicy.py
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/sim/System.py
/gem5/src/sim/TickedObject.py
/gem5/src/sim/power/MathExprPowerModel.py
/gem5/src/sim/power/ThermalModel.py
13634:748418e0ca3f 26-Dec-2018 Austin Harris <austinharris@utexas.edu>

arch-riscv: Enable support for riscv 32-bit in SE mode.

This patch splits up the riscv SE mode support for 32 and 64-bit.
A future patch will add support for decoding rv32 instructions.

Change-Id: Ia79ae19f753caf94dc7e5830a6630efb94b419d7
Signed-off-by: Austin Harris <austinharris@utexas.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/15355
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Alec Roelke <alec.roelke@gmail.com>
Maintainer: Alec Roelke <alec.roelke@gmail.com>

13592:b8972ccebd63 19-Nov-2018 Gabe Black <gabeblack@google.com>

base: arch: Get rid of the now unused FloatRegVal type.

This type is no longer used since FP registers are accessed as integer
bit patterns.

Change-Id: I1070f9443d6247165fd64c6bc041811c28287e9f
Reviewed-on: https://gem5-review.googlesource.com/c/14459
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

13590:d7e018859709 13-Feb-2017 Rekai Gonzalez-Alberquilla <rekai.gonzalezalberquilla@arm.com>

cpu-o3: O3 LSQ Generalisation

This patch does a large modification of the LSQ in the O3 model. The
main goal of the patch is to remove the 'an operation can be served with
one or two memory requests' assumption that is present in the LSQ
and the instruction with the req, reqLow, reqHigh triplet, and
generalising it to operations that can be addressed with one request,
and operations that require many requests, embodied in the
SingleDataRequest and the SplitDataRequest.

This modification has been done mimicking the minor model to an extent,
shifting the responsibilities of dealing with VtoP translation and
tracking the status and resources from the DynInst to the LSQ via the
LSQRequest. The LSQRequest models the information concerning the
operation, handles the creation of fragments for translation and request
as well as assembling/splitting the data accordingly.

With this modifications, the implementation of vector ISAs, particularly
on the memory side, become more rich, as the new model permits a
dissociation of the ISA characteristics as vector length, from the
microarchitectural characteristics that govern how contiguous loads are
executing, allowing exploration of different LSQ to DL1 bus widths to
understand the tradeoffs in complexity and performance.

Part of the complexities introduced stem from the fact that gem5 keeps a
large amount of metadata regarding, in particular, memory operations,
thus, when an instruction is squashed while some operation as TLB lookup
or cache access is ongoing, when the relevant structure communicates to
the LSQ that the operation is over, it tries to access some pieces of
data that should have died when the instruction is squashed, leading to
asserts, panics, or memory corruption. To ensure the correct behaviour,
the LSQRequest rely on assesing who is their owner, and self-destroying
if they detect their owner is done with the request, and there will be
no subsequent action. For example, in the case of an instruction
squashed whal the TLB is doing a walk to serve the translation, when the
translation is served by the TLB, the LSQRequest detects that the
instruction was squashed, and as the translation is done, no one else
expect to access its information, and therefore, it self-destructs.
Having destroyed the LSQRequest earlier, would lead to wrong behaviour
as the TLB walk may access some fields of it.

Additional authors:
- Gabor Dozsa <gabor.dozsa@arm.com>

Change-Id: I9578a1a3f6b899c390cdd886856a24db68ff7d0c
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13516
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

13575:aafa2c83ab3c 19-Nov-2018 Ciro Santilli <ciro.santilli@arm.com>

base: add support for GDB's XML architecture definition

This is done by implementing the Xfer:features:read packet of the GDB
remote protocol.

Before this commit, gem5 used the defaults of the GDB client.

With this commit, gem5 can inform the client which registers it knows
about. This allows in particular to support new registers which an older
GDB client does not yet know about.

The XML is not implemented in this commit for any arch, and falls back
almost exactly to previous behaviour. The only change is that now gem5
replies to the Supported: request which the GDB clients sends at the
beginning of the transaction with an empty feature list containing only
the mandatory PacketSize= argument.

Since the feature list does not contain qXfer:features:read, the GDB
client knows that the gem5 server does support the XML format and uses
its default registers as before.

Change-Id: I5185f28b00e9b9cc8245f4b4262cc324c3d298c1
Reviewed-on: https://gem5-review.googlesource.com/c/15137
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

13531:e6f1bf55d038 11-Oct-2018 Jairo Balart <jairo.balart@metempsy.com>

dev-arm: Add a GICv3 model

Change-Id: Ib0067fc743f84ff7be9f12d2fc33ddf63736bdd1
Reviewed-on: https://gem5-review.googlesource.com/c/13436
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

13530:765c1692adfb 08-Jan-2019 Giacomo Travaglini <giacomo.travaglini@arm.com>

base: Make it possible to convert strings to enums

The __to_number helper function defined in base/str.hh is used by
unserializing code. Its purpose is to convert a string into an
integral/floating point number. Since enums underlying type can only be
an integer type, it makes sense to extend the helper function for enums
as well. In this way it will be possible to unserialize Enums and
containers of Enums without the need of casting.

Change-Id: I74069cc4c04ec8b5eb80939acea7ab18fb366dd4
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15336
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

13487:ed055875261d 07-Dec-2018 Giacomo Travaglini <giacomo.travaglini@arm.com>

base, systemc: Fix clang compilation

This patch is fixing the following issues:

- base: typename should be used only for types
- systemc: 'GCC_VERSION' is not defined for clang

Change-Id: I27c94445d65691a08a0a14a0ffe6b6942f6c455f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14976
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

13483:0d5d061d974f 05-Apr-2017 Rekai Gonzalez-Alberquilla <rekai.gonzalezalberquilla@arm.com>

base: Ported circlebuf to CircularQueue

Ported the existing circlebuf on top of the CircularQueue to condense
shared functionality and minimise code/functionality replication.

Additional contributors: Gabor Dozsa.

Change-Id: Ib4e67c638f0fb66b54cef77007a03439218bda7f
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13128
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

13482:6af7a10675b4 26-Apr-2017 Rekai Gonzalez-Alberquilla <rekai.gonzalezalberquilla@arm.com>

base: Iterable CircularQueue implementation

The former implementation of CircleBuf is functional but a bit too
tailored to match a use-case. This patches introduces a new iterable
circular queue, which adds some more functionality so it can also be
used for the newer LSQ implementation, where iteration and iterators
are a very desirable feature.

Additional contributors: Gabor Dozsa.

Change-Id: I5cfb95c8abc1f5e566a114acdbf23fc52a38ce5e
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13127
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

13476:04bf50476e37 01-Dec-2018 Nikos Nikoleris <nikos.nikoleris@arm.com>

base: Fix fiber compilation issue for Mac OS

Mac OS has deprecated the use of ucontext and at the moment we are
using a workaround to enable it. A side-effect is that the code is
marked as _POSIX_C_SOURCE and consequently <sys/mman.h> requires the
code to be also marked as _DARWIN_C_SOURCE to include the definition
of MAP_ANONYMOUS.

Change-Id: I65550d11a0a21cd36d832a7de6320e7e3f332a9d
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14817
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

13475:5189e2334f1a 28-Nov-2018 Nikos Nikoleris <nikos.nikoleris@arm.com>

base, sim: Add missing destructors

Derived classes with virtual functions need to define a virtual
destructor or a protected destructor otherwise calling the base class
destructor has undefined behavior. This change adds a virtual
distructor in the base class.

Change-Id: I1c855aa56dff6585ff99b9147bdb4eb9729a0a53
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14815
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

13474:291427b0753c 22-Oct-2018 Giacomo Gabrielli <giacomo.gabrielli@arm.com>

base: Add type alias for raw pointer in RefCountingPtr

Change-Id: Ied2204566a8fc5c34fb4702301051b8e5ab84ffe
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13717
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

13470:8f620b550448 13-Nov-2018 Ciro Santilli <ciro.santilli@arm.com>

base: increase the GDB buffer size dynamically

The size was not large enough for the 'G' packet on aarch64, which the
client sends to set registers.

This would lead to the stub not to be able to find the end of the input
packet and keep waiting forever.

Change-Id: Icb149f15a6c769371ebcb6ec5fbebc6170c31fc6
Reviewed-on: https://gem5-review.googlesource.com/c/14497
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

13466:cd8fd8480b4b 28-Nov-2018 Gabe Black <gabeblack@google.com>

base: Change the unit test binary names to use .test, and to be consistent.

Most tests were named *test where * was the base name of the file being
tested, but some were named differently based on, for instance, the
name of the class that file implemented.

This change makes all the test names consistently based off of the file
name they test, and also brings in the new .test convention to make
them easier to read.

Now, if you have a file like fiber.cc you want to test, you'd have a
unit test in a file called fiber.test.cc, and a test called fiber.test
which would generate a binary called fiber.test.opt, fiber.test.debug,
etc.

Change-Id: I61d59016090371a9bae72066e7473a34aecea21f
Reviewed-on: https://gem5-review.googlesource.com/c/14677
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

13465:dee578a46d87 28-Nov-2018 Gabe Black <gabeblack@google.com>

base: Rename unit test cc files to be *.test.cc.

This makes the name easier to read, looks ok if the file is named with
underscores between words or not, is easy to grep for, and shouldn't
introduce any ambiguities in the file names.

Change-Id: I34b7bcccea2d87c10c0de417dd5e3ef27c4b5666
Reviewed-on: https://gem5-review.googlesource.com/c/14676
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>

13462:84c7bffb36e2 28-Nov-2018 Gabe Black <gabeblack@google.com>

base: Fix include order in the inifile unit test.

Even though gtest.h is a C++ header, it looks like a C header which
makes the style check hook upset. Lets move it up so the hook doesn't
complain when the file is changed.

Change-Id: Ibcc2d0b7bf3b254c70e55b30379ebd4b70933c26
Reviewed-on: https://gem5-review.googlesource.com/c/14675
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

13457:b8204512963e 28-Nov-2018 Nikos Nikoleris <nikos.nikoleris@arm.com>

base: Add missing overrides in statistics header

Change-Id: Id5ee2a970a3dceee1b7e24ce3b452b7fece87875
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14619
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

13451:b7bae7b7495a 22-Nov-2018 Giacomo Travaglini <giacomo.travaglini@arm.com>

tests: Convert IniFile unit test to a GTest

Change-Id: I47d6c9cbae21877420a15ffcf8489e3c26959139
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14615
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

13449:2f7efa89c58b 26-Nov-2018 Gabe Black <gabeblack@google.com>

arch, base, cpu, gpu, mem: Replace assert(0 or false with panic.

Neither assert(0) nor assert(false) give any hint as to why control
getting to them is bad, and their more descriptive versions,
assert(0 && "description") and assert(false && "description"), jury
rig assert to add an error message when the utility function panic()
already does that directly with better formatting options.

This change replaces that flavor of call to assert with panic, except
in the actual code which processes the formatting that panic uses (to
avoid infinitely recurring error handling), and in some *.sm files
since I don't know what rules those have to follow and don't want to
accidentaly break them.

Change-Id: I8addfbfaf77eaed94ec8191f2ae4efb477cefdd0
Reviewed-on: https://gem5-review.googlesource.com/c/14636
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

13446:4d742ab7b70f 19-Nov-2018 Gabe Black <gabeblack@google.com>

base: Add some functions to convert floats to bits and vice versa.

These make it easier to extract the binary representation of floats and
doubles, and given a binary representation convert it back again.

The versions with a size prefix are safer to use since they make it
clear what size inputs/outputs are expected. The versions without are
to make writing generic code easier in case the same code snippet,
templated function, etc., needs to be applied in both circumstances.

Change-Id: Ib1f35a7e88e00806a7c639c211c5699b4af5a472
Reviewed-on: https://gem5-review.googlesource.com/c/14455
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

13439:bfded2538477 16-Nov-2018 Gabe Black <gabeblack@google.com>

base: Don't let exceptions leak from the to_number utility function.

This function catches a couple types of exceptions the functions it
calls might throw, but if one that it doesn't catch is thrown, then
it will propogate that exception to its own callers, and not initialize
the value it was asked to convert.

This might be considered desirable behavior since it lets errors
propogate and avoids handling them in code that might not know the
context of when it's called. On the other hand, it upsets g++ since it
thinks that there might be an uninitialized value used elsewhere, even
though that value will only be uninitialized if an exception is
propogating, and the code that would use it is after a point where that
exception would have been caught and execution would have resumed.

To satisfy g++ and to also avoid silently hiding errors, this change
adds a catch all which will panic if an unexpected exception is raised.

Change-Id: Ie94dcef3a50f7902566328a3fa2eac59b3cf9aad
Reviewed-on: https://gem5-review.googlesource.com/c/14399
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

13435:18fc735cae14 16-Nov-2018 Gabe Black <gabeblack@google.com>

base: Set up a guard page for fiber stacks.

This will help detect stack overflow for fibers.

Change-Id: Iff2b102120ec351709e495291d6bead597f8d10c
Reviewed-on: https://gem5-review.googlesource.com/c/14395
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>

13429:a1e199fd8122 06-Feb-2017 Rekai Gonzalez-Alberquilla <rekai.gonzalezalberquilla@arm.com>

cpu: Fix the usage of const DynInstPtr

Summary: Usage of const DynInstPtr& when possible and introduction of
move operators to RefCountingPtr.

In many places, scoped references to dynamic instructions do a copy of
the DynInstPtr when a reference would do. This is detrimental to
performance. On top of that, in case there is a need for reference
tracking for debugging, the redundant copies make the process much more
painful than it already is.

Also, from the theoretical point of view, a function/method that
defines a convenience name to access an instruction should not be
considered an owner of the data, i.e., doing a copy and not a reference
is not justified.

On a related topic, C++11 introduces move semantics, and those are
useful when, for example, there is a class modelling a HW structure that
contains a list, and has a getHeadOfList function, to prevent doing a
copy to an internal variable -> update pointer, remove from the list ->
update pointer, return value making a copy to the assined variable ->
update pointer, destroy the returned value -> update pointer.

Change-Id: I3bb46c20ef23b6873b469fd22befb251ac44d2f6
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13105
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

13385:5295c5bf5fa6 12-Oct-2018 Gabe Black <gabeblack@google.com>

base: Add standard types for floating and nonfloating point register values.

These should be used instead of the ISA specific ones, and should be
at least as large as the largest primitive register type in all the
ISAs.

Change-Id: Iaac104eef74eabcdd87787b1cdf8bea22d449eda
Reviewed-on: https://gem5-review.googlesource.com/c/13615
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

13360:a2254720ecf3 23-Oct-2018 Andreas Sandberg <andreas.sandberg@arm.com>

tests: Convert AddrRangeMap unit test to a GTest

Change-Id: Ifeb0b57c0cda77706691286f78325e50edb31c0d
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13736
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

13359:4f3ab46cc7c7 24-Oct-2018 Andreas Sandberg <andreas.sandberg@arm.com>

tests: Convert CircleBuf unit test to a GTest

Change-Id: I028c6b8d8e0ec06cac3d636689ae647f717096cd
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13735
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

12981:efad272351e3 11-Sep-2018 Gabe Black <gabeblack@google.com>

base: Avoid dividing by zero in Time::[gs]etTick.

Those functions used the value SimClock::Int::ns which, if the time
resolution is larger than 1ns, can/will be zero. That will make
getTick always return zero, and setTick divide by zero. This change
modifies those functions so that the math they do avoids using any
integer Ticks per time unit value except for Frequency. It seems
unlikely that the Ticks will increment at less than 1Hz.

Change-Id: I5cc9db14699c00dcbff48e4593b98522b13b4ccd
Reviewed-on: https://gem5-review.googlesource.com/12573
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

12979:246ea8611e73 11-Sep-2018 Gabe Black <gabeblack@google.com>

base: Save and restore the width setting of streams used with cprintf.

The flags, precision, and fill character were all being saved and
restored, but cprintf might also change the width setting of the
stream, and that wasn't being saved or restored and could leak from
the cprintf statement.

This change adds the code to save and restore that value.

Change-Id: Ibedb26f7f538cd3be4fe0462d2ee4e5efd62bc59
Reviewed-on: https://gem5-review.googlesource.com/12571
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

12977:cdc78a6e54d7 29-Aug-2018 Nikos Nikoleris <nikos.nikoleris@arm.com>

base: Fix isSubset() for addr ranges with interleaving

This change extends isSubset() which checks whether the range is a
subset of an input range to support address ranges with interleaving
and hashing.

Change-Id: I3dc9ceccb189b7c8665de0355f0555fc2c37d872
Reviewed-on: https://gem5-review.googlesource.com/12319
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

12920:76a7817ebea3 22-Aug-2018 Gabe Black <gabeblack@google.com>

base: If valgrind is available, tell it about Fiber stacks.

Valgrind can get confused when switching stacks between different
Fibers. If valgrind (and its headers) are available, this change adds
calls to some hooks so valgrind knows where the new stacks are and
doesn't report a bunch of false positives.

Change-Id: I00aefe60372be6de7371dec29427d7182dbee7b6
Reviewed-on: https://gem5-review.googlesource.com/12227
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>

12895:16e3712d8189 02-Aug-2018 Jason Lowe-Power <jason@lowepower.com>

misc: Appease GCC 8

GCC 8 adds a number of new warnings to -Wall which generate errors.

- Fix memset to 0 for structs by adding casts.
- Fix cast with const when the const was ignored.
- Fix catch a polymorphic type by value

We now compile with GCC 8!

Change-Id: Iab70ce11190eee67608fc25c0bedff170152b153
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/11949
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

12859:4f836bcde760 26-Jul-2018 Bradley <animalvgamer@gmail.com>

base: Replace cppversion == version with >= version

For forward compatibility with later compilers, we should have a greater
than comparison instead of an explicit equality with a particular C++
version.

Change-Id: If848097420b9575f80134986410da3dab32567da
Signed-off-by: Bradley Wang <radwang@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/11871
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

12846:f863a61d8b16 17-Jul-2018 Giacomo Travaglini <giacomo.travaglini@arm.com>

base: Fix ucontext compilation error for macOS

ucontext functions (like getcontext, setcontext etc) have been marked
as deprecated and are hence hidden in latest macOS releases.
This patch uncovers them; warnings wil be produced but compilation
won't fail since -Wno-error=deprecated-declarations flag is currently
used.

Change-Id: Ic10e6f77a38875828b1891eaed2f0626ecffff67
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11729
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

12806:d652f71ce319 02-May-2018 Andreas Sandberg <andreas.sandberg@arm.com>

base: Add a M5_PUBLIC and M5_LOCAL attribute macro

There are cases where we need to limit the symbol visibility to avoid
compilation errors. This is a problem for Python code that relies on
PyBind11 since recent versions enforce hidden symbols. As a
consequence, classes that have member variables from PyBind11 need to
be declared with the hidden attribute (or gem5 needs to be compiled
with -fvisibility=hidden).

Change-Id: I30e582fde494ff61ab7a596a595efc26a2952a5f
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11513
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

12800:7736882bdea5 14-Jun-2018 Giacomo Travaglini <giacomo.travaglini@arm.com>

base: Add an asymmetrical Coroutine class

This patch is providing gem5 a Coroutine class to be used for
instantiating asymmetrical coroutines. Coroutines are built on top of
gem5 fibers, which makes them ucontext based.

Change-Id: I7bb673a954d4a456997afd45b696933534f3e239
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11195
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

12787:1f6e23cddf71 08-Jun-2018 Gabe Black <gabeblack@google.com>

base: Add a class which encapsulates Fibers.

This class encapsulates the idea of a Fiber in such a way that other
implementations can be substituted in in the future. This
implementation uses the ucontext family of functions.

This change also adds a new unit test which exercises the new class. It
creates three new fibers which accept a sequence of other fibers to
switch to, one after the other. The main test function switches to
the these fibers which switch with each other and occasionally back to
the main fiber. Each time a test fiber is activated, it checks against
a list which shows the correct order for the fibers to run in. When the
main fiber gets control, it makes sure that list has been progressed
through by the correct amount.

Change-Id: I1fc2afa414b51baaa91e350a4ebc791d989f0b8a
Reviewed-on: https://gem5-review.googlesource.com/10935
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

12783:a610dc4b5778 20-Jun-2018 Nikos Nikoleris <nikos.nikoleris@arm.com>

base: Fix includes in AddrRangeMap header file

Change-Id: I4bdd6cf7c8d22219c0582ab206ec8372a4357759
Reviewed-on: https://gem5-review.googlesource.com/11429
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

12777:70526b89f66e 18-Oct-2017 Gabe Black <gabeblack@google.com>

base: Build caching into the AddrRangeMap class

Rather than have each consumer of the AddrRangeMap implement caching
lookups on their own, this change adds a centralized mechanism to the
AddrRangeMap class itself.

Some benefits of this approach are that the cache handles deleted
entries correctly/automatically, the cache is maintained by
adding/removing entries from a linked list rather than moving elements
in an array and checking valid bits, and it's easy to enable in places
which might otherwise not bother with caching. The amount of caching
is tunable to balance overhead with improved lookup performance.

Change-Id: Ic25997e23de4eea501e47f039bb52ed0502c58d2
Reviewed-on: https://gem5-review.googlesource.com/5242
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

12776:410b60d8a397 18-Apr-2018 Nikos Nikoleris <nikos.nikoleris@arm.com>

base, mem: Disambiguate if an addr range is contained or overlaps

We need to determined whether an address range is fully contained or
it overlaps with an address range in the address range in the mmap. As
an example, we use address range maps to associate ports to address
ranges and we determine which port we will forward the request based
on which address range contains the addresses accessed by the
request. We also need to make sure that when we add a new port to the
address range map, its address range does not overlap with any of the
existing ports.

This patch splits the function find() into two functions contains()
and intersects() to implement this distinct functionality. It also
changes the xbar and the physical memory to use the right function.

Change-Id: If3fd3f774a16b27db2df76dc04f1d61824938008
Reviewed-on: https://gem5-review.googlesource.com/11115
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

12766:1c347e60c7fd 22-Jan-2018 Tuan Ta <qtt2@cornell.edu>

base,mem: Support AtomicOpFunctor in the classic memory system

AtomicOpFunctor can be used to implement atomic memory operations.
AtomicOpFunctor is captured inside a memory request and executed directly
in the memory hierarchy in a single step.

This patch enables AtomicOpFunctor pointers to be included in a memory
request and executed in a single step in the classic cache system.

This patch also makes the copy constructor of Request class do a deep
copy of AtomicOpFunctor object. This prevents a copy of a Request object
from accessing a deleted AtomicOpFunctor object.

Change-Id: I6649532b37f711e55f4552ad26893efeb300dd37
Reviewed-on: https://gem5-review.googlesource.com/8185
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

12701:d1fd92f06385 15-May-2018 Nikos Nikoleris <nikos.nikoleris@arm.com>

base: Add M5 flag for [[nodiscard]] attribute

This change adds the M5_NODISCARD keyword to allow use of the
[[nodiscard]] attribute with compilers that support C++17. Currently,
C++17 is not a requirement and therefore the M5_NODISCARD has not
effect and does not break compilation for older compilers.

Change-Id: Ifc5c8f34764da3c7291066dcb2ff908c97738c3d
Reviewed-on: https://gem5-review.googlesource.com/10441
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

12693:4db8d6442b44 20-Feb-2018 Andreas Sandberg <andreas.sandberg@arm.com>

base, dev: Fix port message for vnc and terminal

When running gem5, the simulator outputs the following message to
describe the ports used by the VNC server and ther terminal:

Listening for system connection on port 5900
Listening for system connection on port 3456

The code used to extract the basename ('terminal' or 'vncserver') and
print that instead of system. However, this doesn't seem to work any
more. Change the code to output the full object name instead.

Change-Id: Ib27f66a5f8ba64c7a875b4e2f26a2e2ff48db8f3
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10026
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

12631:d48fc4cce6eb 29-Mar-2018 Gabe Black <gabeblack@google.com>

base: Make bitunion output functions static/inline.

The specializations need to be online only and not static, but the
template itself is static and inline.

Originally they were in an anonymous namespace, but that causes
warnings when building on clang or with certain versions of gcc because
the functions may not be used in every .cc.

Change-Id: Iff127337f7bf0c18755de07a49d6e7a9ce6f2f0a
Reviewed-on: https://gem5-review.googlesource.com/9581
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

12625:c0cf272e0456 27-Mar-2018 Gabe Black <gabeblack@google.com>

base: Add a default output function for bitunion types.

This way printing bitunions with, for instance, DPRINTF actually prints
something useful. More specialized overloads will still allow printing
particular bitunion types in ways that might make more sense for that
particular type.

Change-Id: I92beb0ce07683ba8b318cf25aa73e0057e4a60ef
Reviewed-on: https://gem5-review.googlesource.com/9461
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

12595:b5a51007feac 19-Feb-2018 Siddhesh Poyarekar <siddhesh.poyarekar@gmail.com>

arm: Fix implicit-fallthrough warnings when building with gcc-7+

gcc 7 onwards have additional heuristics to detect implicit
fallthroughs and it fails the build with warnings for ARM as a result.
There was one gcc bug[1] that I fixed but the rest are cases that gcc
cannot detect due to the point at which it does the fallthrough check.
Most of this patch adds __builtin_unreachable() hints in places that throw
this warning to indicate to gcc that the fallthrough will never
happen.

The remaining cases are actually possible fallthroughs due to
incorrect code running on the simulator; in which case an Unknown
instruction is returned.

[1] https://gcc.gnu.org/ml/gcc-patches/2018-02/msg01105.html

Change-Id: I1baa9fa0ed15181c10c755c0bd777f88b607c158
Signed-off-by: Siddhesh Poyarekar <siddhesh.poyarekar@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/8541
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

12582:e4f0727b353e 13-Mar-2018 Chun-Chen Hsu <chunchenhsu@google.com>

base: Fix loop range in pngwriter

The inner loop range limit should be width instead of height.

Change-Id: I091c590713c945d4bd04ffcc974d4eb8aa23d1b2
Signed-off-by: Chun-Chen Hsu <chunchenhsu@google.com>
Reviewed-on: https://gem5-review.googlesource.com/9081
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

12517:77e8688fc670 10-Feb-2017 Rekai Gonzalez-Alberquilla <rekai.gonzalezalberquilla@arm.com>

sim: Make Stats truly non-copy-constructible

The stats are silently non-copy constructible. Therefore, when someone
copy-constructs any object with stats, asserts happen when registering
the stats, as they were not constructed in the intended way.

This patch solves that by explicitly deleting the copy constructor,
trading an obscure run-time assert for a compile-time somehow more
meaningful error meassage.

This triggers some compilation errors as the FaultStats in the fault
definitions of ARM and SPARC use brace-enclosed initialisations in which
one of the elements derives from DataWrap, which is not
copy-constructible anymore. To fix that, this patch also adds a
constructor for the FaultVals in both ISAs.

Change-Id: I340e203b9386609b32c66e3b8918a015afe415a4
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8082
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

12491:8765e1fb564d 04-Feb-2018 Gabe Black <gabeblack@google.com>

base: Update #includes for bitunion.hh.

<iostream> isn't actually used anywhere in bitunion.hh. The templated
hash struct type is defined in <functional> and should be included
explicitly.

Change-Id: I8691ccb2f9e28a01610ae8bb4d9591b07cb7320b
Reviewed-on: https://gem5-review.googlesource.com/7781
Reviewed-by: Matthias Jung <jungma@eit.uni-kl.de>
Maintainer: Gabe Black <gabeblack@google.com>

12487:fddccd96c9fc 01-Feb-2018 Nikos Nikoleris <nikos.nikoleris@arm.com>

base: Fix unused function warning

After refactoring the remote gdb interface, break_type is declared as
const function and is only used as a parameter to DPRINTF function
calls. This means that it is seen as unused when compiling
gem5.fast. This changeset fixes the warning.

Change-Id: Iea89b66c53c62341c043d8bd3838ebc27ee333bc
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/7741
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

12481:f8324edb4d24 29-Jan-2018 Gabe Black <gabeblack@google.com>

base: Remove the ability to cprintf stringstreams directly.

The cprintf functions don't know ahead of time what format characters
are going to be used with what underlying data types, and so any
type must be minimally usable with the default specialization of
format_integer, format_char, format_float and format_string. All of
those functions ultimately print their parameter with out << data
except the one which prints stringstreams. That function accesses the
buffer of the string stream with .str(), and then prints that instead.

That should technically work out ok as long as stringstreams are only
printed using %s, but there's no way to guarantee that ahead of time.
To avoid that problem, and because gem5 doesn't ever actually use the
ability to print stringstreams directly, this change removes that
feature and modifies the corresponding part of the unit test.

If we ever do want to print the contents of a string stream, it won't
be difficult to add a .str() to it.

Change-Id: Id902eaff042b96b374efe0183e5e3be9626e8c88
Reviewed-on: https://gem5-review.googlesource.com/7642
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

12480:8ea05a9ce49e 29-Jan-2018 Gabe Black <gabeblack@google.com>

base: Delete commented out versions of the format_integer function.

If they're needed, they'd be fairly easy to recreate and are also
available in the revision history.

Change-Id: I5cf5e4b1271ce488016464048de69bc643dee4d9
Reviewed-on: https://gem5-review.googlesource.com/7641
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

12466:58a7a5e976dd 27-Jan-2018 Gabe Black <gabeblack@google.com>

base: Add an "override" to name() in the HardBreakpoint class.

clang reports an error otherwise and fails to compile.

Change-Id: I3603d6c710641f1289e35c67f89a49f5cb71e95e
Reviewed-on: https://gem5-review.googlesource.com/7582
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

12465:db848583d43e 27-Jan-2018 Gabe Black <gabeblack@google.com>

base: Get bitunions to compile on clang 3.8.

clang was getting very upset and interpretting a member function
pointer as a call to the actual underlying function, and then
complaining that it was a non-static function call without an instance.

It seems what it was really upset about was that the class who's scope
the member function pointer belonged to (the current class) wasn't done
being defined. This *should* be ok as far as I can tell, but clang was
having none of it.

This change reworks how the type of the setter function arguments are
determined to work around that limitation. The bitunion test was run
with clang++ and g++ and both pass, and I've built gem5.opt for ARM
successfully.

Change-Id: Ib9351784a897af4867fe08045577e0247334ea11
Reviewed-on: https://gem5-review.googlesource.com/7581
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

12454:277c1f58ab6d 07-Jan-2018 Gabe Black <gabeblack@google.com>

base: Hide the BitUnion::__StorageType type.

Since this type is now accessible through a clean interface, hide it
from anybody that tries to peak around the curtain.

Change-Id: I1257b6675a45b8648be459ad8e8d0f27a6feee6b
Reviewed-on: https://gem5-review.googlesource.com/7205
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

12453:424595e0a14e 07-Jan-2018 Gabe Black <gabeblack@google.com>

arm, base: Generalize and move the BitUnion hash struct.

The ARM types.hh file defined an STL style hash structure to operate
on the ExtMachInst, but it referred to the underlying storage type
using internal typedefs in the BitUnion types. To avoid having to do
that, this change adds a hash structure to bitunion.hh which will work
on any BitUnion, and gets rid of the ARM ExtMachInst version.

Change-Id: I7c1c84d61b59061fec98abaaeab6becd06537dee
Reviewed-on: https://gem5-review.googlesource.com/7204
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

12451:5a5024ab0364 07-Jan-2018 Gabe Black <gabeblack@google.com>

base: Enable specializing templates on BitUnion types.

Previously these relied on reaching into private internal definitions
in the BitUnion types.

Change-Id: Ia6c94de92986b85ec9e5fcb197459d450111fb36
Reviewed-on: https://gem5-review.googlesource.com/7202
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

12450:b5a0300fc327 06-Jan-2018 Gabe Black <gabeblack@google.com>

base: Rework bitunions so they can be more flexible.

They are now oriented around a class which makes it easy to provide
custom setter/getter functions which let you set or read bits in an
arbitrary way.

Future additions may add the ability to add custom bitfield methods,
and index-able bitfields.

Change-Id: Ibd6d4d9e49107490f6dad30a4379a8c93bda9333
Reviewed-on: https://gem5-review.googlesource.com/7201
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

12449:2260f4a68210 16-Jan-2018 Gabe Black <gabeblack@google.com>

sim, arch, base: Refactor the base remote GDB class.

Fold the GDBListener class into the main BaseRemoteGDB class, move
around a bunch of functions, convert a lot of internal functions to
be private, move some functions into the .cc, make some functions
non-virtual which didn't really need to be overridden.

Change-Id: Id0832b730b0fdfb2eababa5067e72c66de1c147d
Reviewed-on: https://gem5-review.googlesource.com/7422
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

12429:beefb9f5f551 09-Jan-2018 BKP <brandon.potter@amd.com>

style: change C/C++ source permissions to noexec

Several files in the repository were tracked with execute permissions
even though the files are just normal C/C++ files (and the one .isa).

Change-Id: I976b096acab4a1fc74c5699ef1f9b222c1e635c2
Reviewed-on: https://gem5-review.googlesource.com/7241
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

12392:e0dbdf30a2a5 13-Dec-2017 Jason Lowe-Power <jason@lowepower.com>

misc: Updates for gcc7.2 for x86

GCC 7.2 is much stricter than previous GCC versions. The following changes
are needed:

* There is now a warning if there is an implicit fallthrough between two
case statments. C++17 adds the [[fallthrough]]; declaration. However,
to support non C++17 standards (i.e., C++11), we use M5_FALLTHROUGH.
M5_FALLTHROUGH checks for [[fallthrough]] compliant C++17 compiler and
if that doesn't exist, it defaults to nothing (no older compilers
generate warnings).
* The above resulted in a couple of bugs that were found. This is noted
in the review request on gerrit.
* throw() for dynamic exception specification is deprecated
* There were a couple of new uninitialized variable warnings
* Can no longer perform bitwise operations on a bool.
* Must now include <functional> for std::function
* Compiler bug for void* lambda. Changed to auto as work around. See
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82878

Change-Id: I5d4c782a4e133fa4cdb119e35d9aff68c6e2958e
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/5802
Reviewed-by: Gabe Black <gabeblack@google.com>

12386:2bf5fb25a5f1 13-Dec-2017 Gabe Black <gabeblack@google.com>

arm,sparc,x86,base,cpu,sim: Replace the Twin(32|64)_t types with.

Replace them with std::array<>s.

Change-Id: I76624c87a1cd9b21c386a96147a18de92b8a8a34
Reviewed-on: https://gem5-review.googlesource.com/6602
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

12382:face556c9c47 04-Dec-2017 Gabe Black <gabeblack@google.com>

tests: Turn fbtest into a gtest and move it to src/base.

Change-Id: I9ca57e24f27e0eb747d1f27262972a8abcd10fc8
Reviewed-on: https://gem5-review.googlesource.com/6342
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

12381:2f845ce45c9d 04-Dec-2017 Gabe Black <gabeblack@google.com>

tests: Move the cprintftest unit test into src/base.

That way it will live alongside the code it tests.

Change-Id: I00baad2206870a4619b7cee792a1d4c303dad04d
Reviewed-on: https://gem5-review.googlesource.com/6324
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

12379:52b13ae47c42 03-Dec-2017 Gabe Black <gabeblack@google.com>

tests: Move the trietest unit test into base.

This puts it alongside trie.hh, the header file it tests.

Change-Id: Id8ca0c1d68bdc01807c5ba4b51c0142b1221385d
Reviewed-on: https://gem5-review.googlesource.com/6281
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>

12376:d28ea5e874f7 03-Dec-2017 Gabe Black <gabeblack@google.com>

tests: Add an implementation of the Logger interface for use gtests.

On exiting log types (panic and fatal), the message is set to an
ADD_FAILURE_AT macro, and the test is exited by throwing an otherwise
unexpected exception. On non-exiting log types, the message is sent to
the SUCCEEDED macro which currently doesn't output anything.

Change-Id: I1bb569e6cb8308dbc4c3e04eea7a962bd2b1ddd8
Reviewed-on: https://gem5-review.googlesource.com/6264
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

12375:ceeb064dec4a 03-Dec-2017 Gabe Black <gabeblack@google.com>

misc: Rework the logging functions.

Removed the "verbose" switch which wasn't used.

Replaced the "get(LogLevel)" function with a get for each level. The
parameter was always constant, so we can just call the right function
at the right time.

Made the "exit" behavior of panic/fatal a part of the logging
implementation so that it can be overridden, and corrected a comment
which said that both fatal and panic called ::abort().

Got rid of the printEpilogue function by reworking the print() methods.
The subclasses of Logger can now override a "log" function which takes
a composed message, letting the Logger class centralize how the message
is put together and leaving the actual output mechanism to the
subclass.

Unfortunately there wasn't a way to tell gcc that the panic/fatal
macros wouldn't return, so there needed to be an exit_helper wrapper
function which calls the actual logger exit function. That can be
marked as noreturn, unlike the virtual exit function. If the exit
function does return, the wrapper will call ::abort(), placating gcc
and ensuring that even if exit isn't implemented properly, exit_helper
will still not return. That also provides a handy default
implementation.

Change-Id: I66d0cebd59f1127db980f3b565dbdf60687d8862
Reviewed-on: https://gem5-review.googlesource.com/6263
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

12366:3b4b6fa339a9 04-Dec-2017 Gabe Black <gabeblack@google.com>

base: Split out the pixel class in framebuffer.(cc|hh).

These are really two separate things. Also, while it's realitively
straightforward to write a unit test for the pixel conversion code, the
framebuffer object is serializable and brings in more dependencies.

Change-Id: If954caeb0bfedb1002cfb1a7a115a00c90d56d19
Reviewed-on: https://gem5-review.googlesource.com/6341
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

12365:4444393b3551 04-Dec-2017 Gabe Black <gabeblack@google.com>

base: Handle zero fill in cprintf when printing floats.

The fill_zero flag was being followed for ints, but not for floats.
This makes the cprintf unit test pass.

Change-Id: I4d17a3c9327aea05e0a3c81be1886c0c9256f03c
Reviewed-on: https://gem5-review.googlesource.com/6322
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

12335:4a2fde008219 03-Dec-2017 Gabe Black <gabeblack@google.com>

base: Rework the trie dump function to accept a different ostream.

It might often be useful to write output to cout when dumping a trie,
but sometimes it might be useful to dump ot to something else like a
string stream instead.

Change-Id: Iaa4ae772c902b7dbc753f320d1a7eb5fcd4a3db3
Reviewed-on: https://gem5-review.googlesource.com/6266
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>

12334:e0ab29a34764 30-Nov-2017 Gabe Black <gabeblack@google.com>

misc: Rename misc.(hh|cc) to logging.(hh|cc)

These files aren't a collection of miscellaneous stuff, they're the
definition of the Logger interface, and a few utility macros for
calling into that interface (panic, warn, etc.).

Change-Id: I84267ac3f45896a83c0ef027f8f19c5e9a5667d1
Reviewed-on: https://gem5-review.googlesource.com/6226
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>


/gem5/ext/sst/gem5.cc
/gem5/src/arch/alpha/isa.cc
/gem5/src/arch/alpha/locked_mem.hh
/gem5/src/arch/alpha/mt.hh
/gem5/src/arch/alpha/process.cc
/gem5/src/arch/alpha/pseudo_inst.hh
/gem5/src/arch/alpha/utility.hh
/gem5/src/arch/arm/faults.hh
/gem5/src/arch/arm/isa_device.cc
/gem5/src/arch/arm/miscregs.cc
/gem5/src/arch/arm/process.cc
/gem5/src/arch/arm/pseudo_inst.hh
/gem5/src/arch/arm/types.hh
/gem5/src/arch/arm/utility.hh
/gem5/src/arch/generic/debugfaults.hh
/gem5/src/arch/generic/pseudo_inst.cc
/gem5/src/arch/generic/tlb.hh
/gem5/src/arch/generic/vec_reg.hh
/gem5/src/arch/hsail/gpu_isa.hh
/gem5/src/arch/mips/decoder.hh
/gem5/src/arch/mips/dsp.cc
/gem5/src/arch/mips/dsp.hh
/gem5/src/arch/mips/interrupts.hh
/gem5/src/arch/mips/locked_mem.hh
/gem5/src/arch/mips/mt.hh
/gem5/src/arch/mips/pagetable.hh
/gem5/src/arch/mips/process.cc
/gem5/src/arch/mips/pseudo_inst.hh
/gem5/src/arch/mips/registers.hh
/gem5/src/arch/mips/utility.cc
/gem5/src/arch/mips/utility.hh
/gem5/src/arch/power/interrupts.hh
/gem5/src/arch/power/isa.hh
/gem5/src/arch/power/process.cc
/gem5/src/arch/power/pseudo_inst.hh
/gem5/src/arch/power/utility.cc
/gem5/src/arch/riscv/decoder.hh
/gem5/src/arch/riscv/interrupts.hh
/gem5/src/arch/riscv/isa.hh
/gem5/src/arch/riscv/locked_mem.hh
/gem5/src/arch/riscv/pagetable.hh
/gem5/src/arch/riscv/process.cc
/gem5/src/arch/riscv/pseudo_inst.hh
/gem5/src/arch/sparc/isa/includes.isa
/gem5/src/arch/sparc/mt.hh
/gem5/src/arch/sparc/pagetable.hh
/gem5/src/arch/sparc/process.cc
/gem5/src/arch/sparc/pseudo_inst.hh
/gem5/src/arch/sparc/tlb.hh
/gem5/src/arch/sparc/utility.hh
/gem5/src/arch/x86/bios/intelmp.cc
/gem5/src/arch/x86/decoder.cc
/gem5/src/arch/x86/decoder.hh
/gem5/src/arch/x86/emulenv.cc
/gem5/src/arch/x86/faults.hh
/gem5/src/arch/x86/isa/includes.isa
/gem5/src/arch/x86/process.cc
/gem5/src/arch/x86/regs/int.hh
SConscript
addr_range.hh
bigint.hh
bmpwriter.cc
circlebuf.hh
debug.cc
hostinfo.cc
imgwriter.cc
intmath.hh
loader/ecoff_object.cc
loader/elf_object.cc
loader/object_file.hh
loader/symtab.cc
logging.cc
logging.hh
misc.cc
misc.hh
output.cc
pngwriter.cc
pollevent.cc
random.cc
socket.cc
statistics.cc
stats/text.cc
time.cc
trace.cc
trie.hh
vnc/vncinput.cc
vnc/vncserver.cc
/gem5/src/cpu/base.cc
/gem5/src/cpu/func_unit.cc
/gem5/src/cpu/intr_control.hh
/gem5/src/cpu/kvm/device.cc
/gem5/src/cpu/kvm/perfevent.cc
/gem5/src/cpu/kvm/timer.cc
/gem5/src/cpu/minor/buffers.hh
/gem5/src/cpu/o3/free_list.hh
/gem5/src/cpu/o3/store_set.cc
/gem5/src/cpu/pc_event.hh
/gem5/src/cpu/pred/2bit_local.cc
/gem5/src/cpu/pred/btb.hh
/gem5/src/cpu/pred/ltage.cc
/gem5/src/cpu/pred/sat_counter.hh
/gem5/src/cpu/simple/base.cc
/gem5/src/cpu/static_inst.hh
/gem5/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc
/gem5/src/cpu/testers/rubytest/RubyTester.cc
/gem5/src/cpu/thread_context.cc
/gem5/src/dev/intel_8254_timer.cc
/gem5/src/dev/mc146818.hh
/gem5/src/dev/net/dist_iface.hh
/gem5/src/dev/net/etherbus.cc
/gem5/src/dev/net/etherdump.cc
/gem5/src/dev/net/etherint.cc
/gem5/src/dev/net/etherpkt.cc
/gem5/src/dev/net/ethertap.cc
/gem5/src/dev/net/pktfifo.cc
/gem5/src/dev/net/pktfifo.hh
/gem5/src/dev/pci/device.cc
/gem5/src/dev/platform.cc
/gem5/src/dev/ps2.cc
/gem5/src/dev/serial/serial.cc
/gem5/src/dev/serial/terminal.cc
/gem5/src/dev/storage/disk_image.cc
/gem5/src/dev/storage/simple_disk.cc
/gem5/src/gpu-compute/brig_object.cc
/gem5/src/gpu-compute/gpu_tlb.hh
/gem5/src/gpu-compute/hsa_object.cc
/gem5/src/gpu-compute/misc.hh
/gem5/src/gpu-compute/of_scheduling_policy.hh
/gem5/src/gpu-compute/rr_scheduling_policy.hh
/gem5/src/gpu-compute/simple_pool_manager.cc
/gem5/src/gpu-compute/tlb_coalescer.hh
/gem5/src/gpu-compute/vector_register_file.cc
/gem5/src/gpu-compute/wavefront.hh
/gem5/src/kern/operatingsystem.cc
/gem5/src/mem/cache/base.hh
/gem5/src/mem/cache/cache.cc
/gem5/src/mem/cache/cache.hh
/gem5/src/mem/cache/mshr.cc
/gem5/src/mem/cache/tags/fa_lru.cc
/gem5/src/mem/cache/write_queue_entry.cc
/gem5/src/mem/coherent_xbar.cc
/gem5/src/mem/dramsim2_wrapper.cc
/gem5/src/mem/mem_checker.hh
/gem5/src/mem/noncoherent_xbar.cc
/gem5/src/mem/packet.cc
/gem5/src/mem/packet.hh
/gem5/src/mem/request.hh
/gem5/src/mem/ruby/common/Set.hh
/gem5/src/mem/ruby/network/MessageBuffer.cc
/gem5/src/mem/ruby/network/Network.cc
/gem5/src/mem/ruby/network/fault_model/FaultModel.cc
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
/gem5/src/mem/ruby/structures/AbstractReplacementPolicy.cc
/gem5/src/mem/ruby/system/GPUCoalescer.cc
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/VIPERCoalescer.cc
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/mem/slicc/symbols/Type.py
/gem5/src/mem/snoop_filter.cc
/gem5/src/mem/xbar.cc
/gem5/src/proto/protoio.cc
/gem5/src/python/pybind11/core.cc
/gem5/src/python/pybind11/event.cc
/gem5/src/sim/clocked_object.cc
/gem5/src/sim/drain.cc
/gem5/src/sim/dvfs_handler.cc
/gem5/src/sim/eventq.cc
/gem5/src/sim/faults.cc
/gem5/src/sim/fd_array.cc
/gem5/src/sim/init.cc
/gem5/src/sim/init_signals.cc
/gem5/src/sim/mathexpr.cc
/gem5/src/sim/microcode_rom.cc
/gem5/src/sim/root.cc
/gem5/src/sim/serialize.cc
/gem5/src/sim/sim_object.cc
/gem5/src/sim/simulate.cc
/gem5/src/sim/syscall_emul.hh
/gem5/src/unittest/cprintftest.cc
/gem5/src/unittest/nmtest.cc
/gem5/src/unittest/stattest.cc
/gem5/util/systemc/sc_module.cc
12333:6a7e44a88b91 30-Nov-2017 Gabe Black <gabeblack@google.com>

misc: Move the ExitLogger class definition into misc.cc

This class isn't referred to outside of misc.hh, and isn't necessarily
useful outside of the particular logging setup implemented in misc.cc.
The Logger class itself is different since it provides a generic
interface that can be used with different logging schemes.

Change-Id: Ibae926fea039d9e3d75a43d97348bc4a3c5d555e
Reviewed-on: https://gem5-review.googlesource.com/6225
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>

12332:2adbc3f0f65a 29-Nov-2017 Gabe Black <gabeblack@google.com>

tests: Remove trietest's dependence on cprintf.

Dumping the structure of the tries being constructed was useful for
debugging when the trie data structure was being developed, but the
output can't be automatically verified easily, and what's considered
correct depends on the specific implementation of the trie itself.

To make some of the earlier tests more meaningful, additional lookups
were added which verified that the correct values were returned when
the nodes of the trie were in particular arrangements.

Change-Id: Ib464ad1804d13fe40882da2190d7bf452da83818
Reviewed-on: https://gem5-review.googlesource.com/6223
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>

12316:c498e2d5403e 27-Nov-2017 Gabe Black <gabeblack@google.com>

tests: Move the bituniontest to be alongside the bitunion header.

Change-Id: I7c1a49c41672a1108fcf67c5505b0441f90588ef
Reviewed-on: https://gem5-review.googlesource.com/6142
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

12258:08990d24fe41 13-Oct-2017 Giacomo Travaglini <giacomo.travaglini@arm.com>

arm: Add support for armv8 CRC32 instructions

This patch introduces the ARM A32/T32/A64 CRC Instructions, which are
mandatory since ARMv8.1. The UNPREDICTABLE behaviours are implemented as
follows:
1) CRC32(C)X (64 bit) instructions are decoded as Undefined in Aarch32
2) The instructions support predication in Aarch32
3) Using R15(PC) as source/dest operand is permitted in Aarch32

Change-Id: Iaf29b05874e1370c7615da79a07f111ded17b6cc
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5521
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

12231:3bb6eaec2859 29-Sep-2017 Giacomo Travaglini <giacomo.travaglini@arm.com>

vnc: Default image writer type set to Auto

This commit modifies the default behaviour of the vnc frame dumping
process: rather than using 'Bitmap' as a default parameter value, it is
using 'Auto'. Auto parameter is letting gem5 to choose the most
efficient image format among the available ones.

Change-Id: I3c8e2b5a34a5925d24892880ac362dfe38de36e3
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5182
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

12230:48021d6b51eb 28-Sep-2017 Giacomo Travaglini <giacomo.travaglini@arm.com>

base: Introducing utility for writing raw data in png format

Originally it was possible to use a Bitmap writer class for dumping a
framebuffer snapshot in a .bmp file. This patch enables you to choose
another format. In particular it implements the writing of PNG Images
using libpng library. The latter has to be already installed in your
machine, otherwise gem5 will default to the Bitmap format. This
configurable writer has been introduced in the VNC frame dumping mechanism,
which is storing changed frame buffers from the VNC server

Change-Id: Id7e5763c82235f1ce90381c8486b85a7cce734ce
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5181
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

12228:e78be19036e9 28-Oct-2017 Gabe Black <gabeblack@google.com>

base: Fix forcing loopback only binding for listeners.

Despite online documentation, the type used for sin_addr.s_addr is not
actually an unsigned long, it is an in_addr_t. When an unsigned long is a 64
bit value, the endian conversion moves the relevant bits of the 32 bit
in_addr_t to positions which are truncated away. This forces the value to 0
which means to bind to any interface, the opposite of the intended effect.

Change-Id: I53c63dea6bd88144dfef1a9a49b478fab30a8ba2
Reviewed-on: https://gem5-review.googlesource.com/5301
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

12226:36dff288b076 17-Oct-2017 Giacomo Travaglini <giacomo.travaglini@arm.com>

base: Function for mirroring bits in variable length word

This patch introduces a high-speed template function for mirroring the
bits (MSB=>LSB) in a variable length word. The function is achieving
high performances since it is using a look-up table.

Change-Id: Ib0d0480e68d902f25655f74d243de305103eff75
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5261
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

12225:314b451761dc 16-Oct-2017 Giacomo Travaglini <giacomo.travaglini@arm.com>

base: Defining make_unique for C++11

std::make_unique is not available for C++11 compilers, and it has been
introduced only in C++14. Since gem5 is not officially supporting the
latter at the moment, this patch allows to use it in gem5 if including
base/compiler.hh. If compiled under C++14, std::make_unique will be
used instead.

Change-Id: Ibf1897fad0a1eb1cb0c683cc25170feaa6841997
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5201
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

12164:6a4fd7d604b1 31-Jul-2017 Gabe Black <gabeblack@google.com>

base: Give more information when setting up asynchronous IO fails.

When asynchronous IO fails, gem5 currently just says it failed and quits, and
doesn't give any more information about which step failed, or what
specifically about it failed.

This change adds two helpers which will attempt the fcntl, check for error
conditions, and in the event of a failure, include a message describing the
error code and what the arguments to fcntl were.

Change-Id: I316478172ab2aefd3788279dbc12744791385cd5
Reviewed-on: https://gem5-review.googlesource.com/4320
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

12125:0066d9926c1a 27-Jun-2017 Sean Wilson <spwilson2@wisc.edu>

sim, gdb: Refactor some Event subclasses into lambdas

Change-Id: If3e4329204f27eda96b50ec6ac279ebc6ef23d99
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/3921
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

12122:20512f6810d7 28-Jun-2017 Jose Marinho <jose.marinho@arm.com>

cpu, sim: Add param to force CPUs to wait for GDB

By setting the BaseCPU parameter wait_for_dbg_connection, the GDB
server blocks during initialisation waiting for the remote debugger to
connect before starting the simulated CPU.

Change-Id: I4d62c68ce9adf69344bccbb44f66e30b33715a1c
[ Update info message to include remote GDB port, rename param. ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3963
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>

12065:e3e51756dfef 13-Mar-2017 Nikos Nikoleris <nikos.nikoleris@arm.com>

ruby: Add support for address ranges in the directory

Previously the directory covered a flat address range that always
started from address 0. This change adds a vector of address ranges
with interleaving and hashing that each directory keeps track of and
the necessary flexibility to support systems with non continuous
memory ranges.

Change-Id: I6ea1c629bdf4c5137b7d9c89dbaf6c826adfd977
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2903
Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>


/gem5/configs/ruby/GPU_RfO.py
/gem5/configs/ruby/Garnet_standalone.py
/gem5/configs/ruby/MESI_Three_Level.py
/gem5/configs/ruby/MESI_Two_Level.py
/gem5/configs/ruby/MI_example.py
/gem5/configs/ruby/MOESI_AMD_Base.py
/gem5/configs/ruby/MOESI_CMP_directory.py
/gem5/configs/ruby/MOESI_CMP_token.py
/gem5/configs/ruby/MOESI_hammer.py
/gem5/configs/ruby/Ruby.py
addr_range.hh
/gem5/src/mem/protocol/GPU_RfO-TCCdir.sm
/gem5/src/mem/protocol/GPU_VIPER-TCC.sm
/gem5/src/mem/protocol/GPU_VIPER_Region-TCC.sm
/gem5/src/mem/protocol/Garnet_standalone-cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-L2cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-dma.sm
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dma.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-CorePair.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-L3cache.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-Region-CorePair.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-Region-dir.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-RegionBuffer.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-RegionDir.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-probeFilter.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dma.sm
/gem5/src/mem/protocol/MOESI_hammer-cache.sm
/gem5/src/mem/protocol/MOESI_hammer-dma.sm
/gem5/src/mem/protocol/RubySlicc_ComponentMapping.sm
/gem5/src/mem/ruby/network/Network.cc
/gem5/src/mem/ruby/network/Network.hh
/gem5/src/mem/ruby/slicc_interface/AbstractController.cc
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/slicc_interface/Controller.py
/gem5/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
/gem5/src/mem/ruby/structures/DirectoryMemory.cc
/gem5/src/mem/ruby/structures/DirectoryMemory.hh
/gem5/src/mem/ruby/structures/DirectoryMemory.py
/gem5/src/mem/slicc/symbols/Type.py
12060:11f26801e83c 01-Jun-2017 Gabe Black <gabeblack@google.com>

base: misc: Include cstdlib in base/misc.hh.

Some of the macros, notably panic, uses exit(). Callers shouldn't have to
know that or have coincidentally included cstdlib, the provider of exit,
themselves.

Change-Id: I634602ed1795dcc8897b4bddb1167c96763acc18
Reviewed-on: https://gem5-review.googlesource.com/3601
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

12032:d218c2fe9440 18-May-2017 Andreas Sandberg <andreas.sandberg@arm.com>

base, sim, arch: Fix clang 5.0 warnings

Compiling gem5 with recent version of clang (4 and 5) triggers
warnings that are treated as errors:

* Global templatized static functions result in a warning if they
are not used. These should either be declared as static inline or
without the static identifier to avoid the warning.

* Some templatized classes contain static variables. The
instantiated versions of these variables / templates need to be
explicitly declared to avoid a compiler warning.

Change-Id: Ie8261144836e94ebab7ea04ccccb90927672c257
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3420
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

12031:46116545e745 11-May-2017 Gabe Black <gabeblack@google.com>

base: Refactor the GDB code.

The new version modularizes the implementation of the various commands,
gets rid of dynamic allocation of the register cache, fixes some small
style problems, and uses exceptions to simplify error handling internal to
the GDB stub.

Change-Id: Iff3548373ce4adfb99106a810f5713b769df89b2
Reviewed-on: https://gem5-review.googlesource.com/3280
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Boris Shingarov <shingarov@gmail.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

12020:9f290c45493f 10-May-2017 Gabe Black <gabeblack@google.com>

base: Make the VNC server more resilient.

If the client does something bad, don't kill the whole simulation, just
complain, drop the client and keep going.

Change-Id: I824f2d121e2fe03cdf4323a25c192b68e0370acc
Reviewed-on: https://gem5-review.googlesource.com/3200
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

12019:65939e37768a 10-May-2017 Gabe Black <gabeblack@google.com>

misc: Make the remote GDB stub more resilient to bad connections.

Currently, if the remote gdb stub fails to read a byte from an incoming
packet because the connection has been dropped, the read call will return
anyway and the calling code will have no way to know something bad
happened. It might reattempt the read over and over again waiting for some
particular byte, doomed to never make forward progress.

This change modifies the remote GDB code so that if a read or write call
fails, it will instead detach from the debugger and continue. Before this
change, When simulating a port scan, ie connecting to the debugger port
and then immediately dropping the connection using this command:

nc -v -n -z -w 1 127.0.0.1 7000

gem5 would enter the previously described death spiral. After it, gem5
detaches from the bad connection and resumes execution. Subsequently
attaching with gdb was successful.

This code is written in a C centric style, and would benefit from some
refactoring.

Change-Id: Ie3c0bb35b9cfe3671d0f731e3907548bae0d292f
Reviewed-on: https://gem5-review.googlesource.com/3180
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

12010:032f2717dfb7 05-May-2017 Gabe Black <gabeblack@google.com>

base: Teach the socket listeners how to bind to the loopback.

The loopback device will allow access to various services like remote GDB
debugging, connecting to the terminal, etc., without letting external
agents like port scanners connect and disrupting the simulation.

Change-Id: I76dccbf152fa278ae9f342b25f7e345a1329fbe4
Reviewed-on: https://gem5-review.googlesource.com/3080
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

11990:5fad911cc326 29-Jan-2017 Andreas Sandberg <andreas.sandberg@arm.com>

base, sim, dev: Remove SWIG

Remove SWIG guards and SWIG-specific C++ code.

Change-Id: Icaad6720513b6f48153727ef3f70e0dba0df4bee
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2921
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com>

11932:98961d1b51ca 24-Mar-2017 Sascha Bischoff <sascha.bischoff@arm.com>

dev: Align BAR0 size to power of 2 for VirtIO devices

When setting the size of a PCI BAR, the kernel only supports powers of
two (as per the PCI spec). Previously, the size was incorrectly read
by the kernel, and the address ranges assigned to the PCI devices
could overlap, resulting in gem5 crashes. We now round up to the next
power of two.

Kudos to Sergei Trofimov who helped to debug this issue!

Change-Id: I54ca399b62ea07c09d4cd989b17dfa670e841bbe
Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com>
Reviewed-by: Sergei Trofimov <sergei.trofimov@arm.com>
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2580
Reviewed-by: Paul Rosenfeld <prosenfeld@micron.com>

11906:4b99c1bb3b72 01-Mar-2017 Brandon Potter <Brandon.Potter@amd.com>

style: Correct some style issues

This changeset fixes line alignment issues, spacing, spelling,
etc. for files that are used during SE Mode.

Change-Id: Ie61b8d0eb4ebb5af554d72f1297808027833616e
Reviewed-on: https://gem5-review.googlesource.com/2264
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Michael LeBeane <Michael.Lebeane@amd.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Pierre-Yves Péneau <pierre-yves.peneau@lirmm.fr>

11904:870e25baf014 24-Feb-2017 Pierre-Yves Péneau <pierre-yves.peneau@lirmm.fr>

misc: add missing copyright/author information in previous commit

See a06a46f and a854373.

Change-Id: Id66427db22b7d7764c218b9cd78d95db929f4127
Signed-off-by: Pierre-Yves Péneau <pierre-yves.peneau@lirmm.fr>
Reviewed-on: https://gem5-review.googlesource.com/2224
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

11880:8c369af31b6c 27-Feb-2017 Andreas Sandberg <andreas.sandberg@arm.com>

base: Refactor logging to make log level selection cleaner

It's currently possible to change the log level in gem5 by tweaking a
set of global variables. These variables are currently exposed to
Python using SWIG. This mechanism is far from ideal for two reasons:
First, changing the log level requires that the Python world enables
or disables individual levels. Ideally, this should be a single call
where a log level is selected. Second, exporting global variables is
poorly supported by most Python frameworks. SWIG puts variables in
their own namespace and PyBind doesn't seem to support it at all.

This changeset refactors the logging code to create a more abstract
interface. Each log level is associated with an instance of a Logger
class. This class contains common functionality, an enable flag, and a
verbose flag.

Available LogLevels are described by the LogLevel class. Lower log
levels are used for more critical messages (PANIC being level 0) and
higher levels for less critical messages. The highest log level that
is printed is controlled by calling Logger:setLevel().

Change-Id: I31e44299d242d953197a8e62679250c91d6ef776
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

11873:30288728b1c0 23-Feb-2017 Brandon Potter <brandon.potter@amd.com>

base: fix small memory leak in the ELF loader

11848:f438fcbab00e 15-Feb-2017 Pierre-Yves Péneau <pierre-yves.peneau@lirmm.fr>

mem, stats: fix typos in CommMonitor and Stats

Signed-off-by: Pierre-Yves Péneau <pierre-yves.peneau@lirmm.fr>
Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>

Reviewed at http://reviews.gem5.org/r/3802/

11800:54436a1784dc 09-Nov-2016 Brandon Potter <brandon.potter@amd.com>

style: [patch 3/22] reduce include dependencies in some headers

Used cppclean to help identify useless includes and removed them. This
involved erroneously included headers, but also cases where forward
declarations could have been used rather than a full include.


/gem5/src/arch/alpha/process.cc
/gem5/src/arch/alpha/process.hh
/gem5/src/arch/arm/process.cc
/gem5/src/arch/arm/process.hh
/gem5/src/arch/mips/process.cc
/gem5/src/arch/mips/process.hh
/gem5/src/arch/power/interrupts.hh
/gem5/src/arch/power/process.cc
/gem5/src/arch/power/process.hh
/gem5/src/arch/power/remote_gdb.cc
/gem5/src/arch/riscv/interrupts.hh
/gem5/src/arch/riscv/process.cc
/gem5/src/arch/riscv/process.hh
/gem5/src/arch/sparc/process.cc
/gem5/src/arch/sparc/process.hh
/gem5/src/arch/x86/isa_traits.hh
/gem5/src/arch/x86/pagetable.hh
/gem5/src/arch/x86/process.cc
/gem5/src/arch/x86/pseudo_inst.cc
/gem5/src/arch/x86/system.cc
/gem5/src/arch/x86/system.hh
/gem5/src/arch/x86/tlb.cc
/gem5/src/arch/x86/tlb.hh
/gem5/src/arch/x86/utility.cc
/gem5/src/arch/x86/utility.hh
bitfield.hh
bitunion.hh
time.cc
vnc/vncinput.cc
/gem5/src/cpu/minor/buffers.hh
/gem5/src/cpu/testers/directedtest/InvalidateGenerator.cc
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.cc
/gem5/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
/gem5/src/cpu/testers/memtest/memtest.cc
/gem5/src/cpu/testers/rubytest/Check.cc
/gem5/src/cpu/testers/rubytest/CheckTable.cc
/gem5/src/cpu/testers/rubytest/RubyTester.cc
/gem5/src/dev/arm/flash_device.cc
/gem5/src/dev/mc146818.hh
/gem5/src/dev/net/dist_iface.hh
/gem5/src/dev/net/etherbus.cc
/gem5/src/dev/net/etherswitch.cc
/gem5/src/gpu-compute/vector_register_file.hh
/gem5/src/kern/linux/linux.cc
/gem5/src/kern/linux/linux.hh
/gem5/src/mem/cache/prefetch/stride.cc
/gem5/src/mem/external_master.cc
/gem5/src/mem/external_slave.cc
/gem5/src/mem/mem_checker.hh
/gem5/src/mem/multi_level_page_table.hh
/gem5/src/mem/multi_level_page_table_impl.hh
/gem5/src/mem/page_table.cc
/gem5/src/mem/page_table.hh
/gem5/src/mem/ruby/network/MessageBuffer.hh
/gem5/src/mem/ruby/structures/AbstractReplacementPolicy.cc
/gem5/src/mem/se_translating_port_proxy.hh
/gem5/src/mem/simple_mem.cc
/gem5/src/python/swig/pyevent.cc
/gem5/src/sim/SConscript
/gem5/src/sim/arguments.cc
/gem5/src/sim/arguments.hh
/gem5/src/sim/byteswap.hh
/gem5/src/sim/clock_domain.cc
/gem5/src/sim/clocked_object.hh
/gem5/src/sim/cxx_config.hh
/gem5/src/sim/cxx_config_ini.cc
/gem5/src/sim/cxx_config_ini.hh
/gem5/src/sim/cxx_manager.cc
/gem5/src/sim/drain.hh
/gem5/src/sim/dvfs_handler.cc
/gem5/src/sim/dvfs_handler.hh
/gem5/src/sim/eventq.hh
/gem5/src/sim/fd_entry.hh
/gem5/src/sim/init_signals.cc
/gem5/src/sim/insttracer.hh
/gem5/src/sim/microcode_rom.cc
/gem5/src/sim/microcode_rom.hh
/gem5/src/sim/power/mathexpr_powermodel.hh
/gem5/src/sim/power/power_model.cc
/gem5/src/sim/power/power_model.hh
/gem5/src/sim/power/thermal_domain.cc
/gem5/src/sim/power/thermal_domain.hh
/gem5/src/sim/power/thermal_entity.hh
/gem5/src/sim/power/thermal_model.hh
/gem5/src/sim/probe/probe.cc
/gem5/src/sim/probe/probe.hh
/gem5/src/sim/process.cc
/gem5/src/sim/process.hh
/gem5/src/sim/process_impl.hh
/gem5/src/sim/root.cc
/gem5/src/sim/serialize.hh
/gem5/src/sim/sim_exit.hh
/gem5/src/sim/sim_object.cc
/gem5/src/sim/sim_object.hh
/gem5/src/sim/simulate.hh
/gem5/src/sim/stat_register.cc
/gem5/src/sim/stat_register.hh
/gem5/src/sim/sub_system.hh
/gem5/src/sim/syscall_emul.cc
/gem5/src/sim/syscall_emul.hh
/gem5/src/sim/syscall_return.hh
/gem5/src/sim/system.hh
/gem5/src/sim/ticked_object.cc
/gem5/src/sim/ticked_object.hh
/gem5/src/sim/voltage_domain.cc
/gem5/src/sim/vptr.hh
11793:ef606668d247 09-Nov-2016 Brandon Potter <brandon.potter@amd.com>

style: [patch 1/22] use /r/3648/ to reorganize includes


/gem5/src/arch/alpha/faults.cc
/gem5/src/arch/alpha/freebsd/system.cc
/gem5/src/arch/alpha/idle_event.cc
/gem5/src/arch/alpha/ipr.cc
/gem5/src/arch/alpha/isa.cc
/gem5/src/arch/alpha/kernel_stats.cc
/gem5/src/arch/alpha/linux/process.cc
/gem5/src/arch/alpha/linux/system.cc
/gem5/src/arch/alpha/pagetable.cc
/gem5/src/arch/alpha/process.cc
/gem5/src/arch/alpha/remote_gdb.cc
/gem5/src/arch/alpha/stacktrace.cc
/gem5/src/arch/alpha/system.cc
/gem5/src/arch/alpha/utility.cc
/gem5/src/arch/alpha/vtophys.cc
/gem5/src/arch/arm/faults.cc
/gem5/src/arch/arm/insts/macromem.cc
/gem5/src/arch/arm/insts/mem.cc
/gem5/src/arch/arm/insts/mem64.cc
/gem5/src/arch/arm/insts/misc.cc
/gem5/src/arch/arm/insts/pseudo.cc
/gem5/src/arch/arm/insts/static_inst.cc
/gem5/src/arch/arm/interrupts.cc
/gem5/src/arch/arm/isa.cc
/gem5/src/arch/arm/kvm/base_cpu.cc
/gem5/src/arch/arm/linux/process.cc
/gem5/src/arch/arm/linux/system.cc
/gem5/src/arch/arm/miscregs.cc
/gem5/src/arch/arm/nativetrace.cc
/gem5/src/arch/arm/process.cc
/gem5/src/arch/arm/remote_gdb.cc
/gem5/src/arch/arm/stacktrace.cc
/gem5/src/arch/arm/stage2_lookup.cc
/gem5/src/arch/arm/system.cc
/gem5/src/arch/arm/tlb.cc
/gem5/src/arch/arm/utility.cc
/gem5/src/arch/arm/vtophys.cc
/gem5/src/arch/generic/decode_cache.cc
/gem5/src/arch/generic/mmapped_ipr.cc
/gem5/src/arch/generic/pseudo_inst.cc
/gem5/src/arch/mips/bare_iron/system.cc
/gem5/src/arch/mips/dsp.cc
/gem5/src/arch/mips/faults.cc
/gem5/src/arch/mips/idle_event.cc
/gem5/src/arch/mips/interrupts.cc
/gem5/src/arch/mips/isa.cc
/gem5/src/arch/mips/linux/process.cc
/gem5/src/arch/mips/linux/system.cc
/gem5/src/arch/mips/pagetable.cc
/gem5/src/arch/mips/process.cc
/gem5/src/arch/mips/remote_gdb.cc
/gem5/src/arch/mips/stacktrace.cc
/gem5/src/arch/mips/system.cc
/gem5/src/arch/mips/tlb.cc
/gem5/src/arch/mips/utility.cc
/gem5/src/arch/mips/vtophys.cc
/gem5/src/arch/power/insts/branch.cc
/gem5/src/arch/power/insts/mem.cc
/gem5/src/arch/power/insts/static_inst.cc
/gem5/src/arch/power/isa.cc
/gem5/src/arch/power/linux/process.cc
/gem5/src/arch/power/pagetable.cc
/gem5/src/arch/power/process.cc
/gem5/src/arch/power/stacktrace.cc
/gem5/src/arch/power/tlb.cc
/gem5/src/arch/power/utility.cc
/gem5/src/arch/sparc/faults.cc
/gem5/src/arch/sparc/isa.cc
/gem5/src/arch/sparc/linux/process.cc
/gem5/src/arch/sparc/nativetrace.cc
/gem5/src/arch/sparc/pagetable.cc
/gem5/src/arch/sparc/process.cc
/gem5/src/arch/sparc/remote_gdb.cc
/gem5/src/arch/sparc/solaris/process.cc
/gem5/src/arch/sparc/system.cc
/gem5/src/arch/sparc/tlb.cc
/gem5/src/arch/sparc/ua2005.cc
/gem5/src/arch/sparc/utility.cc
/gem5/src/arch/sparc/vtophys.cc
/gem5/src/arch/x86/bios/acpi.cc
/gem5/src/arch/x86/bios/e820.cc
/gem5/src/arch/x86/bios/intelmp.cc
/gem5/src/arch/x86/bios/smbios.cc
/gem5/src/arch/x86/cpuid.cc
/gem5/src/arch/x86/decoder.cc
/gem5/src/arch/x86/emulenv.cc
/gem5/src/arch/x86/faults.cc
/gem5/src/arch/x86/insts/badmicroop.cc
/gem5/src/arch/x86/insts/microfpop.cc
/gem5/src/arch/x86/insts/microldstop.cc
/gem5/src/arch/x86/insts/micromediaop.cc
/gem5/src/arch/x86/insts/microop.cc
/gem5/src/arch/x86/insts/microregop.cc
/gem5/src/arch/x86/insts/static_inst.cc
/gem5/src/arch/x86/interrupts.cc
/gem5/src/arch/x86/isa.cc
/gem5/src/arch/x86/linux/process.cc
/gem5/src/arch/x86/linux/system.cc
/gem5/src/arch/x86/nativetrace.cc
/gem5/src/arch/x86/pagetable.cc
/gem5/src/arch/x86/pagetable_walker.cc
/gem5/src/arch/x86/process.cc
/gem5/src/arch/x86/pseudo_inst.cc
/gem5/src/arch/x86/remote_gdb.cc
/gem5/src/arch/x86/stacktrace.cc
/gem5/src/arch/x86/system.cc
/gem5/src/arch/x86/tlb.cc
/gem5/src/arch/x86/types.cc
/gem5/src/arch/x86/utility.cc
/gem5/src/arch/x86/vtophys.cc
atomicio.cc
bigint.cc
cp_annotate.cc
cprintf.cc
debug.cc
hostinfo.cc
inet.cc
inifile.cc
loader/aout_object.cc
loader/dtb_object.cc
loader/ecoff_object.cc
loader/hex_file.cc
loader/object_file.cc
loader/raw_object.cc
loader/symtab.cc
match.cc
misc.cc
output.cc
pollevent.cc
random.cc
remote_gdb.cc
socket.cc
statistics.cc
stats/text.cc
str.cc
time.cc
trace.cc
vnc/vncinput.cc
vnc/vncserver.cc
/gem5/src/cpu/activity.cc
/gem5/src/cpu/base.cc
/gem5/src/cpu/checker/cpu.cc
/gem5/src/cpu/dummy_checker.cc
/gem5/src/cpu/exetrace.cc
/gem5/src/cpu/func_unit.cc
/gem5/src/cpu/inteltrace.cc
/gem5/src/cpu/intr_control.cc
/gem5/src/cpu/kvm/base.cc
/gem5/src/cpu/kvm/perfevent.cc
/gem5/src/cpu/kvm/timer.cc
/gem5/src/cpu/kvm/vm.cc
/gem5/src/cpu/kvm/x86_cpu.cc
/gem5/src/cpu/minor/activity.cc
/gem5/src/cpu/minor/cpu.cc
/gem5/src/cpu/minor/decode.cc
/gem5/src/cpu/minor/dyn_inst.cc
/gem5/src/cpu/minor/execute.cc
/gem5/src/cpu/minor/fetch1.cc
/gem5/src/cpu/minor/fetch2.cc
/gem5/src/cpu/minor/func_unit.cc
/gem5/src/cpu/minor/lsq.cc
/gem5/src/cpu/minor/pipeline.cc
/gem5/src/cpu/minor/scoreboard.cc
/gem5/src/cpu/nativetrace.cc
/gem5/src/cpu/o3/base_dyn_inst.cc
/gem5/src/cpu/o3/checker.cc
/gem5/src/cpu/o3/cpu.cc
/gem5/src/cpu/o3/deriv.cc
/gem5/src/cpu/o3/free_list.cc
/gem5/src/cpu/o3/fu_pool.cc
/gem5/src/cpu/o3/probe/simple_trace.cc
/gem5/src/cpu/o3/regfile.cc
/gem5/src/cpu/o3/rename_map.cc
/gem5/src/cpu/o3/scoreboard.cc
/gem5/src/cpu/o3/store_set.cc
/gem5/src/cpu/o3/thread_context.cc
/gem5/src/cpu/pc_event.cc
/gem5/src/cpu/pred/2bit_local.cc
/gem5/src/cpu/pred/bi_mode.cc
/gem5/src/cpu/pred/btb.cc
/gem5/src/cpu/pred/tournament.cc
/gem5/src/cpu/profile.cc
/gem5/src/cpu/quiesce_event.cc
/gem5/src/cpu/simple/atomic.cc
/gem5/src/cpu/simple/base.cc
/gem5/src/cpu/simple/probes/simpoint.cc
/gem5/src/cpu/simple/timing.cc
/gem5/src/cpu/simple_thread.cc
/gem5/src/cpu/static_inst.cc
/gem5/src/cpu/testers/directedtest/DirectedGenerator.cc
/gem5/src/cpu/testers/directedtest/InvalidateGenerator.cc
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.cc
/gem5/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
/gem5/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc
/gem5/src/cpu/testers/memtest/memtest.cc
/gem5/src/cpu/testers/rubytest/Check.cc
/gem5/src/cpu/testers/rubytest/CheckTable.cc
/gem5/src/cpu/testers/rubytest/RubyTester.cc
/gem5/src/cpu/thread_context.cc
/gem5/src/cpu/thread_state.cc
/gem5/src/cpu/timing_expr.cc
/gem5/src/dev/alpha/backdoor.cc
/gem5/src/dev/alpha/tsunami.cc
/gem5/src/dev/alpha/tsunami_cchip.cc
/gem5/src/dev/alpha/tsunami_io.cc
/gem5/src/dev/arm/a9scu.cc
/gem5/src/dev/arm/amba_device.cc
/gem5/src/dev/arm/amba_fake.cc
/gem5/src/dev/arm/energy_ctrl.cc
/gem5/src/dev/arm/gic_pl390.cc
/gem5/src/dev/arm/hdlcd.cc
/gem5/src/dev/arm/kmi.cc
/gem5/src/dev/arm/pl011.cc
/gem5/src/dev/arm/pl111.cc
/gem5/src/dev/arm/realview.cc
/gem5/src/dev/arm/rtc_pl031.cc
/gem5/src/dev/arm/timer_cpulocal.cc
/gem5/src/dev/arm/timer_sp804.cc
/gem5/src/dev/arm/vgic.cc
/gem5/src/dev/baddev.cc
/gem5/src/dev/intel_8254_timer.cc
/gem5/src/dev/io_device.cc
/gem5/src/dev/isa_fake.cc
/gem5/src/dev/mc146818.cc
/gem5/src/dev/mips/malta.cc
/gem5/src/dev/mips/malta_cchip.cc
/gem5/src/dev/mips/malta_io.cc
/gem5/src/dev/pci/device.cc
/gem5/src/dev/pci/host.cc
/gem5/src/dev/platform.cc
/gem5/src/dev/ps2.cc
/gem5/src/dev/ps2.hh
/gem5/src/dev/sparc/dtod.cc
/gem5/src/dev/sparc/iob.cc
/gem5/src/dev/sparc/mm_disk.cc
/gem5/src/dev/sparc/t1000.cc
/gem5/src/dev/uart.cc
/gem5/src/dev/uart8250.cc
/gem5/src/dev/virtio/base.cc
/gem5/src/dev/virtio/block.cc
/gem5/src/dev/virtio/console.cc
/gem5/src/dev/virtio/fs9p.cc
/gem5/src/dev/virtio/pci.cc
/gem5/src/dev/x86/cmos.cc
/gem5/src/dev/x86/i8042.cc
/gem5/src/dev/x86/i82094aa.cc
/gem5/src/dev/x86/i8237.cc
/gem5/src/dev/x86/i8254.cc
/gem5/src/dev/x86/i8259.cc
/gem5/src/dev/x86/pc.cc
/gem5/src/dev/x86/south_bridge.cc
/gem5/src/dev/x86/speaker.cc
/gem5/src/kern/linux/linux.cc
/gem5/src/kern/linux/printk.cc
/gem5/src/kern/operatingsystem.cc
/gem5/src/kern/system_events.cc
/gem5/src/mem/abstract_mem.cc
/gem5/src/mem/bridge.cc
/gem5/src/mem/cache/prefetch/base.cc
/gem5/src/mem/cache/prefetch/queued.cc
/gem5/src/mem/cache/prefetch/stride.cc
/gem5/src/mem/coherent_xbar.cc
/gem5/src/mem/comm_monitor.cc
/gem5/src/mem/dram_ctrl.cc
/gem5/src/mem/drampower.cc
/gem5/src/mem/dramsim2.cc
/gem5/src/mem/dramsim2_wrapper.cc
/gem5/src/mem/external_master.cc
/gem5/src/mem/external_slave.cc
/gem5/src/mem/fs_translating_port_proxy.cc
/gem5/src/mem/hmc_controller.cc
/gem5/src/mem/mem_checker.cc
/gem5/src/mem/mem_checker_monitor.cc
/gem5/src/mem/noncoherent_xbar.cc
/gem5/src/mem/packet.cc
/gem5/src/mem/packet_queue.cc
/gem5/src/mem/page_table.cc
/gem5/src/mem/physical.cc
/gem5/src/mem/port.cc
/gem5/src/mem/port_proxy.cc
/gem5/src/mem/probes/base.cc
/gem5/src/mem/ruby/common/Histogram.cc
/gem5/src/mem/ruby/common/NetDest.cc
/gem5/src/mem/ruby/common/SubBlock.cc
/gem5/src/mem/ruby/filters/BlockBloomFilter.cc
/gem5/src/mem/ruby/filters/BulkBloomFilter.cc
/gem5/src/mem/ruby/filters/H3BloomFilter.cc
/gem5/src/mem/ruby/filters/LSB_CountingBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiGrainBloomFilter.cc
/gem5/src/mem/ruby/filters/NonCountingBloomFilter.cc
/gem5/src/mem/ruby/network/MessageBuffer.cc
/gem5/src/mem/ruby/network/Network.cc
/gem5/src/mem/ruby/network/Topology.cc
/gem5/src/mem/ruby/network/simple/PerfectSwitch.cc
/gem5/src/mem/ruby/network/simple/PerfectSwitch.hh
/gem5/src/mem/ruby/network/simple/SimpleNetwork.cc
/gem5/src/mem/ruby/network/simple/Switch.cc
/gem5/src/mem/ruby/network/simple/Throttle.cc
/gem5/src/mem/ruby/profiler/AccessTraceForAddress.cc
/gem5/src/mem/ruby/profiler/AddressProfiler.cc
/gem5/src/mem/ruby/profiler/StoreTrace.cc
/gem5/src/mem/ruby/slicc_interface/AbstractController.cc
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/slicc_interface/RubyRequest.cc
/gem5/src/mem/ruby/structures/BankedArray.cc
/gem5/src/mem/ruby/structures/CacheMemory.cc
/gem5/src/mem/ruby/structures/DirectoryMemory.cc
/gem5/src/mem/ruby/structures/LRUPolicy.cc
/gem5/src/mem/ruby/structures/Prefetcher.cc
/gem5/src/mem/ruby/structures/PseudoLRUPolicy.cc
/gem5/src/mem/ruby/structures/WireBuffer.cc
/gem5/src/mem/ruby/system/CacheRecorder.cc
/gem5/src/mem/ruby/system/DMASequencer.cc
/gem5/src/mem/ruby/system/RubyPort.cc
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/se_translating_port_proxy.cc
/gem5/src/mem/serial_link.cc
/gem5/src/mem/simple_mem.cc
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/mem/snoop_filter.cc
/gem5/src/mem/tport.cc
/gem5/src/mem/xbar.cc
/gem5/src/proto/protoio.cc
/gem5/src/python/swig/pyevent.cc
/gem5/src/python/swig/pyevent.hh
/gem5/src/python/swig/pyobject.cc
/gem5/src/sim/arguments.cc
/gem5/src/sim/backtrace_glibc.cc
/gem5/src/sim/clock_domain.cc
/gem5/src/sim/core.cc
/gem5/src/sim/cxx_manager.cc
/gem5/src/sim/debug.cc
/gem5/src/sim/dvfs_handler.cc
/gem5/src/sim/faults.cc
/gem5/src/sim/init.cc
/gem5/src/sim/probe/probe.cc
/gem5/src/sim/process.cc
/gem5/src/sim/pseudo_inst.cc
/gem5/src/sim/py_interact.cc
/gem5/src/sim/root.cc
/gem5/src/sim/serialize.cc
/gem5/src/sim/sim_events.cc
/gem5/src/sim/sim_object.cc
/gem5/src/sim/simulate.cc
/gem5/src/sim/stat_control.cc
/gem5/src/sim/stat_control.hh
/gem5/src/sim/sub_system.cc
/gem5/src/sim/syscall_emul.cc
/gem5/src/sim/system.cc
/gem5/src/sim/voltage_domain.cc
/gem5/src/unittest/circlebuf.cc
/gem5/src/unittest/unittest.cc
11761:285cab6580a7 09-Nov-2016 Brandon Potter <brandon.potter@amd.com>

base: remove header file to prevent a macro name collision

11723:0596db108c53 30-Nov-2016 Alec Roelke <ar4jc@virginia.edu>

arch: [Patch 1/5] Added RISC-V base instruction set RV64I

First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
The multiply, floating point, and atomic memory instructions will be added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world\!" example for RISC-V is added to test-progs.

Patch 2 will implement the multiply extension, RV64M; patch 3 will implement
the floating point (single- and double-precision) extensions, RV64FD;
patch 4 will implement the atomic memory instructions, RV64A, and patch 5
will add support for timing, minor, and detailed CPU models that is missing
from the first four patches (such as handling locked memory).

[Removed several unused parameters and imports from RiscvInterrupts.py,
RiscvISA.py, and RiscvSystem.py.]
[Fixed copyright information in RISC-V files copied from elsewhere that had
ARM licenses attached.]
[Reorganized instruction definitions in decoder.isa so that they are sorted
by opcode in preparation for the addition of ISA extensions M, A, F, D.]
[Fixed formatting of several files, removed some variables and
instructions that were missed when moving them to other patches, fixed
RISC-V Foundation copyright attribution, and fixed history of files
copied from other architectures using hg copy.]
[Fixed indentation of switch cases in isa.cc.]
[Reorganized syscall descriptions in linux/process.cc to remove large
number of repeated unimplemented system calls and added implmementations
to functions that have received them since it process.cc was first
created.]
[Fixed spacing for some copyright attributions.]
[Replaced the rest of the file copies using hg copy.]
[Fixed style check errors and corrected unaligned memory accesses.]
[Fix some minor formatting mistakes.]
Signed-off by: Alec Roelke

Signed-off by: Jason Lowe-Power <jason@lowepower.com>


/gem5/build_opts/RISCV
/gem5/ext/libelf/elf_common.h
/gem5/src/arch/riscv/RiscvISA.py
/gem5/src/arch/riscv/RiscvInterrupts.py
/gem5/src/arch/riscv/RiscvSystem.py
/gem5/src/arch/riscv/RiscvTLB.py
/gem5/src/arch/riscv/SConscript
/gem5/src/arch/riscv/SConsopts
/gem5/src/arch/riscv/decoder.cc
/gem5/src/arch/riscv/decoder.hh
/gem5/src/arch/riscv/faults.cc
/gem5/src/arch/riscv/faults.hh
/gem5/src/arch/riscv/idle_event.cc
/gem5/src/arch/riscv/idle_event.hh
/gem5/src/arch/riscv/interrupts.cc
/gem5/src/arch/riscv/interrupts.hh
/gem5/src/arch/riscv/isa.cc
/gem5/src/arch/riscv/isa.hh
/gem5/src/arch/riscv/isa/base.isa
/gem5/src/arch/riscv/isa/bitfields.isa
/gem5/src/arch/riscv/isa/decoder.isa
/gem5/src/arch/riscv/isa/formats/basic.isa
/gem5/src/arch/riscv/isa/formats/formats.isa
/gem5/src/arch/riscv/isa/formats/mem.isa
/gem5/src/arch/riscv/isa/formats/type.isa
/gem5/src/arch/riscv/isa/formats/unknown.isa
/gem5/src/arch/riscv/isa/includes.isa
/gem5/src/arch/riscv/isa/main.isa
/gem5/src/arch/riscv/isa/operands.isa
/gem5/src/arch/riscv/isa_traits.hh
/gem5/src/arch/riscv/kernel_stats.hh
/gem5/src/arch/riscv/linux/linux.cc
/gem5/src/arch/riscv/linux/linux.hh
/gem5/src/arch/riscv/linux/process.cc
/gem5/src/arch/riscv/linux/process.hh
/gem5/src/arch/riscv/locked_mem.hh
/gem5/src/arch/riscv/microcode_rom.hh
/gem5/src/arch/riscv/mmapped_ipr.hh
/gem5/src/arch/riscv/pagetable.cc
/gem5/src/arch/riscv/pagetable.hh
/gem5/src/arch/riscv/pra_constants.hh
/gem5/src/arch/riscv/process.cc
/gem5/src/arch/riscv/process.hh
/gem5/src/arch/riscv/pseudo_inst.hh
/gem5/src/arch/riscv/registers.hh
/gem5/src/arch/riscv/remote_gdb.cc
/gem5/src/arch/riscv/remote_gdb.hh
/gem5/src/arch/riscv/stacktrace.cc
/gem5/src/arch/riscv/stacktrace.hh
/gem5/src/arch/riscv/system.cc
/gem5/src/arch/riscv/system.hh
/gem5/src/arch/riscv/tlb.cc
/gem5/src/arch/riscv/tlb.hh
/gem5/src/arch/riscv/types.hh
/gem5/src/arch/riscv/utility.hh
/gem5/src/arch/riscv/vtophys.hh
loader/elf_object.cc
loader/object_file.hh
/gem5/src/cpu/BaseCPU.py
/gem5/src/sim/process.cc
11681:074694750c5d 14-Oct-2016 Jason Lowe-Power <powerjg@cs.wisc.edu>

stats: Add more information to uninitialized error

ClockedObject was changed to require its regStats() to be called from every
child class. If you forget to do this, the error was indecipherable. This
patch makes the error more clear.

11666:10d59d546ea2 06-Oct-2016 Tushar Krishna <tushar@ece.gatech.edu>

ruby: garnet2.0
Revamped version of garnet with more optimized single-cycle routers,
more configurability, and cleaner code.


/gem5/configs/network/Network.py
/gem5/configs/topologies/Crossbar.py
/gem5/configs/topologies/MeshDirCorners_XY.py
/gem5/configs/topologies/Mesh_XY.py
/gem5/configs/topologies/Mesh_westfirst.py
/gem5/configs/topologies/Pt2Pt.py
statistics.cc
/gem5/src/mem/ruby/network/BasicRouter.py
/gem5/src/mem/ruby/network/garnet2.0/CommonTypes.hh
/gem5/src/mem/ruby/network/garnet2.0/Credit.cc
/gem5/src/mem/ruby/network/garnet2.0/Credit.hh
/gem5/src/mem/ruby/network/garnet2.0/CreditLink.hh
/gem5/src/mem/ruby/network/garnet2.0/CrossbarSwitch.cc
/gem5/src/mem/ruby/network/garnet2.0/CrossbarSwitch.hh
/gem5/src/mem/ruby/network/garnet2.0/GarnetLink.cc
/gem5/src/mem/ruby/network/garnet2.0/GarnetLink.hh
/gem5/src/mem/ruby/network/garnet2.0/GarnetLink.py
/gem5/src/mem/ruby/network/garnet2.0/GarnetNetwork.cc
/gem5/src/mem/ruby/network/garnet2.0/GarnetNetwork.hh
/gem5/src/mem/ruby/network/garnet2.0/GarnetNetwork.py
/gem5/src/mem/ruby/network/garnet2.0/InputUnit.cc
/gem5/src/mem/ruby/network/garnet2.0/InputUnit.hh
/gem5/src/mem/ruby/network/garnet2.0/NetworkInterface.cc
/gem5/src/mem/ruby/network/garnet2.0/NetworkInterface.hh
/gem5/src/mem/ruby/network/garnet2.0/NetworkLink.cc
/gem5/src/mem/ruby/network/garnet2.0/NetworkLink.hh
/gem5/src/mem/ruby/network/garnet2.0/OutVcState.cc
/gem5/src/mem/ruby/network/garnet2.0/OutVcState.hh
/gem5/src/mem/ruby/network/garnet2.0/OutputUnit.cc
/gem5/src/mem/ruby/network/garnet2.0/OutputUnit.hh
/gem5/src/mem/ruby/network/garnet2.0/README.txt
/gem5/src/mem/ruby/network/garnet2.0/Router.cc
/gem5/src/mem/ruby/network/garnet2.0/Router.hh
/gem5/src/mem/ruby/network/garnet2.0/RoutingUnit.cc
/gem5/src/mem/ruby/network/garnet2.0/RoutingUnit.hh
/gem5/src/mem/ruby/network/garnet2.0/SConscript
/gem5/src/mem/ruby/network/garnet2.0/SwitchAllocator.cc
/gem5/src/mem/ruby/network/garnet2.0/SwitchAllocator.hh
/gem5/src/mem/ruby/network/garnet2.0/VirtualChannel.cc
/gem5/src/mem/ruby/network/garnet2.0/VirtualChannel.hh
/gem5/src/mem/ruby/network/garnet2.0/flit.cc
/gem5/src/mem/ruby/network/garnet2.0/flit.hh
/gem5/src/mem/ruby/network/garnet2.0/flitBuffer.cc
/gem5/src/mem/ruby/network/garnet2.0/flitBuffer.hh
11658:370d69b00fcf 04-Oct-2016 Alexandru Dutu <alexandru.dutu@amd.com>

misc: Adds a warning in case gdb is attached multiple times
Instead of scheduling another event, this patch adds a warning in case gdb
is attached multiple times and the first attachement event has not been
processed yet.

11655:6c21ab852ed2 04-Oct-2016 Andreas Sandberg <andreas.sandberg@arm.com>

sim: Add a checkpoint function to test for entries

When loading a checkpoint, it's sometimes desirable to be able to test
whether an entry within a secion exists. This is currently done
automatically in the UNSERIALIZE_OPT_SCALAR macro, but it isn't
possible to do for arrays, containers, or enums. Instead of adding
even more macros, add a helper function (CheckpointIn::entryExists())
that tests for the presence of an entry.

Change-Id: I4b4646b03276b889fd3916efefff3bd552317dbc
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

11565:9b9116df5e88 21-Jul-2016 David Guillen Fandos <david.guillen@arm.com>

base: Add total() to Vector2D stat

This patch adds a total() function to the Vector2D
stat type. Similar to other stats such as Scalar or
Vector it is useful to be able to read the total for
a given stat.

11561:704b0198f747 11-Jul-2016 Andreas Sandberg <andreas.sandberg@arm.com>

base: Fix inverted check in ELF .text size warning

11559:3210a0b99c88 11-Jul-2016 Andreas Sandberg <andreas.sandberg@arm.com>

base: Convert ELF .text size check assertion to a warning

The ELF loader currently has an assertion that checks if the size of a
loaded .text secion is non-zero. This is useful in the general case as
an empty text section normally indicates that there is something
strange with the ELF file. However, asserting isn't very useful. This
changeset converts the assert into a warning that tells the user that
something strange is happening.

Change-Id: I313e17847b50a0eca00f6bd00a54c610d626c0f0
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>

11537:93e2bd032c3b 20-Jun-2016 Andreas Sandberg <andreas.sandberg@arm.com>

base: Fix multiple names to one address bug in SymbolTable

The SymbolTable class currently assumes that at most one symbol can
point to a given address. If multiple symbols point to the same
address, only the first one gets added to the internal symbol table
since there is already a match in the address table.

This changeset converts the address table from a map into a multimap
to be able to handle cases where an address maps to multiple
symbols. Additionally, the insert method is changed to not fail if
there is a match in the address table.

Change-Id: I6b4f1d5560c21e49a4af33220efb2a8302961768
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com>

11460:b49763e919c8 27-Apr-2016 Andreas Sandberg <andreas.sandberg@arm.com>

dev: Fix incorrect terminal backlog handling

The Terminal device currently uses the peek functionality in gem5's
circular buffer implementation to send existing buffered content on
the terminal when a new client attaches. This functionallity is
however not implemented correctly and re-sends the same block multiple
time.

Add the required functionality to peek with an offset into the
circular buffer and change the Terminal::accept() implementation to
send the buffered contents.

Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

11392:5967db4cff04 17-Mar-2016 Brandon Potter <brandon.potter@amd.com>

base: add symbol support for dynamic libraries

Libraries are loaded into the process address space using the
mmap system call. Conveniently, this happens to be a good
time to update the process symbol table with the library's
incoming symbols so we handle the table update from within the
system call.

This works just like an application's normal symbols. The only
difference between a dynamic library and a main executable is
when the symbol table update occurs. The symbol table update for
an executable happens at program load time and is finished before
the process ever begins executing. Since dynamic linking happens
at runtime, the symbol loading happens after the library is
first loaded into the process address space. The library binary
is examined at this time for a symbol section and that section
is parsed for symbol types with specific bindings (global,
local, weak). Subsequently, these symbols are added to the table
and are available for use by gem5 for things like trace
generation.

Checkpointing should work just as it did previously. The address
space (and therefore the library) will be recorded and the symbol
table will be entirely recorded. (It's not possible to do anything
clever like checkpoint a program and then load the program back
with different libraries with LD_LIBRARY_PATH, because the
library becomes part of the address space after being loaded.)

11391:484c04261226 17-Mar-2016 Brandon Potter <brandon.potter@amd.com>

base: style cleanup for ObjectFile and ElfObject

11389:1e55f16160cb 17-Mar-2016 Brandon Potter <brandon.potter@amd.com>

base: support dynamic loading of Linux ELF objects in SE mode

11359:b0b976a1ceda 27-Nov-2015 Andreas Sandberg <andreas@sandberg.pp.se>

base: Add support for changing output directories

This changeset adds support for changing the simulator output
directory. This can be useful when the simulation goes through several
stages (e.g., a warming phase, a simulation phase, and a verification
phase) since it allows the output from each stage to be located in a
different directory. Relocation is done by calling core.setOutputDir()
from Python or simout.setOutputDirectory() from C++.

This change affects several parts of the design of the gem5's output
subsystem. First, files returned by an OutputDirectory instance (e.g.,
simout) are of the type OutputStream instead of a std::ostream. This
allows us to do some more book keeping and control re-opening of files
when the output directory is changed. Second, new subdirectories are
OutputDirectory instances, which should be used to create files in
that sub-directory.

Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se>
[sascha.bischoff@arm.com: Rebased patches onto a newer gem5 version]
Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com>
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>

11354:414abc839464 29-Feb-2016 Curtis Dunham <Curtis.Dunham@arm.com>

base: support gzip-compressed object files

11321:02e930db812d 06-Feb-2016 Steve Reinhardt <steve.reinhardt@amd.com>

style: fix missing spaces in control statements

Result of running 'hg m5style --skip-all --fix-control -a'.


/gem5/src/arch/alpha/process.cc
/gem5/src/arch/arm/insts/macromem.cc
/gem5/src/arch/arm/insts/vfp.hh
/gem5/src/arch/arm/kvm/arm_cpu.cc
/gem5/src/arch/arm/linux/system.cc
/gem5/src/arch/arm/tlb.cc
/gem5/src/arch/generic/tlb.cc
/gem5/src/arch/mips/isa.cc
/gem5/src/arch/x86/bios/intelmp.cc
/gem5/src/arch/x86/cpuid.cc
/gem5/src/arch/x86/decoder.cc
/gem5/src/arch/x86/insts/microldstop.cc
/gem5/src/arch/x86/insts/microregop.cc
/gem5/src/arch/x86/insts/static_inst.cc
/gem5/src/arch/x86/insts/static_inst.hh
/gem5/src/arch/x86/nativetrace.cc
/gem5/src/arch/x86/pagetable_walker.cc
/gem5/src/arch/x86/process.cc
/gem5/src/arch/x86/types.hh
atomicio.hh
cp_annotate.cc
fenv.c
loader/elf_object.cc
statistics.cc
/gem5/src/cpu/base.cc
/gem5/src/cpu/kvm/perfevent.cc
/gem5/src/cpu/kvm/x86_cpu.cc
/gem5/src/cpu/minor/decode.cc
/gem5/src/cpu/nativetrace.cc
/gem5/src/cpu/nativetrace.hh
/gem5/src/cpu/o3/inst_queue_impl.hh
/gem5/src/cpu/o3/rename_impl.hh
/gem5/src/cpu/pred/bpred_unit.cc
/gem5/src/cpu/simple/atomic.cc
/gem5/src/cpu/simple/base.cc
/gem5/src/cpu/simple/timing.cc
/gem5/src/dev/alpha/tsunami_cchip.cc
/gem5/src/dev/arm/flash_device.cc
/gem5/src/dev/arm/ufs_device.cc
/gem5/src/dev/intel_8254_timer.cc
/gem5/src/dev/mips/malta_cchip.cc
/gem5/src/dev/virtio/base.cc
/gem5/src/mem/bridge.cc
/gem5/src/mem/cache/prefetch/stride.cc
/gem5/src/mem/dram_ctrl.cc
/gem5/src/mem/physical.cc
/gem5/src/mem/port.cc
/gem5/src/mem/ruby/filters/BulkBloomFilter.cc
/gem5/src/mem/ruby/filters/H3BloomFilter.cc
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiGrainBloomFilter.cc
/gem5/src/mem/ruby/filters/NonCountingBloomFilter.cc
/gem5/src/mem/ruby/network/MessageBuffer.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/simple/PerfectSwitch.cc
/gem5/src/mem/ruby/profiler/AccessTraceForAddress.cc
/gem5/src/mem/ruby/slicc_interface/AbstractController.cc
/gem5/src/mem/ruby/structures/AbstractReplacementPolicy.cc
/gem5/src/mem/ruby/structures/BankedArray.cc
/gem5/src/mem/ruby/structures/CacheMemory.cc
/gem5/src/mem/ruby/structures/PseudoLRUPolicy.cc
/gem5/src/mem/ruby/structures/RubyMemoryControl.cc
/gem5/src/mem/ruby/structures/TBETable.hh
/gem5/src/mem/ruby/system/GPUCoalescer.cc
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/VIPERCoalescer.cc
/gem5/src/mem/ruby/system/WeightedLRUPolicy.cc
/gem5/src/mem/serial_link.cc
/gem5/src/mem/stack_dist_calc.cc
/gem5/src/python/swig/pyobject.cc
/gem5/src/sim/backtrace_glibc.cc
/gem5/src/sim/dvfs_handler.cc
/gem5/src/sim/serialize.hh
/gem5/src/sim/syscall_emul.hh
/gem5/tests/test-progs/gpu-hello/src/gpu-hello-kernel.cl
/gem5/tests/test-progs/gpu-hello/src/gpu-hello.cpp
/gem5/tests/test-progs/mwait/mwait.c
/gem5/util/statetrace/arch/amd64/tracechild.cc
/gem5/util/statetrace/arch/arm/tracechild.cc
/gem5/util/statetrace/arch/sparc/tracechild.cc
/gem5/util/tlm/main.cc
/gem5/util/tlm/sc_mm.cc
/gem5/util/tlm/sc_port.cc
/gem5/util/tlm/sc_target.cc
11320:42ecb523c64a 06-Feb-2016 Steve Reinhardt <steve.reinhardt@amd.com>

style: remove trailing whitespace

Result of running 'hg m5style --skip-all --fix-white -a'.


/gem5/configs/common/CacheConfig.py
/gem5/configs/common/Simulation.py
/gem5/configs/example/ruby_mem_test.py
/gem5/src/arch/alpha/isa/decoder.isa
/gem5/src/arch/alpha/linux/linux.hh
/gem5/src/arch/alpha/process.cc
/gem5/src/arch/alpha/tlb.cc
/gem5/src/arch/arm/SConscript
/gem5/src/arch/arm/interrupts.cc
/gem5/src/arch/arm/isa/bitfields.isa
/gem5/src/arch/arm/isa/formats/pred.isa
/gem5/src/arch/arm/linux/linux.hh
/gem5/src/arch/arm/stacktrace.cc
/gem5/src/arch/mips/isa/decoder.isa
/gem5/src/arch/mips/linux/linux.hh
/gem5/src/arch/mips/linux/process.cc
/gem5/src/arch/mips/pagetable.hh
/gem5/src/arch/power/SConscript
/gem5/src/arch/sparc/interrupts.cc
/gem5/src/arch/sparc/linux/linux.hh
/gem5/src/arch/sparc/pagetable.hh
/gem5/src/arch/x86/cpuid.cc
/gem5/src/arch/x86/faults.cc
/gem5/src/arch/x86/insts/micromediaop.hh
/gem5/src/arch/x86/isa/insts/general_purpose/system_calls.py
/gem5/src/arch/x86/isa/insts/romutil.py
/gem5/src/arch/x86/isa/insts/simd64/integer/data_transfer/move.py
/gem5/src/arch/x86/isa/microops/base.isa
/gem5/src/arch/x86/isa/microops/mediaop.isa
/gem5/src/arch/x86/isa/microops/regop.isa
/gem5/src/arch/x86/process.cc
/gem5/src/arch/x86/process.hh
cp_annotate.cc
cp_annotate.hh
cprintf.hh
flags.hh
inet.cc
inet.hh
loader/ecoff_object.cc
loader/elf_object.cc
statistics.cc
/gem5/src/cpu/o3/decode_impl.hh
/gem5/src/cpu/simple/timing.cc
/gem5/src/cpu/testers/directedtest/DirectedGenerator.cc
/gem5/src/cpu/testers/directedtest/DirectedGenerator.hh
/gem5/src/cpu/testers/directedtest/InvalidateGenerator.cc
/gem5/src/cpu/testers/directedtest/InvalidateGenerator.hh
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.cc
/gem5/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
/gem5/src/cpu/testers/directedtest/SeriesRequestGenerator.hh
/gem5/src/cpu/testers/networktest/networktest.cc
/gem5/src/cpu/timebuf.hh
/gem5/src/dev/mc146818.cc
/gem5/src/dev/net/i8254xGBe.cc
/gem5/src/dev/net/i8254xGBe.hh
/gem5/src/dev/net/i8254xGBe_defs.hh
/gem5/src/dev/x86/i8042.cc
/gem5/src/dev/x86/i8254.hh
/gem5/src/dev/x86/intdev.hh
/gem5/src/mem/mport.hh
/gem5/src/mem/ruby/network/Topology.cc
/gem5/src/mem/ruby/network/Topology.hh
/gem5/src/mem/ruby/network/fault_model/FaultModel.cc
/gem5/src/mem/ruby/network/fault_model/FaultModel.hh
/gem5/src/mem/ruby/network/fault_model/FaultModel.py
/gem5/src/mem/ruby/network/fault_model/SConscript
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.py
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/Router.hh
/gem5/src/mem/ruby/network/simple/SimpleLink.cc
/gem5/src/mem/slicc/ast/StallAndWaitStatementAST.py
/gem5/src/mem/slicc/ast/TypeFieldEnumAST.py
/gem5/src/mem/slicc/ast/TypeFieldStateAST.py
/gem5/src/python/m5/util/__init__.py
/gem5/src/python/swig/event.i
/gem5/src/sim/Root.py
/gem5/src/sim/eventq.cc
/gem5/src/sim/eventq.hh
/gem5/src/sim/insttracer.hh
/gem5/src/sim/pseudo_inst.cc
/gem5/src/unittest/cprintftest.cc
/gem5/system/alpha/console/console.c
/gem5/tests/configs/memtest-ruby.py
/gem5/util/checkpoint-tester.py
/gem5/util/compile
/gem5/util/m5/m5.c
/gem5/util/qdo
/gem5/util/statetrace/SConstruct
11306:a5340a2a24f9 19-Jan-2016 Tony Gutierrez <anthony.gutierrez@amd.com>

* * *
mem: support for gpu-style RMWs in ruby

This patch adds support for GPU-style read-modify-write (RMW) operations in
ruby. Such atomic operations are traditionally executed at the memory controller
(instead of through an L1 cache using cache-line locking).

Currently, this patch works by propogating operation functors through the memory
system.

11294:a368064a2ab5 11-Jan-2016 Andreas Hansson <andreas.hansson@arm.com>

scons: Enable -Wextra by default

Make best use of the compiler, and enable -Wextra as well as
-Wall. There are a few issues that had to be resolved, but they are
all trivial.

11293:25352d3d491e 11-Jan-2016 Andreas Hansson <andreas.hansson@arm.com>

ext: Replace gzstream with iostream3 from zlib to avoid LGPL

This patch replaces the gzstream zlib wrapper with the iostream3
wrapper provided as part of zlib contributions. The main reason for
the switch is to avoid including LGPL in the default gem5
build. iostream3 is provided under a more permissive license:

The code is provided "as is", with the permission to use, copy,
modify, distribute and sell it for any purpose without fee.

11274:d9a0136ab8cc 18-Dec-2015 Boris Shingarov <shingarov@labware.com>

arm: remote GDB: rationalize structure of register offsets

Currently, the wire format of register values in g- and G-packets is
modelled using a union of uint8/16/32/64 arrays. The offset positions
of each register are expressed as a "register count" scaled according
to the width of the register in question. This results in counter-
intuitive and error-prone "register count arithmetic", and some
formats would even be altogether unrepresentable in such model, e.g.
a 64-bit register following a 32-bit one would have a fractional index
in the regs64 array.
Another difficulty is that the array is allocated before the actual
architecture of the workload is known (and therefore before the correct
size for the array can be calculated).

With this patch I propose a simpler mechanism for expressing the
register set structure. In the new code, GdbRegCache is an abstract
class; its subclasses contain straightforward structs reflecting the
register representation. The determination whether to use e.g. the
AArch32 vs. AArch64 register set (or SPARCv8 vs SPARCv9, etc.) is made
by polymorphically dispatching getregs() to the concrete subclass.
The subclass is not instantiated until it is needed for actual
g-/G-packet processing, when the mode is already known.

This patch is not meant to be merged in on its own, because it changes
the contract between src/base/remote_gdb.* and src/arch/*/remote_gdb.*,
so as it stands right now, it would break the other architectures.
In this patch only the base and the ARM code are provided for review;
once we agree on the structure, I will provide src/arch/*/remote_gdb.*
for the other architectures; those patches could then be merged in
together.

Review Request: http://reviews.gem5.org/r/3207/
Pushed by Joel Hestness <jthestness@gmail.com>

11263:8dcc6b40f164 10-Dec-2015 Andreas Sandberg <andreas.sandberg@arm.com>

dev: Move network devices to src/dev/net/


inet.hh
/gem5/src/dev/Ethernet.py
/gem5/src/dev/SConscript
/gem5/src/dev/etherbus.cc
/gem5/src/dev/etherbus.hh
/gem5/src/dev/etherdevice.cc
/gem5/src/dev/etherdevice.hh
/gem5/src/dev/etherdump.cc
/gem5/src/dev/etherdump.hh
/gem5/src/dev/etherint.cc
/gem5/src/dev/etherint.hh
/gem5/src/dev/etherlink.cc
/gem5/src/dev/etherlink.hh
/gem5/src/dev/etherobject.hh
/gem5/src/dev/etherpkt.cc
/gem5/src/dev/etherpkt.hh
/gem5/src/dev/ethertap.cc
/gem5/src/dev/ethertap.hh
/gem5/src/dev/i8254xGBe.cc
/gem5/src/dev/i8254xGBe.hh
/gem5/src/dev/i8254xGBe_defs.hh
/gem5/src/dev/multi_etherlink.cc
/gem5/src/dev/multi_etherlink.hh
/gem5/src/dev/multi_iface.cc
/gem5/src/dev/multi_iface.hh
/gem5/src/dev/multi_packet.cc
/gem5/src/dev/multi_packet.hh
/gem5/src/dev/net/Ethernet.py
/gem5/src/dev/net/SConscript
/gem5/src/dev/net/etherbus.cc
/gem5/src/dev/net/etherbus.hh
/gem5/src/dev/net/etherdevice.cc
/gem5/src/dev/net/etherdevice.hh
/gem5/src/dev/net/etherdump.cc
/gem5/src/dev/net/etherdump.hh
/gem5/src/dev/net/etherint.cc
/gem5/src/dev/net/etherint.hh
/gem5/src/dev/net/etherlink.cc
/gem5/src/dev/net/etherlink.hh
/gem5/src/dev/net/etherobject.hh
/gem5/src/dev/net/etherpkt.cc
/gem5/src/dev/net/etherpkt.hh
/gem5/src/dev/net/ethertap.cc
/gem5/src/dev/net/ethertap.hh
/gem5/src/dev/net/i8254xGBe.cc
/gem5/src/dev/net/i8254xGBe.hh
/gem5/src/dev/net/i8254xGBe_defs.hh
/gem5/src/dev/net/multi_etherlink.cc
/gem5/src/dev/net/multi_etherlink.hh
/gem5/src/dev/net/multi_iface.cc
/gem5/src/dev/net/multi_iface.hh
/gem5/src/dev/net/multi_packet.cc
/gem5/src/dev/net/multi_packet.hh
/gem5/src/dev/net/ns_gige.cc
/gem5/src/dev/net/ns_gige.hh
/gem5/src/dev/net/ns_gige_reg.h
/gem5/src/dev/net/pktfifo.cc
/gem5/src/dev/net/pktfifo.hh
/gem5/src/dev/net/sinic.cc
/gem5/src/dev/net/sinic.hh
/gem5/src/dev/net/sinicreg.hh
/gem5/src/dev/net/tcp_iface.cc
/gem5/src/dev/net/tcp_iface.hh
/gem5/src/dev/ns_gige.cc
/gem5/src/dev/ns_gige.hh
/gem5/src/dev/ns_gige_reg.h
/gem5/src/dev/pktfifo.cc
/gem5/src/dev/pktfifo.hh
/gem5/src/dev/sinic.cc
/gem5/src/dev/sinic.hh
/gem5/src/dev/sinicreg.hh
/gem5/src/dev/tcp_iface.cc
/gem5/src/dev/tcp_iface.hh
/gem5/src/python/swig/pyobject.cc
/gem5/src/python/swig/pyobject.hh
11259:4006183015a1 05-Nov-2015 Sascha Bischoff <sascha.bischoff@ARM.com>

sim: Disable gzip compression for writefile pseudo instruction

The writefile pseudo instruction uses OutputDirectory::create and
OutputDirectory::openFile to create the output files. However, by
default these will check the file extention for .gz, and create a gzip
compressed stream if the file ending matches. When writing out files,
we want to write them out exactly as they are in the guest simulation,
and never want to compress them with gzio. Additionally, this causes
m5 writefile to fail when checking the error flags for the output
steam.

With this patch we add an additional no_gz argument to
OutputDirectory::create and OutputDirectory::openFile which allows us
to override the gzip compression. Therefore, for m5 writefile we
disable the filename check, and always create a standard ostream.

11235:4162427127e9 03-Dec-2015 Andreas Sandberg <andreas.sandberg@arm.com>

sim: Add support for generating back traces on errors

Add functionality to generate a back trace if gem5 crashes (SIGABRT or
SIGSEGV). The current implementation uses glibc's stack traversal
support if available and stubs out the call to print_backtrace()
otherwise.

11189:4237221d3e31 06-Nov-2015 Andreas Hansson <andreas.hansson@arm.com>

misc: Appease clang static analyzer

A few minor fixes to issues identified by the clang static analyzer.

11168:f98eb2da15a4 12-Oct-2015 Andreas Hansson <andreas.hansson@arm.com>

misc: Remove redundant compiler-specific defines

This patch moves away from using M5_ATTR_OVERRIDE and the m5::hashmap
(and similar) abstractions, as these are no longer needed with gcc 4.7
and clang 3.1 as minimum compiler versions.


/gem5/src/arch/alpha/isa.hh
/gem5/src/arch/alpha/kernel_stats.hh
/gem5/src/arch/alpha/pagetable.hh
/gem5/src/arch/alpha/process.hh
/gem5/src/arch/alpha/system.hh
/gem5/src/arch/alpha/tlb.hh
/gem5/src/arch/arm/isa_device.hh
/gem5/src/arch/arm/kvm/armv8_cpu.hh
/gem5/src/arch/arm/kvm/base_cpu.hh
/gem5/src/arch/arm/kvm/gic.hh
/gem5/src/arch/arm/pagetable.hh
/gem5/src/arch/arm/pmu.hh
/gem5/src/arch/arm/table_walker.hh
/gem5/src/arch/arm/tlb.hh
/gem5/src/arch/arm/types.hh
/gem5/src/arch/generic/types.hh
/gem5/src/arch/mips/interrupts.hh
/gem5/src/arch/mips/tlb.hh
/gem5/src/arch/power/tlb.hh
/gem5/src/arch/power/types.hh
/gem5/src/arch/sparc/interrupts.hh
/gem5/src/arch/sparc/isa.hh
/gem5/src/arch/sparc/system.hh
/gem5/src/arch/sparc/tlb.hh
/gem5/src/arch/x86/decoder.hh
/gem5/src/arch/x86/interrupts.hh
/gem5/src/arch/x86/isa.hh
/gem5/src/arch/x86/pagetable.hh
/gem5/src/arch/x86/regs/msr.hh
/gem5/src/arch/x86/tlb.hh
/gem5/src/arch/x86/types.hh
/gem5/src/arch/x86/utility.hh
compiler.hh
cp_annotate.hh
framebuffer.hh
hashmap.hh
inifile.hh
pollevent.hh
random.hh
trace.hh
vnc/vncserver.hh
/gem5/src/cpu/base.hh
/gem5/src/cpu/checker/cpu.hh
/gem5/src/cpu/decode_cache.hh
/gem5/src/cpu/inst_pb_trace.hh
/gem5/src/cpu/kvm/base.hh
/gem5/src/cpu/kvm/x86_cpu.hh
/gem5/src/cpu/minor/cpu.hh
/gem5/src/cpu/minor/pipeline.hh
/gem5/src/cpu/o3/cpu.hh
/gem5/src/cpu/o3/lsq_unit.hh
/gem5/src/cpu/o3/mem_dep_unit.hh
/gem5/src/cpu/o3/thread_state.hh
/gem5/src/cpu/pred/bpred_unit.hh
/gem5/src/cpu/simple/atomic.hh
/gem5/src/cpu/simple/base.hh
/gem5/src/cpu/simple/exec_context.hh
/gem5/src/cpu/simple/probes/simpoint.hh
/gem5/src/cpu/simple/timing.hh
/gem5/src/cpu/simple_thread.hh
/gem5/src/cpu/testers/rubytest/CheckTable.cc
/gem5/src/cpu/testers/rubytest/CheckTable.hh
/gem5/src/cpu/testers/traffic_gen/traffic_gen.hh
/gem5/src/cpu/thread_state.hh
/gem5/src/dev/alpha/backdoor.hh
/gem5/src/dev/alpha/tsunami.hh
/gem5/src/dev/alpha/tsunami_cchip.hh
/gem5/src/dev/alpha/tsunami_io.hh
/gem5/src/dev/alpha/tsunami_pchip.hh
/gem5/src/dev/arm/energy_ctrl.hh
/gem5/src/dev/arm/flash_device.hh
/gem5/src/dev/arm/generic_timer.hh
/gem5/src/dev/arm/gic_pl390.hh
/gem5/src/dev/arm/gpu_nomali.hh
/gem5/src/dev/arm/hdlcd.hh
/gem5/src/dev/arm/kmi.hh
/gem5/src/dev/arm/pl011.hh
/gem5/src/dev/arm/pl111.hh
/gem5/src/dev/arm/rtc_pl031.hh
/gem5/src/dev/arm/rv_ctrl.hh
/gem5/src/dev/arm/timer_cpulocal.hh
/gem5/src/dev/arm/timer_sp804.hh
/gem5/src/dev/arm/ufs_device.hh
/gem5/src/dev/arm/vgic.hh
/gem5/src/dev/copy_engine.hh
/gem5/src/dev/copy_engine_defs.hh
/gem5/src/dev/disk_image.hh
/gem5/src/dev/dma_device.hh
/gem5/src/dev/etherlink.hh
/gem5/src/dev/ethertap.hh
/gem5/src/dev/i2cbus.hh
/gem5/src/dev/i8254xGBe.hh
/gem5/src/dev/i8254xGBe_defs.hh
/gem5/src/dev/ide_ctrl.hh
/gem5/src/dev/ide_disk.hh
/gem5/src/dev/mips/malta.hh
/gem5/src/dev/mips/malta_cchip.hh
/gem5/src/dev/mips/malta_io.hh
/gem5/src/dev/mips/malta_pchip.hh
/gem5/src/dev/multi_etherlink.hh
/gem5/src/dev/multi_iface.hh
/gem5/src/dev/ns_gige.hh
/gem5/src/dev/pcidev.hh
/gem5/src/dev/pixelpump.hh
/gem5/src/dev/sinic.hh
/gem5/src/dev/sparc/dtod.hh
/gem5/src/dev/sparc/iob.hh
/gem5/src/dev/sparc/mm_disk.hh
/gem5/src/dev/tcp_iface.hh
/gem5/src/dev/uart8250.hh
/gem5/src/dev/virtio/base.hh
/gem5/src/dev/virtio/fs9p.hh
/gem5/src/dev/x86/cmos.hh
/gem5/src/dev/x86/i8042.hh
/gem5/src/dev/x86/i82094aa.hh
/gem5/src/dev/x86/i8237.hh
/gem5/src/dev/x86/i8254.hh
/gem5/src/dev/x86/i8259.hh
/gem5/src/dev/x86/speaker.hh
/gem5/src/kern/kernel_stats.hh
/gem5/src/mem/cache/cache.hh
/gem5/src/mem/cache/mshr_queue.hh
/gem5/src/mem/cache/prefetch/stride.hh
/gem5/src/mem/cache/tags/base_set_assoc.hh
/gem5/src/mem/cache/tags/fa_lru.hh
/gem5/src/mem/coherent_xbar.hh
/gem5/src/mem/comm_monitor.hh
/gem5/src/mem/dram_ctrl.hh
/gem5/src/mem/dramsim2.hh
/gem5/src/mem/mem_checker.hh
/gem5/src/mem/multi_level_page_table.hh
/gem5/src/mem/packet_queue.hh
/gem5/src/mem/page_table.hh
/gem5/src/mem/physical.hh
/gem5/src/mem/probes/base.hh
/gem5/src/mem/probes/mem_trace.hh
/gem5/src/mem/probes/stack_dist.hh
/gem5/src/mem/ruby/common/Address.hh
/gem5/src/mem/ruby/profiler/AddressProfiler.hh
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/structures/CacheMemory.cc
/gem5/src/mem/ruby/structures/CacheMemory.hh
/gem5/src/mem/ruby/structures/PerfectCacheMemory.hh
/gem5/src/mem/ruby/structures/PersistentTable.hh
/gem5/src/mem/ruby/structures/RubyMemoryControl.hh
/gem5/src/mem/ruby/structures/TBETable.hh
/gem5/src/mem/ruby/system/CacheRecorder.hh
/gem5/src/mem/ruby/system/DMASequencer.hh
/gem5/src/mem/ruby/system/RubyPort.hh
/gem5/src/mem/ruby/system/RubySystem.hh
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/Sequencer.hh
/gem5/src/mem/simple_mem.hh
/gem5/src/mem/snoop_filter.hh
/gem5/src/mem/xbar.hh
/gem5/src/sim/clock_domain.hh
/gem5/src/sim/dvfs_handler.hh
/gem5/src/sim/eventq.cc
/gem5/src/sim/eventq.hh
/gem5/src/sim/fd_entry.hh
/gem5/src/sim/process.hh
/gem5/src/sim/root.hh
/gem5/src/sim/serialize.cc
/gem5/src/sim/sim_events.hh
/gem5/src/sim/sim_object.hh
/gem5/src/sim/system.hh
/gem5/src/sim/ticked_object.hh
/gem5/src/sim/voltage_domain.hh
11153:20bbfe5b2b86 30-Sep-2015 Curtis Dunham <Curtis.Dunham@arm.com>

base: remove Trace::enabled flag

The DTRACE() macro tests both Trace::enabled and the specific flag. This
change uses the same administrative interface for enabling/disabling
tracing, but masks the SimpleFlags settings directly. This eliminates a
load for every DTRACE() test, e.g. DPRINTF.

11008:be3b60b52b31 07-Aug-2015 Andreas Sandberg <andreas.sandberg@arm.com>

base: Rewrite the CircleBuf to fix bugs and add serialization

The CircleBuf class has at least one bug causing it to overwrite the
wrong elements when wrapping. The current code has a lot of unused
functionality and duplicated code. This changeset replaces the old
implementation with a new version that supports serialization and
arbitrary types in the buffer (not just char).

11005:e7f403b6b76f 07-Aug-2015 Andreas Sandberg <andreas.sandberg@arm.com>

base: Declare a type for context IDs

Context IDs used to be declared as ad hoc (usually as int). This
changeset introduces a typedef for ContextIDs and a constant for
invalid context IDs.

11004:2c347b12cc9c 07-Aug-2015 Andreas Sandberg <Andreas.Sandberg@ARM.com>

base: Use constexpr in Cycles

Declare the constructor and all of the operators that don't change the
state of a Cycles instance as constexpr. This makes it possible to use
Cycles as a static constant and allows the compiler to evaulate simple
expressions at compile time. An unfortunate side-effect of this is
that we cannot use assertions since C++11 doesn't support them in
constexpr functions. As a workaround, we throw an invalid_argument
exception when the assert would have triggered. A nice side-effect of
this is that the compiler will evaluate the "assertion" at compile
time when an expression involving Cycles can be statically evaluated.

10907:94d5a1476c5b 07-Jul-2015 Andreas Sandberg <andreas.sandberg@arm.com>

base: Add serialization support to Pixels and FrameBuffer

Serialize pixels as unsigned 32 bit integers by adding the required
to_number() and stream operators. This is used by the FrameBuffer,
which now implements the Serializable interface. Users of frame
buffers are expected to serialize it into its own section by calling
serializeSection().

10905:a6ca6831e775 07-Jul-2015 Andreas Sandberg <andreas.sandberg@arm.com>

sim: Refactor the serialization base class

Objects that are can be serialized are supposed to inherit from the
Serializable class. This class is meant to provide a unified API for
such objects. However, so far it has mainly been used by SimObjects
due to some fundamental design limitations. This changeset redesigns
to the serialization interface to make it more generic and hide the
underlying checkpoint storage. Specifically:

* Add a set of APIs to serialize into a subsection of the current
object. Previously, objects that needed this functionality would
use ad-hoc solutions using nameOut() and section name
generation. In the new world, an object that implements the
interface has the methods serializeSection() and
unserializeSection() that serialize into a named /subsection/ of
the current object. Calling serialize() serializes an object into
the current section.

* Move the name() method from Serializable to SimObject as it is no
longer needed for serialization. The fully qualified section name
is generated by the main serialization code on the fly as objects
serialize sub-objects.

* Add a scoped ScopedCheckpointSection helper class. Some objects
need to serialize data structures, that are not deriving from
Serializable, into subsections. Previously, this was done using
nameOut() and manual section name generation. To simplify this,
this changeset introduces a ScopedCheckpointSection() helper
class. When this class is instantiated, it adds a new /subsection/
and subsequent serialization calls during the lifetime of this
helper class happen inside this section (or a subsection in case
of nested sections).

* The serialize() call is now const which prevents accidental state
manipulation during serialization. Objects that rely on modifying
state can use the serializeOld() call instead. The default
implementation simply calls serialize(). Note: The old-style calls
need to be explicitly called using the
serializeOld()/serializeSectionOld() style APIs. These are used by
default when serializing SimObjects.

* Both the input and output checkpoints now use their own named
types. This hides underlying checkpoint implementation from
objects that need checkpointing and makes it easier to change the
underlying checkpoint storage code.


/gem5/src/arch/alpha/interrupts.hh
/gem5/src/arch/alpha/isa.cc
/gem5/src/arch/alpha/isa.hh
/gem5/src/arch/alpha/kernel_stats.cc
/gem5/src/arch/alpha/kernel_stats.hh
/gem5/src/arch/alpha/pagetable.cc
/gem5/src/arch/alpha/pagetable.hh
/gem5/src/arch/alpha/process.cc
/gem5/src/arch/alpha/process.hh
/gem5/src/arch/alpha/system.cc
/gem5/src/arch/alpha/system.hh
/gem5/src/arch/alpha/tlb.cc
/gem5/src/arch/alpha/tlb.hh
/gem5/src/arch/arm/interrupts.hh
/gem5/src/arch/arm/isa.hh
/gem5/src/arch/arm/kvm/gic.cc
/gem5/src/arch/arm/kvm/gic.hh
/gem5/src/arch/arm/pagetable.hh
/gem5/src/arch/arm/pmu.cc
/gem5/src/arch/arm/pmu.hh
/gem5/src/arch/arm/tlb.cc
/gem5/src/arch/arm/tlb.hh
/gem5/src/arch/arm/types.hh
/gem5/src/arch/generic/types.hh
/gem5/src/arch/mips/interrupts.hh
/gem5/src/arch/mips/pagetable.cc
/gem5/src/arch/mips/pagetable.hh
/gem5/src/arch/mips/tlb.cc
/gem5/src/arch/mips/tlb.hh
/gem5/src/arch/power/pagetable.cc
/gem5/src/arch/power/pagetable.hh
/gem5/src/arch/power/tlb.cc
/gem5/src/arch/power/tlb.hh
/gem5/src/arch/sparc/interrupts.hh
/gem5/src/arch/sparc/isa.cc
/gem5/src/arch/sparc/isa.hh
/gem5/src/arch/sparc/pagetable.cc
/gem5/src/arch/sparc/pagetable.hh
/gem5/src/arch/sparc/system.cc
/gem5/src/arch/sparc/system.hh
/gem5/src/arch/sparc/tlb.cc
/gem5/src/arch/sparc/tlb.hh
/gem5/src/arch/x86/interrupts.cc
/gem5/src/arch/x86/interrupts.hh
/gem5/src/arch/x86/isa.cc
/gem5/src/arch/x86/isa.hh
/gem5/src/arch/x86/pagetable.cc
/gem5/src/arch/x86/pagetable.hh
/gem5/src/arch/x86/tlb.cc
/gem5/src/arch/x86/tlb.hh
/gem5/src/arch/x86/types.cc
/gem5/src/arch/x86/types.hh
cp_annotate.cc
cp_annotate.hh
loader/symtab.cc
loader/symtab.hh
pollevent.cc
pollevent.hh
random.cc
random.hh
time.cc
time.hh
/gem5/src/cpu/base.cc
/gem5/src/cpu/base.hh
/gem5/src/cpu/checker/cpu.cc
/gem5/src/cpu/checker/cpu.hh
/gem5/src/cpu/checker/thread_context.hh
/gem5/src/cpu/kvm/BaseKvmCPU.py
/gem5/src/cpu/kvm/base.cc
/gem5/src/cpu/kvm/base.hh
/gem5/src/cpu/kvm/x86_cpu.cc
/gem5/src/cpu/kvm/x86_cpu.hh
/gem5/src/cpu/minor/cpu.cc
/gem5/src/cpu/minor/cpu.hh
/gem5/src/cpu/o3/cpu.cc
/gem5/src/cpu/o3/cpu.hh
/gem5/src/cpu/o3/thread_state.hh
/gem5/src/cpu/simple/base.cc
/gem5/src/cpu/simple/base.hh
/gem5/src/cpu/simple_thread.cc
/gem5/src/cpu/simple_thread.hh
/gem5/src/cpu/testers/traffic_gen/traffic_gen.cc
/gem5/src/cpu/testers/traffic_gen/traffic_gen.hh
/gem5/src/cpu/thread_context.cc
/gem5/src/cpu/thread_context.hh
/gem5/src/cpu/thread_state.cc
/gem5/src/cpu/thread_state.hh
/gem5/src/dev/alpha/backdoor.cc
/gem5/src/dev/alpha/backdoor.hh
/gem5/src/dev/alpha/tsunami.cc
/gem5/src/dev/alpha/tsunami.hh
/gem5/src/dev/alpha/tsunami_cchip.cc
/gem5/src/dev/alpha/tsunami_cchip.hh
/gem5/src/dev/alpha/tsunami_io.cc
/gem5/src/dev/alpha/tsunami_io.hh
/gem5/src/dev/alpha/tsunami_pchip.cc
/gem5/src/dev/alpha/tsunami_pchip.hh
/gem5/src/dev/arm/energy_ctrl.cc
/gem5/src/dev/arm/energy_ctrl.hh
/gem5/src/dev/arm/flash_device.cc
/gem5/src/dev/arm/flash_device.hh
/gem5/src/dev/arm/generic_timer.cc
/gem5/src/dev/arm/generic_timer.hh
/gem5/src/dev/arm/gic_pl390.cc
/gem5/src/dev/arm/gic_pl390.hh
/gem5/src/dev/arm/hdlcd.cc
/gem5/src/dev/arm/hdlcd.hh
/gem5/src/dev/arm/kmi.cc
/gem5/src/dev/arm/kmi.hh
/gem5/src/dev/arm/pl011.cc
/gem5/src/dev/arm/pl011.hh
/gem5/src/dev/arm/pl111.cc
/gem5/src/dev/arm/pl111.hh
/gem5/src/dev/arm/rtc_pl031.cc
/gem5/src/dev/arm/rtc_pl031.hh
/gem5/src/dev/arm/rv_ctrl.cc
/gem5/src/dev/arm/rv_ctrl.hh
/gem5/src/dev/arm/timer_cpulocal.cc
/gem5/src/dev/arm/timer_cpulocal.hh
/gem5/src/dev/arm/timer_sp804.cc
/gem5/src/dev/arm/timer_sp804.hh
/gem5/src/dev/arm/ufs_device.cc
/gem5/src/dev/arm/ufs_device.hh
/gem5/src/dev/arm/vgic.cc
/gem5/src/dev/arm/vgic.hh
/gem5/src/dev/copy_engine.cc
/gem5/src/dev/copy_engine.hh
/gem5/src/dev/copy_engine_defs.hh
/gem5/src/dev/disk_image.cc
/gem5/src/dev/disk_image.hh
/gem5/src/dev/etherlink.cc
/gem5/src/dev/etherlink.hh
/gem5/src/dev/etherpkt.cc
/gem5/src/dev/etherpkt.hh
/gem5/src/dev/ethertap.cc
/gem5/src/dev/ethertap.hh
/gem5/src/dev/i2cbus.cc
/gem5/src/dev/i2cbus.hh
/gem5/src/dev/i8254xGBe.cc
/gem5/src/dev/i8254xGBe.hh
/gem5/src/dev/i8254xGBe_defs.hh
/gem5/src/dev/ide_ctrl.cc
/gem5/src/dev/ide_ctrl.hh
/gem5/src/dev/ide_disk.cc
/gem5/src/dev/ide_disk.hh
/gem5/src/dev/intel_8254_timer.cc
/gem5/src/dev/intel_8254_timer.hh
/gem5/src/dev/mc146818.cc
/gem5/src/dev/mc146818.hh
/gem5/src/dev/mips/malta.cc
/gem5/src/dev/mips/malta.hh
/gem5/src/dev/mips/malta_cchip.cc
/gem5/src/dev/mips/malta_cchip.hh
/gem5/src/dev/mips/malta_io.cc
/gem5/src/dev/mips/malta_io.hh
/gem5/src/dev/mips/malta_pchip.cc
/gem5/src/dev/mips/malta_pchip.hh
/gem5/src/dev/ns_gige.cc
/gem5/src/dev/ns_gige.hh
/gem5/src/dev/pcidev.cc
/gem5/src/dev/pcidev.hh
/gem5/src/dev/pktfifo.cc
/gem5/src/dev/pktfifo.hh
/gem5/src/dev/sinic.cc
/gem5/src/dev/sinic.hh
/gem5/src/dev/sparc/dtod.cc
/gem5/src/dev/sparc/dtod.hh
/gem5/src/dev/sparc/iob.cc
/gem5/src/dev/sparc/iob.hh
/gem5/src/dev/sparc/mm_disk.cc
/gem5/src/dev/sparc/mm_disk.hh
/gem5/src/dev/uart8250.cc
/gem5/src/dev/uart8250.hh
/gem5/src/dev/virtio/base.cc
/gem5/src/dev/virtio/base.hh
/gem5/src/dev/virtio/fs9p.cc
/gem5/src/dev/virtio/fs9p.hh
/gem5/src/dev/x86/cmos.cc
/gem5/src/dev/x86/cmos.hh
/gem5/src/dev/x86/i8042.cc
/gem5/src/dev/x86/i8042.hh
/gem5/src/dev/x86/i82094aa.cc
/gem5/src/dev/x86/i82094aa.hh
/gem5/src/dev/x86/i8237.cc
/gem5/src/dev/x86/i8237.hh
/gem5/src/dev/x86/i8254.cc
/gem5/src/dev/x86/i8254.hh
/gem5/src/dev/x86/i8259.cc
/gem5/src/dev/x86/i8259.hh
/gem5/src/dev/x86/speaker.cc
/gem5/src/dev/x86/speaker.hh
/gem5/src/kern/kernel_stats.cc
/gem5/src/kern/kernel_stats.hh
/gem5/src/mem/cache/cache.hh
/gem5/src/mem/cache/cache_impl.hh
/gem5/src/mem/multi_level_page_table.hh
/gem5/src/mem/multi_level_page_table_impl.hh
/gem5/src/mem/page_table.cc
/gem5/src/mem/page_table.hh
/gem5/src/mem/physical.cc
/gem5/src/mem/physical.hh
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/ruby/system/System.hh
/gem5/src/python/m5/SimObject.py
/gem5/src/python/swig/core.i
/gem5/src/python/swig/pyobject.cc
/gem5/src/python/swig/pyobject.hh
/gem5/src/sim/clock_domain.cc
/gem5/src/sim/clock_domain.hh
/gem5/src/sim/cxx_manager.cc
/gem5/src/sim/cxx_manager.hh
/gem5/src/sim/dvfs_handler.cc
/gem5/src/sim/dvfs_handler.hh
/gem5/src/sim/eventq.cc
/gem5/src/sim/eventq.hh
/gem5/src/sim/process.cc
/gem5/src/sim/process.hh
/gem5/src/sim/root.cc
/gem5/src/sim/root.hh
/gem5/src/sim/serialize.cc
/gem5/src/sim/serialize.hh
/gem5/src/sim/sim_events.cc
/gem5/src/sim/sim_events.hh
/gem5/src/sim/sim_object.cc
/gem5/src/sim/sim_object.hh
/gem5/src/sim/system.cc
/gem5/src/sim/system.hh
/gem5/src/sim/ticked_object.cc
/gem5/src/sim/ticked_object.hh
/gem5/src/sim/voltage_domain.cc
/gem5/src/sim/voltage_domain.hh
10880:61a56f76222b 03-Jul-2015 Curtis Dunham <Curtis.Dunham@arm.com>

base: remove fd from object loaders

All the object loaders directly examine the (already completely loaded
by object_file.cc) memory image. There is no current motivation to
keep the fd around.

10874:e4f63f1d502d 21-Jun-2015 Andreas Sandberg <andreas.sandberg@arm.com>

base: Add a warn_if macro

Add a warn if macro that is analogous to the panic_if and fatal_if.

10868:b6cc436bac61 09-Jun-2015 Andreas Sandberg <andreas.sandberg@arm.com>

base: Reset CircleBuf size on flush()

The flush() method in CircleBuf resets the state of the circular
buffer, but fails to set size to zero. This obviously confuses code
that tries to determine the amount of data in the buffer. Set the size
to zero on flush.

10853:5312e4cb6547 26-May-2015 Andreas Hansson <andreas.hansson@arm.com>

base: Allow multiple interleaved ranges

This patch changes how the address range calculates intersection such
that a system can have a number of non-overlapping interleaved ranges
without complaining. Without this patch we end up with a panic.

10839:10cac0f0f419 23-May-2015 Andreas Sandberg <andreas.sandberg@arm.com>

base: Redesign internal frame buffer handling

Currently, frame buffer handling in gem5 is quite ad hoc. In practice,
we pass around naked pointers to raw pixel data and expect consumers
to convert frame buffers using the (broken) VideoConverter.

This changeset completely redesigns the way we handle frame buffers
internally. In summary, it fixes several color conversion bugs, adds
support for more color formats (e.g., big endian), and makes the code
base easier to follow.

In the new world, gem5 always represents pixel data using the Pixel
struct when pixels need to be passed between different classes (e.g.,
a display controller and the VNC server). Producers of entire frames
(e.g., display controllers) should use the FrameBuffer class to
represent a frame.

Frame producers are expected to create one instance of the FrameBuffer
class in their constructors and register it with its consumers
once. Consumers are expected to check the dimensions of the frame
buffer when they consume it.

Conversion between the external representation and the internal
representation is supported for all common "true color" RGB formats of
up to 32-bit color depth. The external pixel representation is
expected to be between 1 and 4 bytes in either big endian or little
endian. Color channels are assumed to be contiguous ranges of bits
within each pixel word. The external pixel value is scaled to an 8-bit
internal representation using a floating multiplication to map it to
the entire 8-bit range.

10838:364e7cc28406 23-May-2015 Andreas Sandberg <andreas.sandberg@arm.com>

base: Clean up bitmap generation code

The bitmap generation code is hard to follow and incorrectly uses the
size of an enum member to calculate the size of a pixel. This
changeset cleans up the code and adds some documentation.

10810:683ab55819fd 29-Apr-2015 Ruslan Bukin <br@bsdpad.com>

arch, base, dev, kern, sym: FreeBSD support

This adds support for FreeBSD/aarch64 FS and SE mode (basic set of syscalls only)

Committed by: Nilay Vaish <nilay@cs.wisc.edu>

10792:11e66ec059c6 22-Apr-2015 Brandon Potter <brandon.potter@amd.com>

base: add new ChunkGenerator method to identify last chunk

10686:1922f9d2ac01 11-Feb-2015 Andreas Sandberg <Andreas.Sandberg@ARM.com>

base: Add compiler macros to add deprecation warnings

Gcc and clang both provide an attribute that can be used to flag a
function as deprecated at compile time. This changeset adds a gem5
compiler macro for that compiler feature. The macro can be used to
indicate that a legacy API within gem5 has been deprecated and provide
a graceful migration to the new API.

10685:a24286e33318 11-Feb-2015 Andreas Hansson <andreas.hansson@arm.com>

base: Do not dereference NULL in CompoundFlag creation

This patch fixes the CompoundFlag constructor, ensuring that it does
not dereference NULL. Doing so has undefined behaviuor, and both clang
and gcc's undefined-behaviour sanitiser was rather unhappy.

10678:d95e81d44e36 03-Feb-2015 Curtis Dunham <Curtis.Dunham@arm.com>

base: add an accessor and operators ==,!= to address ranges

10676:f6c168692b20 03-Feb-2015 Andreas Hansson <andreas.hansson@arm.com>

base: Add XOR-based hashed address interleaving

This patch extends the current address interleaving with basic hashing
support. Instead of directly comparing a number of address bits with a
matching value, it is now possible to use two independent set of
address bits XOR'ed together. This avoids issues where strided address
patterns are heavily biased to a subset of the interleaved ranges.

10640:edbc52a43cd8 07-Jan-2015 Gabe Black <gabeblack@google.com>

base: Fix assigning between identical bitfields.

If two bitfields are of the same type, also implying that they have the same
first and last bit positions, the existing implementation would copy the
entire bitfield. That includes the __data member which is shared among all the
bitfields, effectively overwritting the entire bitunion.

This change also adjusts the write only signed bitfield assignment operator to
be like the unsigned version, using "using" instead of implementing it again
and calling down to the underlying implementation.

10601:6efb37480d87 06-Dec-2014 Gabe Black <gabeblack@google.com>

misc: Generalize GDB single stepping.

The new single stepping implementation for x86 doesn't rely on any ISA
specific properties or functionality. This change pulls out the per ISA
implementation of those functions and promotes the X86 implementation to the
base class.

One drawback of that implementation is that the CPU might stop on an
instruction twice if it's affected by both breakpoints and single stepping.
While that might be a little surprising, it's harmless and would only happen
under somewhat unlikely circumstances.

10599:910fc5624d68 06-Dec-2014 Gabe Black <gabeblack@google.com>

misc: Add some utility functions for schedule inst commit events.

These can be used to simplify the implementation of single step in derived
classes.

10598:3d7653a2538b 06-Dec-2014 Gabe Black <gabeblack@google.com>

misc: Rename the GDB "Event" event class to InputEvent.

The "Event" name is the same as the base event class. That's a bit confusing,
and makes it a little awkward to add other event types.

10597:bd68c6838b9f 05-Dec-2014 Gabe Black <gabeblack@google.com>

sim: Ensure GDB interrupts the simulation at an instruction boundary.

Use the comInstEventQueue to ensure GDB interrupts the simulation at an
instruction boundary and not in the middle of a macroop, memory access, etc.

10595:25ecfc14f73f 05-Dec-2014 Gabe Black <gabeblack@google.com>

misc: Make the GDB register cache accessible in various sized chunks.

Not all ISAs have 64 bit sized registers, so it's not always very convenient
to access the GDB register cache in 64 bit sized chunks. This change makes it
accessible in 8, 16, 32, or 64 bit chunks. The MIPS and ARM implementations
were working around that limitation by bundling and unbundling 32 bit values
into 64 bit values. That code has been removed.

10589:5962812f80fe 03-Dec-2014 Gabe Black <gabeblack@google.com>

sim: Make it possible to override the breakpoint length check.

The check which makes sure the length of the breakpoint being written is the
same as a MachInst is only correct on fixed instruction width ISAs. Instead of
incorrectly applying that check to all ISAs, this change makes that the
default check and lets ISA specific GDB classes override it.

10559:62f5f7363197 24-Nov-2014 Andreas Hansson <andreas.hansson@arm.com>

misc: Another round of static analysis fixups

Mostly addressing uninitialised members.

10545:f66948658a36 17-Nov-2014 Gabe Black <gabeblack@google.com>

vnc: Add a conversion function for bgr888.

10537:47fe87b0cf97 14-Nov-2014 Andreas Hansson <andreas.hansson@arm.com>

arm: Fixes based on UBSan and static analysis

Another churn to clean up undefined behaviour, mostly ARM, but some
parts also touching the generic part of the code base.

Most of the fixes are simply ensuring that proper intialisation. One
of the more subtle changes is the return type of the sign-extension,
which is changed to uint64_t. This is to avoid shifting negative
values (undefined behaviour) in the ISA code.

10531:fe837de10255 12-Nov-2014 Andreas Hansson <andreas.hansson@arm.com>

base: Revert 9277177eccff and use getenv/setenv for UTC time

This patch reverts changeset 9277177eccff which does not do what it
was intended to do. In essence, we go back to implementing mkutctime
much like the non-standard timegm extension.

10508:aa46a8ae3487 30-Oct-2014 Ali Saidi <Ali.Saidi@ARM.com>

arm: Fix multi-system AArch64 boot w/caches.

Automatically extract cpu release address from DTB file.
Check SCTLR_EL1 to verify all caches are enabled.

10493:9277177eccff 20-Oct-2014 Andreas Hansson <andreas.hansson@arm.com>

misc: Use gmtime for conversion to UTC to avoid getenv/setenv

This patch changes how we turn time into UTC. Previously we
manipulated the TZ environment variable, but this has issues as the
strings that are manipulated could be tainted (see e.g. CERT
ENV34-C). Now we simply rely on the built-in gmtime function and avoid
touching getenv/setenv all together.

10491:452c860fd0ee 20-Oct-2014 Andreas Hansson <andreas.hansson@arm.com>

base: Fix for stats node on gcc < 4.6.3

This patch adds an explicit function to get the underlying node as gcc
4.6.1 and 4.6.2 have issues otherwise.

10481:59fb5779ec6e 16-Oct-2014 Andreas Hansson <andreas.hansson@arm.com>

misc: Move AddrRangeList from port.hh to addr_range.hh

The new location seems like a better fit. The iterator typedefs are
removed in favour of using C++11 auto.

10476:f058e09b7d69 16-Oct-2014 Andreas Hansson <andreas.hansson@arm.com>

sim: EventQueue wakeup on events scheduled outside the event loop

This patch adds a 'wakeup' member function to EventQueue which should be
called on an event queue whenever an event is scheduled on the event queue
from outside code within the call tree of the gem5 event loop.

This clearly isn't necessary for normal gem5 EventQueue operation but
becomes the minimum necessary interface to allow hosting gem5's event loop
onto other schedulers where there may be calls into gem5 from external
code which schedules events onto an EventQueue between the current time and
the time of the next scheduled event.

The use case I have in mind is a SystemC hosting where the event loop is:

while (more events) {
wait(time_to_next_event or wakeup)
setCurTick
service events at this time
}

where the 'wait' needs to be woken up if time_to_next_event becomes shorter
due to a scheduled event from SystemC arriving in a gem5 object.

Requiring 'wakeup' to be called is a more efficient interface than
requiring all gem5 event scheduling actions to affect the host scheduler.

This interface could be located elsewhere, say on another global object,
or by being passed by the host scheduler to objects which will schedule
such events, but it seems cleanest to put it on EventQueue as it is
actually a signal to the queue.

EventQueue::wakeup is called for async_event events on event queue 0 as
it's only important that *some* queue be triggered for such events.

10475:5744891a444b 16-Oct-2014 Andrew Bardsley <Andrew.Bardsley@arm.com>

base: Reimplement the DPRINTF mechanism in a Logger class

This patch adds a Logger class encapsulating dprintf. This allows
variants of DPRINTF logging to be constructed and substituted in
place of the default behaviour.

The Logger provides a logMessage(when, name, format, ...) member
function like Trace::dprintf and a getOstream member function to
use a raw ostream for logging.

A class OstreamLogger is provided which generates the customary
debugging output with Trace::OstreamLogger::logMessage being the
old Trace::dprintf.

10474:799c8ee4ecba 16-Oct-2014 Andreas Hansson <andreas.hansson@arm.com>

arch: Use shared_ptr for all Faults

This patch takes quite a large step in transitioning from the ad-hoc
RefCountingPtr to the c++11 shared_ptr by adopting its use for all
Faults. There are no changes in behaviour, and the code modifications
are mostly just replacing "new" with "make_shared".


/gem5/src/arch/alpha/ev5.cc
/gem5/src/arch/alpha/faults.hh
/gem5/src/arch/alpha/interrupts.hh
/gem5/src/arch/alpha/isa/decoder.isa
/gem5/src/arch/alpha/isa/fp.isa
/gem5/src/arch/alpha/isa/opcdec.isa
/gem5/src/arch/alpha/isa/unimp.isa
/gem5/src/arch/alpha/isa/unknown.isa
/gem5/src/arch/alpha/tlb.cc
/gem5/src/arch/alpha/tlb.hh
/gem5/src/arch/arm/insts/static_inst.hh
/gem5/src/arch/arm/interrupts.hh
/gem5/src/arch/arm/isa/formats/breakpoint.isa
/gem5/src/arch/arm/isa/formats/unimp.isa
/gem5/src/arch/arm/isa/insts/branch.isa
/gem5/src/arch/arm/isa/insts/branch64.isa
/gem5/src/arch/arm/isa/insts/data64.isa
/gem5/src/arch/arm/isa/insts/fp.isa
/gem5/src/arch/arm/isa/insts/macromem.isa
/gem5/src/arch/arm/isa/insts/misc.isa
/gem5/src/arch/arm/isa/insts/misc64.isa
/gem5/src/arch/arm/isa/insts/neon.isa
/gem5/src/arch/arm/isa/insts/neon64.isa
/gem5/src/arch/arm/isa/insts/neon64_mem.isa
/gem5/src/arch/arm/isa/insts/swap.isa
/gem5/src/arch/arm/isa/templates/mem64.isa
/gem5/src/arch/arm/isa/templates/neon.isa
/gem5/src/arch/arm/isa/templates/vfp.isa
/gem5/src/arch/arm/table_walker.cc
/gem5/src/arch/arm/table_walker.hh
/gem5/src/arch/arm/tlb.cc
/gem5/src/arch/arm/tlb.hh
/gem5/src/arch/arm/utility.cc
/gem5/src/arch/generic/memhelpers.hh
/gem5/src/arch/mips/interrupts.cc
/gem5/src/arch/mips/isa.hh
/gem5/src/arch/mips/isa/decoder.isa
/gem5/src/arch/mips/isa/formats/control.isa
/gem5/src/arch/mips/isa/formats/dsp.isa
/gem5/src/arch/mips/isa/formats/fp.isa
/gem5/src/arch/mips/isa/formats/int.isa
/gem5/src/arch/mips/isa/formats/mt.isa
/gem5/src/arch/mips/isa/formats/trap.isa
/gem5/src/arch/mips/isa/formats/unimp.isa
/gem5/src/arch/mips/isa/formats/unknown.isa
/gem5/src/arch/mips/mt.hh
/gem5/src/arch/mips/tlb.hh
/gem5/src/arch/power/isa/formats/unimp.isa
/gem5/src/arch/power/isa/formats/unknown.isa
/gem5/src/arch/power/tlb.cc
/gem5/src/arch/power/tlb.hh
/gem5/src/arch/sparc/interrupts.hh
/gem5/src/arch/sparc/isa/base.isa
/gem5/src/arch/sparc/isa/decoder.isa
/gem5/src/arch/sparc/isa/formats/mem/util.isa
/gem5/src/arch/sparc/isa/formats/priv.isa
/gem5/src/arch/sparc/isa/formats/trap.isa
/gem5/src/arch/sparc/isa/formats/unknown.isa
/gem5/src/arch/sparc/tlb.cc
/gem5/src/arch/sparc/tlb.hh
/gem5/src/arch/sparc/utility.cc
/gem5/src/arch/sparc/utility.hh
/gem5/src/arch/x86/interrupts.cc
/gem5/src/arch/x86/isa/formats/string.isa
/gem5/src/arch/x86/isa/formats/unknown.isa
/gem5/src/arch/x86/isa/insts/general_purpose/compare_and_test/bounds.py
/gem5/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py
/gem5/src/arch/x86/isa/insts/general_purpose/control_transfer/jump.py
/gem5/src/arch/x86/isa/insts/system/undefined_operation.py
/gem5/src/arch/x86/isa/insts/x87/arithmetic/addition.py
/gem5/src/arch/x86/isa/insts/x87/arithmetic/subtraction.py
/gem5/src/arch/x86/isa/insts/x87/data_transfer_and_conversion/exchange.py
/gem5/src/arch/x86/isa/microops/debug.isa
/gem5/src/arch/x86/isa/microops/regop.isa
/gem5/src/arch/x86/memhelpers.hh
/gem5/src/arch/x86/pagetable_walker.cc
/gem5/src/arch/x86/tlb.cc
/gem5/src/arch/x86/tlb.hh
/gem5/src/arch/x86/vtophys.cc
types.hh
/gem5/src/cpu/base_dyn_inst.hh
/gem5/src/cpu/exec_context.hh
/gem5/src/cpu/inorder/inorder_dyn_inst.cc
/gem5/src/cpu/inorder/inorder_dyn_inst.hh
/gem5/src/cpu/o3/dyn_inst_impl.hh
/gem5/src/cpu/o3/lsq_unit.hh
/gem5/src/cpu/o3/lsq_unit_impl.hh
/gem5/src/cpu/static_inst.hh
/gem5/src/sim/fault_fwd.hh
/gem5/src/sim/faults.hh
/gem5/src/sim/tlb.hh
10471:0433264984ce 16-Oct-2014 Andreas Hansson <andreas.hansson@arm.com>

base: Use shared_ptr for stat Node

This patch transitions the stat Node and its derived classes from
the ad-hoc RefCountingPtr to the c++11 shared_ptr. There are no
changes in behaviour, and the code modifications are mainly replacing
"new" with "make_shared".

10470:2c6a72e919f6 16-Oct-2014 Andreas Hansson <andreas.hansson@arm.com>

base: Transition CP annotate to use shared_ptr

10469:b16b7dc83139 16-Oct-2014 Andreas Hansson <andreas.hansson@arm.com>

dev: Use shared_ptr for EthPacketData

This patch transitions the EthPacketData from the ad-hoc
RefCountingPtr to the c++11 shared_ptr. There are no changes in
behaviour, and the code modifications are mainly replacing "new" with
"make_shared".

The bool casting operator for the shared_ptr is explicit, and we must
therefore either cast it, compare it to NULL (p != nullptr), double
negate it (!!p) or do a (p ? true : false).

10453:d0365cc3d05f 16-Oct-2014 Andrew Bardsley <Andrew.Bardsley@arm.com>

config: Add a --without-python option to build process

Add the ability to build libgem5 without embedded Python or the
ability to configure with Python.

This is a prelude to a patch to allow config.ini files to be loaded
into libgem5 using only C++ which would make embedding gem5 within
other simulation systems easier.

This adds a few registration interfaces to things which cross
between Python and C++. Namely: stats dumping and SimObject resolving

10435:97d6ed3054ae 11-Oct-2014 Nilay Vaish <nilay@cs.wisc.edu>

base: addr range: slight change to validity check
The validity check is being changed from < to <= since the end of the range
is considered to be a part of it.

10434:63ed22c458e5 11-Oct-2014 Nilay Vaish <nilay@cs.wisc.edu>

base: misc: Add missing header file.

10422:148b96b7bc77 01-Oct-2014 Andreas Hansson <andreas.hansson@arm.com>

misc: Fix issues identified by static analysis

Another bunch of issues addressed.

10412:6400a2ab4e22 27-Sep-2014 Andreas Hansson <andreas.hansson@arm.com>

misc: Fix a bunch of minor issues identified by static analysis

Add some missing initialisation, and fix a handful benign resource
leaks (including some false positives).

10400:0655a3d869ad 24-Apr-2014 Stephan Diestelhorst <stephan.diestelhorst@arm.com>

misc: Add functions for doing popcount and power-of-two checking

Adds two public domain algorithms for determining number of set bits and also
whether a value is a power of two, uses the builtin that is available in GCC
and clang for popcount.

10386:c81407818741 20-Sep-2014 Andreas Hansson <andreas.hansson@arm.com>

base: Clean up redundant string functions and use C++11

This patch does a bit of housekeeping on the string helper functions
and relies on the C++11 standard library where possible. It also does
away with our custom string hash as an implementation is already part
of the standard library.

10385:3f943443ae30 20-Sep-2014 Andrew Bardsley <Andrew.Bardsley@arm.com>

base: Add getSectionNames to IniFile

Add an accessor to IniFile to list all the sections in the file.

10377:434228c914e5 19-Sep-2014 Andreas Hansson <andreas.hansson@arm.com>

base: Ensure the CP annotation compiles again

A bit of revamping to get the CP annotate functionality to compile.

10375:b1bc989611da 19-Sep-2014 Andreas Hansson <andreas.hansson@arm.com>

misc: Restore ostream flags where needed

This patch ensures we adhere to the normal ostream usage rules, and
restore the flags after modifying them.

10374:1813597a92ec 19-Sep-2014 Andreas Hansson <andreas.hansson@arm.com>

stats: Fix flow-control bug in Vector2D printing

10373:342348537a53 19-Sep-2014 Andreas Hansson <andreas.hansson@arm.com>

misc: Remove assertions ensuring unsigned values >= 0

10360:919c02740209 09-Sep-2014 Andreas Hansson <andreas.hansson@arm.com>

misc: Fix a number of unitialised variables and members

Static analysis unearther a bunch of uninitialised variables and
members, and this patch addresses the problem. In all cases these
omissions seem benign in the end, but at least fixing them means less
false positives next time round.

10349:939094c17866 03-Sep-2014 Andreas Hansson <andreas.hansson@arm.com>

base: Use STL C++11 random number generation

This patch changes the random number generator from the in-house
Mersenne twister to an implementation relying entirely on C++11 STL.

The format for the checkpointing of the twister is simplified. As the
functionality was never used this should not matter. Note that this
patch does not actually make use of the checkpointing
functionality. As the random number generator is not thread safe, it
may be sensible to create one generator per thread, system, or even
object. Until this is decided the status quo is maintained in that no
generator state is part of the checkpoint.

10295:9b9ef42122bc 26-Aug-2014 Andreas Hansson <andreas.hansson@arm.com>

base: Add const to intmath and be more flexible with typing

This patch ensures the functions can be used on const variables.

10292:933dfb9d8279 26-Aug-2014 Andreas Sandberg <Andreas.Sandberg@ARM.com>

base: Replace the internal varargs stuff with C++11 constructs

We currently use our own home-baked support for type-safe variadic
functions. This is confusing and somewhat limited (e.g., cprintf only
supports a limited number of arguments). This changeset converts all
uses of our internal varargs support to use C++11 variadic macros.

10291:56772eb01583 26-Aug-2014 Andreas Sandberg <Andreas.Sandberg@ARM.com>

base: Add compiler macros for C++11 final/override

Add the macros M5_ATTR_FINAL and M5_ATTR_OVERRIDE which are defined to
final and override respectively if supported by the compiler. This is
done to allow a smooth transition to gcc >= 4.7.

10289:4593282280e4 26-Aug-2014 Andreas Sandberg <Andreas.Sandberg@ARM.com>

base: Add a static assert to check bit union ranges

If a bit field in a bit union specified as Bitfield<LSB, MSB> instead
of Bitfield<MSB, LSB> the code silently fails and the field is read as
zero. This changeset introduces a static assert that tests, at compile
time, that the bit order is correct.

10277:ef888b246cd0 13-Aug-2014 Andreas Sandberg <Andreas.Sandberg@ARM.com>

base: Remove unused M5_PRAGMA_NORETURN

The M5_PRAGMA_NORETURN macro was only used in for
__exit_message. Since the macro only holds a stub definition and all
functions with noreturn semantics use the M5_ATTR_NORETURN, this
macros is completely redundant.

10276:4cbfdcdb2144 13-Aug-2014 Andreas Sandberg <Andreas.Sandberg@ARM.com>

cpu: Don't forward declare RefCountingPtr

RefCountingPtr is sometimes forward declared to avoid having to
include refcnt.hh. This does not work since we typically return
instances of RefCountingPtr rather than references to instances. The
only reason this currently works is that we include refcnt.hh in
cprintf.hh, which "leaks" the header to most other source files. This
changeset replaces such forward declarations with an include of
refcnt.hh.

10265:0d0be755dda8 10-Aug-2014 Andreas Hansson <andreas.hansson@arm.com>

base: Remove unused files

A bit of pruning

10259:ebb376f73dd2 23-Jul-2014 Andrew Bardsley <Andrew.Bardsley@arm.com>

cpu: `Minor' in-order CPU model

This patch contains a new CPU model named `Minor'. Minor models a four
stage in-order execution pipeline (fetch lines, decompose into
macroops, decompose macroops into microops, execute).

The model was developed to support the ARM ISA but should be fixable
to support all the remaining gem5 ISAs. It currently also works for
Alpha, and regressions are included for ARM and Alpha (including Linux
boot).

Documentation for the model can be found in src/doc/inside-minor.doxygen and
its internal operations can be visualised using the Minorview tool
utils/minorview.py.

Minor was designed to be fairly simple and not to engage in a lot of
instruction annotation. As such, it currently has very few gathered
stats and may lack other gem5 features.

Minor is faster than the o3 model. Sample results:

Benchmark | Stat host_seconds (s)
---------------+--------v--------v--------
(on ARM, opt) | simple | o3 | minor
| timing | timing | timing
---------------+--------+--------+--------
10.linux-boot | 169 | 1883 | 1075
10.mcf | 117 | 967 | 491
20.parser | 668 | 6315 | 3146
30.eon | 542 | 3413 | 2414
40.perlbmk | 2339 | 20905 | 11532
50.vortex | 122 | 1094 | 588
60.bzip2 | 2045 | 18061 | 9662
70.twolf | 207 | 2736 | 1036


/gem5/build_opts/ALPHA
/gem5/build_opts/ARM
/gem5/configs/common/CpuConfig.py
trace.hh
/gem5/src/cpu/SConscript
/gem5/src/cpu/TimingExpr.py
/gem5/src/cpu/minor/MinorCPU.py
/gem5/src/cpu/minor/SConscript
/gem5/src/cpu/minor/SConsopts
/gem5/src/cpu/minor/activity.cc
/gem5/src/cpu/minor/activity.hh
/gem5/src/cpu/minor/buffers.hh
/gem5/src/cpu/minor/cpu.cc
/gem5/src/cpu/minor/cpu.hh
/gem5/src/cpu/minor/decode.cc
/gem5/src/cpu/minor/decode.hh
/gem5/src/cpu/minor/dyn_inst.cc
/gem5/src/cpu/minor/dyn_inst.hh
/gem5/src/cpu/minor/exec_context.hh
/gem5/src/cpu/minor/execute.cc
/gem5/src/cpu/minor/execute.hh
/gem5/src/cpu/minor/fetch1.cc
/gem5/src/cpu/minor/fetch1.hh
/gem5/src/cpu/minor/fetch2.cc
/gem5/src/cpu/minor/fetch2.hh
/gem5/src/cpu/minor/func_unit.cc
/gem5/src/cpu/minor/func_unit.hh
/gem5/src/cpu/minor/lsq.cc
/gem5/src/cpu/minor/lsq.hh
/gem5/src/cpu/minor/pipe_data.cc
/gem5/src/cpu/minor/pipe_data.hh
/gem5/src/cpu/minor/pipeline.cc
/gem5/src/cpu/minor/pipeline.hh
/gem5/src/cpu/minor/scoreboard.cc
/gem5/src/cpu/minor/scoreboard.hh
/gem5/src/cpu/minor/stats.cc
/gem5/src/cpu/minor/stats.hh
/gem5/src/cpu/minor/trace.hh
/gem5/src/cpu/pred/SConscript
/gem5/src/cpu/static_inst.hh
/gem5/src/cpu/timing_expr.cc
/gem5/src/cpu/timing_expr.hh
/gem5/src/doc/inside-minor.doxygen
/gem5/src/sim/SConscript
/gem5/src/sim/TickedObject.py
/gem5/src/sim/ticked_object.cc
/gem5/src/sim/ticked_object.hh
/gem5/util/minorview.py
/gem5/util/minorview/__init__.py
/gem5/util/minorview/blobs.py
/gem5/util/minorview/colours.py
/gem5/util/minorview/minor.pic
/gem5/util/minorview/model.py
/gem5/util/minorview/parse.py
/gem5/util/minorview/point.py
/gem5/util/minorview/view.py
10252:c625a3c51bac 09-Jul-2014 Anthony Gutierrez <atgutier@umich.edu>

base: fix operator== for comparing EthAddr objects

this operator uses memcmp() to detect if two EthAddr object have the same
address, however memcmp() will return 0 if all bytes are equal. operator==
returns the return value of memcmp() to indicate whether or not two
address are equal. this is incorrect as it will always give the opposite of
the intended behavior. this patch fixes that problem.

10251:878f2f30b12d 02-Jul-2014 Anthony Gutierrez <atgutier@umich.edu>

base: fix some bugs in EthAddr

per the IEEE 802 spec:
1) fixed broadcast() to ensure that all bytes are equal to 0xff.
2) fixed unicast() to ensure that bit 0 of the first byte is equal to 0
3) fixed multicast() to ensure that bit 0 of the first byte is equal to 1, and
that it is not a broadcast.

also the constructors in EthAddr are fixed so that all bytes of data are
initialized.

10231:cb2e6950956d 31-May-2014 Steve Reinhardt <steve.reinhardt@amd.com>

style: eliminate equality tests with true and false

Using '== true' in a boolean expression is totally redundant,
and using '== false' is pretty verbose (and arguably less
readable in most cases) compared to '!'.

It's somewhat of a pet peeve, perhaps, but I had some time
waiting for some tests to run and decided to clean these up.

Unfortunately, SLICC appears not to have the '!' operator,
so I had to leave the '== false' tests in the SLICC code.

10191:3ab094e72dad 09-May-2014 Stephan Diestelhorst <stephan.diestelhorst@arm.com>

stats: Method stats source

This source for stats binds an object and a method / function from the object
to a stats object. This allows pulling out stats from object methods without
needing to go through a global, or static shim.

Syntax is somewhat unpleasant, but the templates and method pointer type
specification were quite tricky. Interface is very clean though; and similar
to .functor

10171:a9be596271b7 23-Apr-2014 Curtis Dunham <Curtis.Dunham@arm.com>

base: explicitly suggest potential use of 'All' debug flags

Without this declaration, new clangs will complain about this value
being unused. It has no explicit use in the codebase, but it can be
useful to turn on all debugging flags while in a debugger to greatly
increase simulator verbosity.

10156:37d20d5c5bed 09-Apr-2014 Andreas Sandberg <andreas@sandberg.pp.se>

dev: Protect PollEvent processing when running in parallel mode

The calling thread is undefined when the PollQueue services events.
This implies that PollEvents need to handle the case where they are
processed from a different thread than the thread that created the
event. This changeset adds temporary event queue migrations to the VNC
server, the ethernet tap device, and the terminal to protect them from
inter-thread calls.

10125:615962ba6d05 23-Mar-2014 Andreas Hansson <andreas.hansson@arm.com>

base: Fix error message time unit (cycle -> tick)

This patch fixes the unit used in all error messages.

10105:9c37adf17edf 07-Mar-2014 Stephan Diestelhorst <stephan.diestelhorst@arm.com>

misc: Add panic_if / fatal_if / chatty_assert

This snippet can be used to replace if + {panics, fatals, asserts} constructs.
The idea is to have both the condition checking and a verbose printout in a single statement. The interface is as follows:

panic_if(foo != bar, "These should be equal: foo %i bar %i", foo, bar);
fatal_if(foo != bar, "These should be equal: foo %i bar %i", foo, bar);
chatty_assert(foo == bar, "These should be equal: foo %i bar %i", foo, bar);

10104:ff709c429b7b 07-Mar-2014 Mitch Hayenga <mitch.hayenga@arm.com>

scons: Fixes uninitialized warnings issued by clang

Small fixes to appease recent clang versions.

10060:f60cd60445b7 06-Feb-2014 Nilay Vaish <nilay@cs.wisc.edu>

base: calls abort() from fatal
Currently fatal() ends the simulation in a normal fashion. This results in
the call stack getting lost when using a debugger and it is not always
possible to debug the simulation just from the information provided by the
printed error message. Even though the error is likely due to a user's fault,
the information available should not be thrown away. Hence, this patch to
call abort() from fatal().

10049:801519c624e4 28-Jan-2014 Mitch Hayenga <mitch.hayenga+gem5@gmail.com>

base: Fix race condition in the socket listen function

gem5 makes the incorrect assumption that by binding a socket, it
effectively has allocated a port. Linux only allocates ports once you call
listen on the given socket, not when you call bind. So even if the port was
free when bind was called, another process (gem5 instance) could race in
between the bind & listen calls and steal the port. In the current code, if
the call to bind fails due to the port being in use (EADDRINUSE), gem5 retries
for a different port. However if listen fails, gem5 just panics. The fix is
testing the return value of listen and re-trying if it was due to EADDRINUSE.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>

10037:5cac77888310 24-Jan-2014 ARM gem5 Developers

arm: Add support for ARMv8 (AArch64 & AArch32)

Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64
kernel you are restricted to AArch64 user-mode binaries. This will be addressed
in a later patch.

Note: Virtualization is only supported in AArch32 mode. This will also be fixed
in a later patch.

Contributors:
Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation)
Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation)
Mbou Eyole (AArch64 NEON, validation)
Ali Saidi (AArch64 Linux support, code integration, validation)
Edmund Grimley-Evans (AArch64 FP)
William Wang (AArch64 Linux support)
Rene De Jong (AArch64 Linux support, performance opt.)
Matt Horsnell (AArch64 MP, validation)
Matt Evans (device models, code integration, validation)
Chris Adeniyi-Jones (AArch64 syscall-emulation)
Prakash Ramrakhyani (validation)
Dam Sunwoo (validation)
Chander Sudanthi (validation)
Stephan Diestelhorst (validation)
Andreas Hansson (code integration, performance opt.)
Eric Van Hensbergen (performance opt.)
Gabe Black


/gem5/configs/common/FSConfig.py
/gem5/configs/common/O3_ARM_v7a.py
/gem5/configs/common/Options.py
/gem5/configs/common/cpu2000.py
/gem5/configs/example/fs.py
/gem5/configs/example/se.py
/gem5/ext/libelf/elf_common.h
/gem5/src/arch/arm/ArmISA.py
/gem5/src/arch/arm/ArmSystem.py
/gem5/src/arch/arm/ArmTLB.py
/gem5/src/arch/arm/SConscript
/gem5/src/arch/arm/decoder.cc
/gem5/src/arch/arm/decoder.hh
/gem5/src/arch/arm/faults.cc
/gem5/src/arch/arm/faults.hh
/gem5/src/arch/arm/insts/branch64.cc
/gem5/src/arch/arm/insts/branch64.hh
/gem5/src/arch/arm/insts/data64.cc
/gem5/src/arch/arm/insts/data64.hh
/gem5/src/arch/arm/insts/fplib.cc
/gem5/src/arch/arm/insts/fplib.hh
/gem5/src/arch/arm/insts/macromem.cc
/gem5/src/arch/arm/insts/macromem.hh
/gem5/src/arch/arm/insts/mem.cc
/gem5/src/arch/arm/insts/mem64.cc
/gem5/src/arch/arm/insts/mem64.hh
/gem5/src/arch/arm/insts/misc.cc
/gem5/src/arch/arm/insts/misc.hh
/gem5/src/arch/arm/insts/misc64.cc
/gem5/src/arch/arm/insts/misc64.hh
/gem5/src/arch/arm/insts/neon64_mem.hh
/gem5/src/arch/arm/insts/pred_inst.hh
/gem5/src/arch/arm/insts/static_inst.cc
/gem5/src/arch/arm/insts/static_inst.hh
/gem5/src/arch/arm/insts/vfp.cc
/gem5/src/arch/arm/insts/vfp.hh
/gem5/src/arch/arm/interrupts.cc
/gem5/src/arch/arm/interrupts.hh
/gem5/src/arch/arm/intregs.hh
/gem5/src/arch/arm/isa.cc
/gem5/src/arch/arm/isa.hh
/gem5/src/arch/arm/isa/bitfields.isa
/gem5/src/arch/arm/isa/decoder/aarch64.isa
/gem5/src/arch/arm/isa/decoder/arm.isa
/gem5/src/arch/arm/isa/decoder/decoder.isa
/gem5/src/arch/arm/isa/decoder/thumb.isa
/gem5/src/arch/arm/isa/formats/aarch64.isa
/gem5/src/arch/arm/isa/formats/branch.isa
/gem5/src/arch/arm/isa/formats/formats.isa
/gem5/src/arch/arm/isa/formats/fp.isa
/gem5/src/arch/arm/isa/formats/mem.isa
/gem5/src/arch/arm/isa/formats/misc.isa
/gem5/src/arch/arm/isa/formats/neon64.isa
/gem5/src/arch/arm/isa/formats/uncond.isa
/gem5/src/arch/arm/isa/formats/unimp.isa
/gem5/src/arch/arm/isa/includes.isa
/gem5/src/arch/arm/isa/insts/aarch64.isa
/gem5/src/arch/arm/isa/insts/branch.isa
/gem5/src/arch/arm/isa/insts/branch64.isa
/gem5/src/arch/arm/isa/insts/data.isa
/gem5/src/arch/arm/isa/insts/data64.isa
/gem5/src/arch/arm/isa/insts/div.isa
/gem5/src/arch/arm/isa/insts/fp.isa
/gem5/src/arch/arm/isa/insts/fp64.isa
/gem5/src/arch/arm/isa/insts/insts.isa
/gem5/src/arch/arm/isa/insts/ldr.isa
/gem5/src/arch/arm/isa/insts/ldr64.isa
/gem5/src/arch/arm/isa/insts/m5ops.isa
/gem5/src/arch/arm/isa/insts/macromem.isa
/gem5/src/arch/arm/isa/insts/mem.isa
/gem5/src/arch/arm/isa/insts/misc.isa
/gem5/src/arch/arm/isa/insts/misc64.isa
/gem5/src/arch/arm/isa/insts/neon.isa
/gem5/src/arch/arm/isa/insts/neon64.isa
/gem5/src/arch/arm/isa/insts/neon64_mem.isa
/gem5/src/arch/arm/isa/insts/str.isa
/gem5/src/arch/arm/isa/insts/str64.isa
/gem5/src/arch/arm/isa/insts/swap.isa
/gem5/src/arch/arm/isa/operands.isa
/gem5/src/arch/arm/isa/templates/basic.isa
/gem5/src/arch/arm/isa/templates/branch64.isa
/gem5/src/arch/arm/isa/templates/data64.isa
/gem5/src/arch/arm/isa/templates/macromem.isa
/gem5/src/arch/arm/isa/templates/mem.isa
/gem5/src/arch/arm/isa/templates/mem64.isa
/gem5/src/arch/arm/isa/templates/misc.isa
/gem5/src/arch/arm/isa/templates/misc64.isa
/gem5/src/arch/arm/isa/templates/neon.isa
/gem5/src/arch/arm/isa/templates/neon64.isa
/gem5/src/arch/arm/isa/templates/templates.isa
/gem5/src/arch/arm/isa/templates/vfp.isa
/gem5/src/arch/arm/isa/templates/vfp64.isa
/gem5/src/arch/arm/isa_traits.hh
/gem5/src/arch/arm/linux/linux.cc
/gem5/src/arch/arm/linux/linux.hh
/gem5/src/arch/arm/linux/process.cc
/gem5/src/arch/arm/linux/process.hh
/gem5/src/arch/arm/linux/system.cc
/gem5/src/arch/arm/linux/system.hh
/gem5/src/arch/arm/locked_mem.hh
/gem5/src/arch/arm/miscregs.cc
/gem5/src/arch/arm/miscregs.hh
/gem5/src/arch/arm/nativetrace.cc
/gem5/src/arch/arm/pagetable.hh
/gem5/src/arch/arm/process.cc
/gem5/src/arch/arm/process.hh
/gem5/src/arch/arm/registers.hh
/gem5/src/arch/arm/remote_gdb.cc
/gem5/src/arch/arm/remote_gdb.hh
/gem5/src/arch/arm/stage2_lookup.cc
/gem5/src/arch/arm/stage2_lookup.hh
/gem5/src/arch/arm/stage2_mmu.cc
/gem5/src/arch/arm/stage2_mmu.hh
/gem5/src/arch/arm/system.cc
/gem5/src/arch/arm/system.hh
/gem5/src/arch/arm/table_walker.cc
/gem5/src/arch/arm/table_walker.hh
/gem5/src/arch/arm/tlb.cc
/gem5/src/arch/arm/tlb.hh
/gem5/src/arch/arm/types.hh
/gem5/src/arch/arm/utility.cc
/gem5/src/arch/arm/utility.hh
/gem5/src/arch/arm/vtophys.cc
loader/elf_object.cc
loader/elf_object.hh
loader/object_file.cc
loader/object_file.hh
/gem5/src/cpu/BaseCPU.py
/gem5/src/dev/arm/RealView.py
/gem5/src/dev/arm/SConscript
/gem5/src/dev/arm/generic_timer.cc
/gem5/src/dev/arm/generic_timer.hh
/gem5/src/dev/arm/gic_pl390.cc
/gem5/src/dev/arm/vgic.cc
/gem5/src/dev/arm/vgic.hh
/gem5/src/sim/System.py
/gem5/src/sim/process.cc
/gem5/src/sim/serialize.hh
/gem5/src/sim/system.cc
/gem5/src/sim/system.hh
/gem5/system/arm/aarch64_bootloader/LICENSE.txt
/gem5/system/arm/aarch64_bootloader/boot.S
/gem5/system/arm/aarch64_bootloader/makefile
/gem5/util/cpt_upgrader.py
/gem5/util/m5/m5op_arm_A64.S
10011:69bd1011dcf3 10-Jan-2014 Nilay Vaish <nilay@cs.wisc.edu>

stats: add function for adding two histograms
This patch adds a function to the HistStor class for adding two histograms.
This functionality is required for Ruby. It also adds support for printing
histograms in a single line.

9990:12a0efdde000 29-Nov-2013 Andreas Sandberg <andreas@sandberg.pp.se>

base: Fix race in PollQueue and remove SIGALRM workaround

There is a race between enabling asynchronous IO for a file descriptor
and IO events happening on that descriptor. A SIGIO won't normally be
delivered if an event is pending when asynchronous IO is
enabled. Instead, the signal will be raised the next time there is an
event on the FD. This changeset simulates a SIGIO by setting the
async_io flag when setting up asynchronous IO for an FD. This causes
the main event loop to poll all file descriptors to check for pending
IO. As a consequence of this, the old SIGALRM hack should no longer be
needed and is therefore removed.

9989:ba3be87e2a1d 29-Nov-2013 Andreas Sandberg <andreas@sandberg.pp.se>

base: Clean up signal handling

The PollEvent class dynamically installs a SIGIO and SIGALRM handler
when a file handler is registered. Most signal handlers currently get
registered in the initSignals() function. This changeset moves the
SIGIO/SIGALRM handlers to initSignals() to live with the other signal
handlers. The original code installs SIGIO and SIGALRM with the
SA_RESTART option to prevent syscalls from returning EINTR. This
changeset consistently uses this flag for all signal handlers to
ensure that other signals that trigger asynchronous behavior (e.g.,
statistics dumping) do not cause undesirable EINTR returns.

9983:2cce74fe359e 25-Nov-2013 Steve Reinhardt <stever@gmail.com>, Nilay Vaish <nilay@cs.wisc.edu>, Ali Saidi <Ali.Saidi@ARM.com>

sim: simulate with multiple threads and event queues
This patch adds support for simulating with multiple threads, each of
which operates on an event queue. Each sim object specifies which eventq
is would like to be on. A custom barrier implementation is being added
using which eventqs synchronize.

The patch was tested in two different configurations:
1. ruby_network_test.py: in this simulation L1 cache controllers receive
requests from the cpu. The requests are replied to immediately without
any communication taking place with any other level.
2. twosys-tsunami-simple-atomic: this configuration simulates a client-server
system which are connected by an ethernet link.

We still lack the ability to communicate using message buffers or ports. But
other things like simulation start and end, synchronizing after every quantum
are working.

Committed by: Nilay Vaish

9955:5d8722ab804b 31-Oct-2013 Geoffrey Blake <Geoffrey.Blake@arm.com>

base: Add support for ipv6 into inet.hh/inet.cc

9905:2a7c8ec11cff 07-Oct-2013 Andreas Sandberg <andreas@sandberg.pp.se>

base: Fix a potential race in PollQueue::setupAsyncIO

There is a potential race between enabling asynchronous IO and
selecting the target for the SIGIO signal. This changeset move the
F_SETOWN call to before the F_SETFL call that enables SIGIO
delivery. This ensures that signals are always sent to the correct
process.

9865:cc5797147e1c 09-Sep-2013 Nilay Vaish <nilay@cs.wisc.edu>

stats: add operator= for DataWrapVec class

gcc/g++ 4.4.7 complained about the operator= being undefined.
This changeset adds the operator.

9863:9483739f83ee 06-Sep-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: network: convert to gem5 style stats

9857:8301f882a916 06-Sep-2013 Nilay Vaish <nilay@cs.wisc.edu>

stats: adds a Formula operator for division

9850:87d6b41749e9 04-Sep-2013 Andreas Hansson <andreas.hansson@arm.com>

arch: Resurrect the NOISA build target and rename it NULL

This patch makes it possible to once again build gem5 without any
ISA. The main purpose is to enable work around the interconnect and
memory system without having to build any CPU models or device models.

The regress script is updated to include the NULL ISA target. Currently
no regressions make use of it, but all the testers could (and perhaps
should) transition to it.

9848:a733a8eb6363 04-Sep-2013 Andreas Hansson <andreas.hansson@arm.com>

arch: Header clean up for NOISA resurrection

This patch is a first step to getting NOISA working again. A number of
redundant includes make life more difficult than it has to be and this
patch simply removes them. There are also some redundant forward
declarations removed.

9846:a4b5fd8937c9 04-Sep-2013 Andreas Hansson <andreas.hansson@arm.com>

scons: Enable build on OSX

This patch changes the SConscript to build gem5 with libc++ on OSX as
the conventional libstdc++ does not have the C++11 constructs that the
current code base makes use of (e.g. std::forward).

Since this was the last use of the transitional TR1, the unordered map
and set header can now be simplified as well.

9839:97ef15178067 20-Aug-2013 Andreas Hansson <andreas.hansson@arm.com>

base: Fix VectorPrint initialisation

This patch changes how the initialisation of the VectorPrint struct is
done so that gcc 4.4 is happy again.

9828:4807b780ed0a 19-Aug-2013 Sascha Bischoff <sascha.bischoff@arm.com>

stats: Fix issue when printing 2D vectors

This patch addresses an issue with the text-based stats output which
resulted in Vector2D stats being printed without subnames in the event
that one of the dimensions was of length 1.

This patch also fixes the total printing for the 2D vector. Previously
totals were printed without explicitly stating that a total was being
printed. This has been rectified in this patch.

9810:e895db06e69f 15-Jul-2013 Deyuan Guo <guodeyuan@tsinghua.org.cn>

loader: Load weak symbols for function tracing

9780:704c03c216f7 27-Jun-2013 Andreas Hansson <andreas.hansson@arm.com>

base: Fix address range granularity calculation

This patch fixes a bug in the granularity calculation. For example, if
the high bit is 6 (counting from 0) and we have one interleaving bit,
then the granularity is now 2 ** (6 - 1 + 1) = 64.

9777:68b47cb5c0a6 27-Jun-2013 Sascha Bischoff <sascha.bischoff@arm.com>

stats: Remove printing of SparseHist total

This patch removes the printing of the SparseHist total in the
stats.txt output file. This has been removed as a sparse histogram has
no total, and therefore this was printing out the value of a
non-local, unrelated variable.

9743:436a74146cbc 09-Jun-2013 Nilay Vaish <nilay@cs.wisc.edu>

stats: allow printing vectors on a single line
This patch adds a new flag to specify if the data values for a given vector
should be printed in one line in the stats.txt file. The default behavior
will be to print the data in multiple lines. It makes changes to print
functions to enforce this behavior.

9641:2285b98847d7 17-Apr-2013 Deyuan Guo <guodeyuan@tsinghua.org.cn>, Nilay Vaish <nilay@cs.wisc.edu>

base: load weak symbols from object file
Without loading weak symbols into gem5, some function names and the given PC
cannot correspond correctly, because the binding attributes of unction names
in an ELF file are not only STB_GLOBAL or STB_LOCAL, but also STB_WEAK. This
patch adds a function for loading weak symbols.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>

9581:e507dc092ca3 07-Mar-2013 Andreas Hansson <andreas.hansson@arm.com>

base: Fix address range granularity calculations

This patch fixes a bug in the address range granularity
calculations. Previously it incorrectly used the high bit to establish
the size of the regions created, when it should really be looking at
the low bit.

9557:8666e81607a6 19-Feb-2013 Andreas Hansson <andreas.hansson@arm.com>

scons: Fix warnings issued by clang 3.2svn (XCode 4.6)

This patch fixes the warnings that clang3.2svn emit due to the "-Wall"
flag. There is one case of an uninitialised value in the ARM neon ISA
description, and then a whole range of unused private fields that are
pruned.

9554:406fbcf60223 19-Feb-2013 Andreas Hansson <andreas.hansson@arm.com>

scons: Add warning for missing declarations

This patch enables warnings for missing declarations. To avoid issues
with SWIG-generated code, the warning is only applied to non-SWIG
code.

9550:e0e2c8f83d08 19-Feb-2013 Andreas Hansson <andreas.hansson@arm.com>

scons: Fix up numerous warnings about name shadowing

This patch address the most important name shadowing warnings (as
produced when using gcc/clang with -Wshadow). There are many
locations where constructor parameters and function parameters shadow
local variables, but these are left unchanged.

9541:e476d01bc6a4 19-Feb-2013 Andreas Hansson <andreas.hansson@arm.com>

base: Fix a bug in the address interleaving

This patch fixes a minor (but important) typo in the matching of an
address to an interleaved range.

9538:182d67b5b57a 15-Feb-2013 Anthony Gutierrez <atgutier@umich.edu>

loader: add a flattened device tree blob (dtb) object

this adds a dtb_object so the loader can load in the dtb
file for linux/android ARM kernels.

9500:9c3e3d1c7a87 10-Feb-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: replace Time with Cycles in Message class
Concomitant changes are being committed as well, including the io operator<<
for the Cycles class.

9498:66eb324d4de1 10-Feb-2013 Nilay Vaish <nilay@cs.wisc.edu>

base: add some mathematical operators to Cycles class

9420:965d857ac791 07-Jan-2013 Andreas Hansson <andreas.hansson@arm.com>

scons: Enforce gcc >= 4.4 or clang >= 2.9 and c++0x support

This patch checks that the compiler in use is either gcc >= 4.4 or
clang >= 2.9. and enables building with --std=c++0x in all cases. As a
consequence, we can tidy up the hashmap and always have static_assert
available. If anyone wants to use alternative compilers, icc for
example supports c++0x to a similar level and could be added if
needed.

This patch opens up for a more elaborate use of c++0x features that
are present in gcc 4.4 and clang 2.9, e.g. auto typed variables,
variadic templates, rvalues and move semantics, and strongly typed
enums. There will be no going back on this one...

9419:54d5c0e5852a 07-Jan-2013 Andreas Hansson <andreas.hansson@arm.com>

scons: Remove stale compiler options

This patch simply prunes the SUNCC and ICC compiler options as they
are both sufficiently stale that they would have to be re-written from
scratch anyhow. The patch serves to clean things up before shifting to
a build environment that enforces basic c++11 compliance as done in
the following patch.

9412:190fd0e285f6 07-Jan-2013 Andreas Hansson <andreas.hansson@arm.com>

base: Add support for merging of interleaved address ranges

This patch adds support for merging a vector of interleaved address
ranges into a contigous range. The functionality will be used in the
interconnect and the PhysicalMemory to transform interleaved memory
ranges to contigous ranges before passing them on.

The actual use of the merging is appearing in future patches.

9411:22e15f9c3fda 07-Jan-2013 Andreas Hansson <andreas.hansson@arm.com>

mem: Add interleaving bits to the address ranges

This patch adds support for interleaving bits for the address
ranges. What was previously just a start and end address, now has an
additional three fields, for the high bit, and number of bits to use
for interleaving, and a match value to compare against. If the number
of interleaving bits is set to zero it is effectively disabled.

A number of convenience functions are added to the range to enquire
about the interleaving, its granularity and the number of stripes it
is part of.

9409:e399b6c18b76 07-Jan-2013 Andreas Hansson <andreas.hansson@arm.com>

base: Simplify the AddrRangeMap by removing unused code

This patch cleans up the AddrRangeMap in preparation for the addition
of interleaving by removing unused code. The non-const editions of
find are never used, and hence the duplication is not needed.

9405:c0a0593510db 07-Jan-2013 Andreas Hansson <andreas.hansson@arm.com>

base: Encapsulate the underlying fields in AddrRange

This patch makes the start and end address private in a move to
prevent direct manipulation and matching of ranges based on these
fields. This is done so that a transition to ranges with interleaving
support is possible.

As a result of hiding the start and end, a number of member functions
are needed to perform the comparisons and manipulations that
previously took place directly on the members. An accessor function is
provided for the start address, and a function is added to test if an
address is within a range. As a result of the latter the != and ==
operator is also removed in favour of the member function. A member
function that returns a string representation is also created to allow
debug printing.

In general, this patch does not add any functionality, but it does
take us closer to a situation where interleaving (and more cleverness)
can be added under the bonnet without exposing it to the user. More on
that in a later patch.

9398:6a348f61220c 07-Jan-2013 Andreas Hansson <andreas.hansson@arm.com>

mem: Add tracing support in the communication monitor

This patch adds packet tracing to the communication monitor using a
protobuf as the mechanism for creating the trace.

If no file is specified, then the tracing is disabled. If a file is
specified, then for every packet that is successfully sent, a protobuf
message is serialized to the file.

9356:b279bad40aa3 16-Nov-2012 Nilay Vaish <nilay@cs.wisc.edu>

sim: have a curTick per eventq
This patch adds a _curTick variable to an eventq. This variable is updated
whenever an event is serviced in function serviceOne(), or all events upto
a particular time are processed in function serviceEvents(). This change
helps when there are eventqs that do not make use of curTick for scheduling
events.

9338:97b4a2be1e5b 02-Nov-2012 Andreas Sandberg <Andreas.Sandberg@arm.com>

sim: Include object header files in SWIG interfaces

When casting objects in the generated SWIG interfaces, SWIG uses
classical C-style casts ( (Foo *)bar; ). In some cases, this can
degenerate into the equivalent of a reinterpret_cast (mainly if only a
forward declaration of the type is available). This usually works for
most compilers, but it is known to break if multiple inheritance is
used anywhere in the object hierarchy.

This patch introduces the cxx_header attribute to Python SimObject
definitions, which should be used to specify a header to include in
the SWIG interface. The header should include the declaration of the
wrapped object. We currently don't enforce header the use of the
header attribute, but a warning will be generated for objects that do
not use it.


/gem5/src/SConscript
/gem5/src/arch/alpha/AlphaInterrupts.py
/gem5/src/arch/alpha/AlphaSystem.py
/gem5/src/arch/alpha/AlphaTLB.py
/gem5/src/arch/arm/ArmInterrupts.py
/gem5/src/arch/arm/ArmNativeTrace.py
/gem5/src/arch/arm/ArmSystem.py
/gem5/src/arch/arm/ArmTLB.py
/gem5/src/arch/mips/MipsInterrupts.py
/gem5/src/arch/mips/MipsSystem.py
/gem5/src/arch/mips/MipsTLB.py
/gem5/src/arch/power/PowerInterrupts.py
/gem5/src/arch/power/PowerTLB.py
/gem5/src/arch/sparc/SparcInterrupts.py
/gem5/src/arch/sparc/SparcNativeTrace.py
/gem5/src/arch/sparc/SparcSystem.py
/gem5/src/arch/sparc/SparcTLB.py
/gem5/src/arch/x86/X86LocalApic.py
/gem5/src/arch/x86/X86NativeTrace.py
/gem5/src/arch/x86/X86System.py
/gem5/src/arch/x86/X86TLB.py
/gem5/src/arch/x86/bios/ACPI.py
/gem5/src/arch/x86/bios/E820.py
/gem5/src/arch/x86/bios/IntelMP.py
/gem5/src/arch/x86/bios/SMBios.py
CPA.py
vnc/Vnc.py
/gem5/src/cpu/BaseCPU.py
/gem5/src/cpu/CheckerCPU.py
/gem5/src/cpu/ExeTracer.py
/gem5/src/cpu/FuncUnit.py
/gem5/src/cpu/IntelTrace.py
/gem5/src/cpu/IntrControl.py
/gem5/src/cpu/LegionTrace.py
/gem5/src/cpu/NativeTrace.py
/gem5/src/cpu/inorder/InOrderCPU.py
/gem5/src/cpu/inorder/InOrderTrace.py
/gem5/src/cpu/inteltrace.hh
/gem5/src/cpu/o3/FUPool.py
/gem5/src/cpu/simple/AtomicSimpleCPU.py
/gem5/src/cpu/simple/BaseSimpleCPU.py
/gem5/src/cpu/simple/TimingSimpleCPU.py
/gem5/src/cpu/static_inst.hh
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.py
/gem5/src/cpu/testers/memtest/MemTest.py
/gem5/src/cpu/testers/networktest/NetworkTest.py
/gem5/src/cpu/testers/rubytest/RubyTester.py
/gem5/src/cpu/testers/traffic_gen/TrafficGen.py
/gem5/src/dev/BadDevice.py
/gem5/src/dev/CopyEngine.py
/gem5/src/dev/Device.py
/gem5/src/dev/DiskImage.py
/gem5/src/dev/Ethernet.py
/gem5/src/dev/Ide.py
/gem5/src/dev/Pci.py
/gem5/src/dev/Platform.py
/gem5/src/dev/SimpleDisk.py
/gem5/src/dev/Terminal.py
/gem5/src/dev/Uart.py
/gem5/src/dev/alpha/AlphaBackdoor.py
/gem5/src/dev/alpha/Tsunami.py
/gem5/src/dev/alpha/tsunami_io.hh
/gem5/src/dev/arm/RealView.py
/gem5/src/dev/arm/pl011.hh
/gem5/src/dev/arm/realview.hh
/gem5/src/dev/arm/timer_cpulocal.hh
/gem5/src/dev/copy_engine.hh
/gem5/src/dev/mips/Malta.py
/gem5/src/dev/mips/malta_io.hh
/gem5/src/dev/sparc/T1000.py
/gem5/src/dev/x86/Cmos.py
/gem5/src/dev/x86/I8042.py
/gem5/src/dev/x86/I82094AA.py
/gem5/src/dev/x86/I8237.py
/gem5/src/dev/x86/I8254.py
/gem5/src/dev/x86/I8259.py
/gem5/src/dev/x86/Pc.py
/gem5/src/dev/x86/PcSpeaker.py
/gem5/src/dev/x86/SouthBridge.py
/gem5/src/dev/x86/X86IntPin.py
/gem5/src/dev/x86/speaker.hh
/gem5/src/mem/AbstractMemory.py
/gem5/src/mem/AddrMapper.py
/gem5/src/mem/Bridge.py
/gem5/src/mem/Bus.py
/gem5/src/mem/CommMonitor.py
/gem5/src/mem/MemObject.py
/gem5/src/mem/SimpleDRAM.py
/gem5/src/mem/SimpleMemory.py
/gem5/src/mem/cache/BaseCache.py
/gem5/src/mem/cache/prefetch/Prefetcher.py
/gem5/src/mem/cache/tags/iic_repl/Repl.py
/gem5/src/mem/ruby/network/BasicLink.py
/gem5/src/mem/ruby/network/BasicRouter.py
/gem5/src/mem/ruby/network/Network.py
/gem5/src/mem/ruby/network/fault_model/FaultModel.py
/gem5/src/mem/ruby/network/garnet/BaseGarnetNetwork.py
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.py
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetRouter_d.py
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.py
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.py
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetRouter.py
/gem5/src/mem/ruby/network/simple/SimpleLink.py
/gem5/src/mem/ruby/network/simple/SimpleNetwork.py
/gem5/src/mem/ruby/profiler/Profiler.py
/gem5/src/mem/ruby/slicc_interface/Controller.py
/gem5/src/mem/ruby/system/Cache.py
/gem5/src/mem/ruby/system/DirectoryMemory.py
/gem5/src/mem/ruby/system/MemoryControl.py
/gem5/src/mem/ruby/system/RubyMemoryControl.py
/gem5/src/mem/ruby/system/RubySystem.py
/gem5/src/mem/ruby/system/Sequencer.py
/gem5/src/mem/ruby/system/WireBuffer.py
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/python/m5/SimObject.py
/gem5/src/sim/BaseTLB.py
/gem5/src/sim/ClockedObject.py
/gem5/src/sim/InstTracer.py
/gem5/src/sim/Process.py
/gem5/src/sim/Root.py
/gem5/src/sim/System.py
9334:0a12b040494a 02-Nov-2012 Andreas Sandberg <Andreas.Sandberg@arm.com>

base: Add missing header file to addr_range.hh.

9331:6630b3ffe7c0 02-Nov-2012 Chander Sudanthi <chander.sudanthi@arm.com>

base: Fix a few incorrectly handled print format cases

This patch ensures cases like %0.6u, %06f, and %.6u are processed correctly.
The case like %06f is ambiguous and was made to match printf. Also, this patch
removes the goto statement in cprintf.cc in favor of a function call.

9330:4a3269a11230 02-Nov-2012 Chander Sudanthi <chander.sudanthi@arm.com>

base: split out the VncServer into a VncInput and Server classes

This patch adds a VncInput base class which VncServer inherits from.
Another class can implement the same interface and be used instead
of the VncServer, for example a class that replays Vnc traffic.

9279:8b16c3804bda 15-Oct-2012 Andreas Hansson <andreas.hansson@arm.com>

Mem: Use range operations in bus in preparation for striping

This patch transitions the bus to use the AddrRange operations instead
of directly accessing the start and end. The change facilitates the
move to a more elaborate AddrRange class that also supports address
striping in the bus by specifying interleaving bits in the ranges.

Two new functions are added to the AddrRange to determine if two
ranges intersect, and if one is a subset of another. The bus
propagation of address ranges is also tweaked such that an update is
only propagated if the bus received information from all the
downstream slave modules. This avoids the iteration and need for the
cycle-breaking scheme that was previously used.

9261:f795ce1feb5b 25-Sep-2012 Dam Sunwoo <dam.sunwoo@arm.com>

ARM: added support for flattened device tree blobs

Newer Linux kernels require DTB (device tree blobs) to specify platform
configurations. The input DTB filename can be specified through gem5 parameters
in LinuxArmSystem.

9255:60f043573a65 25-Sep-2012 Andreas Sandberg <Andreas.Sandberg@arm.com>

base: Check for static_assert support and provide fallback

C++11 has support for static_asserts to provide compile-time assertion
checking. This is very useful when testing, for example, structure
sizes to make sure that the compiler got the right alignment or vector
sizes.

9235:5aa4896ed55a 19-Sep-2012 Andreas Hansson <andreas.hansson@arm.com>

AddrRange: Transition from Range<T> to AddrRange

This patch takes the final plunge and transitions from the templated
Range class to the more specific AddrRange. In doing so it changes the
obvious Range<Addr> to AddrRange, and also bumps the range_map to be
AddrRangeMap.

In addition to the obvious changes, including the removal of redundant
includes, this patch also does some house keeping in preparing for the
introduction of address interleaving support in the ranges. The Range
class is also stripped of all the functionality that is never used.

9234:49df6e096beb 19-Sep-2012 Andreas Hansson <andreas.hansson@arm.com>

AddrRange: Simplify Range by removing stream input/output

This patch simplifies the Range class in preparation for the
introduction of a more specific AddrRange class that allows
interleaving/striping.

The only place where the parsing was used was in the unit test.

9233:d45a88688bd7 19-Sep-2012 Andreas Hansson <andreas.hansson@arm.com>

AddrRange: Remove unused range_multimap

This patch simply removes the unused range_multimap in preparation for
a more specific AddrRangeMap that also allows interleaving in addition
to pure ranges.

9224:b0539d08bda8 14-Sep-2012 Andreas Hansson <andreas.hansson@arm.com>

scons: Use c++0x with gcc >= 4.4 instead of 4.6

This patch shifts the version of gcc for which we enable c++0x from
4.6 to 4.4 The more long term plan is to see what the c++0x features
can bring and what level of support would be enabled simply by bumping
the required version of gcc from 4.3 to 4.4.

A few minor things had to be fixed in the code base, most notably the
choice of a hashmap implementation. In the Ruby Sequencer there were
also a few minor issues that gcc 4.4 was not too happy about.

9202:5c8e92f3d6f7 10-Sep-2012 Palle Lyckegaard <palle@lyckegaard.dk>

NetBSD: Build on NetBSD

Minor patch against so building on NetBSD is possible.

9201:be0f1019d442 10-Sep-2012 Andreas Hansson <andreas.hansson@arm.com>

AddrRange: Remove the unused range_ops header

This patch prunes the range_ops header that is no longer used. The
bridge used it to do filtering of address ranges, but this is changed
since quite some time.

Ultimately this patch aims to simplify the handling of ranges before
specialising the AddrRange to an AddrRegion that also allows striping
bits to be selected.

9200:16de812c5f53 10-Sep-2012 Andreas Hansson <andreas.hansson@arm.com>

Inet: Remove the SackRange and its use

This patch aims to simplify the use of the Range class before
introducing a more elaborate AddrRegion to replace the AddrRange. The
SackRange is the only use of the range class besides address ranges,
and the removal of this use makes for an easier modification of the
range class.

The functionlity that is removed with this patch is not used anywhere
throughout the code base.

9186:635a7cdec721 07-Sep-2012 Ali Saidi <Ali.Saidi@ARM.com>

loader: initialize all memory in the ObjectFile objects.

Some bare metal build flows seem to build binaries that we aren't necessarily
expecting. Initialize everything to 0, so we don't make any assumptions about
what is or isn't in the binary.

9184:a1a8f137b796 07-Sep-2012 Andreas Hansson <andreas.hansson@arm.com>

Param: Transition to Cycles for relevant parameters

This patch is a first step to using Cycles as a parameter type. The
main affected modules are the CPUs and the Ruby caches. There are
definitely plenty more places that are affected, but this patch serves
as a starting point to making the transition.

An important part of this patch is to actually enable parameters to be
specified as Param.Cycles which involves some changes to params.py.

9180:ee8d7a51651d 28-Aug-2012 Andreas Hansson <andreas.hansson@arm.com>

Clock: Add a Cycles wrapper class and use where applicable

This patch addresses the comments and feedback on the preceding patch
that reworks the clocks and now more clearly shows where cycles
(relative cycle counts) are used to express time.

Instead of bumping the existing patch I chose to make this a separate
patch, merely to try and focus the discussion around a smaller set of
changes. The two patches will be pushed together though.

This changes done as part of this patch are mostly following directly
from the introduction of the wrapper class, and change enough code to
make things compile and run again. There are definitely more places
where int/uint/Tick is still used to represent cycles, and it will
take some time to chase them all down. Similarly, a lot of parameters
should be changed from Param.Tick and Param.Unsigned to
Param.Cycles.

In addition, the use of curTick is questionable as there should not be
an absolute cycle. Potential solutions can be built on top of this
patch. There is a similar situation in the o3 CPU where
lastRunningCycle is currently counting in Cycles, and is still an
absolute time. More discussion to be had in other words.

An additional change that would be appropriate in the future is to
perform a similar wrapping of Tick and probably also introduce a
Ticks class along with suitable operators for all these classes.


/gem5/src/arch/alpha/mmapped_ipr.hh
/gem5/src/arch/alpha/utility.hh
/gem5/src/arch/arm/mmapped_ipr.hh
/gem5/src/arch/arm/table_walker.cc
/gem5/src/arch/arm/utility.hh
/gem5/src/arch/mips/isa.cc
/gem5/src/arch/mips/isa.hh
/gem5/src/arch/mips/mmapped_ipr.hh
/gem5/src/arch/mips/mt.hh
/gem5/src/arch/mips/utility.cc
/gem5/src/arch/power/mmapped_ipr.hh
/gem5/src/arch/power/utility.hh
/gem5/src/arch/sparc/mmapped_ipr.hh
/gem5/src/arch/sparc/tlb.cc
/gem5/src/arch/sparc/tlb.hh
/gem5/src/arch/sparc/ua2005.cc
/gem5/src/arch/sparc/utility.hh
/gem5/src/arch/x86/mmapped_ipr.hh
/gem5/src/arch/x86/utility.cc
types.hh
/gem5/src/cpu/BaseCPU.py
/gem5/src/cpu/base.hh
/gem5/src/cpu/checker/thread_context.hh
/gem5/src/cpu/inorder/cpu.cc
/gem5/src/cpu/inorder/cpu.hh
/gem5/src/cpu/inorder/pipeline_stage.cc
/gem5/src/cpu/inorder/resource.cc
/gem5/src/cpu/inorder/resource.hh
/gem5/src/cpu/inorder/resource_pool.cc
/gem5/src/cpu/inorder/resource_pool.hh
/gem5/src/cpu/inorder/resources/agen_unit.cc
/gem5/src/cpu/inorder/resources/agen_unit.hh
/gem5/src/cpu/inorder/resources/branch_predictor.cc
/gem5/src/cpu/inorder/resources/branch_predictor.hh
/gem5/src/cpu/inorder/resources/cache_unit.cc
/gem5/src/cpu/inorder/resources/cache_unit.hh
/gem5/src/cpu/inorder/resources/decode_unit.cc
/gem5/src/cpu/inorder/resources/decode_unit.hh
/gem5/src/cpu/inorder/resources/execution_unit.cc
/gem5/src/cpu/inorder/resources/execution_unit.hh
/gem5/src/cpu/inorder/resources/fetch_seq_unit.cc
/gem5/src/cpu/inorder/resources/fetch_seq_unit.hh
/gem5/src/cpu/inorder/resources/fetch_unit.cc
/gem5/src/cpu/inorder/resources/fetch_unit.hh
/gem5/src/cpu/inorder/resources/graduation_unit.cc
/gem5/src/cpu/inorder/resources/graduation_unit.hh
/gem5/src/cpu/inorder/resources/inst_buffer.cc
/gem5/src/cpu/inorder/resources/inst_buffer.hh
/gem5/src/cpu/inorder/resources/mem_dep_unit.hh
/gem5/src/cpu/inorder/resources/mult_div_unit.cc
/gem5/src/cpu/inorder/resources/mult_div_unit.hh
/gem5/src/cpu/inorder/resources/tlb_unit.cc
/gem5/src/cpu/inorder/resources/tlb_unit.hh
/gem5/src/cpu/inorder/resources/use_def.cc
/gem5/src/cpu/inorder/resources/use_def.hh
/gem5/src/cpu/inorder/thread_context.cc
/gem5/src/cpu/inorder/thread_context.hh
/gem5/src/cpu/o3/commit.hh
/gem5/src/cpu/o3/cpu.cc
/gem5/src/cpu/o3/cpu.hh
/gem5/src/cpu/o3/fetch_impl.hh
/gem5/src/cpu/o3/inst_queue_impl.hh
/gem5/src/cpu/o3/lsq_unit.hh
/gem5/src/cpu/o3/thread_context.hh
/gem5/src/cpu/o3/thread_context_impl.hh
/gem5/src/cpu/simple/atomic.cc
/gem5/src/cpu/simple/atomic.hh
/gem5/src/cpu/simple/timing.cc
/gem5/src/cpu/simple/timing.hh
/gem5/src/cpu/simple_thread.cc
/gem5/src/cpu/simple_thread.hh
/gem5/src/cpu/testers/memtest/memtest.cc
/gem5/src/cpu/testers/networktest/networktest.cc
/gem5/src/cpu/thread_context.hh
/gem5/src/dev/arm/pl111.cc
/gem5/src/dev/i8254xGBe.cc
/gem5/src/dev/sinic.cc
/gem5/src/mem/bridge.cc
/gem5/src/mem/bridge.hh
/gem5/src/python/m5/params.py
/gem5/src/sim/clocked_object.hh
/gem5/src/sim/process.cc
/gem5/src/sim/pseudo_inst.cc
9158:d152d34a4adf 21-Aug-2012 Andreas Hansson <andreas.hansson@arm.com>

Clock: Make Tick unsigned and remove UTick

This patch makes the Tick unsigned and removes the UTick typedef. The
ticks should never be negative, and there was only one major issue
with removing it, caused by the o3 CPU using a -1 as an initial value.

The patch has no impact on any regressions.

9142:e9b713df4e1d 06-Aug-2012 Steve Reinhardt <steve.reinhardt@amd.com>

str: add an overloaded startswith() utility method
for various string types and use it in a few places.

9091:9b29b9a4dda6 09-Jul-2012 Andreas Hansson <andreas.hansson@arm.com>

Bus: Replace tickNextIdle and inRetry with a state variable

This patch adds a state enum and member variable in the bus, tracking
the bus state, thus eliminating the need for tickNextIdle and inRetry,
and fixing an issue that allowed the bus to be occupied by multiple
packets at once (hopefully it also makes it easier to understand the
code).

The bus, in its current form, uses tickNextIdle and inRetry to keep
track of the state of the bus. However, it only updates tickNextIdle
_after_ forwarding a packet using sendTiming, and the result is that
the bus is still seen as idle, and a module that receives the packet
and starts transmitting new packets in zero time will still see the
bus as idle (and this is done by a number of DMA devices). The issue
can also be seen in isOccupied where the bus calls reschedule on an
event instead of schedule.

This patch addresses the problem by marking the bus as _not_ idle
already by the time we conclude that the bus is not occupied and we
will deal with the packet.

As a result of not allowing multiple packets to occupy the bus, some
regressions have slight changes in their statistics. A separate patch
updates these accordingly.

Further ahead, a follow-on patch will introduce a separate state
variable for request/responses/snoop responses, and thus implement a
split request/response bus with separate flow control for the
different message types (even further ahead it will introduce a
multi-layer bus).

9086:496304c8017d 09-Jul-2012 Andreas Hansson <andreas.hansson@arm.com>

Fix: Address a few benign memory leaks

This patch is the result of static analysis identifying a number of
memory leaks. The leaks are all benign as they are a result of not
deallocating memory in the desctructor. The fix still has value as it
removes false positives in the static analysis.

9054:4c0f7e5ae72a 05-Jun-2012 William Wang <William.Wang@arm.com>

stats: when applying an operation to two vectors sum the components first.

Previously writing X/Y in a formula would result in:
x[0]/y[0] + x[1]/y[1]
In reality you want:
(x[0] +x[1])/(y[0] + y[1])

9044:904ddeecc653 05-Jun-2012 Ali Saidi <Ali.Saidi@ARM.com>

sim: Remove FastAlloc

While FastAlloc provides a small performance increase (~1.5%) over regular malloc it isn't thread safe.
After removing FastAlloc and using tcmalloc I've seen a performance increase of 12% over libc malloc
when running twolf for ARM.

9042:648b62f95015 05-Jun-2012 Mitchell Hayenga <Mitchell.Hayenga@ARM.com>

stats: Provide a mechanism to get a callback when stats are dumped.

This mechanism is useful for dumping output that is correlated with stats
dumping, but isn't tracked by the gem5 statistics.

9031:32ecc0217c5e 30-May-2012 Andreas Hansson <andreas.hansson@arm.com>

Packet: Unify the use of PortID in packet and port

This patch removes the Packet::NodeID typedef and unifies it with the
Port::PortId. The src and dest fields in the packet are used to hold a
port id (e.g. in the bus), and thus the two should actually be the
same.

The typedef PortID is now global (in base/types.hh) and aligned with
the ThreadID in terms of capitalisation and naming of the
InvalidPortID constant.

Before this patch, two flags were used for valid destination and
source, rather than relying on a named value (InvalidPortID), and
this is now redundant, as the src and dest field themselves are
sufficient to tell whether the current value is a valid port
identifier or not. Consequently, the VALID_SRC and VALID_DST are
removed.

As part of the cleaning up, a number of int parameters and local
variables are updated to use PortID.

Note that Ruby still has its own NodeID typedef. Furthermore, the
MemObject getMaster/SlavePort still has an int idx parameter with a
default value of -1 which should eventually change to PortID idx =
InvalidPortID.

9002:2972c71fccd5 10-May-2012 Ali Saidi <Ali.Saidi@ARM.com>

stats: fix bug in assert for 2d vector

8989:4968bf4ab67c 10-May-2012 Ali Saidi <Ali.Saidi@ARM.com>

base: fix a invalid ?: operator

8986:4cc63185478b 10-May-2012 Ali Saidi <Ali.Saidi@ARM.com>

stats: track if the stats have been enabled and prevent requesting master id

Track the point in the initialization where statistics have been registered.
After this point registering new masterIds can no longer work as some
SimObjects may have sized stats vectors based on the previous value. If someone
tries to register a masterId after this point the simulator executes fatal().

8982:06ce6d08caaa 09-May-2012 Nathan Binkert <nate@binkert.org>

stats: use nan instead of no_value

8964:d9ca1c98a690 25-Apr-2012 Andreas Hansson <andreas.hansson@arm.com>

clang/gcc: Use STL hash function for int64_t and uint64_t

This patch changes the guards for the definition of hash functions to
also exclude the int64_t and uint64_t hash functions in the case we
are using the c++0x STL <unordered_map> (and <hash>) or the TR1
version of the same header. Previously the guard only covered the hash
function for strings, but it seems there is also no need to define a
hash for the 64-bit integer types, and this has caused problems with
builds on 32-bit Ubuntu.

8959:24b06cbf2d67 22-Apr-2012 Gabe Black <gblack@eecs.umich.edu>

base: Include cassert in trie.hh.

trie.hh uses assert, but it wasn't explicitly including cassert.

8952:6188362beee1 15-Apr-2012 Gabe Black <gblack@eecs.umich.edu>

sim: Update some comments in trie.hh that were meant to go in the last change.

8951:4347de090956 15-Apr-2012 Gabe Black <gblack@eecs.umich.edu>

sim: A trie data structure specifically to speed up paging lookups.

This change adds a trie data structure which stores an arbitrary pointer type
based on an address and a number of relevant bits. Then lookups can be done
against the trie where the tree is traversed and the first legitimate match
found is returned.

8946:fb6c89334b86 14-Apr-2012 Andreas Hansson <andreas.hansson@arm.com>

clang/gcc: Fix compilation issues with clang 3.0 and gcc 4.6

This patch addresses a number of minor issues that cause problems when
compiling with clang >= 3.0 and gcc >= 4.6. Most importantly, it
avoids using the deprecated ext/hash_map and instead uses
unordered_map (and similarly so for the hash_set). To make use of the
new STL containers, g++ and clang has to be invoked with "-std=c++0x",
and this is now added for all gcc versions >= 4.6, and for clang >=
3.0. For gcc >= 4.3 and <= 4.5 and clang <= 3.0 we use the tr1
unordered_map to avoid the deprecation warning.

The addition of c++0x in turn causes a few problems, as the
compiler is more stringent and adds a number of new warnings. Below,
the most important issues are enumerated:

1) the use of namespaces is more strict, e.g. for isnan, and all
headers opening the entire namespace std are now fixed.

2) another other issue caused by the more stringent compiler is the
narrowing of the embedded python, which used to be a char array,
and is now unsigned char since there were values larger than 128.

3) a particularly odd issue that arose with the new c++0x behaviour is
found in range.hh, where the operator< causes gcc to complain about
the template type parsing (the "<" is interpreted as the beginning
of a template argument), and the problem seems to be related to the
begin/end members introduced for the range-type iteration, which is
a new feature in c++11.

As a minor update, this patch also fixes the build flags for the clang
debug target that used to be shared with gcc and incorrectly use
"-ggdb".

8931:7a1dfb191e3f 06-Apr-2012 Andreas Hansson <andreas.hansson@arm.com>

MEM: Enable multiple distributed generalized memories

This patch removes the assumption on having on single instance of
PhysicalMemory, and enables a distributed memory where the individual
memories in the system are each responsible for a single contiguous
address range.

All memories inherit from an AbstractMemory that encompasses the basic
behaviuor of a random access memory, and provides untimed access
methods. What was previously called PhysicalMemory is now
SimpleMemory, and a subclass of AbstractMemory. All future types of
memory controllers should inherit from AbstractMemory.

To enable e.g. the atomic CPU and RubyPort to access the now
distributed memory, the system has a wrapper class, called
PhysicalMemory that is aware of all the memories in the system and
their associated address ranges. This class thus acts as an
infinitely-fast bus and performs address decoding for these "shortcut"
accesses. Each memory can specify that it should not be part of the
global address map (used e.g. by the functional memories by some
testers). Moreover, each memory can be configured to be reported to
the OS configuration table, useful for populating ATAG structures, and
any potential ACPI tables.

Checkpointing support currently assumes that all memories have the
same size and organisation when creating and resuming from the
checkpoint. A future patch will enable a more flexible
re-organisation.


/gem5/configs/common/FSConfig.py
/gem5/configs/example/memtest.py
/gem5/configs/example/ruby_direct_test.py
/gem5/configs/example/ruby_mem_test.py
/gem5/configs/example/ruby_network_test.py
/gem5/configs/example/ruby_random_test.py
/gem5/configs/example/se.py
/gem5/configs/ruby/MESI_CMP_directory.py
/gem5/configs/ruby/MI_example.py
/gem5/configs/ruby/MOESI_CMP_directory.py
/gem5/configs/ruby/MOESI_CMP_token.py
/gem5/configs/ruby/MOESI_hammer.py
/gem5/configs/ruby/Network_test.py
/gem5/configs/ruby/Ruby.py
/gem5/configs/splash2/cluster.py
/gem5/configs/splash2/run.py
/gem5/src/arch/alpha/remote_gdb.cc
/gem5/src/arch/alpha/remote_gdb.hh
/gem5/src/arch/arm/ArmSystem.py
/gem5/src/arch/arm/linux/system.cc
/gem5/src/arch/arm/remote_gdb.hh
/gem5/src/arch/arm/system.cc
/gem5/src/arch/mips/remote_gdb.hh
/gem5/src/arch/sparc/SparcSystem.py
/gem5/src/arch/sparc/remote_gdb.hh
remote_gdb.cc
remote_gdb.hh
/gem5/src/cpu/checker/thread_context.hh
/gem5/src/cpu/inorder/thread_context.hh
/gem5/src/cpu/o3/fetch_impl.hh
/gem5/src/cpu/ozone/cpu.hh
/gem5/src/cpu/simple/atomic.cc
/gem5/src/cpu/simple/atomic.hh
/gem5/src/dev/alpha/backdoor.cc
/gem5/src/dev/arm/RealView.py
/gem5/src/dev/ide_disk.hh
/gem5/src/mem/AbstractMemory.py
/gem5/src/mem/PhysicalMemory.py
/gem5/src/mem/SConscript
/gem5/src/mem/SimpleMemory.py
/gem5/src/mem/abstract_mem.cc
/gem5/src/mem/abstract_mem.hh
/gem5/src/mem/cache/mshr.cc
/gem5/src/mem/physical.cc
/gem5/src/mem/physical.hh
/gem5/src/mem/ruby/system/RubyPort.cc
/gem5/src/mem/simple_mem.cc
/gem5/src/mem/simple_mem.hh
/gem5/src/sim/System.py
/gem5/src/sim/system.cc
/gem5/src/sim/system.hh
/gem5/tests/configs/inorder-timing.py
/gem5/tests/configs/memtest-ruby.py
/gem5/tests/configs/memtest.py
/gem5/tests/configs/o3-timing-checker.py
/gem5/tests/configs/o3-timing-mp.py
/gem5/tests/configs/o3-timing.py
/gem5/tests/configs/rubytest-ruby.py
/gem5/tests/configs/simple-atomic-dummychecker.py
/gem5/tests/configs/simple-atomic-mp.py
/gem5/tests/configs/simple-atomic.py
/gem5/tests/configs/simple-timing-mp-ruby.py
/gem5/tests/configs/simple-timing-mp.py
/gem5/tests/configs/simple-timing-ruby.py
/gem5/tests/configs/simple-timing.py
8918:50d1b7dbd23c 26-Mar-2012 Andreas Hansson <andreas.hansson@arm.com>

range_map: Enable const find and iteration

This patch adds const access functions to the range_map to enable its use
in a const context, similar to the STL container classes.

8902:75b524b64c28 19-Mar-2012 Andreas Hansson <andreas.hansson@arm.com>

gcc: Clean-up of non-C++0x compliant code, first steps

This patch cleans up a number of minor issues aiming to get closer to
compliance with the C++0x standard as interpreted by gcc and clang
(compile with std=c++0x and -pedantic-errors). In particular, the
patch cleans up enums where the last item was succeded by a comma,
namespaces closed by a curcly brace followed by a semi-colon, and the
use of the GNU-extension typeof (replaced by templated functions). It
does not address variable-length arrays, zero-size arrays, anonymous
structs, range expressions in switch statements, and the use of long
long. The generated CPU code also has a large number of issues that
remain to be fixed, mainly related to overflows in implicit constant
conversion (due to shifts).


/gem5/src/arch/alpha/isa/main.isa
/gem5/src/arch/alpha/isa_traits.hh
/gem5/src/arch/alpha/types.hh
/gem5/src/arch/arm/intregs.hh
/gem5/src/arch/arm/isa/templates/neon.isa
/gem5/src/arch/arm/linux/atag.hh
/gem5/src/arch/arm/miscregs.cc
/gem5/src/arch/arm/miscregs.hh
/gem5/src/arch/arm/nativetrace.cc
/gem5/src/arch/arm/pagetable.hh
/gem5/src/arch/arm/predecoder.hh
/gem5/src/arch/arm/table_walker.hh
/gem5/src/arch/arm/utility.hh
/gem5/src/arch/arm/vtophys.hh
/gem5/src/arch/x86/bios/e820.hh
/gem5/src/arch/x86/emulenv.hh
/gem5/src/arch/x86/faults.hh
/gem5/src/arch/x86/isa/macroop.isa
/gem5/src/arch/x86/isa_traits.hh
/gem5/src/arch/x86/locked_mem.hh
/gem5/src/arch/x86/mmapped_ipr.hh
/gem5/src/arch/x86/nativetrace.cc
/gem5/src/arch/x86/predecoder.hh
/gem5/src/arch/x86/regs/float.hh
/gem5/src/arch/x86/regs/int.hh
/gem5/src/arch/x86/regs/misc.hh
/gem5/src/arch/x86/regs/segment.hh
/gem5/src/arch/x86/tlb.cc
/gem5/src/arch/x86/types.hh
/gem5/src/arch/x86/utility.hh
/gem5/src/arch/x86/vtophys.hh
bitmap.cc
callback.cc
range.cc
range_map.hh
str.cc
vnc/convert.hh
/gem5/src/cpu/base_dyn_inst.hh
/gem5/src/cpu/exetrace.cc
/gem5/src/cpu/inorder/inorder_dyn_inst.hh
/gem5/src/cpu/inorder/pipeline_traits.hh
/gem5/src/cpu/inorder/resource.hh
/gem5/src/cpu/inteltrace.cc
/gem5/src/cpu/o3/dyn_inst.hh
/gem5/src/cpu/o3/thread_context.hh
/gem5/src/cpu/simple_thread.hh
/gem5/src/cpu/static_inst.hh
/gem5/src/cpu/thread_context.hh
/gem5/src/cpu/thread_state.hh
/gem5/src/dev/i8254xGBe.hh
/gem5/src/dev/ide_atareg.h
/gem5/src/dev/sinicreg.hh
/gem5/src/python/m5/params.py
/gem5/src/sim/byteswap.hh
/gem5/src/sim/eventq.hh
/gem5/src/sim/serialize.hh
8871:136328e218f2 01-Mar-2012 Chander Sudanthi <Chander.Sudanthi@arm.com>

VNC: spacing

Fixed some spacing in a switch statement

8869:fa8dcdd7e26c 01-Mar-2012 Ali Saidi <Ali.Saidi@ARM.com>

ARM: Add RTC device for ARM platforms.

This change implements a PL031 real time clock.

8852:c744483edfcf 24-Feb-2012 Andreas Hansson <andreas.hansson@arm.com>

MEM: Make port proxies use references rather than pointers

This patch is adding a clearer design intent to all objects that would
not be complete without a port proxy by making the proxies members
rathen than dynamically allocated. In essence, if NULL would not be a
valid value for the proxy, then we avoid using a pointer to make this
clear.

The same approach is used for the methods using these proxies, such as
loadSections, that now use references rather than pointers to better
reflect the fact that NULL would not be an acceptable value (in fact
the code would break and that is how this patch started out).

Overall the concept of "using a reference to express unconditional
composition where a NULL pointer is never valid" could be done on a
much broader scale throughout the code base, but for now it is only
done in the locations affected by the proxies.


/gem5/src/arch/alpha/freebsd/system.cc
/gem5/src/arch/alpha/linux/system.cc
/gem5/src/arch/alpha/linux/threadinfo.hh
/gem5/src/arch/alpha/process.cc
/gem5/src/arch/alpha/stacktrace.cc
/gem5/src/arch/alpha/system.cc
/gem5/src/arch/alpha/tru64/system.cc
/gem5/src/arch/alpha/utility.cc
/gem5/src/arch/alpha/vtophys.cc
/gem5/src/arch/alpha/vtophys.hh
/gem5/src/arch/arm/linux/process.cc
/gem5/src/arch/arm/linux/system.cc
/gem5/src/arch/arm/process.cc
/gem5/src/arch/arm/stacktrace.cc
/gem5/src/arch/arm/system.cc
/gem5/src/arch/arm/utility.cc
/gem5/src/arch/arm/vtophys.cc
/gem5/src/arch/mips/linux/threadinfo.hh
/gem5/src/arch/mips/process.cc
/gem5/src/arch/mips/stacktrace.cc
/gem5/src/arch/power/process.cc
/gem5/src/arch/sparc/process.cc
/gem5/src/arch/sparc/utility.cc
/gem5/src/arch/sparc/vtophys.cc
/gem5/src/arch/x86/bios/e820.cc
/gem5/src/arch/x86/bios/e820.hh
/gem5/src/arch/x86/bios/intelmp.cc
/gem5/src/arch/x86/bios/intelmp.hh
/gem5/src/arch/x86/bios/smbios.cc
/gem5/src/arch/x86/bios/smbios.hh
/gem5/src/arch/x86/linux/syscalls.cc
/gem5/src/arch/x86/linux/system.cc
/gem5/src/arch/x86/process.cc
/gem5/src/arch/x86/stacktrace.cc
/gem5/src/arch/x86/system.cc
loader/elf_object.cc
loader/elf_object.hh
loader/hex_file.cc
loader/hex_file.hh
loader/object_file.cc
loader/object_file.hh
remote_gdb.cc
/gem5/src/cpu/checker/thread_context.hh
/gem5/src/cpu/inorder/thread_context.cc
/gem5/src/cpu/inorder/thread_context.hh
/gem5/src/cpu/o3/thread_context.hh
/gem5/src/cpu/o3/thread_context_impl.hh
/gem5/src/cpu/ozone/cpu.hh
/gem5/src/cpu/simple_thread.hh
/gem5/src/cpu/thread_context.hh
/gem5/src/cpu/thread_state.cc
/gem5/src/cpu/thread_state.hh
/gem5/src/dev/simple_disk.cc
/gem5/src/kern/tru64/tru64.hh
/gem5/src/mem/fs_translating_port_proxy.cc
/gem5/src/mem/se_translating_port_proxy.hh
/gem5/src/sim/process.cc
/gem5/src/sim/process.hh
/gem5/src/sim/process_impl.hh
/gem5/src/sim/syscall_emul.cc
/gem5/src/sim/syscall_emul.hh
/gem5/src/sim/system.cc
/gem5/src/sim/system.hh
/gem5/src/sim/vptr.hh
8799:dac1e33e07b0 28-Jan-2012 Gabe Black <gblack@eecs.umich.edu>

Merge with the main repo.


/gem5/src/arch/alpha/linux/system.cc
/gem5/src/arch/alpha/linux/system.hh
/gem5/src/arch/alpha/remote_gdb.cc
/gem5/src/arch/alpha/system.cc
/gem5/src/arch/alpha/system.hh
/gem5/src/arch/alpha/utility.cc
/gem5/src/arch/arm/utility.cc
/gem5/src/arch/mips/linux/system.cc
/gem5/src/arch/mips/stacktrace.cc
/gem5/src/arch/mips/system.cc
/gem5/src/arch/mips/utility.cc
/gem5/src/arch/mips/vtophys.cc
/gem5/src/arch/sparc/utility.cc
/gem5/src/arch/x86/interrupts.cc
/gem5/src/arch/x86/interrupts.hh
remote_gdb.cc
/gem5/src/cpu/BaseCPU.py
/gem5/src/cpu/base.cc
/gem5/src/cpu/base.hh
/gem5/src/cpu/checker/thread_context.hh
/gem5/src/cpu/inorder/cpu.cc
/gem5/src/cpu/inorder/cpu.hh
/gem5/src/cpu/inorder/resources/cache_unit.cc
/gem5/src/cpu/inorder/resources/cache_unit.hh
/gem5/src/cpu/inorder/thread_context.cc
/gem5/src/cpu/inorder/thread_context.hh
/gem5/src/cpu/o3/O3CPU.py
/gem5/src/cpu/o3/cpu.cc
/gem5/src/cpu/o3/cpu.hh
/gem5/src/cpu/o3/fetch_impl.hh
/gem5/src/cpu/o3/iew.hh
/gem5/src/cpu/o3/lsq.hh
/gem5/src/cpu/o3/lsq_impl.hh
/gem5/src/cpu/o3/thread_context.hh
/gem5/src/cpu/o3/thread_context_impl.hh
/gem5/src/cpu/ozone/cpu.hh
/gem5/src/cpu/ozone/cpu_impl.hh
/gem5/src/cpu/ozone/front_end_impl.hh
/gem5/src/cpu/ozone/lw_lsq.hh
/gem5/src/cpu/simple/atomic.cc
/gem5/src/cpu/simple/timing.cc
/gem5/src/cpu/simple_thread.cc
/gem5/src/cpu/simple_thread.hh
/gem5/src/cpu/thread_context.hh
/gem5/src/cpu/thread_state.cc
/gem5/src/cpu/thread_state.hh
/gem5/src/dev/Device.py
/gem5/src/dev/Pci.py
/gem5/src/dev/arm/RealView.py
/gem5/src/dev/arm/gic.cc
/gem5/src/dev/arm/gic.hh
/gem5/src/dev/io_device.cc
/gem5/src/dev/io_device.hh
/gem5/src/dev/pcidev.cc
/gem5/src/dev/pcidev.hh
/gem5/src/dev/simple_disk.cc
/gem5/src/dev/sparc/iob.cc
/gem5/src/dev/x86/i82094aa.hh
/gem5/src/kern/tru64/tru64.hh
/gem5/src/mem/SConscript
/gem5/src/mem/cache/base.cc
/gem5/src/mem/cache/base.hh
/gem5/src/mem/fs_translating_port_proxy.hh
/gem5/src/mem/physical.cc
/gem5/src/mem/port_impl.hh
/gem5/src/mem/se_translating_port_proxy.cc
/gem5/src/mem/se_translating_port_proxy.hh
/gem5/src/mem/translating_port.cc
/gem5/src/mem/translating_port.hh
/gem5/src/mem/vport.cc
/gem5/src/mem/vport.hh
/gem5/src/sim/System.py
/gem5/src/sim/process.cc
/gem5/src/sim/process.hh
/gem5/src/sim/process_impl.hh
/gem5/src/sim/syscall_emul.hh
/gem5/src/sim/system.cc
/gem5/src/sim/system.hh
/gem5/tests/configs/simple-timing-ruby.py
8797:3202eb01e01e 07-Jan-2012 Gabe Black <gblack@eecs.umich.edu>

Another merge with the main repository.

8784:05fb20d7064b 02-Nov-2011 Gabe Black <gblack@eecs.umich.edu>

SE/FS: Get rid of FULL_SYSTEM in sim.

8783:8cd08c045cab 02-Nov-2011 Gabe Black <gblack@eecs.umich.edu>

SE/FS: Get FULL_SYSTEM out of base/remote_gdb.cc.

8739:925f15f96322 30-Sep-2011 Gabe Black <gblack@eecs.umich.edu>

SE/FS: Build the devices in SE mode.

8737:770ccf3af571 31-Jan-2012 Koan-Sin Tan <koansin.tan@gmail.com>

clang: Enable compiling gem5 using clang 2.9 and 3.0

This patch adds the necessary flags to the SConstruct and SConscript
files for compiling using clang 2.9 and later (on Ubuntu et al and OSX
XCode 4.2), and also cleans up a bunch of compiler warnings found by
clang. Most of the warnings are related to hidden virtual functions,
comparisons with unsigneds >= 0, and if-statements with empty
bodies. A number of mismatches between struct and class are also
fixed. clang 2.8 is not working as it has problems with class names
that occur in multiple namespaces (e.g. Statistics in
kernel_stats.hh).

clang has a bug (http://llvm.org/bugs/show_bug.cgi?id=7247) which
causes confusion between the container std::set and the function
Packet::set, and this is currently addressed by not including the
entire namespace std, but rather selecting e.g. "using std::vector" in
the appropriate places.


/gem5/SConstruct
/gem5/ext/libelf/SConscript
/gem5/src/SConscript
/gem5/src/arch/alpha/tlb.cc
/gem5/src/arch/alpha/tlb.hh
/gem5/src/arch/arm/insts/static_inst.hh
/gem5/src/arch/arm/insts/vfp.hh
/gem5/src/arch/arm/isa/templates/basic.isa
/gem5/src/arch/arm/miscregs.cc
/gem5/src/arch/generic/memhelpers.hh
/gem5/src/arch/mips/faults.cc
/gem5/src/arch/mips/faults.hh
/gem5/src/arch/x86/bios/acpi.hh
/gem5/src/arch/x86/bios/intelmp.cc
/gem5/src/arch/x86/bios/intelmp.hh
/gem5/src/arch/x86/bios/smbios.hh
fast_alloc.cc
range_map.hh
remote_gdb.hh
stl_helpers.hh
/gem5/src/cpu/base.cc
/gem5/src/cpu/base.hh
/gem5/src/cpu/func_unit.hh
/gem5/src/cpu/inorder/cpu.cc
/gem5/src/cpu/inorder/cpu.hh
/gem5/src/cpu/inorder/resource.cc
/gem5/src/cpu/inorder/resource.hh
/gem5/src/cpu/inorder/resource_pool.cc
/gem5/src/cpu/inorder/resource_pool.hh
/gem5/src/cpu/inorder/resources/cache_unit.hh
/gem5/src/cpu/inorder/thread_context.cc
/gem5/src/cpu/nativetrace.hh
/gem5/src/cpu/o3/bpred_unit.hh
/gem5/src/cpu/o3/commit.hh
/gem5/src/cpu/o3/cpu.cc
/gem5/src/cpu/o3/cpu.hh
/gem5/src/cpu/o3/decode.hh
/gem5/src/cpu/o3/decode_impl.hh
/gem5/src/cpu/o3/fetch.hh
/gem5/src/cpu/o3/fu_pool.cc
/gem5/src/cpu/o3/fu_pool.hh
/gem5/src/cpu/o3/iew.hh
/gem5/src/cpu/o3/iew_impl.hh
/gem5/src/cpu/o3/inst_queue.hh
/gem5/src/cpu/o3/inst_queue_impl.hh
/gem5/src/cpu/o3/lsq.hh
/gem5/src/cpu/o3/lsq_unit.hh
/gem5/src/cpu/o3/mem_dep_unit.cc
/gem5/src/cpu/o3/mem_dep_unit.hh
/gem5/src/cpu/o3/rename.hh
/gem5/src/cpu/o3/sat_counter.hh
/gem5/src/cpu/quiesce_event.hh
/gem5/src/cpu/sched_list.hh
/gem5/src/cpu/simple/atomic.cc
/gem5/src/cpu/simple/atomic.hh
/gem5/src/cpu/simple/base.cc
/gem5/src/cpu/simple/base.hh
/gem5/src/cpu/simple/timing.cc
/gem5/src/cpu/simple/timing.hh
/gem5/src/cpu/static_inst.hh
/gem5/src/dev/alpha/tsunami_cchip.cc
/gem5/src/dev/alpha/tsunami_io.cc
/gem5/src/dev/arm/pl111.cc
/gem5/src/dev/arm/pl111.hh
/gem5/src/dev/copy_engine.cc
/gem5/src/dev/disk_image.cc
/gem5/src/dev/disk_image.hh
/gem5/src/dev/ide_ctrl.cc
/gem5/src/dev/ns_gige.cc
/gem5/src/dev/pciconfigall.cc
/gem5/src/dev/pcidev.cc
/gem5/src/mem/cache/base.hh
/gem5/src/mem/cache/tags/iic.cc
/gem5/src/mem/cache/tags/iic_repl/gen.cc
/gem5/src/mem/cache/tags/iic_repl/gen.hh
/gem5/src/mem/cache/tags/iic_repl/repl.hh
/gem5/src/mem/packet.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc
/gem5/src/mem/ruby/system/Sequencer.hh
/gem5/src/python/m5/SimObject.py
/gem5/src/sim/core.hh
/gem5/src/sim/process.cc
/gem5/src/sim/process.hh
/gem5/src/sim/process_impl.hh
/gem5/src/sim/serialize.cc
/gem5/src/sim/sim_object.cc
/gem5/src/sim/sim_object.hh
/gem5/src/sim/syscall_emul.hh
8734:79592b2b1d55 31-Jan-2012 Dam Sunwoo <dam.sunwoo@arm.com>

util: implements "writefile" gem5 op to export file from guest to host filesystem

Usage: m5 writefile <filename>

File will be created in the gem5 output folder with the identical filename.
Implementation is largely based on the existing "readfile" functionality.
Currently does not support exporting of folders.

8706:b1838faf3bcc 17-Jan-2012 Andreas Hansson <andreas.hansson@arm.com>

MEM: Add port proxies instead of non-structural ports

Port proxies are used to replace non-structural ports, and thus enable
all ports in the system to correspond to a structural entity. This has
the advantage of accessing memory through the normal memory subsystem
and thus allowing any constellation of distributed memories, address
maps, etc. Most accesses are done through the "system port" that is
used for loading binaries, debugging etc. For the entities that belong
to the CPU, e.g. threads and thread contexts, they wrap the CPU data
port in a port proxy.

The following replacements are made:
FunctionalPort > PortProxy
TranslatingPort > SETranslatingPortProxy
VirtualPort > FSTranslatingPortProxy


/gem5/configs/common/FSConfig.py
/gem5/configs/example/se.py
/gem5/configs/ruby/Ruby.py
/gem5/src/arch/alpha/freebsd/system.cc
/gem5/src/arch/alpha/linux/process.cc
/gem5/src/arch/alpha/linux/system.cc
/gem5/src/arch/alpha/linux/system.hh
/gem5/src/arch/alpha/linux/threadinfo.hh
/gem5/src/arch/alpha/remote_gdb.cc
/gem5/src/arch/alpha/stacktrace.cc
/gem5/src/arch/alpha/system.cc
/gem5/src/arch/alpha/system.hh
/gem5/src/arch/alpha/tru64/process.cc
/gem5/src/arch/alpha/tru64/system.cc
/gem5/src/arch/alpha/utility.cc
/gem5/src/arch/alpha/vtophys.cc
/gem5/src/arch/alpha/vtophys.hh
/gem5/src/arch/arm/linux/process.cc
/gem5/src/arch/arm/linux/system.cc
/gem5/src/arch/arm/process.cc
/gem5/src/arch/arm/stacktrace.cc
/gem5/src/arch/arm/system.cc
/gem5/src/arch/arm/system.hh
/gem5/src/arch/arm/utility.cc
/gem5/src/arch/arm/vtophys.cc
/gem5/src/arch/mips/linux/process.cc
/gem5/src/arch/mips/linux/system.cc
/gem5/src/arch/mips/linux/threadinfo.hh
/gem5/src/arch/mips/stacktrace.cc
/gem5/src/arch/mips/utility.cc
/gem5/src/arch/power/linux/process.cc
/gem5/src/arch/power/process.cc
/gem5/src/arch/sparc/linux/syscalls.cc
/gem5/src/arch/sparc/process.cc
/gem5/src/arch/sparc/solaris/process.cc
/gem5/src/arch/sparc/system.cc
/gem5/src/arch/sparc/system.hh
/gem5/src/arch/sparc/utility.cc
/gem5/src/arch/sparc/vtophys.cc
/gem5/src/arch/x86/bios/intelmp.cc
/gem5/src/arch/x86/bios/intelmp.hh
/gem5/src/arch/x86/bios/smbios.cc
/gem5/src/arch/x86/bios/smbios.hh
/gem5/src/arch/x86/linux/syscalls.cc
/gem5/src/arch/x86/linux/system.cc
/gem5/src/arch/x86/process.cc
/gem5/src/arch/x86/stacktrace.cc
/gem5/src/arch/x86/system.cc
loader/elf_object.cc
loader/elf_object.hh
loader/hex_file.cc
loader/hex_file.hh
loader/object_file.cc
loader/object_file.hh
remote_gdb.cc
/gem5/src/cpu/checker/thread_context.hh
/gem5/src/cpu/inorder/cpu.cc
/gem5/src/cpu/inorder/cpu.hh
/gem5/src/cpu/inorder/resources/cache_unit.cc
/gem5/src/cpu/inorder/resources/cache_unit.hh
/gem5/src/cpu/inorder/thread_context.cc
/gem5/src/cpu/inorder/thread_context.hh
/gem5/src/cpu/o3/cpu.cc
/gem5/src/cpu/o3/cpu.hh
/gem5/src/cpu/o3/lsq.hh
/gem5/src/cpu/o3/lsq_impl.hh
/gem5/src/cpu/o3/thread_context.hh
/gem5/src/cpu/o3/thread_context_impl.hh
/gem5/src/cpu/ozone/cpu.hh
/gem5/src/cpu/ozone/cpu_impl.hh
/gem5/src/cpu/simple/atomic.cc
/gem5/src/cpu/simple/atomic.hh
/gem5/src/cpu/simple/timing.cc
/gem5/src/cpu/simple/timing.hh
/gem5/src/cpu/simple_thread.cc
/gem5/src/cpu/simple_thread.hh
/gem5/src/cpu/thread_context.hh
/gem5/src/cpu/thread_state.cc
/gem5/src/cpu/thread_state.hh
/gem5/src/dev/simple_disk.cc
/gem5/src/kern/tru64/tru64.hh
/gem5/src/kern/tru64/tru64_events.cc
/gem5/src/mem/SConscript
/gem5/src/mem/fs_translating_port_proxy.cc
/gem5/src/mem/fs_translating_port_proxy.hh
/gem5/src/mem/port.hh
/gem5/src/mem/port_impl.hh
/gem5/src/mem/port_proxy.hh
/gem5/src/mem/ruby/system/RubyPort.cc
/gem5/src/mem/ruby/system/RubyPortProxy.cc
/gem5/src/mem/ruby/system/RubyPortProxy.hh
/gem5/src/mem/ruby/system/SConscript
/gem5/src/mem/ruby/system/Sequencer.py
/gem5/src/mem/se_translating_port_proxy.cc
/gem5/src/mem/se_translating_port_proxy.hh
/gem5/src/mem/translating_port.cc
/gem5/src/mem/translating_port.hh
/gem5/src/mem/vport.cc
/gem5/src/mem/vport.hh
/gem5/src/sim/arguments.hh
/gem5/src/sim/process.cc
/gem5/src/sim/process.hh
/gem5/src/sim/process_impl.hh
/gem5/src/sim/syscall_emul.cc
/gem5/src/sim/syscall_emul.hh
/gem5/src/sim/system.cc
/gem5/src/sim/system.hh
/gem5/src/sim/vptr.hh
/gem5/tests/configs/inorder-timing.py
/gem5/tests/configs/memtest-ruby.py
/gem5/tests/configs/memtest.py
/gem5/tests/configs/o3-timing-mp.py
/gem5/tests/configs/o3-timing.py
/gem5/tests/configs/rubytest-ruby.py
/gem5/tests/configs/simple-atomic-mp.py
/gem5/tests/configs/simple-atomic.py
/gem5/tests/configs/simple-timing-mp-ruby.py
/gem5/tests/configs/simple-timing-mp.py
/gem5/tests/configs/simple-timing-ruby.py
/gem5/tests/configs/simple-timing.py
8700:5637ed211912 16-Jan-2012 Steve Reinhardt <steve.reinhardt@amd.com>

Alpha: warn_once about broken PAL breakpoints.

A recent changeset (aae12ce9f34c) removed support for
PAL-mode breakpoints in Alpha, since it was awkward
and likely unused. This patch lets a user know if they
potentially run into this limitation.

8699:d1a507c6329a 16-Jan-2012 Steve Reinhardt <steve.reinhardt@amd.com>

debug: fix AllFlags::disable()

Looks like copy-and-paste bug, apparently I'm the first
person to ever use this since it's plainly broken.

8667:62372a8d4ef2 09-Jan-2012 Dam Sunwoo <dam.sunwoo@arm.com>

stats: fix Vector2d to display stats correctly when y_subname is not specified.

Vector2d stats with no y_subname were not displayed as the VectorPrint subname was not initialized correctly to reflect the empty field.

8666:97d873b8b13e 09-Jan-2012 Prakash Ramrakhyani <Prakash.Ramrakhyani@arm.com>

sim: Enable sampling of run-time for code-sections marked using pseudo insts.

This patch adds a mechanism to collect run time samples for specific portions
of a benchmark, using work_begin and work_end pseudo instructions.It also enhances
the histogram stat to report geometric mean.

8658:f1a69b7246f7 09-Jan-2012 Dam Sunwoo <dam.sunwoo@arm.com>

Base: Fixed shift amount in genrand() to work with large numbers

The previous version didn't work correctly with max integer values (2^31-1 for
32-bit, 2^63-1 for 64bit version), causing "shift" to become -1. For smaller
numbers, it wouldn't have caused functional errors, but would have resulted in
more than necessary loops in the while loop. Special-cased cases when (max + 1
== 0) to prevent the ceilLog2 functions from failing.

8655:e4001326a5ba 09-Jan-2012 Andreas Hansson <andreas.hansson@arm.com>

MAC: Make gem5 compile and run on MacOSX 10.7.2

Adaptations to make gem5 compile and run on OSX 10.7.2, with a stock
gcc 4.2.1 and the remaining dependencies from macports, i.e. python
2.7,.2 swig 2.0.4, mercurial 2.0. The changes include an adaptation of
the SConstruct to handle non-library linker flags, and Darwin-specific
code to find the memory usage of gem5. A number of Ruby files relied
on ambigious uint (without the 32 suffix) which caused compilation
errors.

8641:4d3ecac1abec 13-Dec-2011 Nathan Binkert <nate@binkert.org>

gcc: fix unused variable warnings from GCC 4.6.1

8640:cb8a72779f7e 01-Dec-2011 Ali Saidi <Ali.Saidi@ARM.com>

Trace: FIx issue with creation of trace file with output dir overhaul.

8635:23ba076b2cca 01-Dec-2011 Chris Emmons <chris.emmons@arm.com>

VNC: Add support for capturing frame buffer to file each time it is changed.

When a change in the frame buffer from the VNC server is detected, the new
frame is stored out to the m5out/frames_*/ directory. Specifiy the flag
"--frame-capture" when running configs/example/fs.py to enable this behavior.

8634:8390f2d80227 01-Dec-2011 Chris Emmons <chris.emmons@arm.com>

Output: Add hierarchical output support and cleanup existing codebase.

8620:82ad0f25a758 27-Nov-2011 Gabe Black <gblack@eecs.umich.edu>

Compiler: Add an M5_NO_INLINE define.

8607:5fb918115c07 31-Oct-2011 Gabe Black <gblack@eecs.umich.edu>

GCC: Get everything working with gcc 4.6.1.

And by "everything" I mean all the quick regressions.

8514:57c96df312a1 19-Aug-2011 Thomas Grass <Thomas.Grass@ARM.com>

Stats: Add a sparse histogram stat object.

8350:9fb150de362e 13-Jun-2011 Gabe Black <gblack@eecs.umich.edu>

Loader: Handle bad section names when loading an ELF file.

If there's a problem when reading the section names from a supposed ELF file,
this change makes gem5 print an error message as returned by libelf and die.
Previously these sorts of errors would make gem5 segfault when it tried to
access the section name through a NULL pointer.

8338:4d1005f78496 07-Jun-2011 Gabe Black <gblack@eecs.umich.edu>

gcc 4.0: Add some virtual destructors to make gcc 4.0 happy.

8335:9228e00459d4 02-Jun-2011 Nathan Binkert <nate@binkert.org>

scons: rename TraceFlags to DebugFlags

8332:23711432221f 02-Jun-2011 Nathan Binkert <nate@binkert.org>

copyright: clean up copyright blocks


/gem5/src/arch/alpha/kgdb.h
/gem5/src/arch/alpha/remote_gdb.cc
/gem5/src/arch/arm/remote_gdb.cc
/gem5/src/arch/generic/debugfaults.hh
/gem5/src/arch/sparc/remote_gdb.cc
/gem5/src/arch/x86/insts/badmicroop.cc
/gem5/src/arch/x86/insts/badmicroop.hh
/gem5/src/arch/x86/isa/formats/nop.isa
random_mt.cc
remote_gdb.cc
/gem5/src/dev/ide_wdcreg.h
/gem5/src/dev/sparc/dtod.hh
/gem5/src/mem/ruby/network/orion/Allocator/Arbiter.cc
/gem5/src/mem/ruby/network/orion/Allocator/Arbiter.hh
/gem5/src/mem/ruby/network/orion/Allocator/MatrixArbiter.cc
/gem5/src/mem/ruby/network/orion/Allocator/MatrixArbiter.hh
/gem5/src/mem/ruby/network/orion/Allocator/RRArbiter.cc
/gem5/src/mem/ruby/network/orion/Allocator/RRArbiter.hh
/gem5/src/mem/ruby/network/orion/Allocator/SWAllocator.cc
/gem5/src/mem/ruby/network/orion/Allocator/SWAllocator.hh
/gem5/src/mem/ruby/network/orion/Allocator/VCAllocator.cc
/gem5/src/mem/ruby/network/orion/Allocator/VCAllocator.hh
/gem5/src/mem/ruby/network/orion/Buffer/AmpUnit.cc
/gem5/src/mem/ruby/network/orion/Buffer/AmpUnit.hh
/gem5/src/mem/ruby/network/orion/Buffer/BitlineUnit.cc
/gem5/src/mem/ruby/network/orion/Buffer/BitlineUnit.hh
/gem5/src/mem/ruby/network/orion/Buffer/Buffer.cc
/gem5/src/mem/ruby/network/orion/Buffer/Buffer.hh
/gem5/src/mem/ruby/network/orion/Buffer/DecoderUnit.cc
/gem5/src/mem/ruby/network/orion/Buffer/DecoderUnit.hh
/gem5/src/mem/ruby/network/orion/Buffer/MemUnit.cc
/gem5/src/mem/ruby/network/orion/Buffer/MemUnit.hh
/gem5/src/mem/ruby/network/orion/Buffer/OutdrvUnit.cc
/gem5/src/mem/ruby/network/orion/Buffer/OutdrvUnit.hh
/gem5/src/mem/ruby/network/orion/Buffer/PrechargeUnit.cc
/gem5/src/mem/ruby/network/orion/Buffer/PrechargeUnit.hh
/gem5/src/mem/ruby/network/orion/Buffer/Register.cc
/gem5/src/mem/ruby/network/orion/Buffer/Register.hh
/gem5/src/mem/ruby/network/orion/Buffer/SRAM.cc
/gem5/src/mem/ruby/network/orion/Buffer/SRAM.hh
/gem5/src/mem/ruby/network/orion/Buffer/WordlineUnit.cc
/gem5/src/mem/ruby/network/orion/Buffer/WordlineUnit.hh
/gem5/src/mem/ruby/network/orion/Clock.cc
/gem5/src/mem/ruby/network/orion/Clock.hh
/gem5/src/mem/ruby/network/orion/Crossbar/Crossbar.cc
/gem5/src/mem/ruby/network/orion/Crossbar/Crossbar.hh
/gem5/src/mem/ruby/network/orion/Crossbar/MatrixCrossbar.cc
/gem5/src/mem/ruby/network/orion/Crossbar/MatrixCrossbar.hh
/gem5/src/mem/ruby/network/orion/Crossbar/MultreeCrossbar.cc
/gem5/src/mem/ruby/network/orion/Crossbar/MultreeCrossbar.hh
/gem5/src/mem/ruby/network/orion/FlipFlop.cc
/gem5/src/mem/ruby/network/orion/FlipFlop.hh
/gem5/src/mem/ruby/network/orion/OrionLink.cc
/gem5/src/mem/ruby/network/orion/OrionLink.hh
/gem5/src/mem/ruby/network/orion/OrionRouter.cc
/gem5/src/mem/ruby/network/orion/OrionRouter.hh
/gem5/src/mem/ruby/network/orion/TechParameter.cc
/gem5/src/mem/ruby/network/orion/TechParameter.hh
/gem5/src/mem/ruby/network/orion/Type.hh
/gem5/src/mem/ruby/network/orion/Wire.cc
/gem5/src/mem/ruby/network/orion/Wire.hh
/gem5/src/sim/fault_fwd.hh
/gem5/src/sim/root.cc
/gem5/src/sim/root.hh
/gem5/src/unittest/unittest.cc
/gem5/src/unittest/unittest.hh
8328:03cfd2ecf6bb 30-May-2011 Gabe Black <gblack@eecs.umich.edu>

Misc: Remove the URL from warnings, fatals, panics, etc.

8297:d57afdcf38f5 12-May-2011 Nathan Binkert <nate@binkert.org>

stats: delete mysql support
we can add it back within python in some future changeset

8296:be7f03723412 12-May-2011 Nathan Binkert <nate@binkert.org>

stats: move code that loops over all stats into python

8269:5a9a639ce16f 04-May-2011 Nathan Binkert <nate@binkert.org>

debug: fix help output

8251:ea37585785ab 25-Apr-2011 Nilay Vaish<nilay@cs.wisc.edu>

base: include types.hh in base/stats/mysql.hh
Due to certain changes made via changeset 8229, the compilation was failing
in certain cases. The compiler pointed to base/stats/mysql.hh for not naming
a certain types like uint64_t. To rectify this, base/types.hh is being
included in base/stats/mysql.hh.

8248:d69720504203 20-Apr-2011 Nathan Binkert <nate@binkert.org>

stats: ensure that stat names are valid

8243:63e849f0f341 20-Apr-2011 Brad Danofsky <bradley.danofsky@amd.com>

stats: add user settable separator string for arrayed stats

Default is '::', so no visible change unless it is overridden

8232:b28d06a175be 15-Apr-2011 Nathan Binkert <nate@binkert.org>

trace: reimplement the DTRACE function so it doesn't use a vector
At the same time, rename the trace flags to debug flags since they
have broader usage than simply tracing. This means that
--trace-flags is now --debug-flags and --trace-help is now --debug-help


/gem5/src/SConscript
/gem5/src/arch/alpha/interrupts.hh
/gem5/src/arch/alpha/kernel_stats.cc
/gem5/src/arch/alpha/linux/process.cc
/gem5/src/arch/alpha/linux/system.cc
/gem5/src/arch/alpha/process.cc
/gem5/src/arch/alpha/remote_gdb.cc
/gem5/src/arch/alpha/stacktrace.hh
/gem5/src/arch/alpha/system.cc
/gem5/src/arch/alpha/tlb.cc
/gem5/src/arch/alpha/vtophys.cc
/gem5/src/arch/arm/faults.cc
/gem5/src/arch/arm/isa.cc
/gem5/src/arch/arm/isa.hh
/gem5/src/arch/arm/isa/includes.isa
/gem5/src/arch/arm/nativetrace.cc
/gem5/src/arch/arm/predecoder.cc
/gem5/src/arch/arm/process.cc
/gem5/src/arch/arm/remote_gdb.cc
/gem5/src/arch/arm/stacktrace.hh
/gem5/src/arch/arm/tlb.cc
/gem5/src/arch/arm/types.hh
/gem5/src/arch/mips/faults.cc
/gem5/src/arch/mips/isa.cc
/gem5/src/arch/mips/isa/includes.isa
/gem5/src/arch/mips/linux/process.cc
/gem5/src/arch/mips/locked_mem.hh
/gem5/src/arch/mips/process.cc
/gem5/src/arch/mips/stacktrace.hh
/gem5/src/arch/mips/tlb.cc
/gem5/src/arch/power/process.cc
/gem5/src/arch/power/stacktrace.hh
/gem5/src/arch/power/tlb.cc
/gem5/src/arch/sparc/interrupts.hh
/gem5/src/arch/sparc/isa.cc
/gem5/src/arch/sparc/isa/includes.isa
/gem5/src/arch/sparc/process.cc
/gem5/src/arch/sparc/remote_gdb.cc
/gem5/src/arch/sparc/stacktrace.hh
/gem5/src/arch/sparc/tlb.cc
/gem5/src/arch/sparc/ua2005.cc
/gem5/src/arch/sparc/vtophys.cc
/gem5/src/arch/x86/faults.cc
/gem5/src/arch/x86/insts/microregop.cc
/gem5/src/arch/x86/insts/static_inst.hh
/gem5/src/arch/x86/interrupts.cc
/gem5/src/arch/x86/isa/includes.isa
/gem5/src/arch/x86/nativetrace.cc
/gem5/src/arch/x86/pagetable_walker.cc
/gem5/src/arch/x86/predecoder.cc
/gem5/src/arch/x86/predecoder.hh
/gem5/src/arch/x86/process.cc
/gem5/src/arch/x86/stacktrace.hh
/gem5/src/arch/x86/tlb.cc
/gem5/src/arch/x86/vtophys.cc
debug.cc
debug.hh
loader/aout_object.cc
loader/ecoff_object.cc
loader/elf_object.cc
loader/raw_object.cc
mysql.cc
remote_gdb.cc
trace.cc
trace.hh
vnc/vncserver.cc
/gem5/src/cpu/SConscript
/gem5/src/cpu/activity.cc
/gem5/src/cpu/base.cc
/gem5/src/cpu/base_dyn_inst_impl.hh
/gem5/src/cpu/exetrace.cc
/gem5/src/cpu/exetrace.hh
/gem5/src/cpu/inorder/cpu.cc
/gem5/src/cpu/inorder/first_stage.cc
/gem5/src/cpu/inorder/inorder_dyn_inst.cc
/gem5/src/cpu/inorder/inorder_dyn_inst.hh
/gem5/src/cpu/inorder/inorder_trace.cc
/gem5/src/cpu/inorder/pipeline_stage.cc
/gem5/src/cpu/inorder/reg_dep_map.cc
/gem5/src/cpu/inorder/resource.cc
/gem5/src/cpu/inorder/resource_pool.cc
/gem5/src/cpu/inorder/resource_sked.cc
/gem5/src/cpu/inorder/resources/agen_unit.cc
/gem5/src/cpu/inorder/resources/bpred_unit.cc
/gem5/src/cpu/inorder/resources/branch_predictor.cc
/gem5/src/cpu/inorder/resources/cache_unit.cc
/gem5/src/cpu/inorder/resources/decode_unit.cc
/gem5/src/cpu/inorder/resources/execution_unit.cc
/gem5/src/cpu/inorder/resources/fetch_seq_unit.cc
/gem5/src/cpu/inorder/resources/fetch_unit.cc
/gem5/src/cpu/inorder/resources/graduation_unit.cc
/gem5/src/cpu/inorder/resources/inst_buffer.cc
/gem5/src/cpu/inorder/resources/mult_div_unit.cc
/gem5/src/cpu/inorder/resources/use_def.cc
/gem5/src/cpu/inorder/thread_context.cc
/gem5/src/cpu/inteltrace.hh
/gem5/src/cpu/intr_control.cc
/gem5/src/cpu/nativetrace.cc
/gem5/src/cpu/o3/bpred_unit_impl.hh
/gem5/src/cpu/o3/commit_impl.hh
/gem5/src/cpu/o3/cpu.cc
/gem5/src/cpu/o3/decode_impl.hh
/gem5/src/cpu/o3/fetch_impl.hh
/gem5/src/cpu/o3/free_list.cc
/gem5/src/cpu/o3/free_list.hh
/gem5/src/cpu/o3/iew.hh
/gem5/src/cpu/o3/iew_impl.hh
/gem5/src/cpu/o3/inst_queue_impl.hh
/gem5/src/cpu/o3/lsq_impl.hh
/gem5/src/cpu/o3/lsq_unit.hh
/gem5/src/cpu/o3/lsq_unit_impl.hh
/gem5/src/cpu/o3/mem_dep_unit.hh
/gem5/src/cpu/o3/mem_dep_unit_impl.hh
/gem5/src/cpu/o3/regfile.hh
/gem5/src/cpu/o3/rename_impl.hh
/gem5/src/cpu/o3/rename_map.cc
/gem5/src/cpu/o3/rob_impl.hh
/gem5/src/cpu/o3/scoreboard.cc
/gem5/src/cpu/o3/scoreboard.hh
/gem5/src/cpu/o3/store_set.cc
/gem5/src/cpu/o3/thread_context_impl.hh
/gem5/src/cpu/pc_event.cc
/gem5/src/cpu/pred/2bit_local.cc
/gem5/src/cpu/pred/btb.cc
/gem5/src/cpu/quiesce_event.cc
/gem5/src/cpu/simple/atomic.cc
/gem5/src/cpu/simple/base.cc
/gem5/src/cpu/simple/timing.cc
/gem5/src/cpu/simple_thread.hh
/gem5/src/cpu/testers/directedtest/InvalidateGenerator.cc
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.cc
/gem5/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
/gem5/src/cpu/testers/memtest/memtest.cc
/gem5/src/cpu/testers/networktest/networktest.cc
/gem5/src/cpu/testers/rubytest/Check.cc
/gem5/src/cpu/testers/rubytest/CheckTable.cc
/gem5/src/cpu/testers/rubytest/RubyTester.cc
/gem5/src/cpu/thread_context.cc
/gem5/src/dev/alpha/backdoor.cc
/gem5/src/dev/alpha/tsunami_cchip.cc
/gem5/src/dev/alpha/tsunami_io.cc
/gem5/src/dev/alpha/tsunami_pchip.cc
/gem5/src/dev/copy_engine.cc
/gem5/src/dev/disk_image.cc
/gem5/src/dev/etherbus.cc
/gem5/src/dev/etherlink.cc
/gem5/src/dev/ethertap.cc
/gem5/src/dev/i8254xGBe.cc
/gem5/src/dev/i8254xGBe.hh
/gem5/src/dev/ide_ctrl.cc
/gem5/src/dev/ide_disk.cc
/gem5/src/dev/intel_8254_timer.cc
/gem5/src/dev/intel_8254_timer.hh
/gem5/src/dev/io_device.cc
/gem5/src/dev/isa_fake.cc
/gem5/src/dev/mc146818.cc
/gem5/src/dev/ns_gige.cc
/gem5/src/dev/pciconfigall.cc
/gem5/src/dev/pcidev.cc
/gem5/src/dev/simple_disk.cc
/gem5/src/dev/sinic.cc
/gem5/src/dev/sparc/iob.cc
/gem5/src/dev/sparc/mm_disk.cc
/gem5/src/dev/terminal.cc
/gem5/src/dev/uart8250.cc
/gem5/src/dev/x86/cmos.cc
/gem5/src/dev/x86/i8042.cc
/gem5/src/dev/x86/i82094aa.cc
/gem5/src/dev/x86/i8254.cc
/gem5/src/dev/x86/i8259.cc
/gem5/src/dev/x86/speaker.cc
/gem5/src/kern/linux/events.cc
/gem5/src/kern/linux/linux.cc
/gem5/src/kern/system_events.cc
/gem5/src/kern/tru64/tru64.hh
/gem5/src/kern/tru64/tru64_events.cc
/gem5/src/mem/bridge.cc
/gem5/src/mem/bus.cc
/gem5/src/mem/cache/base.cc
/gem5/src/mem/cache/base.hh
/gem5/src/mem/cache/cache_impl.hh
/gem5/src/mem/cache/mshr.cc
/gem5/src/mem/cache/prefetch/base.cc
/gem5/src/mem/cache/prefetch/ghb.cc
/gem5/src/mem/cache/prefetch/stride.cc
/gem5/src/mem/cache/tags/iic.cc
/gem5/src/mem/cache/tags/lru.cc
/gem5/src/mem/page_table.cc
/gem5/src/mem/physical.cc
/gem5/src/mem/port.cc
/gem5/src/mem/ruby/buffers/MessageBuffer.cc
/gem5/src/mem/ruby/common/NetDest.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/Router.cc
/gem5/src/mem/ruby/network/simple/PerfectSwitch.cc
/gem5/src/mem/ruby/network/simple/Throttle.cc
/gem5/src/mem/ruby/network/simple/Topology.cc
/gem5/src/mem/ruby/system/CacheMemory.cc
/gem5/src/mem/ruby/system/DMASequencer.cc
/gem5/src/mem/ruby/system/DirectoryMemory.cc
/gem5/src/mem/ruby/system/RubyPort.cc
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/SparseMemory.cc
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/mem/tport.cc
/gem5/src/python/m5/debug.py
/gem5/src/python/m5/main.py
/gem5/src/python/m5/trace.py
/gem5/src/python/swig/debug.i
/gem5/src/python/swig/trace.i
/gem5/src/sim/eventq.cc
/gem5/src/sim/eventq.hh
/gem5/src/sim/faults.cc
/gem5/src/sim/pseudo_inst.cc
/gem5/src/sim/root.cc
/gem5/src/sim/sim_object.cc
/gem5/src/sim/syscall_emul.cc
/gem5/src/sim/syscall_emul.hh
/gem5/src/sim/system.cc
8231:51cf7f3cf9ac 15-Apr-2011 Nathan Binkert <nate@binkert.org>

debug: create a Debug namespace

8230:845c8eb5ac49 15-Apr-2011 Nathan Binkert <nate@binkert.org>

includes: fix up code after sorting

8229:78bf55f23338 15-Apr-2011 Nathan Binkert <nate@binkert.org>

includes: sort all includes


/gem5/src/arch/alpha/faults.cc
/gem5/src/arch/alpha/isa.hh
/gem5/src/arch/alpha/isa/main.isa
/gem5/src/arch/alpha/linux/system.cc
/gem5/src/arch/alpha/mt.hh
/gem5/src/arch/alpha/process.cc
/gem5/src/arch/alpha/remote_gdb.cc
/gem5/src/arch/alpha/remote_gdb.hh
/gem5/src/arch/alpha/tlb.cc
/gem5/src/arch/alpha/tru64/process.cc
/gem5/src/arch/alpha/types.hh
/gem5/src/arch/alpha/utility.hh
/gem5/src/arch/arm/faults.cc
/gem5/src/arch/arm/faults.hh
/gem5/src/arch/arm/insts/macromem.cc
/gem5/src/arch/arm/insts/static_inst.cc
/gem5/src/arch/arm/insts/vfp.hh
/gem5/src/arch/arm/intregs.hh
/gem5/src/arch/arm/isa/includes.isa
/gem5/src/arch/arm/linux/atag.hh
/gem5/src/arch/arm/linux/linux.cc
/gem5/src/arch/arm/linux/process.cc
/gem5/src/arch/arm/linux/process.hh
/gem5/src/arch/arm/linux/system.cc
/gem5/src/arch/arm/locked_mem.hh
/gem5/src/arch/arm/pagetable.hh
/gem5/src/arch/arm/predecoder.hh
/gem5/src/arch/arm/process.hh
/gem5/src/arch/arm/registers.hh
/gem5/src/arch/arm/remote_gdb.cc
/gem5/src/arch/arm/system.cc
/gem5/src/arch/arm/system.hh
/gem5/src/arch/arm/table_walker.cc
/gem5/src/arch/arm/table_walker.hh
/gem5/src/arch/arm/tlb.hh
/gem5/src/arch/arm/vtophys.hh
/gem5/src/arch/generic/debugfaults.hh
/gem5/src/arch/generic/types.hh
/gem5/src/arch/mips/dsp.cc
/gem5/src/arch/mips/dsp.hh
/gem5/src/arch/mips/isa.cc
/gem5/src/arch/mips/isa.hh
/gem5/src/arch/mips/isa/includes.isa
/gem5/src/arch/mips/isa_traits.hh
/gem5/src/arch/mips/linux/linux.cc
/gem5/src/arch/mips/linux/process.cc
/gem5/src/arch/mips/linux/process.hh
/gem5/src/arch/mips/linux/system.cc
/gem5/src/arch/mips/mt.hh
/gem5/src/arch/mips/process.cc
/gem5/src/arch/mips/process.hh
/gem5/src/arch/mips/system.cc
/gem5/src/arch/mips/system.hh
/gem5/src/arch/mips/tlb.cc
/gem5/src/arch/mips/tlb.hh
/gem5/src/arch/mips/utility.cc
/gem5/src/arch/mips/utility.hh
/gem5/src/arch/mips/vtophys.hh
/gem5/src/arch/power/insts/floating.hh
/gem5/src/arch/power/insts/integer.hh
/gem5/src/arch/power/isa/includes.isa
/gem5/src/arch/power/linux/linux.cc
/gem5/src/arch/power/linux/process.cc
/gem5/src/arch/power/linux/process.hh
/gem5/src/arch/power/process.hh
/gem5/src/arch/power/tlb.hh
/gem5/src/arch/power/vtophys.hh
/gem5/src/arch/sparc/isa.hh
/gem5/src/arch/sparc/isa/includes.isa
/gem5/src/arch/sparc/isa_traits.hh
/gem5/src/arch/sparc/linux/linux.cc
/gem5/src/arch/sparc/linux/process.cc
/gem5/src/arch/sparc/locked_mem.hh
/gem5/src/arch/sparc/mmapped_ipr.hh
/gem5/src/arch/sparc/nativetrace.cc
/gem5/src/arch/sparc/process.cc
/gem5/src/arch/sparc/process.hh
/gem5/src/arch/sparc/remote_gdb.cc
/gem5/src/arch/sparc/remote_gdb.hh
/gem5/src/arch/sparc/solaris/process.cc
/gem5/src/arch/sparc/solaris/solaris.cc
/gem5/src/arch/sparc/system.cc
/gem5/src/arch/sparc/tlb.cc
/gem5/src/arch/sparc/tlb_map.hh
/gem5/src/arch/sparc/types.hh
/gem5/src/arch/sparc/utility.hh
/gem5/src/arch/sparc/vtophys.cc
/gem5/src/arch/x86/bios/acpi.cc
/gem5/src/arch/x86/bios/intelmp.hh
/gem5/src/arch/x86/emulenv.hh
/gem5/src/arch/x86/faults.hh
/gem5/src/arch/x86/insts/badmicroop.cc
/gem5/src/arch/x86/insts/macroop.hh
/gem5/src/arch/x86/insts/microfpop.cc
/gem5/src/arch/x86/insts/microldstop.cc
/gem5/src/arch/x86/insts/micromediaop.cc
/gem5/src/arch/x86/interrupts.cc
/gem5/src/arch/x86/interrupts.hh
/gem5/src/arch/x86/isa.hh
/gem5/src/arch/x86/isa/includes.isa
/gem5/src/arch/x86/linux/linux.cc
/gem5/src/arch/x86/linux/process.cc
/gem5/src/arch/x86/linux/process.hh
/gem5/src/arch/x86/linux/syscalls.cc
/gem5/src/arch/x86/linux/system.cc
/gem5/src/arch/x86/linux/system.hh
/gem5/src/arch/x86/microcode_rom.hh
/gem5/src/arch/x86/nativetrace.cc
/gem5/src/arch/x86/pagetable_walker.cc
/gem5/src/arch/x86/pagetable_walker.hh
/gem5/src/arch/x86/predecoder.hh
/gem5/src/arch/x86/process.cc
/gem5/src/arch/x86/process.hh
/gem5/src/arch/x86/registers.hh
/gem5/src/arch/x86/remote_gdb.cc
/gem5/src/arch/x86/system.cc
/gem5/src/arch/x86/tlb.cc
/gem5/src/arch/x86/tlb.hh
cp_annotate.cc
cp_annotate.hh
cprintf.hh
debug.cc
fast_alloc.hh
fenv.c
hostinfo.cc
inet.hh
inifile.cc
loader/aout_object.cc
loader/elf_object.cc
loader/elf_object.hh
loader/hex_file.cc
loader/object_file.cc
loader/symtab.cc
misc.cc
mysql.hh
output.cc
pollevent.cc
pollevent.hh
range_map.hh
remote_gdb.cc
remote_gdb.hh
socket.cc
statistics.cc
statistics.hh
stats/info.hh
stats/mysql.cc
stats/output.cc
stats/text.cc
stats/text.hh
str.hh
time.hh
trace.cc
vnc/convert.cc
vnc/vncserver.cc
vnc/vncserver.hh
/gem5/src/cpu/activity.cc
/gem5/src/cpu/activity.hh
/gem5/src/cpu/base.cc
/gem5/src/cpu/base.hh
/gem5/src/cpu/base_dyn_inst_impl.hh
/gem5/src/cpu/checker/cpu.cc
/gem5/src/cpu/checker/cpu.hh
/gem5/src/cpu/checker/cpu_impl.hh
/gem5/src/cpu/cpuevent.hh
/gem5/src/cpu/exetrace.cc
/gem5/src/cpu/func_unit.hh
/gem5/src/cpu/inorder/cpu.cc
/gem5/src/cpu/inorder/cpu.hh
/gem5/src/cpu/inorder/first_stage.cc
/gem5/src/cpu/inorder/first_stage.hh
/gem5/src/cpu/inorder/inorder_cpu_builder.cc
/gem5/src/cpu/inorder/inorder_dyn_inst.cc
/gem5/src/cpu/inorder/inorder_dyn_inst.hh
/gem5/src/cpu/inorder/inorder_trace.cc
/gem5/src/cpu/inorder/pipeline_stage.cc
/gem5/src/cpu/inorder/pipeline_stage.hh
/gem5/src/cpu/inorder/pipeline_traits.5stage.cc
/gem5/src/cpu/inorder/pipeline_traits.5stage.hh
/gem5/src/cpu/inorder/pipeline_traits.9stage.cc
/gem5/src/cpu/inorder/pipeline_traits.9stage.hh
/gem5/src/cpu/inorder/pipeline_traits.9stage.smt2.cc
/gem5/src/cpu/inorder/pipeline_traits.9stage.smt2.hh
/gem5/src/cpu/inorder/pipeline_traits.hh
/gem5/src/cpu/inorder/reg_dep_map.cc
/gem5/src/cpu/inorder/resource.cc
/gem5/src/cpu/inorder/resource.hh
/gem5/src/cpu/inorder/resource_pool.9stage.cc
/gem5/src/cpu/inorder/resource_pool.cc
/gem5/src/cpu/inorder/resource_pool.hh
/gem5/src/cpu/inorder/resource_sked.cc
/gem5/src/cpu/inorder/resource_sked.hh
/gem5/src/cpu/inorder/resources/agen_unit.hh
/gem5/src/cpu/inorder/resources/bpred_unit.hh
/gem5/src/cpu/inorder/resources/branch_predictor.hh
/gem5/src/cpu/inorder/resources/cache_unit.cc
/gem5/src/cpu/inorder/resources/cache_unit.hh
/gem5/src/cpu/inorder/resources/decode_unit.hh
/gem5/src/cpu/inorder/resources/execution_unit.cc
/gem5/src/cpu/inorder/resources/execution_unit.hh
/gem5/src/cpu/inorder/resources/fetch_seq_unit.hh
/gem5/src/cpu/inorder/resources/fetch_unit.cc
/gem5/src/cpu/inorder/resources/fetch_unit.hh
/gem5/src/cpu/inorder/resources/graduation_unit.hh
/gem5/src/cpu/inorder/resources/inst_buffer.cc
/gem5/src/cpu/inorder/resources/inst_buffer.hh
/gem5/src/cpu/inorder/resources/mem_dep_unit.hh
/gem5/src/cpu/inorder/resources/mult_div_unit.cc
/gem5/src/cpu/inorder/resources/mult_div_unit.hh
/gem5/src/cpu/inorder/resources/resource_list.hh
/gem5/src/cpu/inorder/resources/tlb_unit.cc
/gem5/src/cpu/inorder/resources/tlb_unit.hh
/gem5/src/cpu/inorder/resources/use_def.cc
/gem5/src/cpu/inorder/resources/use_def.hh
/gem5/src/cpu/inorder/thread_context.cc
/gem5/src/cpu/inorder/thread_context.hh
/gem5/src/cpu/inorder/thread_state.cc
/gem5/src/cpu/intr_control.cc
/gem5/src/cpu/intr_control.hh
/gem5/src/cpu/nativetrace.hh
/gem5/src/cpu/o3/base_dyn_inst.cc
/gem5/src/cpu/o3/bpred_unit.hh
/gem5/src/cpu/o3/bpred_unit_impl.hh
/gem5/src/cpu/o3/checker_builder.cc
/gem5/src/cpu/o3/commit.cc
/gem5/src/cpu/o3/commit.hh
/gem5/src/cpu/o3/commit_impl.hh
/gem5/src/cpu/o3/cpu.cc
/gem5/src/cpu/o3/cpu.hh
/gem5/src/cpu/o3/cpu_policy.hh
/gem5/src/cpu/o3/decode.cc
/gem5/src/cpu/o3/dyn_inst.hh
/gem5/src/cpu/o3/fetch.cc
/gem5/src/cpu/o3/fetch.hh
/gem5/src/cpu/o3/fetch_impl.hh
/gem5/src/cpu/o3/free_list.cc
/gem5/src/cpu/o3/fu_pool.hh
/gem5/src/cpu/o3/iew.cc
/gem5/src/cpu/o3/iew.hh
/gem5/src/cpu/o3/iew_impl.hh
/gem5/src/cpu/o3/impl.hh
/gem5/src/cpu/o3/inst_queue.cc
/gem5/src/cpu/o3/inst_queue.hh
/gem5/src/cpu/o3/isa_specific.hh
/gem5/src/cpu/o3/lsq.hh
/gem5/src/cpu/o3/lsq_unit.hh
/gem5/src/cpu/o3/lsq_unit_impl.hh
/gem5/src/cpu/o3/mem_dep_unit.cc
/gem5/src/cpu/o3/rename.hh
/gem5/src/cpu/o3/scoreboard.hh
/gem5/src/cpu/o3/thread_context.cc
/gem5/src/cpu/o3/thread_context.hh
/gem5/src/cpu/ozone/back_end.hh
/gem5/src/cpu/ozone/back_end_impl.hh
/gem5/src/cpu/ozone/base_dyn_inst.cc
/gem5/src/cpu/ozone/checker_builder.cc
/gem5/src/cpu/ozone/cpu.hh
/gem5/src/cpu/ozone/cpu_builder.cc
/gem5/src/cpu/ozone/cpu_impl.hh
/gem5/src/cpu/ozone/dyn_inst.hh
/gem5/src/cpu/ozone/dyn_inst_impl.hh
/gem5/src/cpu/ozone/ea_list.cc
/gem5/src/cpu/ozone/front_end.hh
/gem5/src/cpu/ozone/front_end_impl.hh
/gem5/src/cpu/ozone/inorder_back_end.hh
/gem5/src/cpu/ozone/inorder_back_end_impl.hh
/gem5/src/cpu/ozone/inst_queue.cc
/gem5/src/cpu/ozone/inst_queue.hh
/gem5/src/cpu/ozone/inst_queue_impl.hh
/gem5/src/cpu/ozone/lsq_unit.cc
/gem5/src/cpu/ozone/lsq_unit.hh
/gem5/src/cpu/ozone/lw_back_end.hh
/gem5/src/cpu/ozone/lw_lsq.cc
/gem5/src/cpu/ozone/lw_lsq.hh
/gem5/src/cpu/ozone/lw_lsq_impl.hh
/gem5/src/cpu/ozone/ozone_base_dyn_inst.cc
/gem5/src/cpu/ozone/ozone_impl.hh
/gem5/src/cpu/ozone/rename_table.cc
/gem5/src/cpu/ozone/simple_base_dyn_inst.cc
/gem5/src/cpu/ozone/simple_cpu_builder.cc
/gem5/src/cpu/ozone/simple_impl.hh
/gem5/src/cpu/pc_event.cc
/gem5/src/cpu/profile.cc
/gem5/src/cpu/profile.hh
/gem5/src/cpu/quiesce_event.cc
/gem5/src/cpu/sched_list.hh
/gem5/src/cpu/simple/atomic.cc
/gem5/src/cpu/simple/base.cc
/gem5/src/cpu/simple/base.hh
/gem5/src/cpu/simple/timing.cc
/gem5/src/cpu/simple/timing.hh
/gem5/src/cpu/simple_thread.hh
/gem5/src/cpu/static_inst.cc
/gem5/src/cpu/static_inst.hh
/gem5/src/cpu/testers/directedtest/InvalidateGenerator.cc
/gem5/src/cpu/testers/directedtest/InvalidateGenerator.hh
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.hh
/gem5/src/cpu/testers/memtest/memtest.cc
/gem5/src/cpu/testers/memtest/memtest.hh
/gem5/src/cpu/testers/networktest/networktest.cc
/gem5/src/cpu/testers/networktest/networktest.hh
/gem5/src/cpu/testers/rubytest/CheckTable.cc
/gem5/src/cpu/testers/rubytest/RubyTester.hh
/gem5/src/cpu/thread_context.hh
/gem5/src/cpu/thread_state.hh
/gem5/src/cpu/trace/opt_cpu.cc
/gem5/src/cpu/trace/reader/ibm_reader.hh
/gem5/src/cpu/trace/reader/itx_reader.hh
/gem5/src/cpu/trace/reader/mem_trace_reader.hh
/gem5/src/cpu/trace/trace_cpu.cc
/gem5/src/dev/alpha/tsunami.cc
/gem5/src/dev/alpha/tsunami_io.cc
/gem5/src/dev/alpha/tsunami_io.hh
/gem5/src/dev/alpha/tsunami_pchip.cc
/gem5/src/dev/arm/amba_device.cc
/gem5/src/dev/arm/amba_device.hh
/gem5/src/dev/arm/kmi.cc
/gem5/src/dev/arm/kmi.hh
/gem5/src/dev/arm/pl111.cc
/gem5/src/dev/disk_image.cc
/gem5/src/dev/disk_image.hh
/gem5/src/dev/etherbus.hh
/gem5/src/dev/etherdump.hh
/gem5/src/dev/etherint.cc
/gem5/src/dev/etherlink.cc
/gem5/src/dev/etherlink.hh
/gem5/src/dev/ethertap.cc
/gem5/src/dev/ethertap.hh
/gem5/src/dev/ide_ctrl.hh
/gem5/src/dev/ide_disk.cc
/gem5/src/dev/ide_disk.hh
/gem5/src/dev/intel_8254_timer.hh
/gem5/src/dev/io_device.cc
/gem5/src/dev/isa_fake.hh
/gem5/src/dev/mc146818.cc
/gem5/src/dev/mips/malta.cc
/gem5/src/dev/mips/malta_cchip.hh
/gem5/src/dev/mips/malta_io.cc
/gem5/src/dev/mips/malta_pchip.cc
/gem5/src/dev/mips/malta_pchip.hh
/gem5/src/dev/pciconfigall.hh
/gem5/src/dev/platform.hh
/gem5/src/dev/ps2.cc
/gem5/src/dev/simple_disk.hh
/gem5/src/dev/sparc/iob.cc
/gem5/src/dev/sparc/iob.hh
/gem5/src/dev/sparc/mm_disk.cc
/gem5/src/dev/sparc/mm_disk.hh
/gem5/src/dev/terminal.cc
/gem5/src/dev/terminal.hh
/gem5/src/dev/x86/i8042.hh
/gem5/src/dev/x86/i82094aa.hh
/gem5/src/dev/x86/i8259.hh
/gem5/src/dev/x86/intdev.hh
/gem5/src/dev/x86/pc.cc
/gem5/src/dev/x86/south_bridge.hh
/gem5/src/kern/kernel_stats.cc
/gem5/src/kern/kernel_stats.hh
/gem5/src/kern/linux/events.cc
/gem5/src/kern/linux/printk.cc
/gem5/src/kern/operatingsystem.cc
/gem5/src/kern/tru64/dump_mbuf.cc
/gem5/src/kern/tru64/printf.cc
/gem5/src/kern/tru64/tru64.hh
/gem5/src/kern/tru64/tru64_events.cc
/gem5/src/mem/bridge.hh
/gem5/src/mem/bus.hh
/gem5/src/mem/cache/base.hh
/gem5/src/mem/cache/blk.hh
/gem5/src/mem/cache/builder.cc
/gem5/src/mem/cache/cache.hh
/gem5/src/mem/cache/cache_impl.hh
/gem5/src/mem/cache/mshr_queue.hh
/gem5/src/mem/cache/prefetch/base.cc
/gem5/src/mem/cache/prefetch/stride.hh
/gem5/src/mem/cache/tags/base.cc
/gem5/src/mem/cache/tags/base.hh
/gem5/src/mem/cache/tags/cacheset.hh
/gem5/src/mem/cache/tags/fa_lru.hh
/gem5/src/mem/cache/tags/iic.cc
/gem5/src/mem/cache/tags/iic.hh
/gem5/src/mem/cache/tags/iic_repl/gen.cc
/gem5/src/mem/cache/tags/iic_repl/repl.hh
/gem5/src/mem/cache/tags/lru.cc
/gem5/src/mem/cache/tags/lru.hh
/gem5/src/mem/packet.cc
/gem5/src/mem/packet.hh
/gem5/src/mem/page_table.cc
/gem5/src/mem/physical.cc
/gem5/src/mem/ruby/buffers/MessageBuffer.hh
/gem5/src/mem/ruby/common/NetDest.cc
/gem5/src/mem/ruby/common/Set.hh
/gem5/src/mem/ruby/filters/GenericBloomFilter.hh
/gem5/src/mem/ruby/network/Network.cc
/gem5/src/mem/ruby/network/garnet/BaseGarnetNetwork.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/OutVcState_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/OutVcState_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/RoutingUnit_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/RoutingUnit_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/SWallocator_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/SWallocator_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/VCallocator_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/VCallocator_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/VirtualChannel_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/flitBuffer_d.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/FlexibleConsumer.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/Router.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/Router.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/VCarbiter.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/VCarbiter.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/flitBuffer.hh
/gem5/src/mem/ruby/network/orion/Allocator/Arbiter.cc
/gem5/src/mem/ruby/network/orion/Allocator/MatrixArbiter.hh
/gem5/src/mem/ruby/network/orion/Allocator/RRArbiter.cc
/gem5/src/mem/ruby/network/orion/Allocator/RRArbiter.hh
/gem5/src/mem/ruby/network/orion/Allocator/SWAllocator.cc
/gem5/src/mem/ruby/network/orion/Allocator/VCAllocator.cc
/gem5/src/mem/ruby/network/orion/Buffer/Buffer.cc
/gem5/src/mem/ruby/network/orion/Buffer/DecoderUnit.hh
/gem5/src/mem/ruby/network/orion/Buffer/OutdrvUnit.cc
/gem5/src/mem/ruby/network/orion/Buffer/PrechargeUnit.cc
/gem5/src/mem/ruby/network/orion/Buffer/Register.cc
/gem5/src/mem/ruby/network/orion/Buffer/SRAM.cc
/gem5/src/mem/ruby/network/orion/Buffer/SRAM.hh
/gem5/src/mem/ruby/network/orion/Buffer/WordlineUnit.cc
/gem5/src/mem/ruby/network/orion/Clock.cc
/gem5/src/mem/ruby/network/orion/ConfigFile.hh
/gem5/src/mem/ruby/network/orion/Crossbar/Crossbar.cc
/gem5/src/mem/ruby/network/orion/Crossbar/MatrixCrossbar.cc
/gem5/src/mem/ruby/network/orion/Crossbar/MatrixCrossbar.hh
/gem5/src/mem/ruby/network/orion/Crossbar/MultreeCrossbar.cc
/gem5/src/mem/ruby/network/orion/Crossbar/MultreeCrossbar.hh
/gem5/src/mem/ruby/network/orion/FlipFlop.cc
/gem5/src/mem/ruby/network/orion/NetworkPower.cc
/gem5/src/mem/ruby/network/orion/NetworkPower.hh
/gem5/src/mem/ruby/network/orion/OrionConfig.cc
/gem5/src/mem/ruby/network/orion/OrionConfig.hh
/gem5/src/mem/ruby/network/orion/OrionLink.cc
/gem5/src/mem/ruby/network/orion/OrionRouter.cc
/gem5/src/mem/ruby/network/orion/TechParameter.cc
/gem5/src/mem/ruby/network/orion/Wire.cc
/gem5/src/mem/ruby/network/orion/orion.hh
/gem5/src/mem/ruby/network/simple/PerfectSwitch.hh
/gem5/src/mem/ruby/network/simple/Switch.cc
/gem5/src/mem/ruby/network/simple/Throttle.cc
/gem5/src/mem/ruby/network/simple/Throttle.hh
/gem5/src/mem/ruby/network/simple/Topology.cc
/gem5/src/mem/ruby/profiler/CacheProfiler.hh
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/recorder/CacheRecorder.cc
/gem5/src/mem/ruby/recorder/CacheRecorder.hh
/gem5/src/mem/ruby/recorder/Tracer.hh
/gem5/src/mem/ruby/slicc_interface/AbstractEntry.hh
/gem5/src/mem/ruby/slicc_interface/RubyRequest.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.cc
/gem5/src/mem/ruby/slicc_interface/RubySlicc_includes.hh
/gem5/src/mem/ruby/system/CacheMemory.hh
/gem5/src/mem/ruby/system/RubyPort.cc
/gem5/src/mem/ruby/system/RubyPort.hh
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/Sequencer.hh
/gem5/src/mem/ruby/system/WireBuffer.hh
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/mem/tport.hh
/gem5/src/mem/translating_port.cc
/gem5/src/mem/vport.hh
/gem5/src/python/swig/core.i
/gem5/src/python/swig/event.i
/gem5/src/python/swig/inet.i
/gem5/src/python/swig/pyobject.cc
/gem5/src/python/swig/sim_object.i
/gem5/src/python/swig/stats.i
/gem5/src/python/swig/system.i
/gem5/src/sim/faults.cc
/gem5/src/sim/faults.hh
/gem5/src/sim/init.cc
/gem5/src/sim/process.cc
/gem5/src/sim/process_impl.hh
/gem5/src/sim/pseudo_inst.cc
/gem5/src/sim/serialize.cc
/gem5/src/sim/serialize.hh
/gem5/src/sim/stat_control.cc
/gem5/src/sim/syscall_emul.cc
/gem5/src/sim/syscall_emul.hh
/gem5/src/sim/system.cc
/gem5/src/sim/tlb.cc
/gem5/src/sim/vptr.hh
/gem5/src/unittest/cprintftest.cc
/gem5/src/unittest/cprintftime.cc
/gem5/src/unittest/initest.cc
/gem5/src/unittest/rangemaptest.cc
/gem5/src/unittest/stattest.cc
/gem5/src/unittest/symtest.cc
/gem5/util/ccdrv/devtime.c
/gem5/util/m5/m5.c
/gem5/util/statetrace/arch/amd64/tracechild.cc
/gem5/util/statetrace/arch/amd64/tracechild.hh
/gem5/util/statetrace/arch/arm/tracechild.cc
/gem5/util/statetrace/arch/arm/tracechild.hh
/gem5/util/statetrace/arch/i686/tracechild.cc
/gem5/util/statetrace/arch/i686/tracechild.hh
/gem5/util/statetrace/arch/sparc/tracechild.cc
/gem5/util/statetrace/arch/sparc/tracechild.hh
/gem5/util/statetrace/base/regstate.hh
/gem5/util/statetrace/base/statetrace.cc
/gem5/util/statetrace/base/tracechild.cc
/gem5/util/tap/tap.cc
/gem5/util/term/term.c
8221:8b5f900233ee 13-Apr-2011 Nathan Binkert <nate@binkert.org>

refcnt: Update doxygen comments

8220:d9f19c39ddba 13-Apr-2011 Nathan Binkert <nate@binkert.org>

refcnt: Inline comparison functions

8152:a6052f50deed 18-Mar-2011 Steve Reinhardt <steve.reinhardt@amd.com>

base: disable FastAlloc in debug builds by default
FastAlloc's reuse policies can mask allocation bugs, so
we typically want it disabled when debugging. Set
FORCE_FAST_ALLOC to enable even when debugging, and set
NO_FAST_ALLOC to disable even in non-debug builds.

7949:e59dac494020 11-Feb-2011 Ali Saidi <Ali.Saidi@ARM.com>

VNC: Add VNC server to M5

7870:7cb62588fcdc 02-Feb-2011 Gabe Black <gblack@eecs.umich.edu>

Time: Add serialization functions to the Time class.

7866:31a04e5ac4be 23-Jan-2011 Nathan Binkert <nate@binkert.org>

refcnt: Change things around so that we handle constness correctly.
To use a non const pointer:
typedef RefCountingPtr<Foo> FooPtr;

To use a const pointer:
typedef RefCountingPtr<const Foo> ConstFooPtr;

7862:23758c97c227 19-Jan-2011 Gabe Black <gblack@eecs.umich.edu>

Time: Add setTick and getTick functions to the Time class.

7840:ed75cee5c793 15-Jan-2011 Nathan Binkert <nate@binkert.org>

time: improve time datastructure

Use posix clock functions (and librt) if it is available.
Inline a bunch of functions and implement more operators.
* * *
time: more cleanup

7831:c1e158414648 10-Jan-2011 Nathan Binkert <nate@binkert.org>

stats: Add a histogram statistic type

7829:9069448c4fbc 10-Jan-2011 Nathan Binkert <nate@binkert.org>

stats: fix the distribution stat

7825:e49c7db3ac53 10-Jan-2011 Gabe Black <gblack@eecs.umich.edu>

Curtick: Fix mysql.cc build needing curTick.

7823:dac01f14f20f 08-Jan-2011 Steve Reinhardt <steve.reinhardt@amd.com>

Replace curTick global variable with accessor functions.
This step makes it easy to replace the accessor functions
(which still access a global variable) with ones that access
per-thread curTick values.


/gem5/src/arch/alpha/isa/decoder.isa
/gem5/src/arch/alpha/kernel_stats.cc
/gem5/src/arch/alpha/tru64/process.cc
/gem5/src/arch/arm/table_walker.cc
/gem5/src/arch/mips/isa.cc
/gem5/src/arch/mips/isa/formats/mt.isa
/gem5/src/arch/mips/locked_mem.hh
/gem5/src/arch/mips/mt.hh
/gem5/src/arch/sparc/ua2005.cc
/gem5/src/arch/x86/interrupts.cc
cp_annotate.cc
cp_annotate.hh
fast_alloc.cc
misc.cc
remote_gdb.cc
statistics.hh
stats/mysql.cc
stats/output.cc
trace.hh
/gem5/src/cpu/base.cc
/gem5/src/cpu/base.hh
/gem5/src/cpu/checker/cpu.cc
/gem5/src/cpu/checker/cpu_impl.hh
/gem5/src/cpu/inorder/cpu.cc
/gem5/src/cpu/inorder/cpu.hh
/gem5/src/cpu/inorder/inorder_dyn_inst.cc
/gem5/src/cpu/inorder/pipeline_stage.cc
/gem5/src/cpu/inorder/reg_dep_map.cc
/gem5/src/cpu/inorder/resource.cc
/gem5/src/cpu/inorder/resource_pool.9stage.cc
/gem5/src/cpu/inorder/resource_pool.cc
/gem5/src/cpu/inorder/resources/branch_predictor.cc
/gem5/src/cpu/inorder/resources/cache_unit.cc
/gem5/src/cpu/inorder/resources/execution_unit.cc
/gem5/src/cpu/inorder/resources/fetch_seq_unit.cc
/gem5/src/cpu/inorder/resources/graduation_unit.cc
/gem5/src/cpu/inorder/resources/mult_div_unit.cc
/gem5/src/cpu/o3/commit_impl.hh
/gem5/src/cpu/o3/cpu.cc
/gem5/src/cpu/o3/cpu.hh
/gem5/src/cpu/o3/fetch_impl.hh
/gem5/src/cpu/o3/inst_queue_impl.hh
/gem5/src/cpu/o3/lsq_impl.hh
/gem5/src/cpu/o3/lsq_unit.hh
/gem5/src/cpu/o3/lsq_unit_impl.hh
/gem5/src/cpu/o3/thread_context_impl.hh
/gem5/src/cpu/ozone/back_end.hh
/gem5/src/cpu/ozone/cpu.hh
/gem5/src/cpu/ozone/cpu_impl.hh
/gem5/src/cpu/ozone/front_end_impl.hh
/gem5/src/cpu/ozone/inorder_back_end.hh
/gem5/src/cpu/ozone/inst_queue_impl.hh
/gem5/src/cpu/ozone/lsq_unit.hh
/gem5/src/cpu/ozone/lsq_unit_impl.hh
/gem5/src/cpu/ozone/lw_back_end_impl.hh
/gem5/src/cpu/ozone/lw_lsq.hh
/gem5/src/cpu/ozone/lw_lsq_impl.hh
/gem5/src/cpu/pc_event.cc
/gem5/src/cpu/simple/atomic.cc
/gem5/src/cpu/simple/base.cc
/gem5/src/cpu/simple/timing.cc
/gem5/src/cpu/simple_thread.cc
/gem5/src/cpu/static_inst.cc
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.cc
/gem5/src/cpu/testers/memtest/memtest.cc
/gem5/src/cpu/testers/rubytest/Check.cc
/gem5/src/cpu/testers/rubytest/RubyTester.cc
/gem5/src/cpu/trace/trace_cpu.cc
/gem5/src/dev/alpha/backdoor.cc
/gem5/src/dev/arm/pl011.cc
/gem5/src/dev/arm/pl111.cc
/gem5/src/dev/arm/rv_ctrl.cc
/gem5/src/dev/arm/timer_sp804.cc
/gem5/src/dev/etherbus.cc
/gem5/src/dev/etherdump.cc
/gem5/src/dev/etherlink.cc
/gem5/src/dev/ethertap.cc
/gem5/src/dev/i8254xGBe.cc
/gem5/src/dev/ide_disk.cc
/gem5/src/dev/intel_8254_timer.cc
/gem5/src/dev/io_device.cc
/gem5/src/dev/mc146818.cc
/gem5/src/dev/mc146818.hh
/gem5/src/dev/ns_gige.cc
/gem5/src/dev/sinic.cc
/gem5/src/dev/uart8250.cc
/gem5/src/kern/kernel_stats.cc
/gem5/src/mem/bridge.cc
/gem5/src/mem/bus.cc
/gem5/src/mem/cache/base.cc
/gem5/src/mem/cache/base.hh
/gem5/src/mem/cache/blk.hh
/gem5/src/mem/cache/cache_impl.hh
/gem5/src/mem/cache/mshr.cc
/gem5/src/mem/cache/mshr.hh
/gem5/src/mem/cache/mshr_queue.hh
/gem5/src/mem/cache/tags/fa_lru.cc
/gem5/src/mem/cache/tags/iic.cc
/gem5/src/mem/cache/tags/lru.cc
/gem5/src/mem/dram.cc
/gem5/src/mem/mport.cc
/gem5/src/mem/packet.hh
/gem5/src/mem/request.hh
/gem5/src/mem/ruby/eventqueue/RubyEventQueue.hh
/gem5/src/mem/ruby/system/RubyPort.cc
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/tport.cc
/gem5/src/mem/tport.hh
/gem5/src/python/m5/simulate.py
/gem5/src/python/swig/core.i
/gem5/src/python/swig/stats.i
/gem5/src/sim/core.cc
/gem5/src/sim/core.hh
/gem5/src/sim/eventq.cc
/gem5/src/sim/eventq.hh
/gem5/src/sim/init.cc
/gem5/src/sim/pseudo_inst.cc
/gem5/src/sim/serialize.cc
/gem5/src/sim/serialize.hh
/gem5/src/sim/sim_events.cc
/gem5/src/sim/sim_exit.hh
/gem5/src/sim/sim_object.hh
/gem5/src/sim/simulate.cc
/gem5/src/sim/stat_control.cc
/gem5/src/sim/stat_control.hh
/gem5/src/sim/syscall_emul.cc
/gem5/src/sim/syscall_emul.hh
/gem5/src/unittest/stattest.cc
7814:c819526b7c2a 04-Jan-2011 Gabe Black <gblack@eecs.umich.edu>

Params: Print the IP components in the right order.

7813:7338bc628489 03-Jan-2011 Steve Reinhardt <steve.reinhardt@amd.com>

Move sched_list.hh and timebuf.hh from src/base to src/cpu.
These files really aren't general enough to belong in src/base.
This patch doesn't reorder include lines, leaving them unsorted
in many cases, but Nate's magic script will fix that up shortly.

7812:850d71d21135 03-Jan-2011 Steve Reinhardt <steve.reinhardt@amd.com>

Delete unused files from src/base directory.

7811:a8fc35183c10 03-Jan-2011 Steve Reinhardt <steve.reinhardt@amd.com>

Make commenting on close namespace brackets consistent.

Ran all the source files through 'perl -pi' with this script:

s|\s*(};?\s*)?/\*\s*(end\s*)?namespace\s*(\S+)\s*\*/(\s*})?|} // namespace $3|;
s|\s*};?\s*//\s*(end\s*)?namespace\s*(\S+)\s*|} // namespace $2\n|;
s|\s*};?\s*//\s*(\S+)\s*namespace\s*|} // namespace $1\n|;

Also did a little manual editing on some of the arch/*/isa_traits.hh files
and src/SConscript.


/gem5/src/SConscript
/gem5/src/arch/alpha/mt.hh
/gem5/src/arch/alpha/pagetable.cc
/gem5/src/arch/alpha/tlb.cc
/gem5/src/arch/arm/faults.hh
/gem5/src/arch/arm/isa_traits.hh
/gem5/src/arch/arm/kernel_stats.hh
/gem5/src/arch/arm/nativetrace.cc
/gem5/src/arch/arm/nativetrace.hh
/gem5/src/arch/arm/tlb.hh
/gem5/src/arch/mips/dsp.hh
/gem5/src/arch/mips/faults.hh
/gem5/src/arch/mips/isa_traits.hh
/gem5/src/arch/mips/kernel_stats.hh
/gem5/src/arch/mips/linux/threadinfo.hh
/gem5/src/arch/power/faults.hh
/gem5/src/arch/power/insts/branch.hh
/gem5/src/arch/power/insts/condition.hh
/gem5/src/arch/power/insts/floating.hh
/gem5/src/arch/power/insts/integer.hh
/gem5/src/arch/power/insts/mem.hh
/gem5/src/arch/power/insts/misc.hh
/gem5/src/arch/power/insts/static_inst.hh
/gem5/src/arch/power/isa.hh
/gem5/src/arch/power/isa_traits.hh
/gem5/src/arch/power/locked_mem.hh
/gem5/src/arch/power/microcode_rom.hh
/gem5/src/arch/power/miscregs.hh
/gem5/src/arch/power/mmaped_ipr.hh
/gem5/src/arch/power/pagetable.cc
/gem5/src/arch/power/pagetable.hh
/gem5/src/arch/power/predecoder.hh
/gem5/src/arch/power/registers.hh
/gem5/src/arch/power/remote_gdb.hh
/gem5/src/arch/power/stacktrace.hh
/gem5/src/arch/power/tlb.hh
/gem5/src/arch/power/types.hh
/gem5/src/arch/power/utility.cc
/gem5/src/arch/power/utility.hh
/gem5/src/arch/power/vtophys.hh
/gem5/src/arch/sparc/faults.hh
/gem5/src/arch/sparc/kernel_stats.hh
/gem5/src/arch/sparc/nativetrace.cc
/gem5/src/arch/sparc/nativetrace.hh
/gem5/src/arch/sparc/tlb.cc
/gem5/src/arch/sparc/vtophys.cc
/gem5/src/arch/x86/cpuid.cc
/gem5/src/arch/x86/nativetrace.cc
/gem5/src/arch/x86/nativetrace.hh
/gem5/src/arch/x86/registers.hh
/gem5/src/arch/x86/tlb.cc
/gem5/src/arch/x86/utility.cc
cprintf.cc
cprintf.hh
hashmap.hh
inet.cc
inet.hh
mysql.cc
mysql.hh
statistics.cc
statistics.hh
stats/info.hh
stats/mysql.cc
stats/mysql.hh
stats/mysql_run.hh
stats/output.cc
stats/output.hh
stats/text.cc
stats/text.hh
stats/types.hh
stats/visit.cc
stats/visit.hh
stl_helpers.hh
trace.cc
trace.hh
varargs.hh
/gem5/src/cpu/exetrace.cc
/gem5/src/cpu/exetrace.hh
/gem5/src/cpu/inorder/inorder_trace.cc
/gem5/src/cpu/inorder/inorder_trace.hh
/gem5/src/cpu/inteltrace.cc
/gem5/src/cpu/inteltrace.hh
/gem5/src/cpu/legiontrace.cc
/gem5/src/cpu/legiontrace.hh
/gem5/src/cpu/nativetrace.cc
/gem5/src/cpu/nativetrace.hh
/gem5/src/dev/copy_engine_defs.hh
/gem5/src/dev/i8254xGBe_defs.hh
/gem5/src/dev/sinic.cc
/gem5/src/dev/sinic.hh
/gem5/src/dev/sinicreg.hh
/gem5/src/dev/x86/cmos.hh
/gem5/src/dev/x86/i8042.hh
/gem5/src/dev/x86/i82094aa.hh
/gem5/src/dev/x86/i8237.hh
/gem5/src/dev/x86/i8254.hh
/gem5/src/dev/x86/i8259.hh
/gem5/src/dev/x86/intdev.hh
/gem5/src/dev/x86/speaker.hh
/gem5/src/kern/kernel_stats.cc
/gem5/src/kern/kernel_stats.hh
/gem5/src/mem/ruby/common/Address.hh
/gem5/src/python/m5/SimObject.py
/gem5/src/python/m5/params.py
/gem5/src/python/swig/stats.i
/gem5/src/sim/core.cc
/gem5/src/sim/core.hh
/gem5/src/sim/insttracer.hh
/gem5/src/sim/pseudo_inst.cc
/gem5/src/sim/pseudo_inst.hh
/gem5/src/sim/stat_control.cc
/gem5/src/sim/stat_control.hh
7810:3a790012d6ed 03-Jan-2011 Gabe Black <gblack@eecs.umich.edu>

RefCount: Fix reference counting pointer == and != with a T* on the left.

These operators were expecting a const T& instead of a const T*, and were not
being picked up and used by gcc in the right places as a result. Apparently no
one used these operators before. A unit test which exposed these problems,
verified the solution, and checks other basic functionality is on the way.

7803:f4a27beb6fde 22-Dec-2010 Steve Reinhardt <steve.reinhardt@amd.com>

Get rid of unused file src/base/dbl_list.hh

7778:6a7207241112 23-Nov-2010 Gabe Black <gblack@eecs.umich.edu>

Copyright: Add AMD copyright to the param changes I just made.

7777:369f90d32e2e 23-Nov-2010 Gabe Black <gblack@eecs.umich.edu>

Params: Add parameter types for IP addresses in various forms.

New parameter forms are:
IP address in the format "a.b.c.d" where a-d are from decimal 0 to 255.
IP address with netmask which is an IP followed by "/n" where n is a netmask
length in bits from decimal 0 to 32 or by "/e.f.g.h" where e-h are from
decimal 0 to 255 and which is all 1 bits followed by all 0 bits when
represented in binary. These can also be specified as an integral IP and
netmask passed in separately.
IP address with port which is an IP followed by ":p" where p is a port index
from decimal 0 to 65535. These can also be specified as an integral IP and
port value passed in separately.

7771:e10aff32c561 20-Nov-2010 Nathan Binkert <nate@binkert.org>

random: small comment about our random number generator and its origin

7768:cdb18c1b51ea 19-Nov-2010 Ali Saidi <Ali.Saidi@ARM.com>

SCons: Support building without an ISA

7723:ee4ac00d0774 08-Nov-2010 Ali Saidi <Ali.Saidi@ARM.com>

sim: Use forward declarations for ports.

Virtual ports need TLB data which means anything touching a file in the arch
directory rebuilds any file that includes system.hh which in everything.

7720:65d338a8dba4 31-Oct-2010 Gabe Black <gblack@eecs.umich.edu>

ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.



This change is a low level and pervasive reorganization of how PCs are managed
in M5. Back when Alpha was the only ISA, there were only 2 PCs to worry about,
the PC and the NPC, and the lsb of the PC signaled whether or not you were in
PAL mode. As other ISAs were added, we had to add an NNPC, micro PC and next
micropc, x86 and ARM introduced variable length instruction sets, and ARM
started to keep track of mode bits in the PC. Each CPU model handled PCs in
its own custom way that needed to be updated individually to handle the new
dimensions of variability, or, in the case of ARMs mode-bit-in-the-pc hack,
the complexity could be hidden in the ISA at the ISA implementation's expense.
Areas like the branch predictor hadn't been updated to handle branch delay
slots or micropcs, and it turns out that had introduced a significant (10s of
percent) performance bug in SPARC and to a lesser extend MIPS. Rather than
perpetuate the problem by reworking O3 again to handle the PC features needed
by x86, this change was introduced to rework PC handling in a more modular,
transparent, and hopefully efficient way.


PC type:

Rather than having the superset of all possible elements of PC state declared
in each of the CPU models, each ISA defines its own PCState type which has
exactly the elements it needs. A cross product of canned PCState classes are
defined in the new "generic" ISA directory for ISAs with/without delay slots
and microcode. These are either typedef-ed or subclassed by each ISA. To read
or write this structure through a *Context, you use the new pcState() accessor
which reads or writes depending on whether it has an argument. If you just
want the address of the current or next instruction or the current micro PC,
you can get those through read-only accessors on either the PCState type or
the *Contexts. These are instAddr(), nextInstAddr(), and microPC(). Note the
move away from readPC. That name is ambiguous since it's not clear whether or
not it should be the actual address to fetch from, or if it should have extra
bits in it like the PAL mode bit. Each class is free to define its own
functions to get at whatever values it needs however it needs to to be used in
ISA specific code. Eventually Alpha's PAL mode bit could be moved out of the
PC and into a separate field like ARM.

These types can be reset to a particular pc (where npc = pc +
sizeof(MachInst), nnpc = npc + sizeof(MachInst), upc = 0, nupc = 1 as
appropriate), printed, serialized, and compared. There is a branching()
function which encapsulates code in the CPU models that checked if an
instruction branched or not. Exactly what that means in the context of branch
delay slots which can skip an instruction when not taken is ambiguous, and
ideally this function and its uses can be eliminated. PCStates also generally
know how to advance themselves in various ways depending on if they point at
an instruction, a microop, or the last microop of a macroop. More on that
later.

Ideally, accessing all the PCs at once when setting them will improve
performance of M5 even though more data needs to be moved around. This is
because often all the PCs need to be manipulated together, and by getting them
all at once you avoid multiple function calls. Also, the PCs of a particular
thread will have spatial locality in the cache. Previously they were grouped
by element in arrays which spread out accesses.


Advancing the PC:

The PCs were previously managed entirely by the CPU which had to know about PC
semantics, try to figure out which dimension to increment the PC in, what to
set NPC/NNPC, etc. These decisions are best left to the ISA in conjunction
with the PC type itself. Because most of the information about how to
increment the PC (mainly what type of instruction it refers to) is contained
in the instruction object, a new advancePC virtual function was added to the
StaticInst class. Subclasses provide an implementation that moves around the
right element of the PC with a minimal amount of decision making. In ISAs like
Alpha, the instructions always simply assign NPC to PC without having to worry
about micropcs, nnpcs, etc. The added cost of a virtual function call should
be outweighed by not having to figure out as much about what to do with the
PCs and mucking around with the extra elements.

One drawback of making the StaticInsts advance the PC is that you have to
actually have one to advance the PC. This would, superficially, seem to
require decoding an instruction before fetch could advance. This is, as far as
I can tell, realistic. fetch would advance through memory addresses, not PCs,
perhaps predicting new memory addresses using existing ones. More
sophisticated decisions about control flow would be made later on, after the
instruction was decoded, and handed back to fetch. If branching needs to
happen, some amount of decoding needs to happen to see that it's a branch,
what the target is, etc. This could get a little more complicated if that gets
done by the predecoder, but I'm choosing to ignore that for now.


Variable length instructions:

To handle variable length instructions in x86 and ARM, the predecoder now
takes in the current PC by reference to the getExtMachInst function. It can
modify the PC however it needs to (by setting NPC to be the PC + instruction
length, for instance). This could be improved since the CPU doesn't know if
the PC was modified and always has to write it back.


ISA parser:

To support the new API, all PC related operand types were removed from the
parser and replaced with a PCState type. There are two warts on this
implementation. First, as with all the other operand types, the PCState still
has to have a valid operand type even though it doesn't use it. Second, using
syntax like PCS.npc(target) doesn't work for two reasons, this looks like the
syntax for operand type overriding, and the parser can't figure out if you're
reading or writing. Instructions that use the PCS operand (which I've
consistently called it) need to first read it into a local variable,
manipulate it, and then write it back out.


Return address stack:

The return address stack needed a little extra help because, in the presence
of branch delay slots, it has to merge together elements of the return PC and
the call PC. To handle that, a buildRetPC utility function was added. There
are basically only two versions in all the ISAs, but it didn't seem short
enough to put into the generic ISA directory. Also, the branch predictor code
in O3 and InOrder were adjusted so that they always store the PC of the actual
call instruction in the RAS, not the next PC. If the call instruction is a
microop, the next PC refers to the next microop in the same macroop which is
probably not desirable. The buildRetPC function advances the PC intelligently
to the next macroop (in an ISA specific way) so that that case works.


Change in stats:

There were no change in stats except in MIPS and SPARC in the O3 model. MIPS
runs in about 9% fewer ticks. SPARC runs with 30%-50% fewer ticks, which could
likely be improved further by setting call/return instruction flags and taking
advantage of the RAS.


TODO:

Add != operators to the PCState classes, defined trivially to be !(a==b).
Smooth out places where PCs are split apart, passed around, and put back
together later. I think this might happen in SPARC's fault code. Add ISA
specific constructors that allow setting PC elements without calling a bunch
of accessors. Try to eliminate the need for the branching() function. Factor
out Alpha's PAL mode pc bit into a separate flag field, and eliminate places
where it's blindly masked out or tested in the PC.


/gem5/src/arch/alpha/ev5.cc
/gem5/src/arch/alpha/faults.cc
/gem5/src/arch/alpha/interrupts.hh
/gem5/src/arch/alpha/isa/branch.isa
/gem5/src/arch/alpha/isa/decoder.isa
/gem5/src/arch/alpha/isa/main.isa
/gem5/src/arch/alpha/predecoder.hh
/gem5/src/arch/alpha/process.cc
/gem5/src/arch/alpha/remote_gdb.cc
/gem5/src/arch/alpha/stacktrace.cc
/gem5/src/arch/alpha/tlb.cc
/gem5/src/arch/alpha/types.hh
/gem5/src/arch/alpha/utility.cc
/gem5/src/arch/alpha/utility.hh
/gem5/src/arch/arm/faults.cc
/gem5/src/arch/arm/insts/macromem.hh
/gem5/src/arch/arm/insts/mem.hh
/gem5/src/arch/arm/insts/pred_inst.hh
/gem5/src/arch/arm/insts/static_inst.hh
/gem5/src/arch/arm/insts/vfp.hh
/gem5/src/arch/arm/isa.cc
/gem5/src/arch/arm/isa/formats/breakpoint.isa
/gem5/src/arch/arm/isa/insts/branch.isa
/gem5/src/arch/arm/isa/insts/data.isa
/gem5/src/arch/arm/isa/insts/ldr.isa
/gem5/src/arch/arm/isa/insts/macromem.isa
/gem5/src/arch/arm/isa/insts/misc.isa
/gem5/src/arch/arm/isa/operands.isa
/gem5/src/arch/arm/isa_traits.hh
/gem5/src/arch/arm/linux/system.cc
/gem5/src/arch/arm/nativetrace.cc
/gem5/src/arch/arm/predecoder.cc
/gem5/src/arch/arm/predecoder.hh
/gem5/src/arch/arm/process.cc
/gem5/src/arch/arm/system.hh
/gem5/src/arch/arm/table_walker.cc
/gem5/src/arch/arm/tlb.cc
/gem5/src/arch/arm/types.hh
/gem5/src/arch/arm/utility.cc
/gem5/src/arch/arm/utility.hh
/gem5/src/arch/generic/types.hh
/gem5/src/arch/isa_parser.py
/gem5/src/arch/mips/isa/base.isa
/gem5/src/arch/mips/isa/decoder.isa
/gem5/src/arch/mips/isa/formats/branch.isa
/gem5/src/arch/mips/isa/includes.isa
/gem5/src/arch/mips/isa/operands.isa
/gem5/src/arch/mips/mt.hh
/gem5/src/arch/mips/predecoder.hh
/gem5/src/arch/mips/process.cc
/gem5/src/arch/mips/types.hh
/gem5/src/arch/mips/utility.cc
/gem5/src/arch/mips/utility.hh
/gem5/src/arch/power/insts/branch.cc
/gem5/src/arch/power/insts/branch.hh
/gem5/src/arch/power/insts/static_inst.hh
/gem5/src/arch/power/isa/decoder.isa
/gem5/src/arch/power/isa/formats/branch.isa
/gem5/src/arch/power/isa/formats/unknown.isa
/gem5/src/arch/power/isa/operands.isa
/gem5/src/arch/power/predecoder.hh
/gem5/src/arch/power/process.cc
/gem5/src/arch/power/types.hh
/gem5/src/arch/power/utility.cc
/gem5/src/arch/power/utility.hh
/gem5/src/arch/sparc/faults.cc
/gem5/src/arch/sparc/isa/base.isa
/gem5/src/arch/sparc/isa/decoder.isa
/gem5/src/arch/sparc/isa/formats/branch.isa
/gem5/src/arch/sparc/isa/formats/micro.isa
/gem5/src/arch/sparc/isa/operands.isa
/gem5/src/arch/sparc/nativetrace.cc
/gem5/src/arch/sparc/predecoder.hh
/gem5/src/arch/sparc/process.cc
/gem5/src/arch/sparc/remote_gdb.cc
/gem5/src/arch/sparc/types.hh
/gem5/src/arch/sparc/utility.cc
/gem5/src/arch/sparc/utility.hh
/gem5/src/arch/x86/faults.cc
/gem5/src/arch/x86/insts/macroop.hh
/gem5/src/arch/x86/insts/microop.hh
/gem5/src/arch/x86/insts/static_inst.hh
/gem5/src/arch/x86/isa/decoder/two_byte_opcodes.isa
/gem5/src/arch/x86/isa/formats/unknown.isa
/gem5/src/arch/x86/isa/microops/regop.isa
/gem5/src/arch/x86/isa/microops/seqop.isa
/gem5/src/arch/x86/isa/operands.isa
/gem5/src/arch/x86/nativetrace.cc
/gem5/src/arch/x86/predecoder.hh
/gem5/src/arch/x86/process.cc
/gem5/src/arch/x86/system.cc
/gem5/src/arch/x86/tlb.cc
/gem5/src/arch/x86/types.hh
/gem5/src/arch/x86/utility.cc
/gem5/src/arch/x86/utility.hh
remote_gdb.cc
types.hh
/gem5/src/cpu/base_dyn_inst.hh
/gem5/src/cpu/base_dyn_inst_impl.hh
/gem5/src/cpu/checker/cpu.hh
/gem5/src/cpu/exetrace.cc
/gem5/src/cpu/exetrace.hh
/gem5/src/cpu/inorder/comm.hh
/gem5/src/cpu/inorder/cpu.cc
/gem5/src/cpu/inorder/cpu.hh
/gem5/src/cpu/inorder/first_stage.cc
/gem5/src/cpu/inorder/inorder_dyn_inst.cc
/gem5/src/cpu/inorder/inorder_dyn_inst.hh
/gem5/src/cpu/inorder/inorder_trace.cc
/gem5/src/cpu/inorder/inorder_trace.hh
/gem5/src/cpu/inorder/pipeline_stage.cc
/gem5/src/cpu/inorder/pipeline_stage.hh
/gem5/src/cpu/inorder/resources/bpred_unit.cc
/gem5/src/cpu/inorder/resources/bpred_unit.hh
/gem5/src/cpu/inorder/resources/branch_predictor.cc
/gem5/src/cpu/inorder/resources/cache_unit.cc
/gem5/src/cpu/inorder/resources/execution_unit.cc
/gem5/src/cpu/inorder/resources/fetch_seq_unit.cc
/gem5/src/cpu/inorder/resources/fetch_seq_unit.hh
/gem5/src/cpu/inorder/resources/tlb_unit.hh
/gem5/src/cpu/inorder/thread_context.cc
/gem5/src/cpu/inorder/thread_context.hh
/gem5/src/cpu/inorder/thread_state.hh
/gem5/src/cpu/inteltrace.cc
/gem5/src/cpu/inteltrace.hh
/gem5/src/cpu/legiontrace.cc
/gem5/src/cpu/legiontrace.hh
/gem5/src/cpu/nativetrace.hh
/gem5/src/cpu/o3/bpred_unit.hh
/gem5/src/cpu/o3/bpred_unit_impl.hh
/gem5/src/cpu/o3/comm.hh
/gem5/src/cpu/o3/commit.hh
/gem5/src/cpu/o3/commit_impl.hh
/gem5/src/cpu/o3/cpu.cc
/gem5/src/cpu/o3/cpu.hh
/gem5/src/cpu/o3/decode_impl.hh
/gem5/src/cpu/o3/dep_graph.hh
/gem5/src/cpu/o3/dyn_inst.hh
/gem5/src/cpu/o3/dyn_inst_impl.hh
/gem5/src/cpu/o3/fetch.hh
/gem5/src/cpu/o3/fetch_impl.hh
/gem5/src/cpu/o3/iew_impl.hh
/gem5/src/cpu/o3/inst_queue_impl.hh
/gem5/src/cpu/o3/lsq_unit.hh
/gem5/src/cpu/o3/lsq_unit_impl.hh
/gem5/src/cpu/o3/mem_dep_unit_impl.hh
/gem5/src/cpu/o3/rename_impl.hh
/gem5/src/cpu/o3/rob_impl.hh
/gem5/src/cpu/o3/thread_context.hh
/gem5/src/cpu/o3/thread_context_impl.hh
/gem5/src/cpu/pc_event.cc
/gem5/src/cpu/pred/btb.cc
/gem5/src/cpu/pred/btb.hh
/gem5/src/cpu/pred/ras.cc
/gem5/src/cpu/pred/ras.hh
/gem5/src/cpu/simple/atomic.cc
/gem5/src/cpu/simple/base.cc
/gem5/src/cpu/simple/base.hh
/gem5/src/cpu/simple/timing.cc
/gem5/src/cpu/simple_thread.cc
/gem5/src/cpu/simple_thread.hh
/gem5/src/cpu/static_inst.cc
/gem5/src/cpu/static_inst.hh
/gem5/src/cpu/thread_context.cc
/gem5/src/cpu/thread_context.hh
/gem5/src/kern/system_events.cc
/gem5/src/kern/tru64/tru64.hh
/gem5/src/sim/faults.cc
/gem5/src/sim/insttracer.hh
/gem5/src/sim/syscall_emul.cc
/gem5/src/sim/syscall_emul.hh
7678:f19b6a3a8cec 13-Sep-2010 Gabe Black <gblack@eecs.umich.edu>

Faults: Pass the StaticInst involved, if any, to a Fault's invoke method.

Also move the "Fault" reference counted pointer type into a separate file,
sim/fault.hh. It would be better to name this less similarly to sim/faults.hh
to reduce confusion, but fault.hh matches the name of the type. We could change
Fault to FaultPtr to match other pointer types, and then changing the name of
the file would make more sense.


/gem5/src/arch/alpha/faults.cc
/gem5/src/arch/alpha/faults.hh
/gem5/src/arch/alpha/isa.cc
/gem5/src/arch/alpha/process.cc
/gem5/src/arch/alpha/tlb.hh
/gem5/src/arch/alpha/tru64/process.cc
/gem5/src/arch/arm/faults.cc
/gem5/src/arch/arm/faults.hh
/gem5/src/arch/arm/isa.cc
/gem5/src/arch/arm/isa/includes.isa
/gem5/src/arch/arm/nativetrace.cc
/gem5/src/arch/arm/process.cc
/gem5/src/arch/arm/table_walker.hh
/gem5/src/arch/arm/tlb.hh
/gem5/src/arch/arm/utility.hh
/gem5/src/arch/mips/faults.cc
/gem5/src/arch/mips/faults.hh
/gem5/src/arch/mips/isa.hh
/gem5/src/arch/mips/tlb.hh
/gem5/src/arch/mips/utility.cc
/gem5/src/arch/power/tlb.hh
/gem5/src/arch/sparc/faults.cc
/gem5/src/arch/sparc/faults.hh
/gem5/src/arch/sparc/nativetrace.cc
/gem5/src/arch/sparc/remote_gdb.cc
/gem5/src/arch/sparc/tlb.cc
/gem5/src/arch/sparc/tlb.hh
/gem5/src/arch/sparc/utility.cc
/gem5/src/arch/sparc/utility.hh
/gem5/src/arch/x86/faults.cc
/gem5/src/arch/x86/faults.hh
/gem5/src/arch/x86/insts/microldstop.hh
/gem5/src/arch/x86/nativetrace.cc
/gem5/src/arch/x86/tlb.hh
types.hh
/gem5/src/cpu/base_dyn_inst.hh
/gem5/src/cpu/checker/cpu_impl.hh
/gem5/src/cpu/inorder/cpu.cc
/gem5/src/cpu/inorder/cpu.hh
/gem5/src/cpu/inorder/inorder_dyn_inst.cc
/gem5/src/cpu/inorder/resources/cache_unit.cc
/gem5/src/cpu/inorder/resources/execution_unit.cc
/gem5/src/cpu/inorder/resources/mult_div_unit.cc
/gem5/src/cpu/inorder/resources/tlb_unit.cc
/gem5/src/cpu/o3/commit_impl.hh
/gem5/src/cpu/o3/cpu.cc
/gem5/src/cpu/o3/cpu.hh
/gem5/src/cpu/o3/dyn_inst_impl.hh
/gem5/src/cpu/simple/atomic.cc
/gem5/src/cpu/simple/base.cc
/gem5/src/cpu/simple/timing.cc
/gem5/src/cpu/simple_thread.hh
/gem5/src/cpu/static_inst.hh
/gem5/src/cpu/thread_context.hh
/gem5/src/cpu/translation.hh
/gem5/src/kern/kernel_stats.hh
/gem5/src/kern/tru64/tru64.hh
/gem5/src/mem/page_table.cc
/gem5/src/mem/page_table.hh
/gem5/src/sim/fault.hh
/gem5/src/sim/faults.cc
/gem5/src/sim/faults.hh
/gem5/src/sim/process_impl.hh
/gem5/src/sim/syscall_emul.hh
/gem5/src/sim/tlb.cc
/gem5/src/sim/tlb.hh
7676:92274350b953 10-Sep-2010 Nathan Binkert <nate@binkert.org>

style: fix sorting of includes and whitespace in some files

7589:361b287b94b6 23-Aug-2010 Ali Saidi <Ali.Saidi@arm.com>

Loader: Don't insert symbols into the symbol table that begin wiht '$'.

7584:28ddf6d9e982 23-Aug-2010 Ali Saidi <Ali.Saidi@arm.com>

ARM: Add I/O devices for booting linux

7581:692cdb71febd 23-Aug-2010 Ali Saidi <Ali.Saidi@arm.com>

Loader: Use address mask provided to load*Symbols when loading the symbols from the symbol table.

7575:0002812cefe5 23-Aug-2010 Ali Saidi <Ali.Saidi@ARM.com>

BASE: Fix genrand to generate both 0s and 1s when max equals one.
previously was only generating 0s.

7574:f5742240963f 23-Aug-2010 Ali Saidi <Ali.Saidi@ARM.com>

stats: Fix off-by-one error in distributions.

bkt size isn't evenly divisible by max-min and it would round down,
it's possible to sample a distribution and have no place to put the sample.
When this case occured the simulator would assert.

7505:7772a8bf76ee 21-Jul-2010 Nathan Binkert <nate@binkert.org>

stats: unify the two stats distribution type better

7504:ad631c296c9b 21-Jul-2010 Nathan Binkert <nate@binkert.org>

stats: cleanup a few small problems in stats

7494:249f174e6f37 06-Jul-2010 Steve Reinhardt <steve.reinhardt@amd.com>

checkpointing: another small overload fix
On Nate's advice, overload 'char' as well as 'signed char'
and 'unsigned char'.

7492:acc1fbbef239 06-Jul-2010 Steve Reinhardt <steve.reinhardt@amd.com>

sim: fold StartupCallback into SimObject
There used to be a reason to have StartupCallback
be a separate object, but not any more. Now
it's just confusing.

7463:b26258d233d2 15-Jun-2010 Nathan Binkert <nate@binkert.org>

stats: rename print to display in the mysql code too...sorry

7462:0c61c3cf7639 15-Jun-2010 Nathan Binkert <nate@binkert.org>

stats: rename print to display so it work in python

7461:5a07045d0af2 15-Jun-2010 Nathan Binkert <nate@binkert.org>

stats: only consider a formula initialized if there is a formula

7460:41550bb10e08 15-Jun-2010 Nathan Binkert <nate@binkert.org>

stats: get rid of the never-really-used event stuff

7455:586f99bf0dc4 11-Jun-2010 Nathan Binkert <nate@binkert.org>

ruby: get rid of the Map class

7454:3a3e8e8cce1b 11-Jun-2010 Nathan Binkert <nate@binkert.org>

ruby: get rid of Vector and use STL
add a couple of helper functions to base for deleteing all pointers in
a container and outputting containers to a stream


stl_helpers.hh
/gem5/src/cpu/rubytest/CheckTable.cc
/gem5/src/cpu/rubytest/CheckTable.hh
/gem5/src/cpu/rubytest/RubyTester.cc
/gem5/src/cpu/rubytest/RubyTester.hh
/gem5/src/mem/gems_common/Map.hh
/gem5/src/mem/gems_common/PrioHeap.hh
/gem5/src/mem/gems_common/Vector.hh
/gem5/src/mem/ruby/buffers/MessageBuffer.hh
/gem5/src/mem/ruby/common/DataBlock.hh
/gem5/src/mem/ruby/common/Histogram.cc
/gem5/src/mem/ruby/common/Histogram.hh
/gem5/src/mem/ruby/common/NetDest.cc
/gem5/src/mem/ruby/common/NetDest.hh
/gem5/src/mem/ruby/common/SubBlock.cc
/gem5/src/mem/ruby/common/SubBlock.hh
/gem5/src/mem/ruby/eventqueue/RubyEventQueue.hh
/gem5/src/mem/ruby/filters/BlockBloomFilter.cc
/gem5/src/mem/ruby/filters/BlockBloomFilter.hh
/gem5/src/mem/ruby/filters/BulkBloomFilter.cc
/gem5/src/mem/ruby/filters/BulkBloomFilter.hh
/gem5/src/mem/ruby/filters/H3BloomFilter.cc
/gem5/src/mem/ruby/filters/H3BloomFilter.hh
/gem5/src/mem/ruby/filters/LSB_CountingBloomFilter.cc
/gem5/src/mem/ruby/filters/LSB_CountingBloomFilter.hh
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.hh
/gem5/src/mem/ruby/filters/MultiGrainBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiGrainBloomFilter.hh
/gem5/src/mem/ruby/filters/NonCountingBloomFilter.cc
/gem5/src/mem/ruby/filters/NonCountingBloomFilter.hh
/gem5/src/mem/ruby/network/Network.cc
/gem5/src/mem/ruby/network/Network.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/RoutingUnit_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/RoutingUnit_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/SWallocator_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/SWallocator_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/VCallocator_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/VCallocator_d.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/Router.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/Router.hh
/gem5/src/mem/ruby/network/simple/PerfectSwitch.cc
/gem5/src/mem/ruby/network/simple/PerfectSwitch.hh
/gem5/src/mem/ruby/network/simple/SimpleNetwork.cc
/gem5/src/mem/ruby/network/simple/SimpleNetwork.hh
/gem5/src/mem/ruby/network/simple/Switch.cc
/gem5/src/mem/ruby/network/simple/Switch.hh
/gem5/src/mem/ruby/network/simple/Throttle.cc
/gem5/src/mem/ruby/network/simple/Throttle.hh
/gem5/src/mem/ruby/network/simple/Topology.cc
/gem5/src/mem/ruby/network/simple/Topology.hh
/gem5/src/mem/ruby/profiler/AddressProfiler.cc
/gem5/src/mem/ruby/profiler/CacheProfiler.cc
/gem5/src/mem/ruby/profiler/CacheProfiler.hh
/gem5/src/mem/ruby/profiler/MemCntrlProfiler.cc
/gem5/src/mem/ruby/profiler/MemCntrlProfiler.hh
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/system/CacheMemory.cc
/gem5/src/mem/ruby/system/CacheMemory.hh
/gem5/src/mem/ruby/system/MemoryVector.hh
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/ruby/system/System.hh
/gem5/src/mem/ruby/system/TimerTable.cc
/gem5/src/mem/ruby/tester/DeterministicDriver.cc
/gem5/src/mem/ruby/tester/DeterministicDriver.hh
/gem5/src/mem/ruby/tester/RaceyDriver.cc
/gem5/src/mem/ruby/tester/RaceyDriver.hh
/gem5/src/mem/slicc/symbols/StateMachine.py
7444:669c1d2df752 03-Jun-2010 Lisa Hsu <Lisa.Hsu@amd.com>

Stats: fix dist stat and enable VectorDistStat

7095:f7bb2d93cc49 02-Jun-2010 Gabe Black <gblack@eecs.umich.edu>

ARM: Detect thumb mode elf images.

7075:091062b018b7 06-May-2010 Nathan Binkert <nate@binkert.org>

compile: don't #include unnecessary stuff
Time from base/time.hh has a name clash with Time from Ruby's
TypeDefines.hh. Eventually Ruby's Time should go away, so instead of
fixing this properly just try to avoid the clash.

7067:8832fe9b5a57 18-Apr-2010 Nathan Binkert <nate@binkert.org>

callback: Make helper functions that create callback objects for you
clean up callback stuff a little bit while we're at it.

7057:ca72ee5978ce 02-Apr-2010 Nathan Binkert <nate@binkert.org>

refcnt: no default copy contructor or copy operator
We shouldn't allow these because the default versions will copy
the reference count which is definitely not what we want.

6977:039202aafc0d 23-Feb-2010 Lisa Hsu <Lisa.Hsu@amd.com>

stats: this makes some fixes to AverageStat and AverageVector.
Also, make Formulas work on AverageVector. First, Stat::Average (and thus
Stats::AverageVector) was broken when coming out of a checkpoint and on resets,
this fixes that. Formulas also didn't work with AverageVector, but added
support for that.

6869:aa93ab97adf7 23-Jan-2010 Nathan Binkert <nate@binkert.org>

build: need to include cstdio

6712:b95abe00dd9d 04-Nov-2009 Nathan Binkert <nate@binkert.org>

build: fix compile problems pointed out by gcc 4.4

6691:cd68b6ecd68d 27-Oct-2009 Timothy M. Jones <tjones1@inf.ed.ac.uk>

POWER: Add support for the Power ISA

This adds support for the 32-bit, big endian Power ISA. This supports both
integer and floating point instructions based on the Power ISA Book I v2.06.


/gem5/build_opts/POWER_SE
/gem5/src/arch/isa_parser.py
/gem5/src/arch/power/PowerTLB.py
/gem5/src/arch/power/SConscript
/gem5/src/arch/power/SConsopts
/gem5/src/arch/power/faults.hh
/gem5/src/arch/power/insts/branch.cc
/gem5/src/arch/power/insts/branch.hh
/gem5/src/arch/power/insts/condition.cc
/gem5/src/arch/power/insts/condition.hh
/gem5/src/arch/power/insts/floating.cc
/gem5/src/arch/power/insts/floating.hh
/gem5/src/arch/power/insts/integer.cc
/gem5/src/arch/power/insts/integer.hh
/gem5/src/arch/power/insts/mem.cc
/gem5/src/arch/power/insts/mem.hh
/gem5/src/arch/power/insts/misc.cc
/gem5/src/arch/power/insts/misc.hh
/gem5/src/arch/power/insts/static_inst.cc
/gem5/src/arch/power/insts/static_inst.hh
/gem5/src/arch/power/isa.hh
/gem5/src/arch/power/isa/bitfields.isa
/gem5/src/arch/power/isa/decoder.isa
/gem5/src/arch/power/isa/formats/basic.isa
/gem5/src/arch/power/isa/formats/branch.isa
/gem5/src/arch/power/isa/formats/condition.isa
/gem5/src/arch/power/isa/formats/formats.isa
/gem5/src/arch/power/isa/formats/fp.isa
/gem5/src/arch/power/isa/formats/integer.isa
/gem5/src/arch/power/isa/formats/mem.isa
/gem5/src/arch/power/isa/formats/misc.isa
/gem5/src/arch/power/isa/formats/unimp.isa
/gem5/src/arch/power/isa/formats/unknown.isa
/gem5/src/arch/power/isa/formats/util.isa
/gem5/src/arch/power/isa/includes.isa
/gem5/src/arch/power/isa/main.isa
/gem5/src/arch/power/isa/operands.isa
/gem5/src/arch/power/isa_traits.hh
/gem5/src/arch/power/linux/linux.cc
/gem5/src/arch/power/linux/linux.hh
/gem5/src/arch/power/linux/process.cc
/gem5/src/arch/power/linux/process.hh
/gem5/src/arch/power/locked_mem.hh
/gem5/src/arch/power/microcode_rom.hh
/gem5/src/arch/power/miscregs.hh
/gem5/src/arch/power/mmaped_ipr.hh
/gem5/src/arch/power/pagetable.cc
/gem5/src/arch/power/pagetable.hh
/gem5/src/arch/power/predecoder.hh
/gem5/src/arch/power/process.cc
/gem5/src/arch/power/process.hh
/gem5/src/arch/power/registers.hh
/gem5/src/arch/power/remote_gdb.hh
/gem5/src/arch/power/stacktrace.hh
/gem5/src/arch/power/tlb.cc
/gem5/src/arch/power/tlb.hh
/gem5/src/arch/power/types.hh
/gem5/src/arch/power/utility.hh
/gem5/src/arch/power/vtophys.hh
loader/elf_object.cc
loader/object_file.hh
/gem5/src/cpu/BaseCPU.py
/gem5/src/sim/process.cc
6658:f4de76601762 23-Sep-2009 Nathan Binkert <nate@binkert.org>

arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh


/gem5/SConstruct
/gem5/src/SConscript
/gem5/src/arch/arm/stacktrace.hh
/gem5/src/arch/isa_specific.hh
cp_annotate.cc
cp_annotate.hh
remote_gdb.cc
/gem5/src/cpu/base.hh
/gem5/src/cpu/base_dyn_inst.hh
/gem5/src/cpu/base_dyn_inst_impl.hh
/gem5/src/cpu/checker/cpu_impl.hh
/gem5/src/cpu/checker/thread_context.hh
/gem5/src/cpu/exetrace.cc
/gem5/src/cpu/inorder/cpu.cc
/gem5/src/cpu/inorder/cpu.hh
/gem5/src/cpu/inorder/inorder_dyn_inst.cc
/gem5/src/cpu/inorder/inorder_dyn_inst.hh
/gem5/src/cpu/inorder/inorder_trace.cc
/gem5/src/cpu/inorder/pipeline_stage.cc
/gem5/src/cpu/inorder/reg_dep_map.cc
/gem5/src/cpu/inorder/reg_dep_map.hh
/gem5/src/cpu/inorder/resources/bpred_unit.cc
/gem5/src/cpu/inorder/resources/branch_predictor.cc
/gem5/src/cpu/inorder/resources/cache_unit.cc
/gem5/src/cpu/inorder/resources/cache_unit.hh
/gem5/src/cpu/inorder/resources/decode_unit.cc
/gem5/src/cpu/inorder/resources/fetch_seq_unit.cc
/gem5/src/cpu/inorder/resources/fetch_seq_unit.hh
/gem5/src/cpu/inorder/resources/inst_buffer.cc
/gem5/src/cpu/inorder/resources/inst_buffer_new.cc
/gem5/src/cpu/inorder/resources/tlb_unit.cc
/gem5/src/cpu/inorder/resources/tlb_unit.hh
/gem5/src/cpu/inorder/resources/use_def.cc
/gem5/src/cpu/inorder/thread_context.cc
/gem5/src/cpu/inorder/thread_context.hh
/gem5/src/cpu/inteltrace.cc
/gem5/src/cpu/legiontrace.cc
/gem5/src/cpu/o3/bpred_unit_impl.hh
/gem5/src/cpu/o3/commit_impl.hh
/gem5/src/cpu/o3/cpu.cc
/gem5/src/cpu/o3/cpu.hh
/gem5/src/cpu/o3/decode_impl.hh
/gem5/src/cpu/o3/dyn_inst.hh
/gem5/src/cpu/o3/fetch.hh
/gem5/src/cpu/o3/fetch_impl.hh
/gem5/src/cpu/o3/free_list.hh
/gem5/src/cpu/o3/iew_impl.hh
/gem5/src/cpu/o3/impl.hh
/gem5/src/cpu/o3/lsq_unit.hh
/gem5/src/cpu/o3/lsq_unit_impl.hh
/gem5/src/cpu/o3/regfile.hh
/gem5/src/cpu/o3/rename.hh
/gem5/src/cpu/o3/rename_impl.hh
/gem5/src/cpu/o3/rename_map.hh
/gem5/src/cpu/o3/rob.hh
/gem5/src/cpu/o3/scoreboard.cc
/gem5/src/cpu/o3/thread_context.hh
/gem5/src/cpu/o3/thread_context_impl.hh
/gem5/src/cpu/ozone/cpu.hh
/gem5/src/cpu/ozone/cpu_impl.hh
/gem5/src/cpu/ozone/dyn_inst.hh
/gem5/src/cpu/ozone/dyn_inst_impl.hh
/gem5/src/cpu/ozone/front_end.hh
/gem5/src/cpu/ozone/front_end_impl.hh
/gem5/src/cpu/ozone/inorder_back_end_impl.hh
/gem5/src/cpu/ozone/lsq_unit.hh
/gem5/src/cpu/ozone/lsq_unit_impl.hh
/gem5/src/cpu/ozone/lw_back_end_impl.hh
/gem5/src/cpu/ozone/lw_lsq.hh
/gem5/src/cpu/ozone/lw_lsq_impl.hh
/gem5/src/cpu/ozone/rename_table.hh
/gem5/src/cpu/ozone/rename_table_impl.hh
/gem5/src/cpu/ozone/simple_params.hh
/gem5/src/cpu/ozone/thread_state.hh
/gem5/src/cpu/profile.hh
/gem5/src/cpu/simple/atomic.cc
/gem5/src/cpu/simple/base.cc
/gem5/src/cpu/simple/base.hh
/gem5/src/cpu/simple/timing.cc
/gem5/src/cpu/simple_thread.cc
/gem5/src/cpu/simple_thread.hh
/gem5/src/cpu/static_inst.hh
/gem5/src/cpu/thread_context.cc
/gem5/src/cpu/thread_context.hh
/gem5/src/cpu/thread_state.hh
/gem5/src/dev/alpha/tsunami.cc
/gem5/src/dev/alpha/tsunami_cchip.cc
/gem5/src/dev/alpha/tsunami_io.cc
/gem5/src/dev/alpha/tsunami_pchip.cc
/gem5/src/dev/baddev.cc
/gem5/src/dev/ide_disk.cc
/gem5/src/dev/mips/malta.cc
/gem5/src/dev/mips/malta_cchip.cc
/gem5/src/dev/mips/malta_io.cc
/gem5/src/dev/mips/malta_pchip.cc
/gem5/src/dev/ns_gige.cc
/gem5/src/dev/platform.cc
/gem5/src/dev/sinic.cc
/gem5/src/dev/sparc/dtod.cc
/gem5/src/dev/sparc/t1000.cc
/gem5/src/dev/uart8250.cc
/gem5/src/dev/x86/pc.cc
/gem5/src/kern/linux/printk.hh
/gem5/src/kern/system_events.cc
/gem5/src/kern/tru64/dump_mbuf.cc
/gem5/src/kern/tru64/tru64.hh
/gem5/src/kern/tru64/tru64_events.cc
/gem5/src/mem/cache/builder.cc
/gem5/src/mem/cache/prefetch/base.cc
/gem5/src/mem/packet_access.hh
/gem5/src/mem/page_table.cc
/gem5/src/mem/page_table.hh
/gem5/src/mem/physical.cc
/gem5/src/mem/port_impl.hh
/gem5/src/mem/rubymem.cc
/gem5/src/mem/translating_port.cc
/gem5/src/mem/vport.cc
/gem5/src/sim/arguments.cc
/gem5/src/sim/process.cc
/gem5/src/sim/process.hh
/gem5/src/sim/pseudo_inst.cc
/gem5/src/sim/syscall_emul.cc
/gem5/src/sim/syscall_emul.hh
/gem5/src/sim/system.cc
/gem5/src/sim/system.hh
6392:9345de6fca33 27-Jul-2009 Ali Saidi <saidi@eecs.umich.edu>

ARM: Detect OABI binaries and complain that they're no-longer supported.

6274:117dbbf0e1e2 02-Jul-2009 Gabe Black <gblack@eecs.umich.edu>

ARM: Add a findLsbSet function and use it to implement clz.

6249:ba13184587a5 21-Jun-2009 Gabe Black <gblack@eecs.umich.edu>

BitUnion: Add more constiness.

6230:240a5a39e56f 05-Jun-2009 Nathan Binkert <nate@binkert.org>

cleanup: Make use of types properly and make the loop a little more clear.

6227:a17798f2a52c 05-Jun-2009 Nathan Binkert <nate@binkert.org>

types: clean up types, especially signed vs unsigned


/gem5/src/arch/alpha/ev5.cc
/gem5/src/arch/alpha/interrupts.hh
/gem5/src/arch/alpha/isa/decoder.isa
/gem5/src/arch/alpha/isa_traits.hh
/gem5/src/arch/alpha/process.cc
/gem5/src/arch/alpha/stacktrace.hh
atomicio.cc
chunk_generator.hh
crc.cc
fast_alloc.hh
loader/symtab.cc
match.cc
remote_gdb.cc
sat_counter.cc
sat_counter.hh
statistics.cc
statistics.hh
timebuf.hh
/gem5/src/cpu/inorder/cpu.cc
/gem5/src/cpu/inorder/cpu.hh
/gem5/src/cpu/inorder/pipeline_traits.hh
/gem5/src/cpu/memtest/memtest.cc
/gem5/src/cpu/ozone/cpu_impl.hh
/gem5/src/cpu/pred/2bit_local.cc
/gem5/src/cpu/pred/btb.cc
/gem5/src/cpu/pred/ras.cc
/gem5/src/cpu/simple/atomic.cc
/gem5/src/cpu/simple/base.cc
/gem5/src/cpu/simple/timing.cc
/gem5/src/dev/disk_image.cc
/gem5/src/dev/disk_image.hh
/gem5/src/dev/etherdump.hh
/gem5/src/dev/etherpkt.hh
/gem5/src/dev/ethertap.hh
/gem5/src/dev/i8254xGBe.cc
/gem5/src/dev/i8254xGBe.hh
/gem5/src/dev/i8254xGBe_defs.hh
/gem5/src/dev/io_device.hh
/gem5/src/dev/pktfifo.cc
/gem5/src/dev/pktfifo.hh
/gem5/src/dev/sinic.cc
/gem5/src/dev/sinic.hh
/gem5/src/kern/linux/linux.cc
/gem5/src/mem/bus.cc
/gem5/src/mem/bus.hh
/gem5/src/mem/cache/base.cc
/gem5/src/mem/cache/base.hh
/gem5/src/mem/cache/blk.hh
/gem5/src/mem/cache/mshr.hh
/gem5/src/mem/cache/prefetch/base.hh
/gem5/src/mem/cache/tags/fa_lru.cc
/gem5/src/mem/cache/tags/fa_lru.hh
/gem5/src/mem/cache/tags/iic.cc
/gem5/src/mem/cache/tags/iic.hh
/gem5/src/mem/cache/tags/lru.cc
/gem5/src/mem/cache/tags/lru.hh
/gem5/src/mem/gems_common/ioutil/confio.cc
/gem5/src/mem/packet.hh
/gem5/src/mem/page_table.cc
/gem5/src/mem/physical.cc
/gem5/src/mem/physical.hh
/gem5/src/mem/port.cc
/gem5/src/mem/port.hh
/gem5/src/mem/rubymem.cc
/gem5/src/sim/init.cc
/gem5/src/sim/process.cc
/gem5/src/sim/process_impl.hh
/gem5/src/sim/pseudo_inst.cc
/gem5/src/sim/serialize.cc
/gem5/src/sim/serialize.hh
/gem5/src/sim/syscall_emul.hh
/gem5/src/sim/system.hh
6221:58a3c04e6344 26-May-2009 Nathan Binkert <nate@binkert.org>

types: add a type for thread IDs and try to use it everywhere


/gem5/src/arch/alpha/miscregfile.cc
/gem5/src/arch/alpha/miscregfile.hh
/gem5/src/arch/mips/mt.hh
/gem5/src/arch/mips/regfile.cc
/gem5/src/arch/mips/regfile/float_regfile.cc
/gem5/src/arch/mips/regfile/float_regfile.hh
/gem5/src/arch/mips/regfile/misc_regfile.cc
/gem5/src/arch/mips/regfile/misc_regfile.hh
/gem5/src/arch/mips/regfile/regfile.cc
/gem5/src/arch/mips/regfile/regfile.hh
types.hh
/gem5/src/cpu/base.cc
/gem5/src/cpu/base.hh
/gem5/src/cpu/base_dyn_inst.hh
/gem5/src/cpu/btb.cc
/gem5/src/cpu/inorder/cpu.cc
/gem5/src/cpu/inorder/cpu.hh
/gem5/src/cpu/inorder/first_stage.cc
/gem5/src/cpu/inorder/first_stage.hh
/gem5/src/cpu/inorder/inorder_cpu_builder.cc
/gem5/src/cpu/inorder/inorder_dyn_inst.cc
/gem5/src/cpu/inorder/inorder_dyn_inst.hh
/gem5/src/cpu/inorder/pipeline_stage.cc
/gem5/src/cpu/inorder/pipeline_stage.hh
/gem5/src/cpu/inorder/resource.cc
/gem5/src/cpu/inorder/resource.hh
/gem5/src/cpu/inorder/resource_pool.9stage.cc
/gem5/src/cpu/inorder/resource_pool.cc
/gem5/src/cpu/inorder/resource_pool.hh
/gem5/src/cpu/inorder/resources/agen_unit.cc
/gem5/src/cpu/inorder/resources/bpred_unit.cc
/gem5/src/cpu/inorder/resources/bpred_unit.hh
/gem5/src/cpu/inorder/resources/branch_predictor.cc
/gem5/src/cpu/inorder/resources/branch_predictor.hh
/gem5/src/cpu/inorder/resources/cache_unit.cc
/gem5/src/cpu/inorder/resources/cache_unit.hh
/gem5/src/cpu/inorder/resources/decode_unit.cc
/gem5/src/cpu/inorder/resources/decode_unit.hh
/gem5/src/cpu/inorder/resources/execution_unit.cc
/gem5/src/cpu/inorder/resources/fetch_seq_unit.cc
/gem5/src/cpu/inorder/resources/fetch_seq_unit.hh
/gem5/src/cpu/inorder/resources/graduation_unit.cc
/gem5/src/cpu/inorder/resources/inst_buffer.cc
/gem5/src/cpu/inorder/resources/inst_buffer.hh
/gem5/src/cpu/inorder/resources/inst_buffer_new.cc
/gem5/src/cpu/inorder/resources/inst_buffer_new.hh
/gem5/src/cpu/inorder/resources/mult_div_unit.cc
/gem5/src/cpu/inorder/resources/tlb_unit.cc
/gem5/src/cpu/inorder/resources/tlb_unit.hh
/gem5/src/cpu/inorder/resources/use_def.cc
/gem5/src/cpu/inorder/resources/use_def.hh
/gem5/src/cpu/inorder/thread_context.cc
/gem5/src/cpu/inorder/thread_context.hh
/gem5/src/cpu/inorder/thread_state.hh
/gem5/src/cpu/o3/bpred_unit.hh
/gem5/src/cpu/o3/bpred_unit_impl.hh
/gem5/src/cpu/o3/btb.hh
/gem5/src/cpu/o3/commit.hh
/gem5/src/cpu/o3/commit_impl.hh
/gem5/src/cpu/o3/cpu.cc
/gem5/src/cpu/o3/cpu.hh
/gem5/src/cpu/o3/cpu_builder.cc
/gem5/src/cpu/o3/decode.hh
/gem5/src/cpu/o3/decode_impl.hh
/gem5/src/cpu/o3/fetch.hh
/gem5/src/cpu/o3/fetch_impl.hh
/gem5/src/cpu/o3/free_list.cc
/gem5/src/cpu/o3/free_list.hh
/gem5/src/cpu/o3/iew.hh
/gem5/src/cpu/o3/iew_impl.hh
/gem5/src/cpu/o3/inst_queue.hh
/gem5/src/cpu/o3/inst_queue_impl.hh
/gem5/src/cpu/o3/lsq.hh
/gem5/src/cpu/o3/lsq_impl.hh
/gem5/src/cpu/o3/lsq_unit.hh
/gem5/src/cpu/o3/lsq_unit_impl.hh
/gem5/src/cpu/o3/mem_dep_unit.hh
/gem5/src/cpu/o3/mem_dep_unit_impl.hh
/gem5/src/cpu/o3/regfile.hh
/gem5/src/cpu/o3/rename.hh
/gem5/src/cpu/o3/rename_impl.hh
/gem5/src/cpu/o3/rob.hh
/gem5/src/cpu/o3/rob_impl.hh
/gem5/src/cpu/o3/store_set.cc
/gem5/src/cpu/o3/store_set.hh
/gem5/src/cpu/o3/thread_context_impl.hh
/gem5/src/cpu/ozone/back_end_impl.hh
/gem5/src/cpu/ozone/cpu_builder.cc
/gem5/src/cpu/ozone/inst_queue.hh
/gem5/src/cpu/ozone/inst_queue_impl.hh
/gem5/src/cpu/ozone/lw_back_end_impl.hh
/gem5/src/cpu/ozone/null_predictor.hh
/gem5/src/cpu/ozone/simple_cpu_builder.cc
/gem5/src/cpu/simple/atomic.cc
/gem5/src/cpu/simple/base.cc
/gem5/src/cpu/simple/base.hh
/gem5/src/cpu/simple/timing.cc
/gem5/src/cpu/simple_thread.hh
/gem5/src/cpu/smt.hh
/gem5/src/cpu/thread_context.hh
/gem5/src/cpu/thread_state.cc
/gem5/src/cpu/thread_state.hh
/gem5/src/mem/cache/mshr.cc
/gem5/src/mem/cache/mshr.hh
/gem5/src/mem/request.hh
/gem5/src/mem/ruby/system/CacheMemory.hh
/gem5/src/sim/system.hh
6216:2f4020838149 17-May-2009 Nathan Binkert <nate@binkert.org>

includes: sort includes again


/gem5/src/arch/alpha/isa_traits.hh
/gem5/src/arch/alpha/predecoder.hh
/gem5/src/arch/arm/utility.hh
/gem5/src/arch/mips/dsp.hh
/gem5/src/arch/mips/isa_traits.hh
/gem5/src/arch/mips/utility.hh
/gem5/src/arch/sparc/isa_traits.hh
/gem5/src/arch/sparc/predecoder.hh
/gem5/src/arch/sparc/regfile.hh
/gem5/src/arch/x86/bios/acpi.hh
/gem5/src/arch/x86/bios/e820.hh
/gem5/src/arch/x86/bios/intelmp.cc
/gem5/src/arch/x86/bios/smbios.cc
/gem5/src/arch/x86/bios/smbios.hh
/gem5/src/arch/x86/intmessage.hh
/gem5/src/arch/x86/miscregfile.hh
/gem5/src/arch/x86/pagetable.hh
/gem5/src/arch/x86/pagetable_walker.hh
/gem5/src/arch/x86/predecoder.cc
/gem5/src/arch/x86/regfile.hh
/gem5/src/arch/x86/utility.hh
/gem5/src/arch/x86/x86_traits.hh
cp_annotate.hh
crc.cc
inet.cc
inet.hh
intmath.hh
misc.cc
pollevent.cc
res_list.hh
statistics.hh
stats/mysql.cc
stats/output.cc
/gem5/src/cpu/exetrace.hh
/gem5/src/cpu/inorder/comm.hh
/gem5/src/cpu/inorder/inorder_trace.hh
/gem5/src/cpu/inteltrace.hh
/gem5/src/cpu/legiontrace.hh
/gem5/src/cpu/nativetrace.hh
/gem5/src/cpu/o3/2bit_local_pred.hh
/gem5/src/cpu/o3/bpred_unit.hh
/gem5/src/cpu/o3/comm.hh
/gem5/src/cpu/o3/fetch_impl.hh
/gem5/src/cpu/o3/inst_queue.hh
/gem5/src/cpu/o3/ras.hh
/gem5/src/cpu/o3/store_set.hh
/gem5/src/cpu/o3/tournament_pred.hh
/gem5/src/cpu/ozone/ea_list.hh
/gem5/src/cpu/ozone/inst_queue.hh
/gem5/src/cpu/ozone/null_predictor.hh
/gem5/src/cpu/simple/base.cc
/gem5/src/cpu/simple_thread.hh
/gem5/src/cpu/static_inst.hh
/gem5/src/cpu/thread_context.hh
/gem5/src/dev/alpha/backdoor.hh
/gem5/src/dev/etherlink.hh
/gem5/src/dev/etherpkt.hh
/gem5/src/dev/intel_8254_timer.hh
/gem5/src/dev/mips/backdoor.hh
/gem5/src/dev/ns_gige.cc
/gem5/src/dev/sinic.cc
/gem5/src/dev/x86/intdev.hh
/gem5/src/dev/x86/south_bridge.cc
/gem5/src/kern/tru64/dump_mbuf.cc
/gem5/src/kern/tru64/mbuf.hh
/gem5/src/mem/bus.hh
/gem5/src/mem/cache/cache_impl.hh
/gem5/src/mem/cache/mshr.cc
/gem5/src/mem/cache/tags/fa_lru.cc
/gem5/src/mem/cache/tags/fa_lru.hh
/gem5/src/mem/cache/tags/iic_repl/gen.cc
/gem5/src/mem/cache/tags/iic_repl/repl.hh
/gem5/src/mem/cache/tags/lru.hh
/gem5/src/mem/gems_common/util.cc
/gem5/src/mem/packet.hh
/gem5/src/mem/page_table.hh
/gem5/src/mem/physical.cc
/gem5/src/mem/ruby/common/Debug.hh
/gem5/src/mem/ruby/common/Global.hh
/gem5/src/mem/ruby/network/orion/power_ll.cc
/gem5/src/mem/ruby/network/orion/power_utils.cc
/gem5/src/mem/rubymem.cc
/gem5/src/mem/slicc/slicc_global.hh
/gem5/src/python/swig/core.i
/gem5/src/python/swig/event.i
/gem5/src/python/swig/pyobject.hh
/gem5/src/python/swig/sim_object.i
/gem5/src/sim/arguments.hh
/gem5/src/sim/eventq.hh
/gem5/src/sim/init.cc
/gem5/src/sim/insttracer.hh
/gem5/src/sim/sim_object.cc
/gem5/src/sim/simulate.cc
/gem5/src/sim/syscall_emul.hh
/gem5/src/unittest/rangemaptest.cc
/gem5/src/unittest/rangemultimaptest.cc
/gem5/util/statetrace/arch/tracechild_amd64.hh
/gem5/util/statetrace/arch/tracechild_i386.hh
/gem5/util/statetrace/arch/tracechild_sparc.hh
6215:9aed64c9f10f 17-May-2009 Nathan Binkert <nate@binkert.org>

includes: use base/types.hh not inttypes.h or stdint.h

6214:1ec0ec8933ae 17-May-2009 Nathan Binkert <nate@binkert.org>

types: Move stuff for global types into src/base/types.hh


/gem5/src/arch/alpha/isa_traits.hh
/gem5/src/arch/alpha/miscregfile.hh
/gem5/src/arch/alpha/predecoder.hh
/gem5/src/arch/alpha/types.hh
/gem5/src/arch/arm/isa_traits.hh
/gem5/src/arch/arm/predecoder.hh
/gem5/src/arch/arm/types.hh
/gem5/src/arch/arm/utility.hh
/gem5/src/arch/mips/dsp.hh
/gem5/src/arch/mips/isa_traits.hh
/gem5/src/arch/mips/predecoder.hh
/gem5/src/arch/mips/types.hh
/gem5/src/arch/mips/utility.hh
/gem5/src/arch/sparc/isa_traits.hh
/gem5/src/arch/sparc/predecoder.hh
/gem5/src/arch/sparc/regfile.hh
/gem5/src/arch/x86/bios/acpi.hh
/gem5/src/arch/x86/bios/e820.hh
/gem5/src/arch/x86/bios/intelmp.cc
/gem5/src/arch/x86/bios/smbios.cc
/gem5/src/arch/x86/bios/smbios.hh
/gem5/src/arch/x86/intmessage.hh
/gem5/src/arch/x86/isa_traits.hh
/gem5/src/arch/x86/miscregfile.hh
/gem5/src/arch/x86/pagetable.hh
/gem5/src/arch/x86/pagetable_walker.hh
/gem5/src/arch/x86/predecoder.cc
/gem5/src/arch/x86/predecoder.hh
/gem5/src/arch/x86/regfile.hh
/gem5/src/arch/x86/utility.hh
/gem5/src/arch/x86/vtophys.hh
/gem5/src/arch/x86/x86_traits.hh
cp_annotate.hh
crc.cc
crc.hh
fast_alloc.hh
hashmap.hh
hostinfo.cc
hostinfo.hh
inet.cc
inet.hh
intmath.hh
loader/hex_file.hh
loader/object_file.hh
loader/symtab.cc
loader/symtab.hh
misc.cc
pollevent.cc
random.hh
socket.cc
statistics.hh
stats/events.cc
stats/mysql.cc
stats/mysql_run.hh
stats/output.cc
stats/types.hh
stats/visit.hh
trace.hh
types.hh
/gem5/src/cpu/exetrace.hh
/gem5/src/cpu/inorder/comm.hh
/gem5/src/cpu/inorder/inorder_trace.hh
/gem5/src/cpu/inteltrace.hh
/gem5/src/cpu/legiontrace.hh
/gem5/src/cpu/nativetrace.hh
/gem5/src/cpu/o3/2bit_local_pred.hh
/gem5/src/cpu/o3/bpred_unit.hh
/gem5/src/cpu/o3/btb.hh
/gem5/src/cpu/o3/comm.hh
/gem5/src/cpu/o3/fetch_impl.hh
/gem5/src/cpu/o3/inst_queue.hh
/gem5/src/cpu/o3/ras.hh
/gem5/src/cpu/o3/sat_counter.hh
/gem5/src/cpu/o3/store_set.hh
/gem5/src/cpu/o3/tournament_pred.hh
/gem5/src/cpu/ozone/ea_list.hh
/gem5/src/cpu/ozone/inst_queue.hh
/gem5/src/cpu/ozone/null_predictor.hh
/gem5/src/cpu/pc_event.hh
/gem5/src/cpu/profile.hh
/gem5/src/cpu/simple/base.cc
/gem5/src/cpu/simple_thread.hh
/gem5/src/cpu/static_inst.hh
/gem5/src/cpu/thread_context.hh
/gem5/src/dev/alpha/backdoor.hh
/gem5/src/dev/etherlink.hh
/gem5/src/dev/etherpkt.hh
/gem5/src/dev/intel_8254_timer.hh
/gem5/src/dev/mips/backdoor.hh
/gem5/src/dev/ns_gige.cc
/gem5/src/dev/sinic.cc
/gem5/src/kern/tru64/dump_mbuf.cc
/gem5/src/kern/tru64/mbuf.hh
/gem5/src/kern/tru64/printf.cc
/gem5/src/mem/cache/cache_impl.hh
/gem5/src/mem/cache/mshr.cc
/gem5/src/mem/cache/tags/iic_repl/gen.cc
/gem5/src/mem/cache/tags/iic_repl/repl.hh
/gem5/src/mem/packet.hh
/gem5/src/mem/page_table.hh
/gem5/src/mem/physical.cc
/gem5/src/mem/request.hh
/gem5/src/mem/rubymem.cc
/gem5/src/python/m5/params.py
/gem5/src/python/swig/core.i
/gem5/src/python/swig/debug.i
/gem5/src/python/swig/event.i
/gem5/src/python/swig/pyobject.hh
/gem5/src/python/swig/random.i
/gem5/src/python/swig/range.i
/gem5/src/python/swig/sim_object.i
/gem5/src/python/swig/trace.i
/gem5/src/sim/arguments.hh
/gem5/src/sim/byteswap.hh
/gem5/src/sim/core.hh
/gem5/src/sim/debug.hh
/gem5/src/sim/eventq.hh
/gem5/src/sim/host.hh
/gem5/src/sim/init.cc
/gem5/src/sim/insttracer.hh
/gem5/src/sim/process.hh
/gem5/src/sim/pseudo_inst.hh
/gem5/src/sim/serialize.hh
/gem5/src/sim/sim_exit.hh
/gem5/src/sim/sim_object.cc
/gem5/src/sim/simulate.cc
/gem5/src/sim/simulate.hh
/gem5/src/sim/syscall_emul.hh
/gem5/src/unittest/rangemaptest.cc
/gem5/src/unittest/rangemultimaptest.cc
/gem5/src/unittest/stattest.cc
6213:2f07b47d95a1 13-May-2009 Nathan Binkert <nate@binkert.org>

stats: tidy up the Distribution type a little bit

6212:64c3b989238c 13-May-2009 Nathan Binkert <nate@binkert.org>

stats: fancy is a bad name

6211:40e5a315bded 13-May-2009 Nathan Binkert <nate@binkert.org>

stats: clean up the code for printing stats

6172:278d0e37eba2 11-May-2009 Nathan Binkert <nate@binkert.org>

stats: remove a few compat leftovers

6170:b514de04c311 11-May-2009 Nathan Binkert <nate@binkert.org>

stats: forgot an include for the mysql stuff

6169:8ba6a73c8a45 11-May-2009 Nathan Binkert <nate@binkert.org>

scons: add include guards to info.hh

6130:0fb959250892 22-Apr-2009 Nathan Binkert <nate@binkert.org>

stats: Move flags into info.hh and use base/flags.hh to manage the flags

6129:05405c5b8c16 22-Apr-2009 Nathan Binkert <nate@binkert.org>

stats: Shuffle around info stuff so it can be accessed separately

6128:fdfbd4c6e449 22-Apr-2009 Nathan Binkert <nate@binkert.org>

stats: Rename the info classes to hopefully make things a bit clearer
FooInfoBase became FooInfo
FooInfo became FooInfoProxy

6126:5f32f9e3c65a 22-Apr-2009 Nathan Binkert <nate@binkert.org>

stats: remove simplescalar compatibility for printing

6125:3bbbdd324a60 22-Apr-2009 Nathan Binkert <nate@binkert.org>

stats: fix initialization bug in distribution text output

6114:83e66a2e06ee 08-Jan-2009 Steve Reinhardt <steve.reinhardt@amd.com>

FastAlloc: track allocation tick in debug mode,
minor enhancements to debug output

6026:45c8a91d1174 09-Apr-2009 Nathan Binkert <nate@binkert.org>

stats: disallow duplicate statistic names.

6020:0647c8b31a99 06-Apr-2009 Gabe Black <gblack@eecs.umich.edu>

Merge ARM into the head. ARM will compile but may not actually work.


/gem5/ext/dnet/dnet/addr.h
/gem5/ext/dnet/dnet/arp.h
/gem5/ext/dnet/dnet/blob.h
/gem5/ext/dnet/dnet/eth.h
/gem5/ext/dnet/dnet/fw.h
/gem5/ext/dnet/dnet/icmp.h
/gem5/ext/dnet/dnet/intf.h
/gem5/ext/dnet/dnet/ip.h
/gem5/ext/dnet/dnet/ip6.h
/gem5/ext/dnet/dnet/os.h
/gem5/ext/dnet/dnet/rand.h
/gem5/ext/dnet/dnet/route.h
/gem5/ext/dnet/dnet/tcp.h
/gem5/ext/dnet/dnet/udp.h
/gem5/src/arch/alpha/syscallreturn.hh
/gem5/src/arch/arm/ArmTLB.py
/gem5/src/arch/arm/isa_traits.hh
/gem5/src/arch/arm/linux/process.cc
/gem5/src/arch/arm/process.cc
/gem5/src/arch/arm/process.hh
/gem5/src/arch/arm/regfile/regfile.cc
/gem5/src/arch/arm/regfile/regfile.hh
/gem5/src/arch/arm/syscallreturn.hh
/gem5/src/arch/arm/tlb.cc
/gem5/src/arch/arm/tlb.hh
/gem5/src/arch/mips/syscallreturn.hh
/gem5/src/arch/sparc/syscallreturn.hh
/gem5/src/arch/x86/isa/insts/general_purpose/processor_information.py
/gem5/src/arch/x86/smbios.cc
/gem5/src/arch/x86/smbios.hh
/gem5/src/arch/x86/syscallreturn.hh
annotate.cc
annotate.hh
stats/statdb.cc
stats/statdb.hh
/gem5/src/cpu/o3/alpha/cpu.cc
/gem5/src/cpu/o3/alpha/cpu.hh
/gem5/src/cpu/o3/alpha/cpu_builder.cc
/gem5/src/cpu/o3/alpha/cpu_impl.hh
/gem5/src/cpu/o3/alpha/dyn_inst.cc
/gem5/src/cpu/o3/alpha/dyn_inst.hh
/gem5/src/cpu/o3/alpha/dyn_inst_impl.hh
/gem5/src/cpu/o3/alpha/impl.hh
/gem5/src/cpu/o3/alpha/params.hh
/gem5/src/cpu/o3/alpha/thread_context.cc
/gem5/src/cpu/o3/alpha/thread_context.hh
/gem5/src/cpu/o3/mips/cpu.cc
/gem5/src/cpu/o3/mips/cpu.hh
/gem5/src/cpu/o3/mips/cpu_builder.cc
/gem5/src/cpu/o3/mips/cpu_impl.hh
/gem5/src/cpu/o3/mips/dyn_inst.cc
/gem5/src/cpu/o3/mips/dyn_inst.hh
/gem5/src/cpu/o3/mips/dyn_inst_impl.hh
/gem5/src/cpu/o3/mips/impl.hh
/gem5/src/cpu/o3/mips/params.hh
/gem5/src/cpu/o3/mips/thread_context.cc
/gem5/src/cpu/o3/mips/thread_context.hh
/gem5/src/cpu/o3/params.hh
/gem5/src/cpu/o3/sparc/cpu.cc
/gem5/src/cpu/o3/sparc/cpu.hh
/gem5/src/cpu/o3/sparc/cpu_builder.cc
/gem5/src/cpu/o3/sparc/cpu_impl.hh
/gem5/src/cpu/o3/sparc/dyn_inst.cc
/gem5/src/cpu/o3/sparc/dyn_inst.hh
/gem5/src/cpu/o3/sparc/dyn_inst_impl.hh
/gem5/src/cpu/o3/sparc/impl.hh
/gem5/src/cpu/o3/sparc/params.hh
/gem5/src/cpu/o3/sparc/thread_context.cc
/gem5/src/cpu/o3/sparc/thread_context.hh
/gem5/src/dev/SimConsole.py
/gem5/src/dev/alpha/AlphaConsole.py
/gem5/src/dev/alpha/console.cc
/gem5/src/dev/alpha/console.hh
/gem5/src/dev/mips/MipsConsole.py
/gem5/src/dev/mips/console.cc
/gem5/src/dev/mips/console.hh
/gem5/src/dev/pitreg.h
/gem5/src/dev/simconsole.cc
/gem5/src/dev/simconsole.hh
/gem5/src/dev/x86/Opteron.py
/gem5/src/dev/x86/opteron.cc
/gem5/src/dev/x86/opteron.hh
/gem5/src/mem/cache/tags/split.cc
/gem5/src/mem/cache/tags/split.hh
/gem5/src/mem/cache/tags/split_blk.hh
/gem5/src/mem/cache/tags/split_lifo.cc
/gem5/src/mem/cache/tags/split_lifo.hh
/gem5/src/mem/cache/tags/split_lru.cc
/gem5/src/mem/cache/tags/split_lru.hh
/gem5/src/mem/config/prefetch.hh
/gem5/src/python/generate.py
/gem5/src/python/m5/attrdict.py
/gem5/src/python/m5/multidict.py
/gem5/src/python/m5/util.py
/gem5/src/python/swig/init.hh
/gem5/src/unittest/Makefile
/gem5/src/unittest/initest.ini
/gem5/src/unittest/lru_test.cc
/gem5/src/unittest/offtest.cc
/gem5/src/unittest/paramtest.cc
/gem5/src/unittest/rangemaptest2.cc
/gem5/src/unittest/sized_test.cc
/gem5/src/unittest/tracetest.cc
/gem5/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt
/gem5/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr
/gem5/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout
/gem5/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt
/gem5/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stderr
/gem5/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stdout
/gem5/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt
/gem5/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr
/gem5/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stdout
/gem5/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt
/gem5/tests/long/00.gzip/ref/sparc/linux/o3-timing/stderr
/gem5/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout
/gem5/tests/long/00.gzip/ref/sparc/linux/simple-atomic/m5stats.txt
/gem5/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stderr
/gem5/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout
/gem5/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt
/gem5/tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr
/gem5/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout
/gem5/tests/long/00.gzip/ref/x86/linux/simple-atomic/m5stats.txt
/gem5/tests/long/00.gzip/ref/x86/linux/simple-atomic/stderr
/gem5/tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout
/gem5/tests/long/10.mcf/ref/sparc/linux/simple-atomic/m5stats.txt
/gem5/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stderr
/gem5/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout
/gem5/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt
/gem5/tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr
/gem5/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout
/gem5/tests/long/10.mcf/ref/x86/linux/simple-atomic/m5stats.txt
/gem5/tests/long/10.mcf/ref/x86/linux/simple-atomic/stderr
/gem5/tests/long/10.mcf/ref/x86/linux/simple-atomic/stdout
/gem5/tests/long/20.parser/ref/x86/linux/simple-atomic/m5stats.txt
/gem5/tests/long/20.parser/ref/x86/linux/simple-atomic/stderr
/gem5/tests/long/20.parser/ref/x86/linux/simple-atomic/stdout
/gem5/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt
/gem5/tests/long/30.eon/ref/alpha/tru64/o3-timing/stderr
/gem5/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout
/gem5/tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt
/gem5/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stderr
/gem5/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout
/gem5/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt
/gem5/tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr
/gem5/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout
/gem5/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt
/gem5/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stderr
/gem5/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stdout
/gem5/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt
/gem5/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr
/gem5/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stdout
/gem5/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt
/gem5/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr
/gem5/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stdout
/gem5/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt
/gem5/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr
/gem5/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stdout
/gem5/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt
/gem5/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr
/gem5/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout
/gem5/tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt
/gem5/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stderr
/gem5/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout
/gem5/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt
/gem5/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr
/gem5/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout
/gem5/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt
/gem5/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stderr
/gem5/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stdout
/gem5/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt
/gem5/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stderr
/gem5/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stdout
/gem5/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt
/gem5/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr
/gem5/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stdout
/gem5/tests/long/60.bzip2/ref/x86/linux/simple-atomic/m5stats.txt
/gem5/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stderr
/gem5/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stdout
/gem5/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt
/gem5/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr
/gem5/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout
/gem5/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt
/gem5/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stderr
/gem5/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stdout
/gem5/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt
/gem5/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr
/gem5/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout
/gem5/tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt
/gem5/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stderr
/gem5/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout
/gem5/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt
/gem5/tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr
/gem5/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout
/gem5/tests/long/70.twolf/ref/x86/linux/simple-atomic/m5stats.txt
/gem5/tests/long/70.twolf/ref/x86/linux/simple-atomic/stderr
/gem5/tests/long/70.twolf/ref/x86/linux/simple-atomic/stdout
/gem5/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/console.system.t1000.hconsole
/gem5/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/console.system.t1000.pconsole
/gem5/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/m5stats.txt
/gem5/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stderr
/gem5/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stdout
/gem5/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt
/gem5/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr
/gem5/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout
/gem5/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt
/gem5/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stderr
/gem5/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout
/gem5/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt
/gem5/tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr
/gem5/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout
/gem5/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt
/gem5/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr
/gem5/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout
/gem5/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt
/gem5/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stderr
/gem5/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout
/gem5/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt
/gem5/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr
/gem5/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout
/gem5/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt
/gem5/tests/quick/00.hello/ref/mips/linux/simple-atomic/stderr
/gem5/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout
/gem5/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt
/gem5/tests/quick/00.hello/ref/mips/linux/simple-timing/stderr
/gem5/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout
/gem5/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt
/gem5/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stderr
/gem5/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout
/gem5/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt
/gem5/tests/quick/00.hello/ref/sparc/linux/simple-timing/stderr
/gem5/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout
/gem5/tests/quick/00.hello/ref/x86/linux/simple-atomic/m5stats.txt
/gem5/tests/quick/00.hello/ref/x86/linux/simple-atomic/stderr
/gem5/tests/quick/00.hello/ref/x86/linux/simple-atomic/stdout
/gem5/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt
/gem5/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr
/gem5/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout
/gem5/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt
/gem5/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stderr
/gem5/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout
/gem5/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt
/gem5/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stderr
/gem5/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout
/gem5/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt
/gem5/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stderr
/gem5/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout
/gem5/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/console.system.sim_console
/gem5/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt
/gem5/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr
/gem5/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout
/gem5/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/console.system.sim_console
/gem5/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt
/gem5/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr
/gem5/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout
/gem5/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/console.system.sim_console
/gem5/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt
/gem5/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr
/gem5/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout
/gem5/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/console.system.sim_console
/gem5/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt
/gem5/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr
/gem5/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout
/gem5/tests/quick/20.eio-short/ref/alpha/eio/detailed/m5stats.txt
/gem5/tests/quick/20.eio-short/ref/alpha/eio/detailed/stderr
/gem5/tests/quick/20.eio-short/ref/alpha/eio/detailed/stdout
/gem5/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt
/gem5/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stderr
/gem5/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout
/gem5/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt
/gem5/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stderr
/gem5/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout
/gem5/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt
/gem5/tests/quick/50.memtest/ref/alpha/linux/memtest/stderr
/gem5/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout
/gem5/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.drivesys.sim_console
/gem5/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.testsys.sim_console
/gem5/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt
/gem5/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr
/gem5/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout
/gem5/util/batch/jobfile.py
/gem5/util/pbs/jobfile.py
/gem5/util/stats/orderdict.py
6015:4df1c7698e52 16-Mar-2009 Nathan Binkert <nate@binkert.org>

stats: fix compiler error

6004:97660425ff39 07-Mar-2009 Nathan Binkert <nate@binkert.org>

stats: cleanup text output stuff and fix mysql output

6002:7d75f1a525db 07-Mar-2009 Nathan Binkert <nate@binkert.org>

build: fix errors for compilers other than g++ 4.3

6001:00251eb95de7 05-Mar-2009 Nathan Binkert <nate@binkert.org>

stats: create an enable phase, and a prepare phase.
Enable more or less takes the place of check, but also allows stats to
do some other configuration. Prepare moves all of the code that readies
a stat for dumping into a separate function in preparation for supporting
serialization of certain pieces of statistics data.
While we're at it, clean up the visitor code and some of the python code.

6000:4f887be9e1b6 05-Mar-2009 Nathan Binkert <nate@binkert.org>

stats: clean up how templates are used on the data side.
This basically works by taking advantage of the curiously recurring template
pattern in an intelligent way so as to reduce the number of lines of code
and hopefully make things a little bit clearer.

5999:3cf8e71257e0 05-Mar-2009 Nathan Binkert <nate@binkert.org>

stats: Fix all stats usages to deal with template fixes


/gem5/src/arch/alpha/kernel_stats.hh
/gem5/src/arch/alpha/tlb.hh
/gem5/src/arch/mips/tlb.hh
hybrid_pred.hh
sat_counter.hh
/gem5/src/cpu/base.hh
/gem5/src/cpu/inorder/cpu.hh
/gem5/src/cpu/inorder/pipeline_stage.hh
/gem5/src/cpu/inorder/resource.hh
/gem5/src/cpu/inorder/resources/bpred_unit.hh
/gem5/src/cpu/inorder/resources/branch_predictor.hh
/gem5/src/cpu/inorder/resources/execution_unit.hh
/gem5/src/cpu/inorder/resources/inst_buffer.hh
/gem5/src/cpu/inorder/resources/mult_div_unit.hh
/gem5/src/cpu/memtest/memtest.hh
/gem5/src/cpu/o3/bpred_unit.hh
/gem5/src/cpu/o3/commit.hh
/gem5/src/cpu/o3/cpu.hh
/gem5/src/cpu/o3/decode.hh
/gem5/src/cpu/o3/fetch.hh
/gem5/src/cpu/o3/iew.hh
/gem5/src/cpu/o3/inst_queue.hh
/gem5/src/cpu/o3/lsq_unit.hh
/gem5/src/cpu/o3/mem_dep_unit.hh
/gem5/src/cpu/o3/rename.hh
/gem5/src/cpu/ozone/back_end.hh
/gem5/src/cpu/ozone/cpu.hh
/gem5/src/cpu/ozone/front_end.hh
/gem5/src/cpu/ozone/inorder_back_end.hh
/gem5/src/cpu/ozone/inst_queue.hh
/gem5/src/cpu/ozone/lsq_unit.hh
/gem5/src/cpu/ozone/lw_back_end.hh
/gem5/src/cpu/ozone/lw_lsq.hh
/gem5/src/cpu/simple/base.hh
/gem5/src/cpu/thread_state.hh
/gem5/src/dev/copy_engine.hh
/gem5/src/dev/etherdevice.hh
/gem5/src/dev/ide_disk.hh
/gem5/src/dev/sinic.hh
/gem5/src/kern/kernel_stats.hh
/gem5/src/mem/cache/base.hh
/gem5/src/mem/cache/prefetch/base.hh
/gem5/src/mem/cache/tags/base.hh
/gem5/src/mem/cache/tags/fa_lru.hh
/gem5/src/mem/cache/tags/iic.hh
/gem5/src/mem/cache/tags/iic_repl/gen.hh
/gem5/src/mem/dram.hh
/gem5/src/sim/faults.hh
/gem5/src/sim/process.hh
/gem5/src/unittest/stattest.cc
5998:a4c935e9cf99 05-Mar-2009 Nathan Binkert <nate@binkert.org>

stats: remove the template wart left over from the ancient binning stuff

5997:471090ec173e 05-Mar-2009 Nathan Binkert <nate@binkert.org>

stats: stick the distribution's fancy parameter into the parameters structure.

5996:7674070ccc92 05-Mar-2009 Nathan Binkert <nate@binkert.org>

stats: Add a wrapper class for the information side of things.
This provides an easy way to provide the callbacks into the data side
of things from the info side of things. Rename Wrap to DataWrap so it
is more easily distinguishable from InfoWrap

5995:2c9823c60c8c 05-Mar-2009 Nathan Binkert <nate@binkert.org>

stats: better naming of template parameters for the wrapper stuff
Parent and Child are bad names. Derived and Base are better.

5994:19131d568007 05-Mar-2009 Nathan Binkert <nate@binkert.org>

stats: get rid of meaningless uses of virtual

5993:71e56052768f 05-Mar-2009 Nathan Binkert <nate@binkert.org>

stats: miscellaneous cleanup

5984:4842a7d78634 04-Mar-2009 Korey Sewell <ksewell@umich.edu>

Give TimeBuffer an ID that can be set. Necessary because InOrder uses generic stages so w/o an ID there is no way to differentiate buffers when debugging

5952:c1ee8282291d 26-Feb-2009 Ali Saidi <saidi@eecs.umich.edu>

CPA: Add new object for gathering critical path annotations.

5889:02e5bc7ca9ba 23-Feb-2009 Nathan Binkert <nate@binkert.org>

stats: reorganize how parameters are stored and accessed.

5888:9775f70fbe66 23-Feb-2009 Nathan Binkert <nate@binkert.org>

stats: move the limits stuff into the types.hh file

5887:6b312cafaa59 23-Feb-2009 Nathan Binkert <nate@binkert.org>

stats: get rid of the convoluted 'database' code.
Just use the stuff directly and things ought to be more clear

5886:12431dc9a30a 23-Feb-2009 Nathan Binkert <nate@binkert.org>

stats: Try to make the names of things more intuitive.
Basically, this means renaming several things called data to info, which
is information about the statistics. Things that are named data now are
actual data stored for the statistic.

5884:cba4b5495d7b 23-Feb-2009 Nathan Binkert <nate@binkert.org>

stats: fix text printout for distributions

5882:5a047c3f3795 23-Feb-2009 Nathan Binkert <nate@binkert.org>

debug: Move debug_break into src/base

5874:7a74edaa8741 16-Feb-2009 Gabe Black <gblack@eecs.umich.edu>

X86: Make the loader recognize 32 bit x86 processes.

5822:05ffa2c3c800 30-Jan-2009 Ali Saidi <saidi@eecs.umich.edu>

Errors: Print a URL with a hash of the format string to find more information about an error.

5806:130e19359857 23-Jan-2009 Ali Saidi <saidi@eecs.umich.edu>

Trace: Add DPRINTFS macro that takes parameter to call name() for trace printing.

5800:19c06c037040 19-Jan-2009 Nathan Binkert <nate@binkert.org>

tracing: Add help strings for some of the trace flags

5782:ff12aefd2cc2 06-Jan-2009 Ali Saidi <saidi@eecs.umich.edu>

INET: Add functions to header types to get offset in packet and start of payload; add function to split packet at last known header

5764:f07df23e1fc8 06-Dec-2008 Nathan Binkert <nate@binkert.org>

flags: Change naming of functions to be clearer

5761:94d56a48d7e3 05-Dec-2008 Ali Saidi <saidi@eecs.umich.edu>

INet: Allow updating on id, len, seq, and flag field for TCP segment offload

5759:6e65ac8a2c80 05-Dec-2008 Lisa Hsu <hsul@eecs.umich.edu>

This brings M5 closer to modernity - the kernel being advertised is newer so it won't die on binaries compiled with newer glibc's, and enables use of TLS-toolchain built binaries for ALPHA_SE by putting auxiliary vectors on the stack. There are some comments in the code to help. Finally, stats changes for ALPHA are from slight perturbations to the initial stack frame, all minimal diffs.


/gem5/src/arch/alpha/linux/process.cc
/gem5/src/arch/alpha/process.cc
/gem5/src/arch/alpha/process.hh
loader/elf_object.cc
/gem5/src/sim/process.cc
/gem5/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt
/gem5/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout
/gem5/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt
/gem5/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stdout
/gem5/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt
/gem5/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stdout
/gem5/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/m5stats.txt
/gem5/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stdout
/gem5/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/m5stats.txt
/gem5/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stdout
/gem5/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt
/gem5/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout
/gem5/tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt
/gem5/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout
/gem5/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt
/gem5/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout
/gem5/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/m5stats.txt
/gem5/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stdout
/gem5/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt
/gem5/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stdout
/gem5/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt
/gem5/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stdout
/gem5/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt
/gem5/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stdout
/gem5/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt
/gem5/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stdout
/gem5/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt
/gem5/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout
/gem5/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt
/gem5/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stdout
/gem5/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt
/gem5/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stdout
/gem5/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt
/gem5/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stdout
/gem5/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt
/gem5/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout
/gem5/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt
/gem5/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stdout
/gem5/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt
/gem5/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout
/gem5/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt
/gem5/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout
/gem5/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt
/gem5/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout
/gem5/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt
/gem5/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout
/gem5/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt
/gem5/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout
/gem5/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt
/gem5/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout
/gem5/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt
/gem5/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout
/gem5/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt
/gem5/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout
/gem5/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt
/gem5/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout
/gem5/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt
/gem5/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout
/gem5/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt
/gem5/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout
/gem5/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt
/gem5/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout
/gem5/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt
/gem5/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout
/gem5/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt
/gem5/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout
/gem5/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/m5stats.txt
/gem5/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stderr
/gem5/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stdout
/gem5/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/m5stats.txt
/gem5/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stderr
/gem5/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stdout
/gem5/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt
/gem5/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout
/gem5/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
/gem5/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt
/gem5/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout
5756:88038cdbb9e1 03-Dec-2008 Nathan Binkert <nate@binkert.org>

cprintf: support a configurable width and precision ("*" in printf)

5749:7015e400bd1d 15-Nov-2008 Clint Smullen <cws3k@cs.virginia.edu>

Output: Include gzstream package to allow automatically-gzipped output
The gzstream package provides an ostream-interface for writing gzipped files.
The package comes from:
http://www.cs.unc.edu/Research/compgeom/gzstream/
And is distributed under the LGPL license. Both the license and version
information has been preservered, though all other files in the package have
been purged. Minor modifications to the code have been made. The output module
detects when a filename ends in .gz and constructs an ogzstream object instead
of an ofstream object. This works for both the create(...) and find(...)
commands. Additionally, since gzstream objects needs to be closed to ensure
proper file termination, I have the output deconstructor deleting all ostream's
that it manages on behalf of find(...). At the moment, the only output file
that I know this functionality works for is stats, i.e. by specifying
"--stats-file=m5stats.txt.gz" on the command line.

5745:6b0f8306704b 14-Nov-2008 Nathan Binkert <nate@binkert.org>

Fix a bunch of bugs I introduced when I changed the flags stuff for packets.
I did some of the flags and assertions wrong. Thanks to Brad Beckmann
for pointing this out. I should have run the opt regressions instead
of the fast. I also screwed up some of the logical functions in the Flags
class.

5734:f3733e2b19d5 10-Nov-2008 Nathan Binkert <nate@binkert.org>

flags: Provide an object for managing boolean flags for an object.
In many cases it might be preferable to use bitset, but this object
allows the user more easily manipulate groups of flags because the
underlying type (e.g. uint64_t) is exposed.

5733:83cc5483a8da 10-Nov-2008 Nathan Binkert <nate@binkert.org>

safe_cast: add a new cast function for casts that should always succeed.
In DEBUG mode, this does a dynamic_cast and asserts that the result is
non null. Otherwise, it just does a static_cast. Again, this is only
intended for cases where the cast should always succeed and what's
desired is a debugging check to make sure.

5731:453f320129a1 10-Nov-2008 Steve Reinhardt <Steve.Reinhardt@amd.com>

mem: Assert that requests have non-negative size.
Would have saved me much debugging time if these
had been in there previously.

5624:6af9ce00486e 11-Oct-2008 Nathan Binkert <nate@binkert.org>

cprintf: properly deal with pointer types

5622:e93e5b190bcc 10-Oct-2008 Nathan Binkert <nate@binkert.org>

Rename the info function to inform to avoid likely name conflicts

5620:c13b446714ca 10-Oct-2008 Nathan Binkert <nate@binkert.org>

output: Make panic/fatal/warn more flexible so we can add some new ones.
The major thrust of this change is to limit the amount of code
duplication surrounding the code for these functions. This code also
adds two new message types called info and hack. Info is meant to be
less harsh than warn so people don't get confused and start thinking
that the simulator is broken. Hack is a way for people to add runtime
messages indicating that the simulator just executed a code "hack"
that should probably be fixed. The benefit of knowing about these
code hacks is that it will let people know what sorts of inaccuracies
or potential bugs might be entering their experiments. Finally, I've
added some flags to turn on and off these message types so command
line options can change them.

5616:05fd71ca96db 10-Oct-2008 Nathan Binkert <nate@binkert.org>

misc: remove #include <cassert> from misc.hh since not everyone needs it.

5609:6782d007ca45 10-Oct-2008 Nathan Binkert <nate@binkert.org>

range_map: Add a method to find which range a single value falls into.

5608:cc5eed86382f 09-Oct-2008 Nathan Binkert <nate@binkert.org>

style: conform to M5 style.

5599:5bad83cddb8c 09-Oct-2008 Nathan Binkert <nate@binkert.org>

stats: use properly signed types for looping and comparison

5598:345ef3bda3d2 09-Oct-2008 Nathan Binkert <nate@binkert.org>

style: Bring statistics code in line with the proper style.

5582:c2fd66e6a919 02-Oct-2008 Nathan Binkert <nate@binkert.org>

stats: Fix small bug pointed out by unit testing.

5581:5e1863e9afa2 02-Oct-2008 Ali Saidi <saidi@eecs.umich.edu>

Output: Verify output files are open after opening them.

5570:13592d41f290 28-Sep-2008 Nathan Binkert <nate@binkert.org>

gcc: Add extra parens to quell warnings.
Even though we're not incorrect about operator precedence, let's add
some parens in some particularly confusing places to placate GCC 4.3
so that we don't have to turn the warning off. Agreed that this is a
bit of a pain for those users who get the order of operations correct,
but it is likely to prevent bugs in certain cases.

5564:78b95c17a14c 27-Sep-2008 Nathan Binkert <nate@binkert.org>

add a bit of style

5553:de0fa35df4cb 22-Sep-2008 Nathan Binkert <nate@binkert.org>

gcc: Version 4.3 is pretty anal about shadowing types, placate it.
In the future, it would be nice to put the O3CPU into its own
namespace so that we don't end up hardcoding pointers to the global
namespace.

5548:19d45fa7315c 19-Sep-2008 Nathan Binkert <nate@binkert.org>

atomicio: provide atomic read and write functions.

These functions keep trying to read and write until all data has been
transferred, or an error occurrs. In the case where an end of file
hasn't been reached, but all of the bytes have not been read/written,
try again. On EINTR, try again.

5547:747034106af4 19-Sep-2008 Nathan Binkert <nate@binkert.org>

Use C++ limits where applicable for portability

5546:4ffc3cafba9b 19-Sep-2008 Nathan Binkert <nate@binkert.org>

Use the proper version of C++ headers

5545:d7c7b6752e2c 19-Sep-2008 Nathan Binkert <nate@binkert.org>

Check the return value of I/O operations for failure

5544:65b27e939646 19-Sep-2008 Nathan Binkert <nate@binkert.org>

inifile: Whack preprocessor access.
We haven't used the preprocessor feature of the inifile stuff in a
very long time, so let's get rid of it since it would otherwise take
effort to maintain.

5543:3af77710f397 10-Sep-2008 Ali Saidi <saidi@eecs.umich.edu>

style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs


/gem5/configs/common/Benchmarks.py
/gem5/src/arch/alpha/aout_machdep.h
/gem5/src/arch/alpha/ev5.cc
/gem5/src/arch/alpha/floatregfile.hh
/gem5/src/arch/alpha/ipr.cc
/gem5/src/arch/alpha/ipr.hh
/gem5/src/arch/alpha/isa_traits.hh
/gem5/src/arch/alpha/linux/linux.cc
/gem5/src/arch/alpha/linux/linux.hh
/gem5/src/arch/alpha/miscregfile.hh
/gem5/src/arch/alpha/osfpal.cc
/gem5/src/arch/alpha/pagetable.hh
/gem5/src/arch/alpha/regfile.hh
/gem5/src/arch/alpha/remote_gdb.cc
/gem5/src/arch/alpha/system.cc
/gem5/src/arch/alpha/tlb.cc
/gem5/src/arch/alpha/tru64/process.cc
/gem5/src/arch/alpha/tru64/tru64.cc
/gem5/src/arch/alpha/tru64/tru64.hh
/gem5/src/arch/isa_parser.py
/gem5/src/arch/isa_specific.hh
/gem5/src/arch/mips/isa_traits.hh
/gem5/src/arch/mips/linux/linux.cc
/gem5/src/arch/mips/linux/linux.hh
/gem5/src/arch/mips/regfile/regfile.hh
/gem5/src/arch/mips/system.cc
/gem5/src/arch/mips/tlb.cc
/gem5/src/arch/mips/tlb.hh
/gem5/src/arch/sparc/isa_traits.hh
/gem5/src/arch/sparc/linux/linux.cc
/gem5/src/arch/sparc/linux/linux.hh
/gem5/src/arch/sparc/miscregfile.hh
/gem5/src/arch/sparc/regfile.hh
/gem5/src/arch/sparc/remote_gdb.cc
/gem5/src/arch/sparc/solaris/solaris.cc
/gem5/src/arch/sparc/solaris/solaris.hh
/gem5/src/arch/sparc/sparc_traits.hh
/gem5/src/arch/x86/isa/insts/general_purpose/cache_and_memory_management.py
/gem5/src/arch/x86/isa/insts/general_purpose/control_transfer/call.py
/gem5/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py
/gem5/src/arch/x86/isa/insts/general_purpose/data_conversion/ascii_adjust.py
/gem5/src/arch/x86/isa/insts/general_purpose/data_conversion/bcd_adjust.py
/gem5/src/arch/x86/isa/insts/general_purpose/data_conversion/endian_conversion.py
/gem5/src/arch/x86/isa/insts/general_purpose/data_conversion/extract_sign_mask.py
/gem5/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py
/gem5/src/arch/x86/isa/insts/general_purpose/load_segment_registers.py
/gem5/src/arch/x86/isa/insts/general_purpose/semaphores.py
/gem5/src/arch/x86/isa/insts/general_purpose/system_calls.py
/gem5/src/arch/x86/linux/linux.hh
/gem5/src/arch/x86/remote_gdb.cc
bitunion.hh
crc.cc
fast_alloc.cc
fast_alloc.hh
inifile.hh
loader/aout_object.cc
loader/coff_sym.h
loader/coff_symconst.h
loader/ecoff_object.cc
loader/elf_object.cc
loader/hex_file.hh
loader/object_file.hh
loader/symtab.hh
remote_gdb.cc
res_list.hh
stats/flags.hh
stats/mysql.cc
time.hh
trace.hh
/gem5/src/cpu/base_dyn_inst.hh
/gem5/src/cpu/checker/cpu.hh
/gem5/src/cpu/checker/cpu_impl.hh
/gem5/src/cpu/memtest/memtest.hh
/gem5/src/cpu/o3/alpha/dyn_inst.hh
/gem5/src/cpu/o3/mips/dyn_inst.hh
/gem5/src/cpu/o3/regfile.hh
/gem5/src/cpu/ozone/back_end.hh
/gem5/src/cpu/ozone/cpu_impl.hh
/gem5/src/cpu/ozone/front_end.hh
/gem5/src/cpu/ozone/inorder_back_end.hh
/gem5/src/cpu/ozone/lsq_unit_impl.hh
/gem5/src/cpu/ozone/lw_back_end.hh
/gem5/src/cpu/simple/base.hh
/gem5/src/cpu/simple_thread.cc
/gem5/src/cpu/simple_thread.hh
/gem5/src/cpu/static_inst.hh
/gem5/src/dev/alpha/access.h
/gem5/src/dev/etherdump.cc
/gem5/src/dev/mips/access.h
/gem5/src/dev/ns_gige.hh
/gem5/src/dev/pcidev.cc
/gem5/src/dev/pcireg.h
/gem5/src/dev/sinicreg.hh
/gem5/src/kern/linux/linux.hh
/gem5/src/kern/operatingsystem.hh
/gem5/src/kern/solaris/solaris.hh
/gem5/src/kern/tru64/mbuf.hh
/gem5/src/kern/tru64/tru64.hh
/gem5/src/kern/tru64/tru64_syscalls.cc
/gem5/src/mem/cache/blk.hh
/gem5/src/mem/cache/builder.cc
/gem5/src/mem/cache/prefetch/stride.cc
/gem5/src/mem/cache/prefetch/stride.hh
/gem5/src/mem/cache/tags/iic.cc
/gem5/src/mem/cache/tags/lru.cc
/gem5/src/mem/cache/tags/lru.hh
/gem5/src/mem/cache/tags/split_lru.cc
/gem5/src/mem/dram.cc
/gem5/src/mem/physical.hh
/gem5/src/mem/request.hh
/gem5/src/python/m5/SimObject.py
/gem5/src/sim/async.hh
/gem5/src/sim/debug.cc
/gem5/src/sim/eventq.hh
/gem5/src/sim/host.hh
/gem5/src/sim/insttracer.hh
/gem5/src/sim/process.hh
/gem5/src/sim/serialize.cc
/gem5/src/sim/serialize.hh
/gem5/src/sim/sim_events.hh
/gem5/src/sim/syscall_emul.cc
/gem5/src/sim/syscall_emul.hh
/gem5/util/m5/m5op_alpha.S
/gem5/util/m5/m5ops.h
/gem5/util/term/term.c
5541:bb31ea8583d8 08-Sep-2008 Nathan Binkert <nate@binkert.org>

style: This file hugely violated the M5 style.
Remove a bunch of unused cruft from the interface while we're at it

5527:cdcfaac59d70 04-Aug-2008 Steve Reinhardt <stever@gmail.com>

Get rid of outputStream... wasn't really being used
(except for warn()) and new -r/-e options make it
not worth fixing.

5524:e5fbd38bc828 04-Aug-2008 Steve Reinhardt <stever@gmail.com>

Add -r/-e options to redirect stdout/stderr.
Better than using shell since it automatically uses -d directory
for output files (creating it as needed).

5523:6279e78a2df2 03-Aug-2008 Nathan Binkert <nate@binkert.org>

sockets: Add a function to disable all listening sockets.
When invoking several copies of m5 on the same machine at the same
time, there can be a race for TCP ports for the terminal connections
or remote gdb. Expose a function to disable those ports, and have the
regression scripts disable them. There are some SimObjects that have
no other function than to be used with ports (NativeTrace and
EtherTap), so they will panic if the ports are disabled.

5508:992aeed13743 15-Jul-2008 Steve Reinhardt <stever@gmail.com>

Get rid of useless m5_assert macro.
Its only purpose was to print the cycle number but that already
happens in the SIGABRT handler. No one used it anyway.

5499:8bfc7650c344 01-Jul-2008 Ali Saidi <saidi@eecs.umich.edu>

Remove delVirtPort() and make getVirtPort() only return cached version.

5498:2af99511ded4 01-Jul-2008 Ali Saidi <saidi@eecs.umich.edu>

Change everything to use the cached virtPort rather than created their own each time.
This appears to work, but I don't want to commit it until it gets tested a lot more.
I haven't deleted the functionality in this patch that will come later, but one question
is how to enforce encourage objects that call getVirtPort() to not cache the virtual port
since if the CPU changes out from under them it will be worse than useless. Perhaps a null
function like delVirtPort() is still useful in that case.

5484:dc6a459769a1 18-Jun-2008 Nathan Binkert <nate@binkert.org>

inet: initialization fixes.
Make sure variables are properly initialized and also make sure that
truth testing works properly.

5442:0552284c5b8b 12-Jun-2008 Gabe Black <gblack@eecs.umich.edu>

BitUnion: Take out namespace declaration so bitunions can be declared inside classes.

5402:05c388940eb6 15-May-2008 Ali Saidi <saidi@eecs.umich.edu>

Make sure that output files are always checked success before they're used.
Make OutputDirectory::resolve() private and change the functions using
resolve() to instead use create().

5385:658926ff82ed 24-Mar-2008 Steve Reinhardt <stever@gmail.com>

Add FAST_ALLOC_DEBUG and FAST_ALLOC_STATS as SConstruct options.

5383:51dc65015ca9 20-Mar-2008 Gabe Black <gblack@eecs.umich.edu>

MIPS: Check endianness of binaries in SE mode.

5335:69d45f5f21a2 05-Feb-2008 Stephen Hines <hines@cs.fsu.edu>

Add base ARM code to M5

5315:30997e988446 02-Jan-2008 Steve Reinhardt <stever@gmail.com>

Additional comments and helper functions for PrintReq.

5314:e902f12a3af1 02-Jan-2008 Steve Reinhardt <stever@gmail.com>

Add functional PrintReq command for memory-system debugging.

5280:f3d2fbe3c86b 21-Nov-2007 Gabe Black <gblack@eecs.umich.edu>

Get rid of a file that should have never been committed.

5229:74fe2ad63864 09-Nov-2007 Gabe Black <gblack@eecs.umich.edu>

Make non Apple compilation work again. Ali may have to refix this.

5226:b958de8d0ade 08-Nov-2007 Ali Saidi <saidi@eecs.umich.edu>

Compiling: Fix for 64bit compile on Darwin/OSX 10.5.

5223:5f581fe175ce 14-Nov-2007 Korey Sewell <ksewell@umich.edu>

remove unnecessary debug messages I added

5222:bb733a878f85 13-Nov-2007 Korey Sewell <ksewell@umich.edu>

Add in files from merge-bare-iron, get them compiling in FS and SE mode


/gem5/build_opts/MIPS_FS
/gem5/configs/common/FSConfig.py
/gem5/configs/example/fs.py
/gem5/src/arch/alpha/regfile.hh
/gem5/src/arch/isa_parser.py
/gem5/src/arch/mips/BISystem.py
/gem5/src/arch/mips/MipsCPU.py
/gem5/src/arch/mips/MipsSystem.py
/gem5/src/arch/mips/MipsTLB.py
/gem5/src/arch/mips/SConscript
/gem5/src/arch/mips/SConsopts
/gem5/src/arch/mips/bare_iron/system.cc
/gem5/src/arch/mips/bare_iron/system.hh
/gem5/src/arch/mips/constants.hh
/gem5/src/arch/mips/dsp.cc
/gem5/src/arch/mips/dsp.hh
/gem5/src/arch/mips/dt_constants.hh
/gem5/src/arch/mips/faults.cc
/gem5/src/arch/mips/faults.hh
/gem5/src/arch/mips/idle_event.cc
/gem5/src/arch/mips/idle_event.hh
/gem5/src/arch/mips/interrupts.cc
/gem5/src/arch/mips/interrupts.hh
/gem5/src/arch/mips/isa/base.isa
/gem5/src/arch/mips/isa/bitfields.isa
/gem5/src/arch/mips/isa/decoder.isa
/gem5/src/arch/mips/isa/formats/basic.isa
/gem5/src/arch/mips/isa/formats/branch.isa
/gem5/src/arch/mips/isa/formats/control.isa
/gem5/src/arch/mips/isa/formats/dsp.isa
/gem5/src/arch/mips/isa/formats/formats.isa
/gem5/src/arch/mips/isa/formats/fp.isa
/gem5/src/arch/mips/isa/formats/int.isa
/gem5/src/arch/mips/isa/formats/mem.isa
/gem5/src/arch/mips/isa/formats/mt.isa
/gem5/src/arch/mips/isa/formats/noop.isa
/gem5/src/arch/mips/isa/formats/tlbop.isa
/gem5/src/arch/mips/isa/formats/trap.isa
/gem5/src/arch/mips/isa/formats/unimp.isa
/gem5/src/arch/mips/isa/formats/unknown.isa
/gem5/src/arch/mips/isa/formats/util.isa
/gem5/src/arch/mips/isa/includes.isa
/gem5/src/arch/mips/isa/main.isa
/gem5/src/arch/mips/isa/operands.isa
/gem5/src/arch/mips/isa_traits.hh
/gem5/src/arch/mips/kernel_stats.hh
/gem5/src/arch/mips/linux/aligned.hh
/gem5/src/arch/mips/linux/hwrpb.hh
/gem5/src/arch/mips/linux/linux.cc
/gem5/src/arch/mips/linux/linux.hh
/gem5/src/arch/mips/linux/process.cc
/gem5/src/arch/mips/linux/process.hh
/gem5/src/arch/mips/linux/system.cc
/gem5/src/arch/mips/linux/system.hh
/gem5/src/arch/mips/linux/thread_info.hh
/gem5/src/arch/mips/linux/threadinfo.hh
/gem5/src/arch/mips/locked_mem.hh
/gem5/src/arch/mips/mips_core_specific.cc
/gem5/src/arch/mips/mips_core_specific.hh
/gem5/src/arch/mips/mmaped_ipr.hh
/gem5/src/arch/mips/mt.hh
/gem5/src/arch/mips/mt_constants.hh
/gem5/src/arch/mips/pagetable.cc
/gem5/src/arch/mips/pagetable.hh
/gem5/src/arch/mips/pra_constants.hh
/gem5/src/arch/mips/predecoder.hh
/gem5/src/arch/mips/process.cc
/gem5/src/arch/mips/process.hh
/gem5/src/arch/mips/regfile.cc
/gem5/src/arch/mips/regfile.hh
/gem5/src/arch/mips/regfile/float_regfile.cc
/gem5/src/arch/mips/regfile/float_regfile.hh
/gem5/src/arch/mips/regfile/int_regfile.cc
/gem5/src/arch/mips/regfile/int_regfile.hh
/gem5/src/arch/mips/regfile/misc_regfile.cc
/gem5/src/arch/mips/regfile/misc_regfile.hh
/gem5/src/arch/mips/regfile/regfile.cc
/gem5/src/arch/mips/regfile/regfile.hh
/gem5/src/arch/mips/remote_gdb.hh
/gem5/src/arch/mips/stacktrace.cc
/gem5/src/arch/mips/stacktrace.hh
/gem5/src/arch/mips/syscallreturn.hh
/gem5/src/arch/mips/system.cc
/gem5/src/arch/mips/system.hh
/gem5/src/arch/mips/tlb.cc
/gem5/src/arch/mips/tlb.hh
/gem5/src/arch/mips/types.hh
/gem5/src/arch/mips/utility.cc
/gem5/src/arch/mips/utility.hh
/gem5/src/arch/mips/vtophys.cc
/gem5/src/arch/mips/vtophys.hh
SConscript
loader/hex_file.cc
loader/hex_file.cc~
loader/hex_file.hh
loader/object_file.cc
/gem5/src/cpu/BaseCPU.py
/gem5/src/cpu/base.hh
/gem5/src/cpu/o3/thread_context.hh
/gem5/src/cpu/simple/base.cc
/gem5/src/cpu/simple/base.hh
/gem5/src/cpu/simple_thread.hh
/gem5/src/cpu/static_inst.hh
/gem5/src/cpu/thread_context.hh
/gem5/src/dev/mips/Malta.py
/gem5/src/dev/mips/MipsConsole.py
/gem5/src/dev/mips/SConscript
/gem5/src/dev/mips/access.h
/gem5/src/dev/mips/console
/gem5/src/dev/mips/console.cc
/gem5/src/dev/mips/console.hh
/gem5/src/dev/mips/malta.cc
/gem5/src/dev/mips/malta.hh
/gem5/src/dev/mips/malta_cchip.cc
/gem5/src/dev/mips/malta_cchip.hh
/gem5/src/dev/mips/malta_io.cc
/gem5/src/dev/mips/malta_io.hh
/gem5/src/dev/mips/malta_pchip.cc
/gem5/src/dev/mips/malta_pchip.hh
/gem5/src/dev/mips/maltareg.h
/gem5/src/mem/physical.cc
/gem5/src/mem/request.hh
/gem5/src/sim/system.cc
5202:ff56fa8c2091 31-Oct-2007 Steve Reinhardt <stever@gmail.com>

String constant const-ness changes to placate g++ 4.2.
Also some bug fixes in MIPS ISA uncovered by g++ warnings
(Python string compares don't work in C++!).

5196:34e4eb707fd9 31-Oct-2007 Ali Saidi <saidi@eecs.umich.edu>

Traceflags: Old traceflags.py file is no longer needed.

5192:582e583f8e7e 31-Oct-2007 Ali Saidi <saidi@eecs.umich.edu>

Traceflags: Add SCons function to created a traceflag instead of having one file with them all.

5190:fc46e0d647b6 31-Oct-2007 Ali Saidi <saidi@eecs.umich.edu>

Base: Rework the way M5 provides and creates random numbers.

5189:00f8fa0811ea 30-Oct-2007 Vilas Sridharan <vilas.sridharan@gmail.com>

Add constant stat.

Signed Off: Ali Saidi <saidi@eecs.umich.edu>

5152:20fc3ce35147 12-Oct-2007 Gabe Black <gblack@eecs.umich.edu>

Loader: Identify sections based on virtual addresses, and set the LoadAddrMask correctly for x86.

5143:4207b1d8b161 09-Oct-2007 Gabe Black <gblack@eecs.umich.edu>

ELF Loader: Use physical addresses instead of virtual ones.
This works in SE mode because the virtual and physical addresses specified for
segments are the same. In Alpha, the LoadAddrMask is still necessary because
the virtual and physical addresses are the same and apparently rely on the
super page mechanism. All of the regressions pass.

5136:53c8a5da3d65 07-Oct-2007 Gabe Black <gblack@eecs.umich.edu>

BitUnion: Fix some types in the bitunion classes.

5105:511fe87ea24c 02-Oct-2007 Gabe Black <gblack@eecs.umich.edu>

Remote GDB: Get rid of an unwanted delete in SE.

5098:65373916c468 25-Sep-2007 Gabe Black <gblack@eecs.umich.edu>

Condition Codes: Fix the findParity function.

5092:e418877ee8cb 25-Sep-2007 Gabe Black <gblack@eecs.umich.edu>

Condition Codes: Fix type error.

5090:ac0d2ccc9c3b 25-Sep-2007 Gabe Black <gblack@eecs.umich.edu>

Loader: Load all segments of an elf, rather than just the "text" and "data".

5070:3d6a1e37b944 11-Sep-2007 Ali Saidi <saidi@eecs.umich.edu>

Loader: Error if a TLS section is found in the binary.

5066:8a917863f2de 10-Sep-2007 Gabe Black <gblack@eecs.umich.edu>

Remove redundant endian.hh and use byteswap.hh in its place.

4965:ad0e792a5c78 10-Aug-2007 Ali Saidi <saidi@eecs.umich.edu>

DMA: Add IOCache and fix bus bridge to optionally only send requests one
way so a cache can handle partial block requests for i/o devices.

4964:7a8a941f4059 10-Aug-2007 Ali Saidi <saidi@eecs.umich.edu>

Bus: Only call end() on an stl object once in a loop

4889:a557a85bdb96 14-Jul-2007 Steve Reinhardt <stever@eecs.umich.edu>

Add CacheRepl trace flag and move a couple DPRINTFs to it.

4840:ad2beb0f9fd8 02-Aug-2007 Ali Saidi <saidi@eecs.umich.edu>

Output: Make OutputDirectory::create() be able to create binary files.

4740:c3a0f86f1f70 14-Jul-2007 Steve Reinhardt <stever@eecs.umich.edu>

Make NO_FAST_ALLOC compile.

4715:2c37daa0ff2e 20-Jul-2007 Gabe Black <gblack@eecs.umich.edu>

Fix function which calculates the carry flag.

4698:88acffc31e4a 18-Jul-2007 Gabe Black <gblack@eecs.umich.edu>

Fix a compilation error for SubBitUnions,

4683:3b49d35562ed 17-Jul-2007 Gabe Black <gblack@eecs.umich.edu>

Create a file of functions for computing condition codes.
These haven't been very thuroughly tested, so use at your own risk.

4681:5a8ff2219a2f 17-Jul-2007 Gabe Black <gblack@eecs.umich.edu>

Add a conversion constructor so a bitunion can be initialized to a value.
Previously, the bitunion would need to be declared and then assigned to separately.

4680:09867d787df8 14-Jul-2007 Gabe Black <gblack@eecs.umich.edu>

Move bitunion code into it's own file.

4664:216afef21d82 23-Jun-2007 Steve Reinhardt <stever@eecs.umich.edu>

Merge vm1.(none):/home/stever/bk/newmem-head
into vm1.(none):/home/stever/bk/newmem-cache2

src/base/traceflags.py:
Hand merge.

4661:44458219add1 22-Jun-2007 Korey Sewell <ksewell@umich.edu>

mips import pt. 1

src/arch/mips/SConscript:
"mips import pt.1".


/gem5/src/arch/mips/SConscript
/gem5/src/arch/mips/constants.hh
/gem5/src/arch/mips/dsp.cc
/gem5/src/arch/mips/dsp.hh
/gem5/src/arch/mips/dt_constants.hh
/gem5/src/arch/mips/faults.cc
/gem5/src/arch/mips/faults.hh
/gem5/src/arch/mips/isa/bitfields.isa
/gem5/src/arch/mips/isa/decoder.isa
/gem5/src/arch/mips/isa/formats/branch.isa
/gem5/src/arch/mips/isa/formats/control.isa
/gem5/src/arch/mips/isa/formats/dsp.isa
/gem5/src/arch/mips/isa/formats/formats.isa
/gem5/src/arch/mips/isa/formats/fp.isa
/gem5/src/arch/mips/isa/formats/int.isa
/gem5/src/arch/mips/isa/formats/mem.isa
/gem5/src/arch/mips/isa/formats/mt.isa
/gem5/src/arch/mips/isa/formats/tlbop.isa
/gem5/src/arch/mips/isa/formats/util.isa
/gem5/src/arch/mips/isa/includes.isa
/gem5/src/arch/mips/isa/operands.isa
/gem5/src/arch/mips/isa_traits.cc
/gem5/src/arch/mips/isa_traits.hh
/gem5/src/arch/mips/linux/linux.cc
/gem5/src/arch/mips/linux/linux.hh
/gem5/src/arch/mips/linux/process.cc
/gem5/src/arch/mips/linux/process.hh
/gem5/src/arch/mips/locked_mem.hh
/gem5/src/arch/mips/mt.hh
/gem5/src/arch/mips/mt_constants.hh
/gem5/src/arch/mips/pra_constants.hh
/gem5/src/arch/mips/process.hh
/gem5/src/arch/mips/regfile/float_regfile.hh
/gem5/src/arch/mips/regfile/int_regfile.hh
/gem5/src/arch/mips/regfile/misc_regfile.cc
/gem5/src/arch/mips/regfile/misc_regfile.hh
/gem5/src/arch/mips/regfile/regfile.hh
/gem5/src/arch/mips/utility.cc
/gem5/src/arch/mips/utility.hh
bitfield.hh
traceflags.py
/gem5/src/cpu/simple/base.hh
/gem5/src/cpu/simple_thread.hh
/gem5/src/cpu/thread_context.hh
4649:899f745b3c21 08-May-2007 Gabe Black <gblack@eecs.umich.edu>

Fix insertBits so it doesn't shift things into oblivion

4628:17b3ce796176 21-Jun-2007 Steve Reinhardt <stever@eecs.umich.edu>

Getting closer...

configs/example/memtest.py:
Add progress interval option.
src/base/traceflags.py:
Add MemTest flag.
src/cpu/memtest/memtest.cc:
Clean up tracing.
src/cpu/memtest/memtest.hh:
Get rid of unused code.

4571:04b82abadd44 14-Jun-2007 Gabe Black <gblack@eecs.umich.edu>

Fix an assert to allow rounding mode 0.

4550:bb6cb68244bd 10-Jun-2007 Nathan Binkert <binkertn@umich.edu>

only compile fenv.c if we're using fenv

4484:7c56a6c9c265 26-May-2007 Nathan Binkert <binkertn@umich.edu>

Get rid of GNU libelf and its autoconf nastiness and replace
it with FreeBSD's implementation


/gem5/ext/libelf/SConscript
/gem5/ext/libelf/_libelf.h
/gem5/ext/libelf/elf32.h
/gem5/ext/libelf/elf64.h
/gem5/ext/libelf/elf_begin.c
/gem5/ext/libelf/elf_cntl.c
/gem5/ext/libelf/elf_common.h
/gem5/ext/libelf/elf_data.c
/gem5/ext/libelf/elf_end.c
/gem5/ext/libelf/elf_errmsg.c
/gem5/ext/libelf/elf_errno.c
/gem5/ext/libelf/elf_fill.c
/gem5/ext/libelf/elf_flag.c
/gem5/ext/libelf/elf_getarhdr.c
/gem5/ext/libelf/elf_getarsym.c
/gem5/ext/libelf/elf_getbase.c
/gem5/ext/libelf/elf_getident.c
/gem5/ext/libelf/elf_hash.c
/gem5/ext/libelf/elf_kind.c
/gem5/ext/libelf/elf_memory.c
/gem5/ext/libelf/elf_next.c
/gem5/ext/libelf/elf_phnum.c
/gem5/ext/libelf/elf_queue.h
/gem5/ext/libelf/elf_rand.c
/gem5/ext/libelf/elf_rawfile.c
/gem5/ext/libelf/elf_scn.c
/gem5/ext/libelf/elf_shnum.c
/gem5/ext/libelf/elf_shstrndx.c
/gem5/ext/libelf/elf_strptr.c
/gem5/ext/libelf/elf_types.m4
/gem5/ext/libelf/elf_update.c
/gem5/ext/libelf/elf_version.c
/gem5/ext/libelf/gelf.h
/gem5/ext/libelf/gelf_checksum.c
/gem5/ext/libelf/gelf_dyn.c
/gem5/ext/libelf/gelf_ehdr.c
/gem5/ext/libelf/gelf_fsize.c
/gem5/ext/libelf/gelf_getclass.c
/gem5/ext/libelf/gelf_phdr.c
/gem5/ext/libelf/gelf_rel.c
/gem5/ext/libelf/gelf_rela.c
/gem5/ext/libelf/gelf_shdr.c
/gem5/ext/libelf/gelf_sym.c
/gem5/ext/libelf/gelf_symshndx.c
/gem5/ext/libelf/gelf_xlate.c
/gem5/ext/libelf/libelf.c
/gem5/ext/libelf/libelf.h
/gem5/ext/libelf/libelf_align.c
/gem5/ext/libelf/libelf_allocate.c
/gem5/ext/libelf/libelf_ar.c
/gem5/ext/libelf/libelf_checksum.c
/gem5/ext/libelf/libelf_convert.m4
/gem5/ext/libelf/libelf_data.c
/gem5/ext/libelf/libelf_ehdr.c
/gem5/ext/libelf/libelf_extended.c
/gem5/ext/libelf/libelf_fsize.m4
/gem5/ext/libelf/libelf_msize.m4
/gem5/ext/libelf/libelf_phdr.c
/gem5/ext/libelf/libelf_shdr.c
/gem5/ext/libelf/libelf_xlate.c
loader/elf_object.cc
/gem5/util/make_release.py
4445:398ffa3f4e45 11-May-2007 Nathan Binkert <binkertn@umich.edu>

total should be the sum of the vector result of an operation,
not sum the operands and then apply the operation.

4425:e94d396daad9 09-May-2007 Ali Saidi <saidi@eecs.umich.edu>

bit_val was being used directly in the statement in return. If type B had fewer bits than last, bit_val << last would get the wrong answer.

src/base/bitfield.hh:
bit_val was being used directly in the statement in
return. If type B had fewer bits than last, bit_val << last would get
the wrong answer.

4395:9acb011a6c35 21-Apr-2007 Ali Saidi <saidi@eecs.umich.edu>

fixes for solaris compile

4394:dbaff14bb974 21-Apr-2007 Ali Saidi <saidi@eecs.umich.edu>

create base/fenv.c to standerdize fenv across platforms. It's a c file and not a cpp file because c99
(which defines fenv) doesn't necessarily extend to c++ and it is a problem with solaris. If really
desired this could wrap the ieeefp interface found in bsd* as well, but I see no need at the moment.

src/arch/alpha/isa/fp.isa:
src/arch/sparc/isa/formats/basic.isa:
use m5_fesetround()/m5_fegetround() istead of fenv interface directly
src/arch/sparc/isa/includes.isa:
use base/fenv instead of fenv directly
src/base/SConscript:
add fenv to sconscript
src/base/fenv.hh:
src/base/random.cc:
m5 implementation to standerdize fenv across platforms.

4382:b35e75e1b890 13-Apr-2007 Nathan Binkert <binkertn@umich.edu>

Completely re-work how the scons framework incorporates swig
and python code into m5 to allow swig an python code to
easily added by any SConscript instead of just the one in
src/python. This provides SwigSource and PySource for
adding new files to m5 (similar to Source for C++). Also
provides SimObject for including files that contain SimObject
information and build the m5.objects __init__.py file.

4295:28a2ef59d0ca 27-Mar-2007 Nathan Binkert <binkertn@umich.edu>

Instead of creating a new python process to run traceflags.py,
just directly exec the file and generate the flags

4275:8a37341c7507 21-Mar-2007 Gabe Black <gblack@eecs.umich.edu>

Missed a const

4274:638f735c9bc7 20-Mar-2007 Gabe Black <gblack@eecs.umich.edu>

Fixed up some types and const placement, and added signed bitfields that sign extend themselves.

4262:e851cdcf279b 19-Mar-2007 Gabe Black <gblack@eecs.umich.edu>

Ditched read or write only subbitfields for now since they were proving difficult to implement. Allow component Bitfields to be instantiated without templates, clean up the implementation a little, and adjust the comments to match.

4261:0a667162b5fa 19-Mar-2007 Gabe Black <gblack@eecs.umich.edu>

For the _BitfieldRO and _BitfieldWO classes, make sure the undesired operator is redefined as private.

4260:cb8a68017b41 19-Mar-2007 Gabe Black <gblack@eecs.umich.edu>

Formatting fixes.

4259:ca1ca13665ba 19-Mar-2007 Gabe Black <gblack@eecs.umich.edu>

Lots and lots of comments.

4258:a84b8cce90ce 19-Mar-2007 Gabe Black <gblack@eecs.umich.edu>

Reworked the BitUnion stuff a bit. There is moderately better isolation of the backend parts, although there are still macros.

4257:337f01885f36 17-Mar-2007 Gabe Black <gblack@eecs.umich.edu>

Created BitUnion type which lets you define nested bitfields for an integer in a portable way.

4244:18391d0467c6 15-Mar-2007 Ali Saidi <saidi@eecs.umich.edu>

fix a bug gabe found

4243:ba259d97bd84 15-Mar-2007 Gabe Black <gblack@eecs.umich.edu>

Changed warns to DPRINTFs and multiply by 8 where needed.

4224:7e828583f2cb 11-Mar-2007 Gabe Black <gblack@eecs.umich.edu>

Make sttw and sttwa use the twin memory operations.

4216:c01745179a1f 13-Mar-2007 Ali Saidi <saidi@eecs.umich.edu>

fix interrupting during a quisce on sparc

src/arch/sparc/ua2005.cc:
fix interrupting when quisced. Since sticks correspond to instructions when not quisced we need to
check if were suspended and interrupt at the guess time
src/base/traceflags.py:
add trace flag for Iob
src/cpu/simple/base.cc:
Use Quisce instead of IPI trace flag
src/dev/sparc/iob.cc:
add some Dprintfs

4213:37a61d11f39f 12-Mar-2007 Ali Saidi <saidi@eecs.umich.edu>

call ccprintf() with the appropriate argument types so we don't recuse forever

4212:0d50e6c98d13 12-Mar-2007 Ali Saidi <saidi@eecs.umich.edu>

remove the extern C around gdb helper functions. It's need needed for any new version of gdb to work and it causes at least mine to segfault

4209:57ff8c2ae0cf 12-Mar-2007 Ali Saidi <saidi@eecs.umich.edu>

Get rid of those pesky valgrind warnings, Conditional jump or move depends on uninitialised value(s), in the stats package

4202:f7a05daec670 11-Mar-2007 Nathan Binkert <binkertn@umich.edu>

Rework the way SCons recurses into subdirectories, making it
automatic. The point is that now a subdirectory can be added
to the build process just by creating a SConscript file in it.
The process has two passes. On the first pass, all subdirs
of the root of the tree are searched for SConsopts files.
These files contain any command line options that ought to be
added for a particular subdirectory. On the second pass,
all subdirs of the src directory are searched for SConscript
files. These files describe how to build any given subdirectory.
I have added a Source() function. Any file (relative to the
directory in which the SConscript resides) passed to that
function is added to the build. Clean up everything to take
advantage of Source().
function is added to the list of files to be built.

4177:eeb07aef07d0 07-Mar-2007 Gabe Black <gblack@eecs.umich.edu>

Add some constructors and an output operator to the Twin??_t types so that o3 SPARC will compile again.

4167:ce5d0f62f13b 06-Mar-2007 Nathan Binkert <binkertn@umich.edu>

Move all of the parameters of the Root SimObject so they are
directly configured by python. Move stuff from root.(cc|hh) to
core.(cc|hh) since it really belogs there now.
In the process, simplify how ticks are used in the python code.


/gem5/configs/common/FSConfig.py
/gem5/configs/common/Simulation.py
/gem5/configs/example/fs.py
annotate.cc
misc.cc
pollevent.cc
pollevent.hh
trace.hh
/gem5/src/cpu/o3/cpu.cc
/gem5/src/cpu/o3/fetch_impl.hh
/gem5/src/cpu/o3/inst_queue_impl.hh
/gem5/src/cpu/ozone/inst_queue_impl.hh
/gem5/src/cpu/pc_event.cc
/gem5/src/cpu/static_inst.cc
/gem5/src/dev/etherbus.cc
/gem5/src/dev/etherdump.cc
/gem5/src/dev/etherlink.cc
/gem5/src/dev/ide_disk.cc
/gem5/src/dev/pcidev.cc
/gem5/src/kern/tru64/tru64.hh
/gem5/src/mem/cache/cache_blk.hh
/gem5/src/mem/cache/miss/mshr.cc
/gem5/src/mem/cache/tags/iic.cc
/gem5/src/mem/cache/tags/lru.cc
/gem5/src/mem/cache/tags/split_lifo.cc
/gem5/src/mem/cache/tags/split_lru.cc
/gem5/src/mem/packet.hh
/gem5/src/mem/request.hh
/gem5/src/python/m5/__init__.py
/gem5/src/python/m5/convert.py
/gem5/src/python/m5/event.py
/gem5/src/python/m5/main.py
/gem5/src/python/m5/objects/BaseCPU.py
/gem5/src/python/m5/objects/PhysicalMemory.py
/gem5/src/python/m5/objects/Root.py
/gem5/src/python/m5/params.py
/gem5/src/python/m5/ticks.py
/gem5/src/python/swig/core.i
/gem5/src/python/swig/event.i
/gem5/src/sim/builder.cc
/gem5/src/sim/core.cc
/gem5/src/sim/core.hh
/gem5/src/sim/eventq.cc
/gem5/src/sim/main.cc
/gem5/src/sim/root.cc
/gem5/src/sim/sim_events.cc
/gem5/src/sim/sim_events.hh
/gem5/tests/configs/t1000-simple-atomic.py
/gem5/tests/configs/tsunami-simple-atomic-dual.py
/gem5/tests/configs/tsunami-simple-atomic.py
/gem5/tests/configs/tsunami-simple-timing-dual.py
/gem5/tests/configs/tsunami-simple-timing.py
4166:ecebe3ac19b4 06-Mar-2007 Gabe Black <gblack@eecs.umich.edu>

Get X86 to load an elf and start a process for it.

src/arch/x86/SConscript:
Add in process source files.
src/arch/x86/isa_traits.hh:
Replace magic constant numbers with the x86 register names.
src/arch/x86/miscregfile.cc:
Make clear the miscreg file succeed. There aren't any misc regs, so clearing them is very easy.
src/arch/x86/process.hh:
An X86 process class.
src/base/loader/elf_object.cc:
Add in code to recognize x86 as an architecture.
src/base/traceflags.py:
Add an x86 traceflag
src/sim/process.cc:
Add in code to create an x86 process.
src/arch/x86/intregs.hh:
A file which declares names for the integer register indices.
src/arch/x86/linux/linux.cc:
src/arch/x86/linux/linux.hh:
A very simple translation of SPARC's linux.cc and linux.hh. It's probably not correct for x86, but it might not be correct for SPARC either.
src/arch/x86/linux/process.cc:
src/arch/x86/linux/process.hh:
An x86 linux process. The syscall table is split out into it's own file.
src/arch/x86/linux/syscalls.cc:
The x86 Linux syscall table and the uname function.
src/arch/x86/process.cc:
The x86 process base class.
tests/test-progs/hello/bin/x86/linux/hello:
An x86 hello world test binary.

4155:4ac95b9c9149 05-Mar-2007 Gabe Black <gblack@eecs.umich.edu>

Add x86 to the Arch enum in the object file class.

4126:0bb1fc1236a0 03-Mar-2007 Nathan Binkert <binkertn@umich.edu>

Do the default argument stuff in python

4115:cc1d6df13c7d 02-Mar-2007 Ali Saidi <saidi@eecs.umich.edu>

make ldtw(a) -- Twin 32 bit load work correctly -- by doing it the same way as the twin 64 bit loads

src/arch/isa_parser.py:
src/arch/sparc/isa/decoder.isa:
src/arch/sparc/isa/operands.isa:
src/base/bigint.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
src/mem/packet_access.hh:
make ldtw(a) Twin 32 bit load work correctly

4111:65fffcb4fae9 28-Feb-2007 Gabe Black <gblack@eecs.umich.edu>

Make trap instructions always generate TrapInstruction Fault objects which call into the Process object to handle system calls. Refactored the Process objects, and move the handler code into it's own file, and add some syscalls which are used in a natively compiled hello world. Software traps with trap number 3 (not syscall number 3) are supposed to cause the register windows to be flushed but are ignored right now. Finally, made uname for SPARC report a 2.6.12 kernel which is what m22-018.pool happens to be running.

4103:785279436bdd 03-Mar-2007 Ali Saidi <saidi@eecs.umich.edu>

Implement Niagara I/O interface and rework interrupts

configs/common/FSConfig.py:
Use binaries we've compiled instead of the ones that come with Legion
src/arch/alpha/interrupts.hh:
get rid of post(int int_type) and add a get_vec function that gets the interrupt vector for an interrupt number
src/arch/sparc/asi.cc:
Add AsiIsInterrupt() to AsiIsMmu()
src/arch/sparc/faults.cc:
src/arch/sparc/faults.hh:
Add InterruptVector type
src/arch/sparc/interrupts.hh:
rework interrupts. They are no longer cleared when created... A I/O or ASI read/write needs to happen before they are cleared
src/arch/sparc/isa_traits.hh:
Add the "interrupt" trap types to isa traits
src/arch/sparc/miscregfile.cc:
add names for all the misc registers and possible post an interrupt when TL is changed.
src/arch/sparc/miscregfile.hh:
Add a helper function to post an interrupt when pil < some set softint
src/arch/sparc/regfile.cc:
src/arch/sparc/regfile.hh:
InterruptLevel shouldn't really live here, moved to interrupt.hh
src/arch/sparc/tlb.cc:
Add interrupt ASIs to TLB
src/arch/sparc/ua2005.cc:
Add checkSoftInt to check if a softint needs to be posted
Check that a tickCompare isn't scheduled before scheduling one
Post and clear interrupts on queue writes and what not
src/base/bitfield.hh:
Add an helper function to return the msb that is set
src/cpu/base.cc:
src/cpu/base.hh:
get rid of post_interrupt(type) since it's no longer needed.. Add a way to see what interrupts are pending
src/cpu/intr_control.cc:
src/cpu/intr_control.hh:
src/dev/alpha/tsunami_cchip.cc:
src/python/m5/objects/IntrControl.py:
Make IntrControl have a system pointer rather than using a cpu pointer to get one
src/dev/sparc/SConscript:
add iob to SConsscrip
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out:
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini:
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out:
update config.ini/out for intrcntrl not having a cpu pointer anymore


/gem5/configs/common/FSConfig.py
/gem5/src/arch/alpha/interrupts.hh
/gem5/src/arch/sparc/asi.cc
/gem5/src/arch/sparc/faults.cc
/gem5/src/arch/sparc/faults.hh
/gem5/src/arch/sparc/interrupts.hh
/gem5/src/arch/sparc/isa_traits.hh
/gem5/src/arch/sparc/miscregfile.cc
/gem5/src/arch/sparc/miscregfile.hh
/gem5/src/arch/sparc/regfile.cc
/gem5/src/arch/sparc/regfile.hh
/gem5/src/arch/sparc/tlb.cc
/gem5/src/arch/sparc/ua2005.cc
bitfield.hh
/gem5/src/cpu/base.cc
/gem5/src/cpu/base.hh
/gem5/src/cpu/intr_control.cc
/gem5/src/cpu/intr_control.hh
/gem5/src/dev/alpha/tsunami_cchip.cc
/gem5/src/dev/sparc/SConscript
/gem5/src/python/m5/objects/IntrControl.py
/gem5/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
/gem5/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out
/gem5/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
/gem5/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out
/gem5/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
/gem5/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out
/gem5/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
/gem5/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out
/gem5/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
/gem5/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out
4092:851cb6397444 21-Feb-2007 Nathan Binkert <binkertn@umich.edu>

Make comments refer to ticks not cycles

4085:4df21265d806 21-Feb-2007 Nathan Binkert <binkertn@umich.edu>

Fix majory brokenness in my previous MySQL commit, basically
this is just a shuffling around of code and fixes to make
stuff commit properly

4081:80f1e833d118 18-Feb-2007 Nathan Binkert <binkertn@umich.edu>

Get rid of the stand alone ParamContext since all of the
relevant stuff has now been moved to python.

4078:3f73f808bbd4 18-Feb-2007 Nathan Binkert <binkertn@umich.edu>

Get rid of the Statistics and Statreset ParamContexts, and
expose all of the relevant functionality to python. Clean
up the mysql code while we're at it.

4076:e1c56b6b3072 18-Feb-2007 Nathan Binkert <binkertn@umich.edu>

Remove the event_ignore stuff since it was never really used

4074:f2c4afa8cd46 17-Feb-2007 Nathan Binkert <binkertn@umich.edu>

Default to tracing being disabled in C++, it will be turned
on in python. Fix the trace start code so it actually starts
when it is suppsed to. Make the Exec tracing stuff obey the
trace enabled flag.

4070:74449a198a44 18-Feb-2007 Ali Saidi <saidi@eecs.umich.edu>

implement vtophys and 32bit gdb support

src/arch/alpha/vtophys.cc:
src/arch/alpha/vtophys.hh:
src/arch/sparc/arguments.hh:
move Copy* to vport since it's generic for all the ISAs
src/arch/sparc/isa_traits.hh:
the Solaris kernel sets up a virtual-> real mapping for all memory starting at SegKPMBase
src/arch/sparc/pagetable.hh:
add a class for getting bits out of the TteTag
src/arch/sparc/remote_gdb.cc:
add 32bit support kinda.... If its 32 bit
src/arch/sparc/remote_gdb.hh:
Add 32bit register offsets too.
src/arch/sparc/tlb.cc:
cleanup generation of tsb pointers
src/arch/sparc/tlb.hh:
add function to return tsb pointers for an address
make lookup public so vtophys can use it
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
write vtophys for sparc
src/base/bitfield.hh:
return a mask of bits first->last
src/mem/vport.cc:
src/mem/vport.hh:
move Copy* here since it's ISA generic

4055:3b00870359aa 13-Feb-2007 Ali Saidi <saidi@eecs.umich.edu>

fix compiling problems

4054:3d617b3be4fa 13-Feb-2007 Nathan Binkert <binkertn@umich.edu>

Merge all of the execution trace configuration stuff into
the traceflags infrastructure. InstExec is now just Exec
and all of the command line options are now trace options.

4053:ee914b22709e 13-Feb-2007 Nathan Binkert <binkertn@umich.edu>

Rearrange traceflags.py so that the file generation only happens if
the script is invoked as main. This allows us to import traceflags.py
if we just want the list of available flags.
Embed traceflags.py into the zipfile so it can be accessed from the
python side of things. With this, print an error on invalid flags and
add --trace-help option that will print out the list of trace flags
that are compiled in. If a flag is prefixed with a '-', now that flag
will be disabled.

4048:16bc6d222019 12-Feb-2007 Nathan Binkert <binkertn@umich.edu>

cleanup

4046:ef34b290091e 10-Feb-2007 Nathan Binkert <binkertn@umich.edu>

Clean up tracing stuff more, get rid of the trace log since
its not all that useful. Fix a few bugs with python/C++
integration.

4045:43eb54e807d1 09-Feb-2007 Nathan Binkert <binkertn@umich.edu>

Get rid of the Random context and add the support directly to python.
We don't currently use randomness much, so I didn't go too far, but
in the future, we may want to actually expose the random number values
themselves to python. For now, I'll at least let you seed it.
While we're at it, clean up a clearly bad way for generating random
doubles.

4042:dbd98b2264ed 09-Feb-2007 Nathan Binkert <binkertn@umich.edu>

Get rid of the Trace ParamContext and give python direct
access to enabling/disabling tracing. Command line is
unchanged except for the removal of --trace-cycle since
it's not so clear what that means.

4041:f42c73e7e639 08-Feb-2007 Nathan Binkert <binkertn@umich.edu>

Use c99 variadic macros for non gnu compilers

4040:eb894f3fc168 12-Feb-2007 Ali Saidi <saidi@eecs.umich.edu>

rename store conditional stuff as extra data so it can be used for conditional swaps as well
Add support for a twin 64 bit int load
Add Memory barrier and write barrier flags as appropriate
Make atomic memory ops atomic

src/arch/alpha/isa/mem.isa:
src/arch/alpha/locked_mem.hh:
src/cpu/base_dyn_inst.hh:
src/mem/cache/cache_blk.hh:
src/mem/cache/cache_impl.hh:
rename store conditional stuff as extra data so it can be used for conditional swaps as well
src/arch/alpha/types.hh:
src/arch/mips/types.hh:
src/arch/sparc/types.hh:
add a largest read data type for statically allocating read buffers in atomic simple cpu
src/arch/isa_parser.py:
Add support for a twin 64 bit int load
src/arch/sparc/isa/decoder.isa:
Make atomic memory ops atomic
Add Memory barrier and write barrier flags as appropriate
src/arch/sparc/isa/formats/mem/basicmem.isa:
add post access code block and define a twinload format for twin loads
src/arch/sparc/isa/formats/mem/blockmem.isa:
remove old microcoded twin load coad
src/arch/sparc/isa/formats/mem/mem.isa:
swap.isa replaces the code in loadstore.isa
src/arch/sparc/isa/formats/mem/util.isa:
add a post access code block
src/arch/sparc/isa/includes.isa:
need bigint.hh for Twin64_t
src/arch/sparc/isa/operands.isa:
add a twin 64 int type
src/cpu/simple/atomic.cc:
src/cpu/simple/atomic.hh:
src/cpu/simple/base.hh:
src/cpu/simple/timing.cc:
add support for twinloads
add support for swap and conditional swap instructions
rename store conditional stuff as extra data so it can be used for conditional swaps as well
src/mem/packet.cc:
src/mem/packet.hh:
Add support for atomic swap memory commands
src/mem/packet_access.hh:
Add endian conversion function for Twin64_t type
src/mem/physical.cc:
src/mem/physical.hh:
src/mem/request.hh:
Add support for atomic swap memory commands
Rename sc code to extradata

4039:b910b61a52b9 08-Feb-2007 Nathan Binkert <binkertn@umich.edu>

Get rid of the gross operator,()/variadic macro hack
that made ccprintf and friends work, turn it into a
normal function (though it still has a slightly strange
implementation.) All instances of variadic macros
are not yet removed, but I know how, and it will happen.

One side effect of this new implementation is that a
cprintf statement can now only have 16 parameters, though
it's easy enough to raise this number if needed.

4003:fe771fb5e3cf 30-Jan-2007 Gabe Black <gblack@eecs.umich.edu>

sizeof with a pointer to dynamically allocated memory will return the size of the pointer, not the memory.

3980:9bcb2a2e9bb8 27-Jan-2007 Gabe Black <gblack@eecs.umich.edu>

Merge zizzer:/bk/newmem
into zower.eecs.umich.edu:/eecshome/m5/newmem

src/arch/sparc/isa/formats/mem/util.isa:
src/arch/sparc/isa_traits.hh:
src/arch/sparc/system.cc:
Hand Merge

3960:1dca397b2bab 20-Dec-2006 Gabe Black <gblack@eecs.umich.edu>

Initial work to make remote gdb available in SE mode. This is completely untested.

3940:b87f85bb4275 27-Jan-2007 Ali Saidi <saidi@eecs.umich.edu>

While I'm waiting for legion to run make m5 compile with a few more compilers

SConstruct:
src/SConscript:
Add flags for Intel CC while i'm at it
src/base/compiler.hh:
the _Pragma stuff needst to be called this way unless someone happens to have a cleaner way
src/base/cprintf_formats.hh:
add std:: where appropriate
src/base/statistics.hh:
use this->map since icc was getting confused about std::map vs the locally defined map
src/cpu/static_inst.hh:
Add some more dummy returns where needed
src/mem/packet.hh:
add more dummy returns where needed
src/sim/host.hh:
use limits to come up with max tick

3938:470d8d731f42 26-Jan-2007 Ali Saidi <saidi@eecs.umich.edu>

forgot to include this file

3930:f96f7e258255 26-Jan-2007 Ali Saidi <saidi@eecs.umich.edu>

Merge zeep.pool:/z/saidi/work/m5.newmem
into zeep.pool:/z/saidi/work/m5.suncc

3925:08252e3cb1c0 22-Jan-2007 Ali Saidi <saidi@eecs.umich.edu>

we decided to check for .interp instead of .dynamic

3918:1f9a98d198e8 26-Jan-2007 Ali Saidi <saidi@eecs.umich.edu>

make our code a little more standards compliant
pretty close to compiling w/ suns compiler

briefly:
add dummy return after panic()/fatal()
split out flags by compiler vendor
include cstring and cmath where appropriate
use std namespace for string ops

SConstruct:
Add code to detect compiler and choose cflags based on detected compiler
Fix zlib check to work with suncc
src/SConscript:
split out flags by compiler vendor
src/arch/sparc/isa/decoder.isa:
use correct namespace for sqrt
src/arch/sparc/isa/formats/basic.isa:
add dummy return around panic
src/arch/sparc/isa/formats/integerop.isa:
use correct namespace for stringops
src/arch/sparc/isa/includes.isa:
include cstring and cmath where appropriate
src/arch/sparc/isa_traits.hh:
remove dangling comma
src/arch/sparc/system.cc:
dummy return to make sun cc front end happy
src/arch/sparc/tlb.cc:
src/base/compression/lzss_compression.cc:
use std namespace for string ops
src/arch/sparc/utility.hh:
no reason to say something is unsigned unsigned int
src/base/compression/null_compression.hh:
dummy returns to for suncc front end
src/base/cprintf.hh:
use standard variadic argument syntax instead of gnuc specefic renaming
src/base/hashmap.hh:
don't need to define hash for suncc
src/base/hostinfo.cc:
need stdio.h for sprintf
src/base/loader/object_file.cc:
munmap is in std namespace not null
src/base/misc.hh:
use M5 generic noreturn macros
use standard variadic macro __VA_ARGS__
src/base/pollevent.cc:
we need file.h for file flags
src/base/random.cc:
mess with include files to make suncc happy
src/base/remote_gdb.cc:
malloc memory for function instead of having a non-constant in an array size
src/base/statistics.hh:
use std namespace for floor
src/base/stats/text.cc:
include math.h for rint (cmath won't work)
src/base/time.cc:
use suncc version of ctime_r
src/base/time.hh:
change macro to work with both gcc and suncc
src/base/timebuf.hh:
include cstring from memset and use std::
src/base/trace.hh:
change variadic macros to be normal format
src/cpu/SConscript:
add dummy returns where appropriate
src/cpu/activity.cc:
include cstring for memset
src/cpu/exetrace.hh:
include cstring fro memcpy
src/cpu/simple/base.hh:
add dummy return for panic
src/dev/baddev.cc:
src/dev/pciconfigall.cc:
src/dev/platform.cc:
src/dev/sparc/t1000.cc:
add dummy return where appropriate
src/dev/ide_atareg.h:
make define work for both gnuc and suncc
src/dev/io_device.hh:
add dummy returns where approirate
src/dev/pcidev.hh:
src/mem/cache/cache_impl.hh:
src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/tags/lru.hh:
src/mem/cache/tags/split.hh:
src/mem/cache/tags/split_lifo.hh:
src/mem/cache/tags/split_lru.hh:
src/mem/dram.cc:
src/mem/packet.cc:
src/mem/port.cc:
include cstring for string ops
src/dev/sparc/mm_disk.cc:
add dummy return where appropriate
include cstring for string ops
src/mem/cache/miss/blocking_buffer.hh:
src/mem/port.hh:
Add dummy return where appropriate
src/mem/cache/tags/iic.cc:
cast hastSets to double for log() call
src/mem/physical.cc:
cast pmemAddr to char* for munmap
src/sim/byteswap.hh:
make define work for suncc and gnuc

3917:a6cc1842f529 22-Jan-2007 Ali Saidi <saidi@eecs.umich.edu>

check if an executable is dynamic and die if it is
Only implemented for ELf. Someone might want to implement it for ecoff and some point

src/base/loader/elf_object.cc:
src/base/loader/elf_object.hh:
src/base/loader/object_file.cc:
src/base/loader/object_file.hh:
add a function to check if an executable is dynamic
src/sim/process.cc:
check if an executable is dynamic and die if it is

3904:88a6585546e1 16-Jan-2007 Ali Saidi <saidi@eecs.umich.edu>

Don't add symbols for loaded files to symbol table since they are pretty much meaningless with all the copying that goes on

3877:2432a50b7d25 27-Dec-2006 Nathan Binkert <binkertn@umich.edu>

No need to use NULL, just use 0
The result of operator= cannot be an l-value

3874:964682aaad3d 24-Dec-2006 Nathan Binkert <binkertn@umich.edu>

remove some output formatting stuff that we don't use

3857:2d724684bef3 18-Dec-2006 Nathan Binkert <binkertn@umich.edu>

cast chars to int when we want to print integers so we get a number
instead of a character

3832:49c95a73e29c 12-Dec-2006 Ali Saidi <saidi@eecs.umich.edu>

Fix bugs in tlbmap (and thus rangemap since the code is nearly identical)
Deal with block initializing stores (by doing nothing, at some point we might want to do the write hint 64 like thing)
Fix tcc instruction igoner in legion-lock stuff to be correct in all cases
Have console interrupts warn rather than panicing until we figure out what to do with interrupts

src/arch/sparc/miscregfile.cc:
src/arch/sparc/miscregfile.hh:
add a magic miscreg which reads all the bits the tlb needs in one go
src/arch/sparc/tlb.cc:
initialized the context type and id to reasonable values and handle block init stores
src/arch/sparc/tlb_map.hh:
fix bug in tlb map code
src/base/range_map.hh:
fix bug in rangemap code and add range_multimap
(these are probably useful for bus range stuff)
src/cpu/exetrace.cc:
fixup tcc ignore code to be correct
src/dev/sparc/t1000.cc:
make console interrupt stuff warn instead of panicing until we get interrupt stuff figured out
src/unittest/rangemaptest.cc:
fix up the rangemap unit test to catch the missing case

3823:1c8f87aa103e 06-Dec-2006 Ali Saidi <saidi@eecs.umich.edu>

Many more fixes for SPARC_FS. Gets us to the point where SOFTINT starts
getting touched.

configs/common/FSConfig.py:
Physical memory on the T1 starts at 1MB, The first megabyte is unmapped to catch bugs
src/arch/isa_parser.py:
we should readmiscregwitheffect not readmiscreg
src/arch/sparc/asi.cc:
Fix AsiIsNucleus spelling with respect to header file
Add ASI_LSU_CONTROL_REG to AsiSiMmu
src/arch/sparc/asi.hh:
Fix spelling of two ASIs
src/arch/sparc/isa/decoder.isa:
switch back to defaults letting the isa_parser insert readMiscRegWithEffect
src/arch/sparc/isa/formats/mem/util.isa:
Flesh out priviledgedString with hypervisor checks
Make load alternate set the flags correctly
src/arch/sparc/miscregfile.cc:
insert some forgotten break statements
src/arch/sparc/miscregfile.hh:
Add some comments to make it easier to find which misc register is which number
src/arch/sparc/tlb.cc:
flesh out the tlb memory mapped registers a lot more
src/base/traceflags.py:
add an IPR traceflag
src/mem/request.hh:
Fix a bad assert() in request

3814:33bd4ec9d66a 04-Dec-2006 Ali Saidi <saidi@eecs.umich.edu>

More changes to get SPARC fs closer. Now at 1.2M cycles before difference

configs/common/FSConfig.py:
seperate the hypervisor memory and the guest0 memory. In reality we're going to need a better way to do this at some point. Perhaps auto generating the hv-desc image based on the specified config.
src/arch/sparc/isa/decoder.isa:
change reads/writes to the [hs]tick(cmpr) registers to use readmiscregwitheffect
src/arch/sparc/miscregfile.cc:
For niagra stick and tick are aliased to one value (if we end up doing mps we might not want this).
Use instruction count from cpu rather than cycles because that is what legion does
we can change it back after were done with legion
src/base/bitfield.hh:
add a new function mbits() that just masks off bits of interest but doesn't shift
src/cpu/base.cc:
src/cpu/base.hh:
add instruction count to cpu
src/cpu/exetrace.cc:
src/cpu/m5legion_interface.h:
compare instruction count between legion and m5 too
src/cpu/simple/atomic.cc:
change asserts of packet success to if panics wrapped with NDEBUG defines
so we can get some more useful information when we have a bad address
src/dev/isa_fake.cc:
src/dev/isa_fake.hh:
src/python/m5/objects/Device.py:
expand isa fake a bit more having data for each size request, the ability to have writes update the data and to warn on accesses
src/python/m5/objects/System.py:
convert some tabs to spaces
src/python/m5/objects/T1000.py:
add more fake devices for each l1 bank and each memory controller

3812:eaa215123a26 30-Nov-2006 Ali Saidi <saidi@eecs.umich.edu>

Load the hypervisor symbols twice, once with an address mask so that we can get symbols for where it's copied to in memory
Add the ability to use an address mask for symbol loading
Rather then silently failing on platform accesses panic
Move BadAddr/IsaFake no Device from Tsunami
Let the system kernel be none, but warn about it

configs/common/FSConfig.py:
We don't have a kernel for sparc yet
src/arch/sparc/system.cc:
Load the hypervisor symbols twice, once with an address mask so that we can get symbols for where it's copied to in memory
src/base/loader/aout_object.cc:
src/base/loader/aout_object.hh:
src/base/loader/ecoff_object.cc:
src/base/loader/ecoff_object.hh:
src/base/loader/elf_object.cc:
src/base/loader/elf_object.hh:
src/base/loader/object_file.hh:
src/base/loader/raw_object.cc:
src/base/loader/raw_object.hh:
Add the ability to use an address mask for symbol loading
src/dev/sparc/t1000.cc:
Rather then silently failing on platform accesses panic
src/dev/sparc/t1000.hh:
fix up a couple of platform comments
src/python/m5/objects/Bus.py:
src/python/m5/objects/Device.py:
src/python/m5/objects/T1000.py:
src/python/m5/objects/Tsunami.py:
Move BadAddr/IsaFake no Device from Tsunami
src/python/m5/objects/System.py:
Let kernel be none
src/sim/system.cc:
Let the system kernel be none, but warn about it

3804:fa7a01dddc7a 23-Nov-2006 Ali Saidi <saidi@eecs.umich.edu>

first cut at a sparc tlb

src/arch/sparc/SConscript:
Add code to serialize/unserialze tlb entries
src/arch/sparc/asi.cc:
src/arch/sparc/asi.hh:
update asi names for how they're listed in the supplement
add asis
add more asi functions
src/arch/sparc/isa_traits.hh:
move the interrupt stuff and some basic address space stuff into isa traits
src/arch/sparc/miscregfile.cc:
src/arch/sparc/miscregfile.hh:
add mmu registers to tlb
get rid of implicit asi stuff... the tlb will handle it
src/arch/sparc/regfile.hh:
make isnt/dataAsid return ints not asis
src/arch/sparc/tlb.cc:
src/arch/sparc/tlb.hh:
first cut at sparc tlb
src/arch/sparc/vtophys.hh:
pagatable nedes to be included here
src/mem/request.hh:
add asi and if the request is a memory mapped register to the requset object
src/sim/host.hh:
fix incorrect definition of LL

3712:c8a8938402cd 03-Dec-2006 Steve Reinhardt <stever@eecs.umich.edu>

Make cache compression policy a runtime virtual thing
instead of a template policy.

3672:1906dcace7c2 16-Nov-2006 Nathan Binkert <binkertn@umich.edu>

add warn_once which will print any given warning message
only once.

3619:b3dab7606e0e 11-Nov-2006 Nathan Binkert <binkertn@umich.edu>

set TRACING_ON one way or another explicitly in the
SConscript file instead of basing it on DEBUG

3603:714467743f9b 10-Nov-2006 Ali Saidi <saidi@eecs.umich.edu>

fix endian issues with condition codes
use memcpy instead of bcopy
s/u_int32_t/uint32_t/g
fixup endian code to work with solaris
hack to make sure htole() works... Nate, have a good idea to fix this?

src/arch/sparc/faults.cc:
set the reset address to be 40 bits. Makes PC printing easier at least for now.
src/arch/sparc/isa/base.isa:
fix endian issues with condition codes
src/arch/sparc/tlb.hh:
add implemented physical addres constants
src/arch/sparc/utility.hh:
add tlb.hh to utilities
src/base/loader/raw_object.cc:
add a symbol <filename>_start to the symbol table for binaries files
src/base/remote_gdb.cc:
use memcpy instead of bcopy
src/cpu/exetrace.cc:
clean up printing a bit more
src/cpu/m5legion_interface.h:
add tons to the shared interface
src/dev/ethertap.cc:
s/u_int32_t/uint32_t/g
src/dev/ide_atareg.h:
fixup endian code to work with solaris
src/dev/pcidev.cc:
src/sim/param.hh:
hack to make sure htole() works...

3594:e401993e0cbb 10-Nov-2006 Kevin Lim <ktlim@umich.edu>

Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem

3584:8c3cdb2c001c 09-Nov-2006 Ali Saidi <saidi@eecs.umich.edu>

Get SPARC to the point that it starts running. Add ability to load the ROM bin files, cleanup lockstep printing a bit
Since we don't have a platform yet, you need to comment out the default responder stuff in Bus.py to make it work.

SConstruct:
Add TARGET_ISA to the list of environment variables that end up in the build_env for python
configs/common/FSConfig.py:
add a simple SPARC system to being testing with, you'll need to change makeLinuxAlphaSystem to makeSparcSystem in fs.py for now
src/SConscript:
add a raw file object, at least until we get more info about how to compile openboot properly
src/arch/sparc/system.cc:
src/arch/sparc/system.hh:
add parameters for ROM files (OBP/Reset/Hypervisor), a ROM, load files into ROM
src/base/loader/object_file.cc:
src/base/loader/object_file.hh:
add option to try raw when nothing works
src/cpu/exetrace.cc:
cleanup lockstep printing a little bit
src/cpu/m5legion_interface.h:
change the instruction to be 32 bits because it is
src/mem/physical.cc:
fix assert that doesn't work if memory starts somewhere above 0
src/python/m5/objects/BaseCPU.py:
Add if statement to choose between sparc tlbs and alpha tlbs
src/python/m5/objects/System.py:
Add a sparc system that sets the rom addresses correctly
src/python/m5/params.py:
add the ability to add Addr() together

3579:e9976b62c259 08-Nov-2006 Gabe Black <gblack@eecs.umich.edu>

Make a function to say how big gdbregs is in bytes vs. regs.

3550:515e876568b4 07-Nov-2006 Gabe Black <gblack@eecs.umich.edu>

Broke remote_gdb into a base class and architecture specific derived classes.

3536:89aa06409e4d 06-Nov-2006 Gabe Black <gblack@eecs.umich.edu>

Remote GDB support has been changed to use inheritance. Alpha should work, but isn't tested. Other architectures will not.

3534:b838ec79077d 06-Nov-2006 Gabe Black <gblack@eecs.umich.edu>

Created seperate SConscript for the dev directory. Made subdirectories for Alpha and SPARC and put SConscripts in them.

3515:98655e4fd9f1 08-Nov-2006 Ali Saidi <saidi@eecs.umich.edu>

DWARF2 symbol support seems to be broken on Solaris. Use stabs+
align the character arrays that are used by placement-new for classes lest we have an unaligned fault on SPARC/Solaris

src/SConscript:
DWARF2 symbol support seems to be broken on Solaris. Use stabs+
src/base/statistics.hh:
align the character arrays that are used by placement-new for classes lest we have an unaligned fault on SPARC/Solaris

3483:edede8473667 04-Nov-2006 Ali Saidi <saidi@eecs.umich.edu>

fixes so that M5 will compile under solaris

SConstruct:
Add check to see if we need to include libsocket
src/arch/sparc/floatregfile.cc:
src/arch/sparc/intregfile.cc:
use memset rather than bzero and include the appropriate headerfile
src/base/pollevent.cc:
If we're compling under solaris we need sys/file.h
src/base/random.cc:
src/base/random.hh:
solaris doesn't have random(), so use rint with the correct rounding mode
if we're compiling on solaris
src/base/stats/flags.hh:
u_int32_t??
src/base/time.hh:
grab the timersub() define from freebsd since it doesn't exist in solaris
src/cpu/inst_seq.hh:
we don't need to include stdint here
src/sim/byteswap.hh:
the method to detect endianness on Solaris is a little more complex...

3422:426a8ebd677c 26-Oct-2006 Gabe Black <gblack@eecs.umich.edu>

Added a few functions to stuff values into bitfields in an instruction.

3397:21bc4be1ffea 24-Oct-2006 Ali Saidi <saidi@eecs.umich.edu>

Merge zizzer:/bk/newmem
into zeep.pool:/z/saidi/work/m5.newmem.head

3386:6094e8865bb8 23-Oct-2006 Gabe Black <gblack@eecs.umich.edu>

Files in base shouldn't depend on things in sim. Changed "sim/host.hh" to <inttypes.hh>

3368:3342dd3f5248 22-Oct-2006 Steve Reinhardt <stever@eecs.umich.edu>

Add Quiesce trace flag to track CPU quiesce/wakeup events.

3351:3ec31cd94535 24-Oct-2006 Ali Saidi <saidi@eecs.umich.edu>

Add more traceflags for ethernet

3330:2f71fdea7341 19-Oct-2006 Steve Reinhardt <stever@eecs.umich.edu>

Add "All" compund flag to enable all defined trace flags.

3286:21d9d32ab8ab 12-Oct-2006 Ali Saidi <saidi@eecs.umich.edu>

Merge zizzer:/bk/newmem
into zeep.pool:/z/saidi/work/m5.newmem.head

src/mem/packet.hh:
hand merge

3281:d0f7a2e1573f 12-Oct-2006 Ron Dreslinski <rdreslin@umich.edu>

Fix problems with unCacheable addresses in timing-coherence

src/base/traceflags.py:
src/mem/physical.cc:
Add debug falgs fro physical memory accesses
src/mem/cache/cache_impl.hh:
Snoops to uncacheable blocks should not happen
src/mem/cache/miss/miss_queue.cc:
Set the size properly on unCacheable accesses

3260:d9ef6d4cbe2a 12-Oct-2006 Ali Saidi <saidi@eecs.umich.edu>

add a traceflag for functional accesses
implement fix packet and add the ability to print a packet to a ostream
remove tabs in packet.hh (Could people stop inserting them??!?!?!)
mark const functions in packet.hh as such

src/base/traceflags.py:
add a traceflag for functional accesses
src/mem/packet.cc:
implement fix packet and add the ability to print a packet to a ostream
src/mem/packet.hh:
add the ability to print a packet to an ostream
remove tabs in file
mark const functions as such

3246:29acc553907f 10-Oct-2006 Ron Dreslinski <rdreslin@umich.edu>

Debugging info

src/base/traceflags.py:
Add new flags for cacheport
src/mem/bus.cc:
Add debugging info
src/mem/cache/base_cache.cc:
Add debuggin info

3170:37fd1e73f836 08-Oct-2006 Steve Reinhardt <stever@eecs.umich.edu>

Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing)
and PhysicalMemory. *No* support for caches or O3CPU.
Note that properly setting cpu_id on all CPUs is now required
for correct operation.

src/arch/SConscript:
src/base/traceflags.py:
src/cpu/base.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
src/cpu/simple/timing.hh:
src/mem/physical.cc:
src/mem/physical.hh:
src/mem/request.hh:
src/python/m5/objects/BaseCPU.py:
tests/configs/simple-atomic.py:
tests/configs/simple-timing.py:
tests/configs/tsunami-simple-atomic-dual.py:
tests/configs/tsunami-simple-atomic.py:
tests/configs/tsunami-simple-timing-dual.py:
tests/configs/tsunami-simple-timing.py:
Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing)
and PhysicalMemory. *No* support for caches or O3CPU.

3089:0ea2eb13c4de 11-Sep-2006 Ali Saidi <saidi@eecs.umich.edu>

add annotation code to m5

configs/common/Benchmarks.py:
add annotate test app
src/SConscript:
add annotate.cc to lis
src/arch/alpha/isa/decoder.isa:
add annotate instructions
src/base/traceflags.py:
Add annotate trace flag
src/sim/pseudo_inst.cc:
src/sim/pseudo_inst.hh:
add annotate pseudo ops
util/m5/m5op.S:
util/m5/m5op.h:
add anotate ops

3082:2b5c51982f78 28-Aug-2006 Steve Reinhardt <stever@eecs.umich.edu>

Fix remote gdb buffer overflow.

2989:9a6f66c38acc 15-Aug-2006 Ali Saidi <saidi@eecs.umich.edu>

fixes for gcc 4.1
Nate needs to fix sinic builder stuff
Gabe needs to verify my fixes to decoder.isa

OPT/DEBUG compiles for ALPHA_FS, ALPHA_SE, MIPS_SE, SPARC_SE with this changeset

README:
Fix the swig version in the readme
src/SConscript:
remove sinic until nate fixes the builder crap for it
src/arch/alpha/system.hh:
src/arch/mips/isa/includes.isa:
src/arch/sparc/isa/decoder.isa:
src/base/stats/visit.cc:
src/base/timebuf.hh:
src/dev/ide_disk.cc:
src/dev/sinic.cc:
src/mem/cache/miss/mshr.cc:
src/mem/cache/miss/mshr_queue.cc:
src/mem/packet.hh:
src/mem/request.hh:
src/sim/builder.hh:
src/sim/system.hh:
fixes for gcc 4.1

2986:99640058db70 15-Aug-2006 Gabe Black <gblack@eecs.umich.edu>

Some touchup to the reorganized includes and "using" directives.

2982:0ecdb0879b14 14-Aug-2006 Steve Reinhardt <stever@eecs.umich.edu>

Fix up doxygen.

2976:371224501196 11-Aug-2006 Gabe Black <gblack@eecs.umich.edu>

Added code to support setting up all of the auxillieary vectors configured by the sparc linux elf loader.

src/arch/sparc/process.cc:
All of the auxilliary vectors are now set like they are in the linux elf loader. This code should probably be moved to arch/sparc/linux/process.cc somehow.

2873:1377a68cd00e 10-Jul-2006 Kevin Lim <ktlim@umich.edu>

Add parameters for backwards and forwards sizes for time buffers.

src/base/timebuf.hh:
Add a function to return the size of the time buffer.

2837:10ae172449b3 05-Jul-2006 Kevin Lim <ktlim@umich.edu>

Fix up some merge problems.

src/base/traceflags.py:
Remove BaseCPU traceflag.
src/cpu/o3/alpha/params.hh:
Move non-Alpha specific parameters out of this params class.
src/cpu/o3/params.hh:
Move non-Alpha specific params into this params class.

2836:c8f549058964 05-Jul-2006 Kevin Lim <ktlim@umich.edu>

Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge

src/base/traceflags.py:
src/cpu/SConscript:
Hand merge.
src/cpu/o3/alpha/params.hh:
Hand merge. This needs to get changed.

2831:0a42b294727c 02-Jul-2006 Korey Sewell <ksewell@umich.edu>

Fix default SMT configuration in O3CPU (i.e. fetch policy, workloads/numThreads)

Edit Test3 for newmem

src/base/traceflags.py:
Add O3CPU flag
src/cpu/base.cc:
for some reason adding a BaseCPU flag doesnt work so just go back to old way...
src/cpu/o3/alpha/cpu_builder.cc:
Determine number threads by workload size instead of solely by parameter.

Default SMT fetch policy to RoundRobin if it's not specified in Config file
src/cpu/o3/commit.hh:
only use nextNPC for !ALPHA
src/cpu/o3/commit_impl.hh:
add FetchTrapPending as condition for commit
src/cpu/o3/cpu.cc:
panic if active threads is more than Impl::MaxThreads
src/cpu/o3/fetch.hh:
src/cpu/o3/inst_queue.hh:
src/cpu/o3/inst_queue_impl.hh:
src/cpu/o3/rob.hh:
src/cpu/o3/rob_impl.hh:
name stuff
src/cpu/o3/fetch_impl.hh:
fatal if try to use SMT branch count, that's unimplemented right now
src/python/m5/config.py:
make it clearer that a parameter is not valid within a configuration class

2830:14ecb0704388 01-Jul-2006 Korey Sewell <ksewell@umich.edu>

traceflag stuff

src/base/traceflags.py:
add BaseCPU flag, O3CPUAll flag grouping
src/cpu/base.cc:
Use BaseCPU flag instead of FullCPU flag

2822:c0f64fa9f219 05-Jul-2006 Kevin Lim <ktlim@umich.edu>

Alphabetize traceflags, rename FullCPUAll flag to O3CPUAll.

2802:babfc298ac86 26-Jun-2006 Ali Saidi <saidi@eecs.umich.edu>

remove extern "C" from the functions we all from gdb. This isn't requried and trips up GDB sometimes when i thinks the extern
name should be mangled, but it isn't

2760:4dbf498165ac 17-Jun-2006 Nathan Binkert <binkertn@umich.edu>

Add myself to list of authors

2733:e0eac8fc5774 16-Jun-2006 Kevin Lim <ktlim@umich.edu>

Two updates that got combined into one ChangeSet accidentally. They're both pretty simple so they shouldn't cause any trouble.

First: Rename FullCPU and its variants in the o3 directory to O3CPU to differentiate from the old model, and also to specify it's an out of order model.

Second: Include build options for selecting the Checker to be used. These options make sure if the Checker is being used there is a CPU that supports it also being compiled.

SConstruct:
Add in option USE_CHECKER to allow for not compiling in checker code. The checker is enabled through this option instead of through the CPU_MODELS list. However it's still necessary to treat the Checker like a CPU model, so it is appended onto the CPU_MODELS list if enabled.
configs/test/test.py:
Name change for DetailedCPU to DetailedO3CPU. Also include option for max tick.
src/base/traceflags.py:
Add in O3CPU trace flag.
src/cpu/SConscript:
Rename AlphaFullCPU to AlphaO3CPU.

Only include checker sources if they're necessary. Also add a list of CPUs that support the Checker, and only allow the Checker to be compiled in if one of those CPUs are also being included.
src/cpu/base_dyn_inst.cc:
src/cpu/base_dyn_inst.hh:
Rename typedef to ImplCPU instead of FullCPU, to differentiate from the old FullCPU.
src/cpu/cpu_models.py:
src/cpu/o3/alpha_cpu.cc:
src/cpu/o3/alpha_cpu.hh:
src/cpu/o3/alpha_cpu_builder.cc:
src/cpu/o3/alpha_cpu_impl.hh:
Rename AlphaFullCPU to AlphaO3CPU to differentiate from old FullCPU model.
src/cpu/o3/alpha_dyn_inst.hh:
src/cpu/o3/alpha_dyn_inst_impl.hh:
src/cpu/o3/alpha_impl.hh:
src/cpu/o3/alpha_params.hh:
src/cpu/o3/commit.hh:
src/cpu/o3/cpu.hh:
src/cpu/o3/decode.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/iew.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue.hh:
src/cpu/o3/lsq.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/o3/lsq_unit.hh:
src/cpu/o3/regfile.hh:
src/cpu/o3/rename.hh:
src/cpu/o3/rename_impl.hh:
src/cpu/o3/rob.hh:
src/cpu/o3/rob_impl.hh:
src/cpu/o3/thread_state.hh:
src/python/m5/objects/AlphaO3CPU.py:
Rename FullCPU to O3CPU to differentiate from old FullCPU model.
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/lsq_unit_impl.hh:
Rename FullCPU to O3CPU to differentiate from old FullCPU model.
Also #ifdef the checker code so it doesn't need to be included if it's not selected.

2716:b9114064d77a 11-Jun-2006 Nathan Binkert <binkertn@umich.edu>

Merge iceaxe.:/Volumes/work/research/m5/head
into iceaxe.:/Volumes/work/research/m5/merge

src/cpu/simple/base.cc:
src/kern/kernel_stats.cc:
src/kern/kernel_stats.hh:
src/kern/system_events.cc:
src/kern/system_events.hh:
src/python/m5/objects/System.py:
src/sim/system.cc:
src/sim/system.hh:
hand merge

2684:71f3cabf891f 08-Jun-2006 Ali Saidi <saidi@eecs.umich.edu>

add write/read functions that have endian conversions in them
when we get a virtual port delete it (even though delete does nothing in these cases)

src/arch/alpha/linux/system.cc:
src/arch/alpha/stacktrace.cc:
src/base/remote_gdb.cc:
src/cpu/simple_thread.cc:
when we get a virtual port delete it (even though delete does nothing in this case)
src/mem/port.hh:
src/mem/vport.hh:
add write/read functions that have endian conversions in them

2680:246e7104f744 06-Jun-2006 Kevin Lim <ktlim@umich.edu>

Change ExecContext to ThreadContext. This is being renamed to differentiate between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh.

Further renames/reorganization will be coming shortly; what is currently CPUExecContext (the old ExecContext from m5) will be renamed to SimpleThread or something similar.

src/arch/alpha/arguments.cc:
src/arch/alpha/arguments.hh:
src/arch/alpha/ev5.cc:
src/arch/alpha/faults.cc:
src/arch/alpha/faults.hh:
src/arch/alpha/freebsd/system.cc:
src/arch/alpha/freebsd/system.hh:
src/arch/alpha/isa/branch.isa:
src/arch/alpha/isa/decoder.isa:
src/arch/alpha/isa/main.isa:
src/arch/alpha/linux/process.cc:
src/arch/alpha/linux/system.cc:
src/arch/alpha/linux/system.hh:
src/arch/alpha/linux/threadinfo.hh:
src/arch/alpha/process.cc:
src/arch/alpha/regfile.hh:
src/arch/alpha/stacktrace.cc:
src/arch/alpha/stacktrace.hh:
src/arch/alpha/tlb.cc:
src/arch/alpha/tlb.hh:
src/arch/alpha/tru64/process.cc:
src/arch/alpha/tru64/system.cc:
src/arch/alpha/tru64/system.hh:
src/arch/alpha/utility.hh:
src/arch/alpha/vtophys.cc:
src/arch/alpha/vtophys.hh:
src/arch/mips/faults.cc:
src/arch/mips/faults.hh:
src/arch/mips/isa_traits.cc:
src/arch/mips/isa_traits.hh:
src/arch/mips/linux/process.cc:
src/arch/mips/process.cc:
src/arch/mips/regfile/float_regfile.hh:
src/arch/mips/regfile/int_regfile.hh:
src/arch/mips/regfile/misc_regfile.hh:
src/arch/mips/regfile/regfile.hh:
src/arch/mips/stacktrace.hh:
src/arch/sparc/faults.cc:
src/arch/sparc/faults.hh:
src/arch/sparc/isa_traits.hh:
src/arch/sparc/linux/process.cc:
src/arch/sparc/linux/process.hh:
src/arch/sparc/process.cc:
src/arch/sparc/regfile.hh:
src/arch/sparc/solaris/process.cc:
src/arch/sparc/stacktrace.hh:
src/arch/sparc/ua2005.cc:
src/arch/sparc/utility.hh:
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
src/base/remote_gdb.cc:
src/base/remote_gdb.hh:
src/cpu/base.cc:
src/cpu/base.hh:
src/cpu/base_dyn_inst.hh:
src/cpu/checker/cpu.cc:
src/cpu/checker/cpu.hh:
src/cpu/checker/exec_context.hh:
src/cpu/cpu_exec_context.cc:
src/cpu/cpu_exec_context.hh:
src/cpu/cpuevent.cc:
src/cpu/cpuevent.hh:
src/cpu/exetrace.hh:
src/cpu/intr_control.cc:
src/cpu/memtest/memtest.hh:
src/cpu/o3/alpha_cpu.hh:
src/cpu/o3/alpha_cpu_impl.hh:
src/cpu/o3/alpha_dyn_inst_impl.hh:
src/cpu/o3/commit.hh:
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/regfile.hh:
src/cpu/o3/thread_state.hh:
src/cpu/ozone/back_end.hh:
src/cpu/ozone/cpu.hh:
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/front_end_impl.hh:
src/cpu/ozone/inorder_back_end.hh:
src/cpu/ozone/lw_back_end.hh:
src/cpu/ozone/lw_back_end_impl.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/ozone/lw_lsq_impl.hh:
src/cpu/ozone/thread_state.hh:
src/cpu/pc_event.cc:
src/cpu/pc_event.hh:
src/cpu/profile.cc:
src/cpu/profile.hh:
src/cpu/quiesce_event.cc:
src/cpu/quiesce_event.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/base.cc:
src/cpu/simple/base.hh:
src/cpu/simple/timing.cc:
src/cpu/static_inst.cc:
src/cpu/static_inst.hh:
src/cpu/thread_state.hh:
src/dev/alpha_console.cc:
src/dev/ns_gige.cc:
src/dev/sinic.cc:
src/dev/tsunami_cchip.cc:
src/kern/kernel_stats.cc:
src/kern/kernel_stats.hh:
src/kern/linux/events.cc:
src/kern/linux/events.hh:
src/kern/system_events.cc:
src/kern/system_events.hh:
src/kern/tru64/dump_mbuf.cc:
src/kern/tru64/tru64.hh:
src/kern/tru64/tru64_events.cc:
src/kern/tru64/tru64_events.hh:
src/mem/vport.cc:
src/mem/vport.hh:
src/sim/faults.cc:
src/sim/faults.hh:
src/sim/process.cc:
src/sim/process.hh:
src/sim/pseudo_inst.cc:
src/sim/pseudo_inst.hh:
src/sim/syscall_emul.cc:
src/sim/syscall_emul.hh:
src/sim/system.cc:
src/cpu/thread_context.hh:
src/sim/system.hh:
src/sim/vptr.hh:
Change ExecContext to ThreadContext.


/gem5/src/arch/alpha/arguments.cc
/gem5/src/arch/alpha/arguments.hh
/gem5/src/arch/alpha/ev5.cc
/gem5/src/arch/alpha/faults.cc
/gem5/src/arch/alpha/faults.hh
/gem5/src/arch/alpha/freebsd/system.cc
/gem5/src/arch/alpha/freebsd/system.hh
/gem5/src/arch/alpha/isa/branch.isa
/gem5/src/arch/alpha/isa/decoder.isa
/gem5/src/arch/alpha/isa/main.isa
/gem5/src/arch/alpha/linux/process.cc
/gem5/src/arch/alpha/linux/system.cc
/gem5/src/arch/alpha/linux/system.hh
/gem5/src/arch/alpha/linux/threadinfo.hh
/gem5/src/arch/alpha/process.cc
/gem5/src/arch/alpha/regfile.hh
/gem5/src/arch/alpha/stacktrace.cc
/gem5/src/arch/alpha/stacktrace.hh
/gem5/src/arch/alpha/tlb.cc
/gem5/src/arch/alpha/tlb.hh
/gem5/src/arch/alpha/tru64/process.cc
/gem5/src/arch/alpha/tru64/system.cc
/gem5/src/arch/alpha/tru64/system.hh
/gem5/src/arch/alpha/utility.hh
/gem5/src/arch/alpha/vtophys.cc
/gem5/src/arch/alpha/vtophys.hh
/gem5/src/arch/mips/faults.cc
/gem5/src/arch/mips/faults.hh
/gem5/src/arch/mips/isa_traits.cc
/gem5/src/arch/mips/isa_traits.hh
/gem5/src/arch/mips/linux/process.cc
/gem5/src/arch/mips/process.cc
/gem5/src/arch/mips/regfile/float_regfile.hh
/gem5/src/arch/mips/regfile/int_regfile.hh
/gem5/src/arch/mips/regfile/misc_regfile.hh
/gem5/src/arch/mips/regfile/regfile.hh
/gem5/src/arch/mips/stacktrace.hh
/gem5/src/arch/sparc/faults.cc
/gem5/src/arch/sparc/faults.hh
/gem5/src/arch/sparc/isa_traits.hh
/gem5/src/arch/sparc/linux/process.cc
/gem5/src/arch/sparc/linux/process.hh
/gem5/src/arch/sparc/process.cc
/gem5/src/arch/sparc/regfile.hh
/gem5/src/arch/sparc/solaris/process.cc
/gem5/src/arch/sparc/stacktrace.hh
/gem5/src/arch/sparc/ua2005.cc
/gem5/src/arch/sparc/utility.hh
/gem5/src/arch/sparc/vtophys.cc
/gem5/src/arch/sparc/vtophys.hh
remote_gdb.cc
remote_gdb.hh
/gem5/src/cpu/base.cc
/gem5/src/cpu/base.hh
/gem5/src/cpu/base_dyn_inst.hh
/gem5/src/cpu/checker/cpu.cc
/gem5/src/cpu/checker/cpu.hh
/gem5/src/cpu/checker/exec_context.hh
/gem5/src/cpu/cpu_exec_context.cc
/gem5/src/cpu/cpu_exec_context.hh
/gem5/src/cpu/cpuevent.cc
/gem5/src/cpu/cpuevent.hh
/gem5/src/cpu/exec_context.hh
/gem5/src/cpu/exetrace.hh
/gem5/src/cpu/intr_control.cc
/gem5/src/cpu/memtest/memtest.hh
/gem5/src/cpu/o3/alpha_cpu.hh
/gem5/src/cpu/o3/alpha_cpu_impl.hh
/gem5/src/cpu/o3/alpha_dyn_inst_impl.hh
/gem5/src/cpu/o3/commit.hh
/gem5/src/cpu/o3/commit_impl.hh
/gem5/src/cpu/o3/cpu.cc
/gem5/src/cpu/o3/cpu.hh
/gem5/src/cpu/o3/fetch_impl.hh
/gem5/src/cpu/o3/regfile.hh
/gem5/src/cpu/o3/thread_state.hh
/gem5/src/cpu/ozone/back_end.hh
/gem5/src/cpu/ozone/cpu.hh
/gem5/src/cpu/ozone/cpu_impl.hh
/gem5/src/cpu/ozone/front_end.hh
/gem5/src/cpu/ozone/front_end_impl.hh
/gem5/src/cpu/ozone/inorder_back_end.hh
/gem5/src/cpu/ozone/lw_back_end.hh
/gem5/src/cpu/ozone/lw_back_end_impl.hh
/gem5/src/cpu/ozone/lw_lsq.hh
/gem5/src/cpu/ozone/lw_lsq_impl.hh
/gem5/src/cpu/ozone/thread_state.hh
/gem5/src/cpu/pc_event.cc
/gem5/src/cpu/pc_event.hh
/gem5/src/cpu/profile.cc
/gem5/src/cpu/profile.hh
/gem5/src/cpu/quiesce_event.cc
/gem5/src/cpu/quiesce_event.hh
/gem5/src/cpu/simple/atomic.cc
/gem5/src/cpu/simple/base.cc
/gem5/src/cpu/simple/base.hh
/gem5/src/cpu/simple/timing.cc
/gem5/src/cpu/static_inst.cc
/gem5/src/cpu/static_inst.hh
/gem5/src/cpu/thread_context.hh
/gem5/src/cpu/thread_state.hh
/gem5/src/dev/alpha_console.cc
/gem5/src/dev/ns_gige.cc
/gem5/src/dev/sinic.cc
/gem5/src/dev/tsunami_cchip.cc
/gem5/src/kern/kernel_stats.cc
/gem5/src/kern/kernel_stats.hh
/gem5/src/kern/linux/events.cc
/gem5/src/kern/linux/events.hh
/gem5/src/kern/system_events.cc
/gem5/src/kern/system_events.hh
/gem5/src/kern/tru64/dump_mbuf.cc
/gem5/src/kern/tru64/tru64.hh
/gem5/src/kern/tru64/tru64_events.cc
/gem5/src/kern/tru64/tru64_events.hh
/gem5/src/mem/vport.cc
/gem5/src/mem/vport.hh
/gem5/src/sim/faults.cc
/gem5/src/sim/faults.hh
/gem5/src/sim/process.cc
/gem5/src/sim/process.hh
/gem5/src/sim/pseudo_inst.cc
/gem5/src/sim/pseudo_inst.hh
/gem5/src/sim/syscall_emul.cc
/gem5/src/sim/syscall_emul.hh
/gem5/src/sim/system.cc
/gem5/src/sim/system.hh
/gem5/src/sim/vptr.hh
2670:9107b8bd08cd 02-Jun-2006 Kevin Lim <ktlim@umich.edu>

Merge ktlim@zizzer:/bk/newmem
into zizzer.eecs.umich.edu:/.automount/zamp/z/ktlim2/clean/newmem


/gem5/SConstruct
/gem5/src/SConscript
/gem5/src/arch/alpha/ev5.cc
/gem5/src/arch/alpha/isa/decoder.isa
/gem5/src/arch/alpha/isa/pal.isa
traceflags.py
/gem5/src/cpu/SConscript
/gem5/src/cpu/base.cc
/gem5/src/cpu/base.hh
/gem5/src/cpu/base_dyn_inst.cc
/gem5/src/cpu/base_dyn_inst.hh
/gem5/src/cpu/cpu_exec_context.cc
/gem5/src/cpu/cpu_exec_context.hh
/gem5/src/cpu/cpu_models.py
/gem5/src/cpu/exec_context.hh
/gem5/src/cpu/exetrace.cc
/gem5/src/cpu/exetrace.hh
/gem5/src/cpu/inst_seq.hh
/gem5/src/cpu/o3/2bit_local_pred.cc
/gem5/src/cpu/o3/2bit_local_pred.hh
/gem5/src/cpu/o3/alpha_cpu.hh
/gem5/src/cpu/o3/alpha_cpu_builder.cc
/gem5/src/cpu/o3/alpha_cpu_impl.hh
/gem5/src/cpu/o3/alpha_dyn_inst.hh
/gem5/src/cpu/o3/alpha_dyn_inst_impl.hh
/gem5/src/cpu/o3/alpha_impl.hh
/gem5/src/cpu/o3/alpha_params.hh
/gem5/src/cpu/o3/bpred_unit.cc
/gem5/src/cpu/o3/bpred_unit.hh
/gem5/src/cpu/o3/bpred_unit_impl.hh
/gem5/src/cpu/o3/btb.cc
/gem5/src/cpu/o3/btb.hh
/gem5/src/cpu/o3/comm.hh
/gem5/src/cpu/o3/commit.cc
/gem5/src/cpu/o3/commit.hh
/gem5/src/cpu/o3/commit_impl.hh
/gem5/src/cpu/o3/cpu.cc
/gem5/src/cpu/o3/cpu.hh
/gem5/src/cpu/o3/cpu_policy.hh
/gem5/src/cpu/o3/decode.cc
/gem5/src/cpu/o3/decode.hh
/gem5/src/cpu/o3/decode_impl.hh
/gem5/src/cpu/o3/fetch.cc
/gem5/src/cpu/o3/fetch.hh
/gem5/src/cpu/o3/fetch_impl.hh
/gem5/src/cpu/o3/free_list.cc
/gem5/src/cpu/o3/free_list.hh
/gem5/src/cpu/o3/iew.cc
/gem5/src/cpu/o3/iew.hh
/gem5/src/cpu/o3/iew_impl.hh
/gem5/src/cpu/o3/inst_queue.cc
/gem5/src/cpu/o3/inst_queue.hh
/gem5/src/cpu/o3/inst_queue_impl.hh
/gem5/src/cpu/o3/mem_dep_unit.cc
/gem5/src/cpu/o3/mem_dep_unit.hh
/gem5/src/cpu/o3/mem_dep_unit_impl.hh
/gem5/src/cpu/o3/ras.cc
/gem5/src/cpu/o3/ras.hh
/gem5/src/cpu/o3/regfile.hh
/gem5/src/cpu/o3/rename.cc
/gem5/src/cpu/o3/rename.hh
/gem5/src/cpu/o3/rename_impl.hh
/gem5/src/cpu/o3/rename_map.cc
/gem5/src/cpu/o3/rename_map.hh
/gem5/src/cpu/o3/rob.hh
/gem5/src/cpu/o3/rob_impl.hh
/gem5/src/cpu/o3/sat_counter.cc
/gem5/src/cpu/o3/sat_counter.hh
/gem5/src/cpu/o3/store_set.cc
/gem5/src/cpu/o3/store_set.hh
/gem5/src/cpu/o3/tournament_pred.cc
/gem5/src/cpu/o3/tournament_pred.hh
/gem5/src/cpu/op_class.hh
/gem5/src/cpu/ozone/cpu.cc
/gem5/src/cpu/ozone/cpu.hh
/gem5/src/cpu/ozone/cpu_impl.hh
/gem5/src/cpu/static_inst.hh
/gem5/src/kern/system_events.cc
/gem5/src/kern/tru64/tru64.hh
/gem5/src/mem/request.hh
/gem5/src/sim/pseudo_inst.cc
2669:f2b336e89d2a 02-Jun-2006 Kevin Lim <ktlim@umich.edu>

Fixes to get compiling to work. This is mainly fixing up some includes; changing functions within the XCs; changing MemReqPtrs to Requests or Packets where appropriate.

Currently the O3 and Ozone CPUs do not work in the new memory system; I still need to fix up the ports to work and handle responses properly. This check-in is so that the merge between m5 and newmem is no longer outstanding.

src/SConscript:
Need to include FU Pool for new CPU model. I'll try to figure out a cleaner way to handle this in the future.
src/base/traceflags.py:
Include new traces flags, fix up merge mess up.
src/cpu/SConscript:
Include the base_dyn_inst.cc as one of othe sources.
Don't compile the Ozone CPU for now.
src/cpu/base.cc:
Remove an extra } from the merge.
src/cpu/base_dyn_inst.cc:
Fixes to make compiling work. Don't instantiate the OzoneCPU for now.
src/cpu/base_dyn_inst.hh:
src/cpu/o3/2bit_local_pred.cc:
src/cpu/o3/alpha_cpu_builder.cc:
src/cpu/o3/alpha_cpu_impl.hh:
src/cpu/o3/alpha_dyn_inst.hh:
src/cpu/o3/alpha_params.hh:
src/cpu/o3/bpred_unit.cc:
src/cpu/o3/btb.hh:
src/cpu/o3/commit.hh:
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/free_list.hh:
src/cpu/o3/iew.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue.hh:
src/cpu/o3/inst_queue_impl.hh:
src/cpu/o3/regfile.hh:
src/cpu/o3/sat_counter.hh:
src/cpu/op_class.hh:
src/cpu/ozone/cpu.hh:
src/cpu/checker/cpu.cc:
src/cpu/checker/cpu.hh:
src/cpu/checker/exec_context.hh:
src/cpu/checker/o3_cpu_builder.cc:
src/cpu/ozone/cpu_impl.hh:
src/mem/request.hh:
src/cpu/o3/fu_pool.hh:
src/cpu/o3/lsq.hh:
src/cpu/o3/lsq_unit.hh:
src/cpu/o3/lsq_unit_impl.hh:
src/cpu/o3/thread_state.hh:
src/cpu/ozone/back_end.hh:
src/cpu/ozone/dyn_inst.cc:
src/cpu/ozone/dyn_inst.hh:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/inorder_back_end.hh:
src/cpu/ozone/lw_back_end.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/ozone/ozone_impl.hh:
src/cpu/ozone/thread_state.hh:
Fixes to get compiling to work.
src/cpu/o3/alpha_cpu.hh:
Fixes to get compiling to work.
Float reg accessors have changed, as well as MemReqPtrs to RequestPtrs.
src/cpu/o3/alpha_dyn_inst_impl.hh:
Fixes to get compiling to work.
Pass in the packet to the completeAcc function.
Fix up syscall function.


/gem5/cpu/activity.cc
/gem5/cpu/activity.hh
/gem5/cpu/checker/cpu.cc
/gem5/cpu/checker/cpu.hh
/gem5/cpu/checker/cpu_builder.cc
/gem5/cpu/checker/exec_context.hh
/gem5/cpu/checker/o3_cpu_builder.cc
/gem5/cpu/o3/dep_graph.hh
/gem5/cpu/o3/fu_pool.cc
/gem5/cpu/o3/fu_pool.hh
/gem5/cpu/o3/lsq.cc
/gem5/cpu/o3/lsq.hh
/gem5/cpu/o3/lsq_impl.hh
/gem5/cpu/o3/lsq_unit.cc
/gem5/cpu/o3/lsq_unit.hh
/gem5/cpu/o3/lsq_unit_impl.hh
/gem5/cpu/o3/scoreboard.cc
/gem5/cpu/o3/scoreboard.hh
/gem5/cpu/o3/thread_state.hh
/gem5/cpu/ozone/back_end.cc
/gem5/cpu/ozone/back_end.hh
/gem5/cpu/ozone/back_end_impl.hh
/gem5/cpu/ozone/cpu_builder.cc
/gem5/cpu/ozone/dyn_inst.cc
/gem5/cpu/ozone/dyn_inst.hh
/gem5/cpu/ozone/dyn_inst_impl.hh
/gem5/cpu/ozone/front_end.cc
/gem5/cpu/ozone/front_end.hh
/gem5/cpu/ozone/front_end_impl.hh
/gem5/cpu/ozone/inorder_back_end.cc
/gem5/cpu/ozone/inorder_back_end.hh
/gem5/cpu/ozone/inorder_back_end_impl.hh
/gem5/cpu/ozone/inst_queue.cc
/gem5/cpu/ozone/inst_queue.hh
/gem5/cpu/ozone/inst_queue_impl.hh
/gem5/cpu/ozone/lsq_unit.cc
/gem5/cpu/ozone/lsq_unit.hh
/gem5/cpu/ozone/lsq_unit_impl.hh
/gem5/cpu/ozone/lw_back_end.cc
/gem5/cpu/ozone/lw_back_end.hh
/gem5/cpu/ozone/lw_back_end_impl.hh
/gem5/cpu/ozone/lw_lsq.cc
/gem5/cpu/ozone/lw_lsq.hh
/gem5/cpu/ozone/lw_lsq_impl.hh
/gem5/cpu/ozone/null_predictor.hh
/gem5/cpu/ozone/ozone_impl.hh
/gem5/cpu/ozone/rename_table.cc
/gem5/cpu/ozone/rename_table.hh
/gem5/cpu/ozone/rename_table_impl.hh
/gem5/cpu/ozone/simple_impl.hh
/gem5/cpu/ozone/simple_params.hh
/gem5/cpu/ozone/thread_state.hh
/gem5/cpu/quiesce_event.cc
/gem5/cpu/quiesce_event.hh
/gem5/cpu/thread_state.hh
/gem5/python/m5/objects/FUPool.py
/gem5/python/m5/objects/OzoneCPU.py
/gem5/python/m5/objects/SimpleOzoneCPU.py
/gem5/src/SConscript
traceflags.py
/gem5/src/cpu/SConscript
/gem5/src/cpu/activity.cc
/gem5/src/cpu/activity.hh
/gem5/src/cpu/base.cc
/gem5/src/cpu/base_dyn_inst.cc
/gem5/src/cpu/base_dyn_inst.hh
/gem5/src/cpu/checker/cpu.cc
/gem5/src/cpu/checker/cpu.hh
/gem5/src/cpu/checker/cpu_builder.cc
/gem5/src/cpu/checker/exec_context.hh
/gem5/src/cpu/checker/o3_cpu_builder.cc
/gem5/src/cpu/o3/2bit_local_pred.cc
/gem5/src/cpu/o3/alpha_cpu.hh
/gem5/src/cpu/o3/alpha_cpu_builder.cc
/gem5/src/cpu/o3/alpha_cpu_impl.hh
/gem5/src/cpu/o3/alpha_dyn_inst.hh
/gem5/src/cpu/o3/alpha_dyn_inst_impl.hh
/gem5/src/cpu/o3/alpha_params.hh
/gem5/src/cpu/o3/bpred_unit.cc
/gem5/src/cpu/o3/btb.hh
/gem5/src/cpu/o3/commit.hh
/gem5/src/cpu/o3/commit_impl.hh
/gem5/src/cpu/o3/cpu.cc
/gem5/src/cpu/o3/cpu.hh
/gem5/src/cpu/o3/dep_graph.hh
/gem5/src/cpu/o3/fetch.hh
/gem5/src/cpu/o3/fetch_impl.hh
/gem5/src/cpu/o3/free_list.hh
/gem5/src/cpu/o3/fu_pool.cc
/gem5/src/cpu/o3/fu_pool.hh
/gem5/src/cpu/o3/iew.hh
/gem5/src/cpu/o3/iew_impl.hh
/gem5/src/cpu/o3/inst_queue.hh
/gem5/src/cpu/o3/inst_queue_impl.hh
/gem5/src/cpu/o3/lsq.cc
/gem5/src/cpu/o3/lsq.hh
/gem5/src/cpu/o3/lsq_impl.hh
/gem5/src/cpu/o3/lsq_unit.cc
/gem5/src/cpu/o3/lsq_unit.hh
/gem5/src/cpu/o3/lsq_unit_impl.hh
/gem5/src/cpu/o3/regfile.hh
/gem5/src/cpu/o3/sat_counter.hh
/gem5/src/cpu/o3/scoreboard.cc
/gem5/src/cpu/o3/scoreboard.hh
/gem5/src/cpu/o3/thread_state.hh
/gem5/src/cpu/op_class.hh
/gem5/src/cpu/ozone/back_end.cc
/gem5/src/cpu/ozone/back_end.hh
/gem5/src/cpu/ozone/back_end_impl.hh
/gem5/src/cpu/ozone/cpu.hh
/gem5/src/cpu/ozone/cpu_builder.cc
/gem5/src/cpu/ozone/cpu_impl.hh
/gem5/src/cpu/ozone/dyn_inst.cc
/gem5/src/cpu/ozone/dyn_inst.hh
/gem5/src/cpu/ozone/dyn_inst_impl.hh
/gem5/src/cpu/ozone/front_end.cc
/gem5/src/cpu/ozone/front_end.hh
/gem5/src/cpu/ozone/front_end_impl.hh
/gem5/src/cpu/ozone/inorder_back_end.cc
/gem5/src/cpu/ozone/inorder_back_end.hh
/gem5/src/cpu/ozone/inorder_back_end_impl.hh
/gem5/src/cpu/ozone/inst_queue.cc
/gem5/src/cpu/ozone/inst_queue.hh
/gem5/src/cpu/ozone/inst_queue_impl.hh
/gem5/src/cpu/ozone/lsq_unit.cc
/gem5/src/cpu/ozone/lsq_unit.hh
/gem5/src/cpu/ozone/lsq_unit_impl.hh
/gem5/src/cpu/ozone/lw_back_end.cc
/gem5/src/cpu/ozone/lw_back_end.hh
/gem5/src/cpu/ozone/lw_back_end_impl.hh
/gem5/src/cpu/ozone/lw_lsq.cc
/gem5/src/cpu/ozone/lw_lsq.hh
/gem5/src/cpu/ozone/lw_lsq_impl.hh
/gem5/src/cpu/ozone/null_predictor.hh
/gem5/src/cpu/ozone/ozone_impl.hh
/gem5/src/cpu/ozone/rename_table.cc
/gem5/src/cpu/ozone/rename_table.hh
/gem5/src/cpu/ozone/rename_table_impl.hh
/gem5/src/cpu/ozone/simple_impl.hh
/gem5/src/cpu/ozone/simple_params.hh
/gem5/src/cpu/ozone/thread_state.hh
/gem5/src/cpu/quiesce_event.cc
/gem5/src/cpu/quiesce_event.hh
/gem5/src/cpu/thread_state.hh
/gem5/src/mem/request.hh
/gem5/src/python/m5/objects/FUPool.py
/gem5/src/python/m5/objects/OzoneCPU.py
/gem5/src/python/m5/objects/SimpleOzoneCPU.py
2665:a124942bacb8 31-May-2006 Ali Saidi <saidi@eecs.umich.edu>

Updated Authors from bk prs info


/gem5/SConstruct
/gem5/docs/stl.hh
/gem5/src/SConscript
/gem5/src/arch/SConscript
/gem5/src/arch/alpha/SConscript
/gem5/src/arch/alpha/aout_machdep.h
/gem5/src/arch/alpha/arguments.cc
/gem5/src/arch/alpha/arguments.hh
/gem5/src/arch/alpha/ev5.cc
/gem5/src/arch/alpha/ev5.hh
/gem5/src/arch/alpha/faults.cc
/gem5/src/arch/alpha/faults.hh
/gem5/src/arch/alpha/freebsd/system.cc
/gem5/src/arch/alpha/freebsd/system.hh
/gem5/src/arch/alpha/isa/branch.isa
/gem5/src/arch/alpha/isa/decoder.isa
/gem5/src/arch/alpha/isa/fp.isa
/gem5/src/arch/alpha/isa/int.isa
/gem5/src/arch/alpha/isa/main.isa
/gem5/src/arch/alpha/isa/mem.isa
/gem5/src/arch/alpha/isa/opcdec.isa
/gem5/src/arch/alpha/isa/pal.isa
/gem5/src/arch/alpha/isa/unimp.isa
/gem5/src/arch/alpha/isa/unknown.isa
/gem5/src/arch/alpha/isa/util.isa
/gem5/src/arch/alpha/isa_traits.hh
/gem5/src/arch/alpha/linux/aligned.hh
/gem5/src/arch/alpha/linux/linux.cc
/gem5/src/arch/alpha/linux/linux.hh
/gem5/src/arch/alpha/linux/process.cc
/gem5/src/arch/alpha/linux/process.hh
/gem5/src/arch/alpha/linux/system.cc
/gem5/src/arch/alpha/linux/system.hh
/gem5/src/arch/alpha/linux/thread_info.hh
/gem5/src/arch/alpha/linux/threadinfo.hh
/gem5/src/arch/alpha/osfpal.cc
/gem5/src/arch/alpha/osfpal.hh
/gem5/src/arch/alpha/process.cc
/gem5/src/arch/alpha/process.hh
/gem5/src/arch/alpha/regfile.hh
/gem5/src/arch/alpha/stacktrace.cc
/gem5/src/arch/alpha/stacktrace.hh
/gem5/src/arch/alpha/system.cc
/gem5/src/arch/alpha/system.hh
/gem5/src/arch/alpha/tlb.cc
/gem5/src/arch/alpha/tlb.hh
/gem5/src/arch/alpha/tru64/process.cc
/gem5/src/arch/alpha/tru64/process.hh
/gem5/src/arch/alpha/tru64/system.cc
/gem5/src/arch/alpha/tru64/system.hh
/gem5/src/arch/alpha/tru64/tru64.cc
/gem5/src/arch/alpha/tru64/tru64.hh
/gem5/src/arch/alpha/types.hh
/gem5/src/arch/alpha/utility.hh
/gem5/src/arch/alpha/vtophys.cc
/gem5/src/arch/alpha/vtophys.hh
/gem5/src/arch/isa_parser.py
/gem5/src/arch/isa_specific.hh
/gem5/src/arch/mips/SConscript
/gem5/src/arch/mips/faults.cc
/gem5/src/arch/mips/faults.hh
/gem5/src/arch/mips/isa/formats/mem.isa
/gem5/src/arch/mips/isa/formats/unimp.isa
/gem5/src/arch/mips/isa/formats/unknown.isa
/gem5/src/arch/mips/isa/main.isa
/gem5/src/arch/mips/isa_traits.cc
/gem5/src/arch/mips/isa_traits.hh
/gem5/src/arch/mips/linux/process.cc
/gem5/src/arch/mips/linux/process.hh
/gem5/src/arch/mips/process.cc
/gem5/src/arch/mips/process.hh
/gem5/src/arch/mips/regfile/float_regfile.hh
/gem5/src/arch/mips/regfile/int_regfile.hh
/gem5/src/arch/mips/regfile/misc_regfile.hh
/gem5/src/arch/mips/regfile/regfile.hh
/gem5/src/arch/mips/stacktrace.hh
/gem5/src/arch/mips/types.hh
/gem5/src/arch/sparc/SConscript
/gem5/src/arch/sparc/faults.cc
/gem5/src/arch/sparc/faults.hh
/gem5/src/arch/sparc/isa/main.isa
/gem5/src/arch/sparc/isa_traits.hh
/gem5/src/arch/sparc/linux/linux.cc
/gem5/src/arch/sparc/linux/linux.hh
/gem5/src/arch/sparc/linux/process.cc
/gem5/src/arch/sparc/linux/process.hh
/gem5/src/arch/sparc/process.cc
/gem5/src/arch/sparc/process.hh
/gem5/src/arch/sparc/regfile.hh
/gem5/src/arch/sparc/solaris/process.cc
/gem5/src/arch/sparc/solaris/process.hh
/gem5/src/arch/sparc/solaris/solaris.cc
/gem5/src/arch/sparc/solaris/solaris.hh
/gem5/src/arch/sparc/stacktrace.hh
/gem5/src/arch/sparc/system.cc
/gem5/src/arch/sparc/system.hh
/gem5/src/arch/sparc/ua2005.cc
/gem5/src/arch/sparc/utility.hh
/gem5/src/arch/sparc/vtophys.cc
/gem5/src/arch/sparc/vtophys.hh
bitfield.hh
callback.hh
chunk_generator.hh
circlebuf.cc
circlebuf.hh
compression/lzss_compression.cc
compression/lzss_compression.hh
compression/null_compression.hh
cprintf.cc
cprintf.hh
cprintf_formats.hh
crc.hh
date.cc
dbl_list.hh
endian.hh
fast_alloc.cc
fast_alloc.hh
fenv.hh
fifo_buffer.cc
fifo_buffer.hh
hashmap.hh
hostinfo.cc
hostinfo.hh
hybrid_pred.cc
hybrid_pred.hh
inet.cc
inet.hh
inifile.cc
inifile.hh
intmath.cc
intmath.hh
loader/aout_object.cc
loader/aout_object.hh
loader/ecoff_object.cc
loader/ecoff_object.hh
loader/elf_object.cc
loader/elf_object.hh
loader/object_file.cc
loader/object_file.hh
loader/symtab.cc
loader/symtab.hh
match.cc
match.hh
misc.cc
misc.hh
mod_num.hh
mysql.cc
mysql.hh
output.cc
output.hh
pollevent.cc
pollevent.hh
predictor.hh
random.cc
random.hh
range.cc
range.hh
refcnt.hh
remote_gdb.cc
remote_gdb.hh
res_list.hh
sat_counter.cc
sat_counter.hh
sched_list.hh
socket.cc
socket.hh
statistics.cc
statistics.hh
stats/events.cc
stats/events.hh
stats/flags.hh
stats/mysql.cc
stats/mysql.hh
stats/mysql_run.hh
stats/output.hh
stats/statdb.cc
stats/statdb.hh
stats/text.cc
stats/text.hh
stats/types.hh
stats/visit.cc
stats/visit.hh
str.cc
str.hh
time.cc
time.hh
timebuf.hh
trace.cc
trace.hh
traceflags.py
userinfo.cc
userinfo.hh
/gem5/src/cpu/SConscript
/gem5/src/cpu/base.cc
/gem5/src/cpu/base.hh
/gem5/src/cpu/base_dyn_inst.cc
/gem5/src/cpu/base_dyn_inst.hh
/gem5/src/cpu/cpu_exec_context.cc
/gem5/src/cpu/cpu_exec_context.hh
/gem5/src/cpu/cpu_models.py
/gem5/src/cpu/exec_context.hh
/gem5/src/cpu/exetrace.cc
/gem5/src/cpu/exetrace.hh
/gem5/src/cpu/inst_seq.hh
/gem5/src/cpu/intr_control.cc
/gem5/src/cpu/intr_control.hh
/gem5/src/cpu/memtest/memtest.cc
/gem5/src/cpu/memtest/memtest.hh
/gem5/src/cpu/o3/2bit_local_pred.cc
/gem5/src/cpu/o3/2bit_local_pred.hh
/gem5/src/cpu/o3/alpha_cpu.cc
/gem5/src/cpu/o3/alpha_cpu.hh
/gem5/src/cpu/o3/alpha_cpu_builder.cc
/gem5/src/cpu/o3/alpha_cpu_impl.hh
/gem5/src/cpu/o3/alpha_dyn_inst.cc
/gem5/src/cpu/o3/alpha_dyn_inst.hh
/gem5/src/cpu/o3/alpha_dyn_inst_impl.hh
/gem5/src/cpu/o3/alpha_impl.hh
/gem5/src/cpu/o3/alpha_params.hh
/gem5/src/cpu/o3/bpred_unit.cc
/gem5/src/cpu/o3/bpred_unit.hh
/gem5/src/cpu/o3/bpred_unit_impl.hh
/gem5/src/cpu/o3/btb.cc
/gem5/src/cpu/o3/btb.hh
/gem5/src/cpu/o3/comm.hh
/gem5/src/cpu/o3/commit.cc
/gem5/src/cpu/o3/commit.hh
/gem5/src/cpu/o3/commit_impl.hh
/gem5/src/cpu/o3/cpu.cc
/gem5/src/cpu/o3/cpu.hh
/gem5/src/cpu/o3/cpu_policy.hh
/gem5/src/cpu/o3/decode.cc
/gem5/src/cpu/o3/decode.hh
/gem5/src/cpu/o3/decode_impl.hh
/gem5/src/cpu/o3/fetch.cc
/gem5/src/cpu/o3/fetch.hh
/gem5/src/cpu/o3/fetch_impl.hh
/gem5/src/cpu/o3/free_list.cc
/gem5/src/cpu/o3/free_list.hh
/gem5/src/cpu/o3/iew.cc
/gem5/src/cpu/o3/iew.hh
/gem5/src/cpu/o3/iew_impl.hh
/gem5/src/cpu/o3/inst_queue.cc
/gem5/src/cpu/o3/inst_queue.hh
/gem5/src/cpu/o3/inst_queue_impl.hh
/gem5/src/cpu/o3/mem_dep_unit.cc
/gem5/src/cpu/o3/mem_dep_unit.hh
/gem5/src/cpu/o3/mem_dep_unit_impl.hh
/gem5/src/cpu/o3/ras.cc
/gem5/src/cpu/o3/ras.hh
/gem5/src/cpu/o3/regfile.hh
/gem5/src/cpu/o3/rename.cc
/gem5/src/cpu/o3/rename.hh
/gem5/src/cpu/o3/rename_impl.hh
/gem5/src/cpu/o3/rename_map.cc
/gem5/src/cpu/o3/rename_map.hh
/gem5/src/cpu/o3/rob.cc
/gem5/src/cpu/o3/rob.hh
/gem5/src/cpu/o3/rob_impl.hh
/gem5/src/cpu/o3/sat_counter.cc
/gem5/src/cpu/o3/sat_counter.hh
/gem5/src/cpu/o3/store_set.cc
/gem5/src/cpu/o3/store_set.hh
/gem5/src/cpu/o3/tournament_pred.cc
/gem5/src/cpu/o3/tournament_pred.hh
/gem5/src/cpu/op_class.cc
/gem5/src/cpu/op_class.hh
/gem5/src/cpu/ozone/cpu.cc
/gem5/src/cpu/ozone/cpu.hh
/gem5/src/cpu/ozone/cpu_impl.hh
/gem5/src/cpu/ozone/ea_list.cc
/gem5/src/cpu/ozone/ea_list.hh
/gem5/src/cpu/pc_event.cc
/gem5/src/cpu/pc_event.hh
/gem5/src/cpu/profile.cc
/gem5/src/cpu/profile.hh
/gem5/src/cpu/simple/atomic.cc
/gem5/src/cpu/simple/atomic.hh
/gem5/src/cpu/simple/base.cc
/gem5/src/cpu/simple/base.hh
/gem5/src/cpu/simple/timing.cc
/gem5/src/cpu/simple/timing.hh
/gem5/src/cpu/smt.hh
/gem5/src/cpu/static_inst.cc
/gem5/src/cpu/static_inst.hh
/gem5/src/cpu/trace/opt_cpu.cc
/gem5/src/cpu/trace/opt_cpu.hh
/gem5/src/cpu/trace/reader/ibm_reader.cc
/gem5/src/cpu/trace/reader/ibm_reader.hh
/gem5/src/cpu/trace/reader/itx_reader.cc
/gem5/src/cpu/trace/reader/itx_reader.hh
/gem5/src/cpu/trace/reader/m5_reader.cc
/gem5/src/cpu/trace/reader/m5_reader.hh
/gem5/src/cpu/trace/reader/mem_trace_reader.cc
/gem5/src/cpu/trace/reader/mem_trace_reader.hh
/gem5/src/cpu/trace/trace_cpu.cc
/gem5/src/cpu/trace/trace_cpu.hh
/gem5/src/dev/alpha_access.h
/gem5/src/dev/alpha_console.cc
/gem5/src/dev/alpha_console.hh
/gem5/src/dev/baddev.cc
/gem5/src/dev/baddev.hh
/gem5/src/dev/disk_image.cc
/gem5/src/dev/disk_image.hh
/gem5/src/dev/etherbus.cc
/gem5/src/dev/etherbus.hh
/gem5/src/dev/etherdump.cc
/gem5/src/dev/etherdump.hh
/gem5/src/dev/etherint.cc
/gem5/src/dev/etherint.hh
/gem5/src/dev/etherlink.cc
/gem5/src/dev/etherlink.hh
/gem5/src/dev/etherpkt.cc
/gem5/src/dev/etherpkt.hh
/gem5/src/dev/ethertap.cc
/gem5/src/dev/ethertap.hh
/gem5/src/dev/ide_ctrl.cc
/gem5/src/dev/ide_ctrl.hh
/gem5/src/dev/ide_disk.cc
/gem5/src/dev/ide_disk.hh
/gem5/src/dev/io_device.cc
/gem5/src/dev/io_device.hh
/gem5/src/dev/isa_fake.cc
/gem5/src/dev/isa_fake.hh
/gem5/src/dev/ns_gige.cc
/gem5/src/dev/ns_gige.hh
/gem5/src/dev/ns_gige_reg.h
/gem5/src/dev/pciconfigall.cc
/gem5/src/dev/pciconfigall.hh
/gem5/src/dev/pcidev.cc
/gem5/src/dev/pcidev.hh
/gem5/src/dev/pcireg.h
/gem5/src/dev/pitreg.h
/gem5/src/dev/pktfifo.cc
/gem5/src/dev/pktfifo.hh
/gem5/src/dev/platform.cc
/gem5/src/dev/platform.hh
/gem5/src/dev/rtcreg.h
/gem5/src/dev/simconsole.cc
/gem5/src/dev/simconsole.hh
/gem5/src/dev/simple_disk.cc
/gem5/src/dev/simple_disk.hh
/gem5/src/dev/sinic.cc
/gem5/src/dev/sinic.hh
/gem5/src/dev/sinicreg.hh
/gem5/src/dev/tsunami.cc
/gem5/src/dev/tsunami.hh
/gem5/src/dev/tsunami_cchip.cc
/gem5/src/dev/tsunami_cchip.hh
/gem5/src/dev/tsunami_io.cc
/gem5/src/dev/tsunami_io.hh
/gem5/src/dev/tsunami_pchip.cc
/gem5/src/dev/tsunami_pchip.hh
/gem5/src/dev/tsunamireg.h
/gem5/src/dev/uart.cc
/gem5/src/dev/uart.hh
/gem5/src/dev/uart8250.cc
/gem5/src/dev/uart8250.hh
/gem5/src/kern/kernel_stats.cc
/gem5/src/kern/kernel_stats.hh
/gem5/src/kern/linux/events.cc
/gem5/src/kern/linux/events.hh
/gem5/src/kern/linux/linux.hh
/gem5/src/kern/linux/linux_syscalls.cc
/gem5/src/kern/linux/linux_syscalls.hh
/gem5/src/kern/linux/printk.cc
/gem5/src/kern/linux/printk.hh
/gem5/src/kern/linux/sched.hh
/gem5/src/kern/solaris/solaris.hh
/gem5/src/kern/system_events.cc
/gem5/src/kern/system_events.hh
/gem5/src/kern/tru64/dump_mbuf.cc
/gem5/src/kern/tru64/dump_mbuf.hh
/gem5/src/kern/tru64/mbuf.hh
/gem5/src/kern/tru64/printf.cc
/gem5/src/kern/tru64/printf.hh
/gem5/src/kern/tru64/tru64.hh
/gem5/src/kern/tru64/tru64_events.cc
/gem5/src/kern/tru64/tru64_events.hh
/gem5/src/kern/tru64/tru64_syscalls.cc
/gem5/src/kern/tru64/tru64_syscalls.hh
/gem5/src/mem/bridge.cc
/gem5/src/mem/bridge.hh
/gem5/src/mem/bus.cc
/gem5/src/mem/bus.hh
/gem5/src/mem/cache/prefetch/tagged_prefetcher_impl.hh
/gem5/src/mem/config/prefetch.hh
/gem5/src/mem/mem_object.cc
/gem5/src/mem/mem_object.hh
/gem5/src/mem/packet.cc
/gem5/src/mem/packet.hh
/gem5/src/mem/page_table.cc
/gem5/src/mem/page_table.hh
/gem5/src/mem/physical.cc
/gem5/src/mem/physical.hh
/gem5/src/mem/port.cc
/gem5/src/mem/port.hh
/gem5/src/mem/request.hh
/gem5/src/mem/translating_port.cc
/gem5/src/mem/translating_port.hh
/gem5/src/mem/vport.cc
/gem5/src/mem/vport.hh
/gem5/src/python/SConscript
/gem5/src/python/m5/__init__.py
/gem5/src/python/m5/config.py
/gem5/src/python/m5/convert.py
/gem5/src/python/m5/multidict.py
/gem5/src/python/m5/smartdict.py
/gem5/src/sim/async.hh
/gem5/src/sim/builder.cc
/gem5/src/sim/builder.hh
/gem5/src/sim/byteswap.hh
/gem5/src/sim/debug.cc
/gem5/src/sim/debug.hh
/gem5/src/sim/eventq.cc
/gem5/src/sim/eventq.hh
/gem5/src/sim/faults.cc
/gem5/src/sim/faults.hh
/gem5/src/sim/host.hh
/gem5/src/sim/main.cc
/gem5/src/sim/param.cc
/gem5/src/sim/param.hh
/gem5/src/sim/process.cc
/gem5/src/sim/process.hh
/gem5/src/sim/pseudo_inst.cc
/gem5/src/sim/pseudo_inst.hh
/gem5/src/sim/root.cc
/gem5/src/sim/serialize.cc
/gem5/src/sim/serialize.hh
/gem5/src/sim/sim_events.cc
/gem5/src/sim/sim_events.hh
/gem5/src/sim/sim_exit.hh
/gem5/src/sim/sim_object.cc
/gem5/src/sim/sim_object.hh
/gem5/src/sim/startup.cc
/gem5/src/sim/startup.hh
/gem5/src/sim/stat_control.cc
/gem5/src/sim/stat_control.hh
/gem5/src/sim/stats.hh
/gem5/src/sim/syscall_emul.cc
/gem5/src/sim/syscall_emul.hh
/gem5/src/sim/system.hh
/gem5/src/sim/vptr.hh
/gem5/src/unittest/bitvectest.cc
/gem5/src/unittest/circletest.cc
/gem5/src/unittest/cprintftest.cc
/gem5/src/unittest/genini.py
/gem5/src/unittest/initest.cc
/gem5/src/unittest/lru_test.cc
/gem5/src/unittest/nmtest.cc
/gem5/src/unittest/offtest.cc
/gem5/src/unittest/paramtest.cc
/gem5/src/unittest/rangetest.cc
/gem5/src/unittest/sized_test.cc
/gem5/src/unittest/stattest.cc
/gem5/src/unittest/strnumtest.cc
/gem5/src/unittest/symtest.cc
/gem5/src/unittest/tokentest.cc
/gem5/src/unittest/tracetest.cc
/gem5/util/ccdrv/devtime.c
/gem5/util/m5/Makefile
/gem5/util/m5/m5.c
/gem5/util/m5/m5op.S
/gem5/util/m5/m5op.h
/gem5/util/oprofile-top.py
/gem5/util/qdo
/gem5/util/rundiff
/gem5/util/stats/db.py
/gem5/util/stats/dbinit.py
/gem5/util/stats/display.py
/gem5/util/stats/info.py
/gem5/util/stats/orderdict.py
/gem5/util/stats/print.py
/gem5/util/stats/profile.py
/gem5/util/stats/stats.py
/gem5/util/tap/tap.cc
2654:9559cfa91b9d 30-May-2006 Kevin Lim <ktlim@umich.edu>

Merge ktlim@zizzer:/bk/m5
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem

SConstruct:
src/SConscript:
src/arch/SConscript:
src/arch/alpha/faults.cc:
src/arch/alpha/tlb.cc:
src/base/traceflags.py:
src/cpu/SConscript:
src/cpu/base.cc:
src/cpu/base.hh:
src/cpu/base_dyn_inst.cc:
src/cpu/cpu_exec_context.cc:
src/cpu/cpu_exec_context.hh:
src/cpu/exec_context.hh:
src/cpu/o3/alpha_cpu.hh:
src/cpu/o3/alpha_cpu_impl.hh:
src/cpu/o3/alpha_dyn_inst.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/regfile.hh:
src/cpu/ozone/cpu.hh:
src/cpu/simple/base.cc:
src/cpu/base_dyn_inst.hh:
src/cpu/o3/2bit_local_pred.cc:
src/cpu/o3/2bit_local_pred.hh:
src/cpu/o3/alpha_cpu.cc:
src/cpu/o3/alpha_cpu_builder.cc:
src/cpu/o3/alpha_dyn_inst.cc:
src/cpu/o3/alpha_dyn_inst_impl.hh:
src/cpu/o3/alpha_impl.hh:
src/cpu/o3/alpha_params.hh:
src/cpu/o3/bpred_unit.cc:
src/cpu/o3/bpred_unit.hh:
src/cpu/o3/bpred_unit_impl.hh:
src/cpu/o3/btb.cc:
src/cpu/o3/btb.hh:
src/cpu/o3/comm.hh:
src/cpu/o3/commit.cc:
src/cpu/o3/commit.hh:
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu_policy.hh:
src/cpu/o3/decode.cc:
src/cpu/o3/decode.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch.cc:
src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/free_list.cc:
src/cpu/o3/free_list.hh:
src/cpu/o3/iew.cc:
src/cpu/o3/iew.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue.cc:
src/cpu/o3/inst_queue.hh:
src/cpu/o3/inst_queue_impl.hh:
src/cpu/o3/mem_dep_unit.cc:
src/cpu/o3/mem_dep_unit.hh:
src/cpu/o3/mem_dep_unit_impl.hh:
src/cpu/o3/ras.cc:
src/cpu/o3/ras.hh:
src/cpu/o3/rename.cc:
src/cpu/o3/rename.hh:
src/cpu/o3/rename_impl.hh:
src/cpu/o3/rename_map.cc:
src/cpu/o3/rename_map.hh:
src/cpu/o3/rob.cc:
src/cpu/o3/rob.hh:
src/cpu/o3/rob_impl.hh:
src/cpu/o3/sat_counter.cc:
src/cpu/o3/sat_counter.hh:
src/cpu/o3/store_set.cc:
src/cpu/o3/store_set.hh:
src/cpu/o3/tournament_pred.cc:
src/cpu/o3/tournament_pred.hh:
Hand merges.


/gem5/SConstruct
/gem5/src/SConscript
/gem5/src/arch/alpha/ev5.cc
/gem5/src/arch/alpha/isa/decoder.isa
/gem5/src/arch/alpha/isa/pal.isa
traceflags.py
/gem5/src/cpu/SConscript
/gem5/src/cpu/base.cc
/gem5/src/cpu/base.hh
/gem5/src/cpu/base_dyn_inst.cc
/gem5/src/cpu/base_dyn_inst.hh
/gem5/src/cpu/cpu_exec_context.cc
/gem5/src/cpu/cpu_exec_context.hh
/gem5/src/cpu/cpu_models.py
/gem5/src/cpu/exec_context.hh
/gem5/src/cpu/exetrace.cc
/gem5/src/cpu/exetrace.hh
/gem5/src/cpu/inst_seq.hh
/gem5/src/cpu/o3/2bit_local_pred.cc
/gem5/src/cpu/o3/2bit_local_pred.hh
/gem5/src/cpu/o3/alpha_cpu.hh
/gem5/src/cpu/o3/alpha_cpu_builder.cc
/gem5/src/cpu/o3/alpha_cpu_impl.hh
/gem5/src/cpu/o3/alpha_dyn_inst.hh
/gem5/src/cpu/o3/alpha_dyn_inst_impl.hh
/gem5/src/cpu/o3/alpha_impl.hh
/gem5/src/cpu/o3/alpha_params.hh
/gem5/src/cpu/o3/bpred_unit.cc
/gem5/src/cpu/o3/bpred_unit.hh
/gem5/src/cpu/o3/bpred_unit_impl.hh
/gem5/src/cpu/o3/btb.cc
/gem5/src/cpu/o3/btb.hh
/gem5/src/cpu/o3/comm.hh
/gem5/src/cpu/o3/commit.cc
/gem5/src/cpu/o3/commit.hh
/gem5/src/cpu/o3/commit_impl.hh
/gem5/src/cpu/o3/cpu.cc
/gem5/src/cpu/o3/cpu.hh
/gem5/src/cpu/o3/cpu_policy.hh
/gem5/src/cpu/o3/decode.cc
/gem5/src/cpu/o3/decode.hh
/gem5/src/cpu/o3/decode_impl.hh
/gem5/src/cpu/o3/fetch.cc
/gem5/src/cpu/o3/fetch.hh
/gem5/src/cpu/o3/fetch_impl.hh
/gem5/src/cpu/o3/free_list.cc
/gem5/src/cpu/o3/free_list.hh
/gem5/src/cpu/o3/iew.cc
/gem5/src/cpu/o3/iew.hh
/gem5/src/cpu/o3/iew_impl.hh
/gem5/src/cpu/o3/inst_queue.cc
/gem5/src/cpu/o3/inst_queue.hh
/gem5/src/cpu/o3/inst_queue_impl.hh
/gem5/src/cpu/o3/mem_dep_unit.cc
/gem5/src/cpu/o3/mem_dep_unit.hh
/gem5/src/cpu/o3/mem_dep_unit_impl.hh
/gem5/src/cpu/o3/ras.cc
/gem5/src/cpu/o3/ras.hh
/gem5/src/cpu/o3/regfile.hh
/gem5/src/cpu/o3/rename.cc
/gem5/src/cpu/o3/rename.hh
/gem5/src/cpu/o3/rename_impl.hh
/gem5/src/cpu/o3/rename_map.cc
/gem5/src/cpu/o3/rename_map.hh
/gem5/src/cpu/o3/rob.hh
/gem5/src/cpu/o3/rob_impl.hh
/gem5/src/cpu/o3/sat_counter.cc
/gem5/src/cpu/o3/sat_counter.hh
/gem5/src/cpu/o3/store_set.cc
/gem5/src/cpu/o3/store_set.hh
/gem5/src/cpu/o3/tournament_pred.cc
/gem5/src/cpu/o3/tournament_pred.hh
/gem5/src/cpu/ozone/cpu.cc
/gem5/src/cpu/ozone/cpu.hh
/gem5/src/cpu/ozone/cpu_impl.hh
/gem5/src/cpu/static_inst.hh
/gem5/src/kern/system_events.cc
/gem5/src/kern/tru64/tru64.hh
/gem5/src/python/m5/objects/AlphaFullCPU.py
/gem5/src/sim/pseudo_inst.cc
2650:a012c079984a 29-May-2006 Ali Saidi <saidi@eecs.umich.edu>

split off fullsystem and se iprs into two functions to remove lots of #ifs
setup all initialization stuff for UA2005
Setup fullsys build options
Start to make fullsystem compile

src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
RCS to BitKeeper
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
Add support for doing virtual to physical translation using the in-memory
page table
src/arch/sparc/vtophys.cc:
a tad bit of error checking
src/arch/sparc/vtophys.hh:
Cleanup of full-system global variables, primarily in simple_cpu.cc,
to allow multi-system simulations. (Multiple systems not yet yested
though.) Also changes to build sim_smt in full-system mode (though
with only SimpleCPU and not the full timing CPU for now).

Still to do: minimize changes in SimpleCPU code between full-system
and application modes... way too many ifdefs there. Much of the
full-system stuff moved into SimpleCPU should be put in a new System
object to allow multiprocessor simulations.

Converted last remaining modules from C to C++ (mostly in /old).
Renamed all .c files to .cc and a few .h files to .hh.

Renamed architecture-specific files in arch/$TARGET from
$TARGET.{cc,hh,def} to machine.{cc,hh,def} to get rid of pointless
intermediate files in object directory. Split exo-specific
definitions out of machine.hh into machine_exo.h.

Specifics:

In machine.def, null resource descriptors must be FUClamd_NA (and not
NA) to pass C++ type checking.

Enhanced error checking/reporting in bas
src/arch/sparc/vtophys.cc:
- Get rid of my String class, the Vector class, the bitvector class, and my
doubly linked list class.
- Convert tokenize, to_number (formerly StringToNumber) and eat_white to
function on stl strings.
- Change most cases of char * and const char * to string, or const string &
- Some formatting and style nits, but not too many.
src/arch/sparc/vtophys.cc:
simplify
src/arch/sparc/vtophys.cc:

Renamed SimpleCPU::(read|write)_(byte|half|word|qword) to just read &
write, overloaded on the type of the 'data' argument. Merged the
full-system and non-full-system implementations of these eight
original functions into two common template functions.

To support this, also renamed (read|write)[1248] on memory_object and
derivatives to just read & write, again overloaded on the type of the
'data' argument. Many of these functions could now be condensed into
a few template functions (though with a level of indirection so that
the interface can remain virtual). I did not do that though.
src/arch/sparc/vtophys.cc:
First pass at compiling with gcc 3.x. Lots of "std::" in header files,
"using namespace std" in source files. (Note policy of not putting "using"
statements in headers or before includes in sources.)

Still not able to compile with gcc 3.2.
Errors:
- Can't create an ifstream from a file descriptor anymore (breaks IniFile).
- "`class MSHR::MSHRegister' is private" errors in mshr.cc and prefetch_cache.cc:
not clear why since it's in the public part of the class declaration.
- cpu.cc:879: can't match a reference and 0 (specifically "no match for `bool ?
SimObjectParam<PipeTrace*>& : int' operator")
- pipetrace.cc: "invalid conversion from `int' to `std::_Ios_Fmtflags'"
Warnings:
- strstream now deprecated... needs some rewriting in sat_counter.hh
and hybrid_pred.hh (need to get all that code out of the headers anyway)
- trace.hh macro problem: cpp now says 'pasting "::" and "Event" does not
give a valid preprocessing token'
- major "implicit typename" issues in base/sized.hh
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
Implement some interval statistics for full system mode.
Create a callpal function that is called when a callpal occurs so it's easier
to manipulate the statics.
Rework the vtophys stuff to make it a bit cleaner.
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
Get rid of almost all old-style object names. This commit is equivalent
to running the following script on the current head:

#! /bin/sh

find \( -name '*.cc' -o -name '*.hh' \) -exec perl -pi -e '\
s/\bmemory_object\b(?!\.hh)/FunctionalMemory/g;\
s/\bvirtual_memory\b(?!\.hh)/VirtualMemory/g;\
s/\bmain_memory\b(?!\.hh)/MainMemory/g;\
s/\bphysical_memory\b(?!\.hh)/PhysicalMemory/g;\
s/\bspec_memory\b(?!\.hh)/SpeculativeMemory/g;\
s/\bMemObj\b(?!\.hh)/TimingMemObj/g;\
s/\bmemory_translation\b(?!\.hh)/AddressTranslator/g;\
s/\balpha_tlb\b(?!\.hh)/AlphaTlb/g;\
s/\balpha_itb\b(?!\.hh)/AlphaItb/g;\
s/\balpha_dtb\b(?!\.hh)/AlphaDtb/g;\
s/\bmemory_controller\b(?!\.hh)/MemoryController/g;\
s/\bstorebuffer_t\b(?!\.hh)/StoreBuffer/g;\
s/\bstorebuffer_entry_t\b(?!\.hh)/StoreBufferEntry/g;\
s/\bcreate_vector_t\b(?!\.hh)/CreateVector/g;\
s/\bcv_spec_state\b(?!\.hh)/CreateVecSpecState/g;\
s/\bspec_state_list\b(?!\.hh)/SpecStateList/g;\
s/\bdyn_inst_t\b(?!\.hh)/DynInst/g;' {} \;
src/arch/sparc/vtophys.cc:
since cprintf properly deals with 64-bit types, stop using FMT* as much as
possible
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
Change byte_t etc. to C99 standard int8_t etc.
Other than old/host.h, all other changes were produced by this script:

#! /bin/sh

find \( -name '*.cc' -o -name '*.hh' -o -name '*.c' -o -name '*.h' -o -name 'machine.def' \) -exec perl -pi -e '\
s/\bbyte_t\b(?!\.hh)/uint8_t/g;\
s/\bsbyte_t\b(?!\.hh)/int8_t/g;\
s/\bhalf_t\b(?!\.hh)/uint16_t/g;\
s/\bshalf_t\b(?!\.hh)/int16_t/g;\
s/\bword_t\b(?!\.hh)/uint32_t/g;\
s/\bsword_t\b(?!\.hh)/int32_t/g;\
s/\bqword_t\b(?!\.hh)/uint64_t/g;\
s/\bsqword_t\b(?!\.hh)/int64_t/g;\
s/\bbool_t\b(?!\.hh)/bool/g;\
s/\bdfloat_t\b(?!\.hh)/double/g;\
s/\bsfloat_t\b(?!\.hh)/float/g;' {} \;
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
Add CVS Id tags
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
Massive renaming to (almost) eliminate all md_* and MD_* names
in preparation for total exorcism of machine.def.

Most of the changes in this commit were performed with the
following perl script (perl -pi <script> <files>). A small
amount of manual fixup was needed to (mostly getting rid of
the Addr typedefs in the various memory objects now that
the former md_addr_t has that name).

# rename machine-dependent types and constants (will be moving into ISA traits object)
s/md_addr_t/Addr/g;
s/md_intreg_t/IntReg/g;
s/md_gpr_t/IntRegFile/g;
s/md_fpreg_t/FloatReg/g;
s/md_fpr_t/FloatRegFile/g;
s/md_ctrlreg_t/MiscReg/g;
s/md_ctrl_t/MiscRegFile/g;
s/md_ipr_t/InternalProcReg/g;
s/md_anyreg_t/AnyReg/g;
s/md_inst_t/MachInst/g;
s/regs_t/RegFile/g;
# manually fix declaration in old/regs.h and a few forward decls
s/struct RegFile/RegFile/g;
s/MD_NUM_IREGS/NumIntRegs/g;
s/MD_NUM_FREGS/NumFloatRegs/g;
s/MD_NUM_CREGS/NumMiscRegs/g;
s/MD_IPR_NUM/NumInternalProcRegs/g;
s/MD_TOTAL_REGS/TotalNumRegs/g;
s/MD_REG_ZERO/ZeroReg/g;
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
New ISA description system. No more machine.def!
Instructions are now decoded into StaticInst objects, and all static
instruction properties (including execution behavior) are associated
with those objects. Extended documentation in progress.
Currently supports Alpha only; PISA will not compile.
Use END_OF_MACHINE_DOT_DEF tag to extract previous version.
src/arch/sparc/vtophys.cc:
get rid of MD_IPR_foo and call it IPR_foo
add some comments to describe what the various PALtemp registers do
formatting
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
license
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
a little style
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
Add attribution to license.
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
Make include paths explicit.
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
CopyData and CopyString moved from kernel.cc to vtophys.cc
kernel.cc and kernel.hh moved to kern/tru64
src/arch/sparc/vtophys.hh:
Include isa_traits.hh for Addr
src/arch/sparc/vtophys.cc:
formatting fixes
src/arch/sparc/vtophys.cc:
fix up vtophys to deal with translations if there
is no ptbr, and to deal with PAL addresses
add ptomem which is just a wrapper for dma_addr
src/arch/sparc/vtophys.hh:
add ptomem which is a wrapper for dma_addr with the
same usage as vtomem
src/arch/sparc/vtophys.cc:
Fix to remote debugger while in PAL code
src/arch/sparc/vtophys.cc:
Remote an old hack that is now unnecessary
src/arch/sparc/vtophys.cc:
Removed buggy code that tries to fix PAL addresses (may cause problems
while trying to debug in PAL code, but that should do this fix outside
of vtophys)
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
Updated Copyright
src/arch/sparc/vtophys.cc:
added back some code andrew removed and couldn't remember why.
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
rename CopyData to CopyOut and implement CopyIn to copy data
from the simulator into the simulatee
src/arch/sparc/vtophys.cc:
fixed a bad merge from linux<->tru64
src/arch/sparc/vtophys.cc:
Check max address pal can be at so we don't do the wrong conversion
if gdb asks for an unaligned access.
src/arch/sparc/vtophys.cc:
PGOFSET -> ALPHA_PGOFSET to avoid include file problems
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
in the arch/alpha directory we should use arch/alpha, not
targetarch. sort includes while we're here.
src/arch/sparc/vtophys.cc:
use new constants, functions and structs to clean up the
vtophys code.
src/arch/sparc/vtophys.hh:
Clean up a little bit and make the protypes match new changes.
src/arch/sparc/vtophys.cc:
deal with isa addition
src/arch/sparc/vtophys.cc:
shuffle files around for new directory structure
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
Remove RCS Id string
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
Update copyright dates and author list
src/arch/sparc/vtophys.cc:
Added a using directive for AlphaISA
src/arch/sparc/vtophys.hh:
Added the AlphaISA namespace specifier where needed
src/arch/sparc/vtophys.hh:
Made Addr a global type
src/arch/sparc/vtophys.cc:
Change access to the IPR to go through the XC.
src/arch/sparc/vtophys.cc:
Avoid directly accessing objects within the XC.
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
fixed for new memory system
put in namespace AlphaISA
src/arch/alpha/vtophys.cc:
src/arch/alpha/vtophys.hh:
Remove authors from copyright.
src/arch/sparc/vtophys.cc:
bk cp alpha/vtophys.cc sparc/vtophys.cc
src/arch/sparc/vtophys.hh:
bk cp alpha/vtophys.hh sparc/vtophys.hh
src/arch/sparc/SConscript:
remove fullsystem files that don't exist
src/arch/sparc/isa_traits.hh:
split off fullsystem and se iprs into two functions to remove lots of #ifs
src/arch/sparc/regfile.hh:
split off fullsystem and se iprs into two functions to remove lots of #ifs
setup all initialization stuff for UA2005
src/arch/sparc/system.cc:
src/arch/sparc/system.hh:
Add system level tick storage to make stick be syncronized across multiple processors
src/arch/sparc/vtophys.hh:
start to create a vtophys for Sparc
src/base/loader/symtab.hh:
Addr is defined in sim/host.hh

2642:c162e0359b49 26-May-2006 Steve Reinhardt <stever@eecs.umich.edu>

Add a little more tracing support for Bus/Port stuff.

src/base/traceflags.py:
Sort flags so you can find things.
Add BusAddrRanges flag for tracking RangeChange events
separately from general bus activity.
src/mem/bus.cc:
Add BusAddrRanges flag for tracking RangeChange events
separately from general bus activity.
src/mem/port.cc:
src/mem/port.hh:
Print Config trace message when peers are set up.

2634:db0b1133abd5 22-May-2006 Steve Reinhardt <stever@eecs.umich.edu>

Clean up libelf handling.

SConstruct:
Clean up libelf handling. Required better handling of
per-build-root stuff in general (though libelf is the
only thing in that category currently).
src/SConscript:
No libelf-specific stuff in here anymore.
src/base/loader/elf_object.cc:
Just need to include gelf.h... it includes libelf.h.

2632:1bb2f91485ea 22-May-2006 Steve Reinhardt <stever@eecs.umich.edu>

New directory structure:
- simulator source now in 'src' subdirectory
- imported files from 'ext' repository
- support building in arbitrary places, including
outside of the source tree. See comment at top
of SConstruct file for more details.
Regression tests are temporarily disabled; that
syetem needs more extensive revisions.

SConstruct:
Update for new directory structure.
Modify to support build trees that are not subdirectories
of the source tree. See comment at top of file for
more details.
Regression tests are temporarily disabled.
src/arch/SConscript:
src/arch/isa_parser.py:
src/python/SConscript:
Update for new directory structure.


/gem5/Doxyfile
/gem5/SConscript
/gem5/SConstruct
/gem5/arch/SConscript
/gem5/arch/alpha/SConscript
/gem5/arch/alpha/aout_machdep.h
/gem5/arch/alpha/arguments.cc
/gem5/arch/alpha/arguments.hh
/gem5/arch/alpha/ecoff_machdep.h
/gem5/arch/alpha/ev5.cc
/gem5/arch/alpha/ev5.hh
/gem5/arch/alpha/faults.cc
/gem5/arch/alpha/faults.hh
/gem5/arch/alpha/freebsd/system.cc
/gem5/arch/alpha/freebsd/system.hh
/gem5/arch/alpha/isa/branch.isa
/gem5/arch/alpha/isa/decoder.isa
/gem5/arch/alpha/isa/fp.isa
/gem5/arch/alpha/isa/int.isa
/gem5/arch/alpha/isa/main.isa
/gem5/arch/alpha/isa/mem.isa
/gem5/arch/alpha/isa/opcdec.isa
/gem5/arch/alpha/isa/pal.isa
/gem5/arch/alpha/isa/unimp.isa
/gem5/arch/alpha/isa/unknown.isa
/gem5/arch/alpha/isa/util.isa
/gem5/arch/alpha/isa_traits.hh
/gem5/arch/alpha/linux/aligned.hh
/gem5/arch/alpha/linux/hwrpb.hh
/gem5/arch/alpha/linux/linux.cc
/gem5/arch/alpha/linux/linux.hh
/gem5/arch/alpha/linux/process.cc
/gem5/arch/alpha/linux/process.hh
/gem5/arch/alpha/linux/system.cc
/gem5/arch/alpha/linux/system.hh
/gem5/arch/alpha/linux/thread_info.hh
/gem5/arch/alpha/linux/threadinfo.hh
/gem5/arch/alpha/osfpal.cc
/gem5/arch/alpha/osfpal.hh
/gem5/arch/alpha/process.cc
/gem5/arch/alpha/process.hh
/gem5/arch/alpha/regfile.hh
/gem5/arch/alpha/stacktrace.cc
/gem5/arch/alpha/stacktrace.hh
/gem5/arch/alpha/system.cc
/gem5/arch/alpha/system.hh
/gem5/arch/alpha/tlb.cc
/gem5/arch/alpha/tlb.hh
/gem5/arch/alpha/tru64/process.cc
/gem5/arch/alpha/tru64/process.hh
/gem5/arch/alpha/tru64/system.cc
/gem5/arch/alpha/tru64/system.hh
/gem5/arch/alpha/tru64/tru64.cc
/gem5/arch/alpha/tru64/tru64.hh
/gem5/arch/alpha/types.hh
/gem5/arch/alpha/utility.hh
/gem5/arch/alpha/vtophys.cc
/gem5/arch/alpha/vtophys.hh
/gem5/arch/isa_parser.py
/gem5/arch/isa_specific.hh
/gem5/arch/mips/SConscript
/gem5/arch/mips/faults.cc
/gem5/arch/mips/faults.hh
/gem5/arch/mips/isa/base.isa
/gem5/arch/mips/isa/bitfields.isa
/gem5/arch/mips/isa/decoder.isa
/gem5/arch/mips/isa/formats/basic.isa
/gem5/arch/mips/isa/formats/branch.isa
/gem5/arch/mips/isa/formats/formats.isa
/gem5/arch/mips/isa/formats/fp.isa
/gem5/arch/mips/isa/formats/int.isa
/gem5/arch/mips/isa/formats/mem.isa
/gem5/arch/mips/isa/formats/noop.isa
/gem5/arch/mips/isa/formats/tlbop.isa
/gem5/arch/mips/isa/formats/trap.isa
/gem5/arch/mips/isa/formats/unimp.isa
/gem5/arch/mips/isa/formats/unknown.isa
/gem5/arch/mips/isa/formats/util.isa
/gem5/arch/mips/isa/includes.isa
/gem5/arch/mips/isa/main.isa
/gem5/arch/mips/isa/operands.isa
/gem5/arch/mips/isa_traits.cc
/gem5/arch/mips/isa_traits.hh
/gem5/arch/mips/linux/linux.cc
/gem5/arch/mips/linux/linux.hh
/gem5/arch/mips/linux/process.cc
/gem5/arch/mips/linux/process.hh
/gem5/arch/mips/process.cc
/gem5/arch/mips/process.hh
/gem5/arch/mips/regfile/float_regfile.hh
/gem5/arch/mips/regfile/int_regfile.hh
/gem5/arch/mips/regfile/misc_regfile.hh
/gem5/arch/mips/regfile/regfile.hh
/gem5/arch/mips/stacktrace.hh
/gem5/arch/mips/types.hh
/gem5/arch/mips/utility.hh
/gem5/arch/sparc/SConscript
/gem5/arch/sparc/faults.cc
/gem5/arch/sparc/faults.hh
/gem5/arch/sparc/isa/base.isa
/gem5/arch/sparc/isa/bitfields.isa
/gem5/arch/sparc/isa/decoder.isa
/gem5/arch/sparc/isa/formats.isa
/gem5/arch/sparc/isa/formats/basic.isa
/gem5/arch/sparc/isa/formats/branch.isa
/gem5/arch/sparc/isa/formats/integerop.isa
/gem5/arch/sparc/isa/formats/mem.isa
/gem5/arch/sparc/isa/formats/nop.isa
/gem5/arch/sparc/isa/formats/priv.isa
/gem5/arch/sparc/isa/formats/trap.isa
/gem5/arch/sparc/isa/formats/unknown.isa
/gem5/arch/sparc/isa/includes.isa
/gem5/arch/sparc/isa/main.isa
/gem5/arch/sparc/isa/operands.isa
/gem5/arch/sparc/isa_traits.hh
/gem5/arch/sparc/linux/linux.cc
/gem5/arch/sparc/linux/linux.hh
/gem5/arch/sparc/linux/process.cc
/gem5/arch/sparc/linux/process.hh
/gem5/arch/sparc/process.cc
/gem5/arch/sparc/process.hh
/gem5/arch/sparc/regfile.hh
/gem5/arch/sparc/solaris/process.cc
/gem5/arch/sparc/solaris/process.hh
/gem5/arch/sparc/solaris/solaris.cc
/gem5/arch/sparc/solaris/solaris.hh
/gem5/arch/sparc/stacktrace.hh
/gem5/arch/sparc/system.cc
/gem5/arch/sparc/system.hh
/gem5/arch/sparc/utility.hh
/gem5/base/bitfield.hh
/gem5/base/callback.hh
/gem5/base/chunk_generator.hh
/gem5/base/circlebuf.cc
/gem5/base/circlebuf.hh
/gem5/base/compression/lzss_compression.cc
/gem5/base/compression/lzss_compression.hh
/gem5/base/compression/null_compression.hh
/gem5/base/cprintf.cc
/gem5/base/cprintf.hh
/gem5/base/cprintf_formats.hh
/gem5/base/crc.cc
/gem5/base/crc.hh
/gem5/base/date.cc
/gem5/base/dbl_list.hh
/gem5/base/endian.hh
/gem5/base/fast_alloc.cc
/gem5/base/fast_alloc.hh
/gem5/base/fenv.hh
/gem5/base/fifo_buffer.cc
/gem5/base/fifo_buffer.hh
/gem5/base/hashmap.hh
/gem5/base/hostinfo.cc
/gem5/base/hostinfo.hh
/gem5/base/hybrid_pred.cc
/gem5/base/hybrid_pred.hh
/gem5/base/inet.cc
/gem5/base/inet.hh
/gem5/base/inifile.cc
/gem5/base/inifile.hh
/gem5/base/intmath.cc
/gem5/base/intmath.hh
/gem5/base/kgdb.h
/gem5/base/loader/aout_object.cc
/gem5/base/loader/aout_object.hh
/gem5/base/loader/coff_sym.h
/gem5/base/loader/coff_symconst.h
/gem5/base/loader/ecoff_object.cc
/gem5/base/loader/ecoff_object.hh
/gem5/base/loader/elf_object.cc
/gem5/base/loader/elf_object.hh
/gem5/base/loader/exec_aout.h
/gem5/base/loader/exec_ecoff.h
/gem5/base/loader/object_file.cc
/gem5/base/loader/object_file.hh
/gem5/base/loader/symtab.cc
/gem5/base/loader/symtab.hh
/gem5/base/match.cc
/gem5/base/match.hh
/gem5/base/misc.cc
/gem5/base/misc.hh
/gem5/base/mod_num.hh
/gem5/base/mysql.cc
/gem5/base/mysql.hh
/gem5/base/output.cc
/gem5/base/output.hh
/gem5/base/pollevent.cc
/gem5/base/pollevent.hh
/gem5/base/predictor.hh
/gem5/base/random.cc
/gem5/base/random.hh
/gem5/base/range.cc
/gem5/base/range.hh
/gem5/base/refcnt.hh
/gem5/base/remote_gdb.cc
/gem5/base/remote_gdb.hh
/gem5/base/res_list.hh
/gem5/base/sat_counter.cc
/gem5/base/sat_counter.hh
/gem5/base/sched_list.hh
/gem5/base/socket.cc
/gem5/base/socket.hh
/gem5/base/statistics.cc
/gem5/base/statistics.hh
/gem5/base/stats/events.cc
/gem5/base/stats/events.hh
/gem5/base/stats/flags.hh
/gem5/base/stats/mysql.cc
/gem5/base/stats/mysql.hh
/gem5/base/stats/mysql_run.hh
/gem5/base/stats/output.hh
/gem5/base/stats/statdb.cc
/gem5/base/stats/statdb.hh
/gem5/base/stats/text.cc
/gem5/base/stats/text.hh
/gem5/base/stats/types.hh
/gem5/base/stats/visit.cc
/gem5/base/stats/visit.hh
/gem5/base/str.cc
/gem5/base/str.hh
/gem5/base/time.cc
/gem5/base/time.hh
/gem5/base/timebuf.hh
/gem5/base/trace.cc
/gem5/base/trace.hh
/gem5/base/traceflags.py
/gem5/base/userinfo.cc
/gem5/base/userinfo.hh
/gem5/build/SConstruct
/gem5/build/default_options/ALPHA_FS
/gem5/build/default_options/ALPHA_FS_TL
/gem5/build/default_options/ALPHA_SE
/gem5/build/default_options/MIPS_SE
/gem5/build/default_options/SPARC_SE
/gem5/build_opts/ALPHA_FS
/gem5/build_opts/ALPHA_FS_TL
/gem5/build_opts/ALPHA_SE
/gem5/build_opts/MIPS_SE
/gem5/build_opts/SPARC_SE
/gem5/cpu/SConscript
/gem5/cpu/base.cc
/gem5/cpu/base.hh
/gem5/cpu/base_dyn_inst.cc
/gem5/cpu/base_dyn_inst.hh
/gem5/cpu/cpu_exec_context.cc
/gem5/cpu/cpu_exec_context.hh
/gem5/cpu/cpu_models.py
/gem5/cpu/exec_context.hh
/gem5/cpu/exetrace.cc
/gem5/cpu/exetrace.hh
/gem5/cpu/inst_seq.hh
/gem5/cpu/intr_control.cc
/gem5/cpu/intr_control.hh
/gem5/cpu/memtest/memtest.cc
/gem5/cpu/memtest/memtest.hh
/gem5/cpu/o3/2bit_local_pred.cc
/gem5/cpu/o3/2bit_local_pred.hh
/gem5/cpu/o3/alpha_cpu.cc
/gem5/cpu/o3/alpha_cpu.hh
/gem5/cpu/o3/alpha_cpu_builder.cc
/gem5/cpu/o3/alpha_cpu_impl.hh
/gem5/cpu/o3/alpha_dyn_inst.cc
/gem5/cpu/o3/alpha_dyn_inst.hh
/gem5/cpu/o3/alpha_dyn_inst_impl.hh
/gem5/cpu/o3/alpha_impl.hh
/gem5/cpu/o3/alpha_params.hh
/gem5/cpu/o3/bpred_unit.cc
/gem5/cpu/o3/bpred_unit.hh
/gem5/cpu/o3/bpred_unit_impl.hh
/gem5/cpu/o3/btb.cc
/gem5/cpu/o3/btb.hh
/gem5/cpu/o3/comm.hh
/gem5/cpu/o3/commit.cc
/gem5/cpu/o3/commit.hh
/gem5/cpu/o3/commit_impl.hh
/gem5/cpu/o3/cpu.cc
/gem5/cpu/o3/cpu.hh
/gem5/cpu/o3/cpu_policy.hh
/gem5/cpu/o3/decode.cc
/gem5/cpu/o3/decode.hh
/gem5/cpu/o3/decode_impl.hh
/gem5/cpu/o3/fetch.cc
/gem5/cpu/o3/fetch.hh
/gem5/cpu/o3/fetch_impl.hh
/gem5/cpu/o3/free_list.cc
/gem5/cpu/o3/free_list.hh
/gem5/cpu/o3/iew.cc
/gem5/cpu/o3/iew.hh
/gem5/cpu/o3/iew_impl.hh
/gem5/cpu/o3/inst_queue.cc
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