arch-x86: ignore non-temporal hint for movntps/movntpd SSE insts

Making the implementation of movntps/movntpd consistent with other
non-temporal instructions. We are ignoring the hint here, and
implementing those instructions as cacheable instructions.

This change adds a warning to let user know about this workaround.
Also, this change add the address check for second part of move.

Change-Id: I811652b24cf39ca2f5c5d4c9e9e417f69190b55c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20408
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-x86: Change warn to warn_once for NT instructions

Change-Id: I50353716f2a913b9b106b140644d95991879f662
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21039
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-x86: implement movntq/movntdq instructions

Non-temporal quadword/double-quadword move instructions.
This change ignores the non-temporal hint and instructions are
implemented to send cacheable request to memory.
This would have some "performance" impact (i.e. having some cache
pollution) to get better "correctness" in behavior.

Change-Id: I2052ac0970f61a54bafb7332762debcb7103202d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20288
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

x86: fix movsd bug on %xmm register

The movsd instruction should zero out half the register, but
does not do it. This changeset adds the necessary microop to
the instruction to cause correct behavior.

Change-Id: I5278da3634c78a97ed0586f687a36c6dc5a34c60
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19068
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Michael LeBeane <Michael.Lebeane@amd.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-x86: implement movntps/movntpd SSE insts

These are non-temporal packed SSE stores.

Change-Id: I526cd6551b38d6d35010bc6173f23d017106b466
Reviewed-on: https://gem5-review.googlesource.com/9861
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

x86: implement rcpps and rcpss SSE insts

These are packed single-precision approximate reciprocal operations,
vector and scalar versions, respectively.

This code was basically developed by copying the code for
sqrtps and sqrtss. The mrcp micro-op was simplified relative to
msqrt since there are no double-precision versions of this operation.

x86: Adjust the size of the values written to the x87 misc registers
All x87 misc registers are implemented in an array of 64 bit values
but in real hardware the size of some of these registers is smaller.
Previsouly all 64 bits where incorrectly set and then later read. To
ensure correctness we mask the value in setMiscRegNoEffect to write
only the valid bits.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>

x86 : fxsave and fxrestore missing template code

This patch corrects the FXSAVE and FXRSTOR Macroops. The actual code used for
saving/restore the FP registers is in the file but it was not used.

The FXSAVE and FXRSTOR instructions are used in the kernel for saving and
loading the state of the mmx,xmm and fpu registers.

This operation is triggered in FS by issuing a Device Not Available Fault. The
cr0 register has a TS flag that is set upon each context change. Every time a
task access any FP related register (SIMD as well) if the TS flag is set to
one, the device not available fault is issued. The kernel saves the current
state of the registers, and restore the previous state of the currently running
task.

Right now Gem5 lacks of this capability. the Device Not Available Fault is
never issued, leading to several problems when different threads share the same
CPU and SMT is not used. The PARSEC Ferret benchmark is an example of this
behavior.

In order to test this a hack in the atomic cpu code was done to detect if a
static instruction has any FP operands and the cr0 reg TS bit is set. This
check must be done in the ISA dependent code. But it seems to be tricky to
access the cr0 register while executing an instruction.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>

x86: implements the simd128 ADDSUBPD instruction

This patch implements the simd128 ADDSUBPD instruction for the x86 architecture.

Tested with a simple program in assembly language which executes the
instruction. Checked that different versions of the instruction are executed
by using the execution tracing option.

Committed by: Nilay Vaish <nilay@cs.wisc.edu

x86: Add support for FXSAVE, FXSAVE64, FXRSTOR, and FXRSTOR64

x86 ISA: Implement the sse3 haddps instruction.

Shuffle the 32 bit values into position, and then add in parallel.

copyright: Change HP copyright on x86 code to be more friendly

X86: Add a common named flag for signed media operations.

X86: Create a common flag with a name to indicate high multiplies.

X86: Create a common flag with a name to indicate scalar media instructions.

X86: Fix problem with movhps instruction

This problem is like the one fixed with movhpd a few weeks ago.
A +8 displacement is used to access memory when there should
be none.

This fix is needed for the perlbmk spec2k benchmark to run.

X86: Add support for x86 psrldq and pslldq instructions

These are complicated instructions and the micro-code might be suboptimal.

This has been tested with some small sample programs (attached)

The psrldq instruction is needed by various spec2k programs.

X86: Implement the X86 sse2 haddpd instruction

This patch implements the haddpd instruction.

It fixes the problem in the previous version (pointed out by Gabe Black)
where an incorrect result would happen if you issue the instruction
with the same argument twice, i.e. "haddpd %xmm0,%xmm0"

This instruction is used by many spec2k benchmarks.

X86: Replace "DISPLACEMENT" with disp in movhpd.

Fix problem with the x86 sse movhpd instruction.

The movhpd instruction was writing to the wrong memory offset.

Implement X86 sse2 movdqu and movdqa instructions

The movdqa instruction should enforce 16-byte alignment.
This implementation does not do that.

These instructions are needed for most of x86_64 spec2k to run.

X86: Implement MOVQ2DQ.

X86: Implement MOVDQ2Q.

X86: Implement the media instructions that convert fp values to ints.

X86: Implement the instructions that compare fp values and write a mask as a result.

X86: Implement the instructions that compare fp values and write to rflags.

X86: Implement MOVSS.

X86: Implement LDMXCSR.

X86: Implement STMXCSR.

X86: Implement the shuffle media instructions.

X86: Implement the mask move instructions.

X86: Implement the instructions that move sign bits.

X86: Implement the insert/extract instructions.

X86: Implement the media average instructions.

X86: Implement the multiply and add instructions.

X86: Implement the media shifts that operate on 64 bits or less at a time.

X86: Implement the sum of absolute differences instructions.

X86: Implement the media integer subtract instructions.

X86: Implement the integer media multiply instructions.

X86: Implement the integer media max instructions.

X86: Implement the integer media min instructions.

X86: Implement the media integer addition instructions.

X86: Implement the instructions that convert between forms of floating point.

X86: Implement the instructions that compare fp values and write masks as the result.

X86: Implement the MOVDDUP instruction.

X86: Implement many of the media mov instructions.

X86: Implement the media instructions that convert integer values to floating point.

X86: Implement the floating point media instructions.

X86: Implement the floating point media multiply instructions.

X86: Implement the floating point media subtract instructions.

X86: Implement the floating point media add instructions.

X86: Implement the media sqrt instructions.

X86: Implement the media floating point max instructions.

X86: Implement the media floating point min instructions.

X86: Implement the pack instructions.

X86: Rename sel to ext for media microops.

X86: Move the MMX version of MOVD into the simd64 directory.

X86: Implement the remaining unpack instructions.

X86: Implement PANDN, ANDNPS, and ANDNPD.

X86: Implement PAND, ANDPS, and ANDPD.

X86: Implement POR, ORPD and ORPS.

X86: Implement PXOR.

X86: (Re)implement XORPS and XORPD.

X86: Implement PUNPCKLQDQ.

X86: Implement PUNPCKHQDQ.

X86: Implement PUNPCKHDQ.

X86: Implement PUNPCKHWD.

X86: Implement PUNPCKHBW.

X86: Implement PUNPCKLDQ.

X86: Implement PUNPCKLWD.

X86: Implement the versions of PUNPCKLBW that use XMM registers.

X86: Implement the MOVQ instruction.

X86: Implement the versions of MOVD that have an MMX source.

X86: Implement the versions of MOVD that have an MMX destination.

X86: Ignore the size part of XMM/MMX operands. The instructions know what they want.

X86: Use suffixes to differentiate XMM/MMX/GPR operands.

X86: Fix places where movfp was used incorrectly.

X86: Put ldst into the microcode (the earlier changeset didn't really).
Also clean things up as much as possible so that faulting won't break an
instruction. More microops which verify addresses are needed.

X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.