x86: Replace the .serializing directive with .serialize_(before|after).

This makes it explicit which type of serialization you want, and also
makes it possible to make a macroop serialize before. The old
serializing directive was renamed .serialize_after in the microcode
assembler, and throughout the microcode implementation, and its
behavior is unchanged. More specifically, it still marks the last
microop within the macroop as IsSerializing and IsSerializeAfter.

The new .serialize_before directive does something similar and marks
the first microop as IsSerializing and IsSerializeBefore.

Change-Id: Ia53466c734c651c65400809de7ef903c4a6c3e7e
Reviewed-on: https://gem5-review.googlesource.com/9041
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

x86: LOOP's operand size defaults to 64 bits in 64 bit mode.

The microcode for those instructions needs a directive which overrides
that setting in the instructions emulation environment.

Reported-by: Matt Sinclair <mattdsinclair@gmail.com>

Change-Id: I474d938c0b3cf01da92ec817a58b08de783f1967
Reviewed-on: https://gem5-review.googlesource.com/6301
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

x86: Fix implicit stack addressing in 64-bit mode

When in 64-bit mode, if the stack is accessed implicitly by an instruction
the alternate address prefix should be ignored if present.

This patch adds an extra flag to the ldstop which signifies when the
address override should be ignored. Then, for all of the affected
instructions, this patch adds two options to the ld and st opcode to use
the current stack addressing mode for all addresses and to ignore the
AddressSizeFlagBit. Finally, this patch updates the x86 TLB to not
truncate the address if it is in 64-bit mode and the IgnoreAddrSizeFlagBit
is set.

This fixes a problem when calling __libc_start_main with a binary that is
linked with a recent version of ld. This version of ld uses the address
override prefix (0x67) on the call instruction instead of a nop.

Note: This has not been tested in compatibility mode and only the call
instruction with the address override prefix has been tested.

See [1] page 9 (pdf page 45)

For instructions that are affected see [1] page 519 (pdf page 555).

[1] http://support.amd.com/TechDocs/24594.pdf

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>

x86: x86 instruction-implementation bug fixes

Added explicit data sizes and an opcode type for correct execution.

x86: Fix setting segment bases in real mode.

The data size used for actually writing the base value for the segment was the
default size, but really it should set the entire value without any possible
truncation.

x86: Fix some bugs in the real mode far jmp instruction.

The far pointer should be shifted right to get the selector value, not left.
Also, when calculating the width of the offset, the wrong register was used in
one spot.

arch: Use shared_ptr for all Faults

This patch takes quite a large step in transitioning from the ad-hoc
RefCountingPtr to the c++11 shared_ptr by adopting its use for all
Faults. There are no changes in behaviour, and the code modifications
are mostly just replacing "new" with "make_shared".

x86: Implementation of Int3 and Int_Ib in long mode

This is an implementation of the x86 int3 and int immediate
instructions for long mode according to 'AMD64 Programmers Manual
Volume 3'.

x86: mark instructions for being function call/return
Currently call and return instructions are marked as IsCall and IsReturn. Thus, the
branch predictor does not use RAS for these instructions. Similarly, the number of
function calls that took place is recorded as 0. This patch marks these instructions
as they should be.

x86: increment the stack pointer in lret inst
The 'lret' instruction reloads instruction pointer and code segment from the
stack and then pops them. But the popping part is missing from the current
implementation. This caused incorrect behavior in some code related to the
Fiasco OS. Microops are being added to rectify the behavior of the instruction.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>

X86: Fix JMP_FAR_I to unpack a far pointer correctly.

JMP_FAR_I was unpacking its far pointer operand using sll instead of srl like
it should, and also putting the components in the wrong registers for use by
other microcode.

X86: Read the LDT/GDT at CPL0 when executing an iret.

During iret access LDT/GDT at CPL0 rather than after transition to user mode
(if I'm reading the Intel IA-64 architecture spec correctly, the contents of
the descriptor table are read before the CPL is updated).

X86: Replace the stupd microop with a store/update sequence.

X86: Mark serializing macroops and regular instructions as such.

copyright: Change HP copyright on x86 code to be more friendly

X86: Fix checking the NT bit during an IRET.

X86: Fix a number of places where the wrong form of a microop was used.

X86: Fix a bug in IRET_PROT's microcode. The immediate form of sra was intended.

X86: Implement far jmp.

X86: Make the segment register reading microops use merge.

X86: Update CS later so stack accesses have the right permission checks.

X86: Fix a bug in the iret microcode.

X86: Fix the segment setting code in IRET, and make it restore the flags.

X86: Create a SeqOp class of microops and make Br one of them.

X86: Make far ret modify CS instead of some random selector.

style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs

X86: Implement a partial, sort of correct version of the protected mode variant of iret.

X86: Change how segment loading is performed.

X86: First crack at far returns. This is grossly approximate.

X86: Start using the stupd microop, and update statistics accordingly.

X86: Implement the LOOP instructions.

X86: Implemented the jrcx instruction.

X86: Put ldst into the microcode (the earlier changeset didn't really).
Also clean things up as much as possible so that faulting won't break an
instruction. More microops which verify addresses are needed.

X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.