History log of /gem5/src/arch/x86/bios/
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14010:0e1e887507c0 01-May-2019 Gabe Black <gabeblack@google.com>

arch, base, dev, sim: Remove now unnecessary casts from PortProxy methods.

Change-Id: Ia73b2d86a10d02fa09c924a4571477bb5f200eb7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18572
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

12334:e0ab29a34764 30-Nov-2017 Gabe Black <gabeblack@google.com>

misc: Rename misc.(hh|cc) to logging.(hh|cc)

These files aren't a collection of miscellaneous stuff, they're the
definition of the Logger interface, and a few utility macros for
calling into that interface (panic, warn, etc.).

Change-Id: I84267ac3f45896a83c0ef027f8f19c5e9a5667d1
Reviewed-on: https://gem5-review.googlesource.com/6226
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>


/gem5/ext/sst/gem5.cc
/gem5/src/arch/alpha/isa.cc
/gem5/src/arch/alpha/locked_mem.hh
/gem5/src/arch/alpha/mt.hh
/gem5/src/arch/alpha/process.cc
/gem5/src/arch/alpha/pseudo_inst.hh
/gem5/src/arch/alpha/utility.hh
/gem5/src/arch/arm/faults.hh
/gem5/src/arch/arm/isa_device.cc
/gem5/src/arch/arm/miscregs.cc
/gem5/src/arch/arm/process.cc
/gem5/src/arch/arm/pseudo_inst.hh
/gem5/src/arch/arm/types.hh
/gem5/src/arch/arm/utility.hh
/gem5/src/arch/generic/debugfaults.hh
/gem5/src/arch/generic/pseudo_inst.cc
/gem5/src/arch/generic/tlb.hh
/gem5/src/arch/generic/vec_reg.hh
/gem5/src/arch/hsail/gpu_isa.hh
/gem5/src/arch/mips/decoder.hh
/gem5/src/arch/mips/dsp.cc
/gem5/src/arch/mips/dsp.hh
/gem5/src/arch/mips/interrupts.hh
/gem5/src/arch/mips/locked_mem.hh
/gem5/src/arch/mips/mt.hh
/gem5/src/arch/mips/pagetable.hh
/gem5/src/arch/mips/process.cc
/gem5/src/arch/mips/pseudo_inst.hh
/gem5/src/arch/mips/registers.hh
/gem5/src/arch/mips/utility.cc
/gem5/src/arch/mips/utility.hh
/gem5/src/arch/power/interrupts.hh
/gem5/src/arch/power/isa.hh
/gem5/src/arch/power/process.cc
/gem5/src/arch/power/pseudo_inst.hh
/gem5/src/arch/power/utility.cc
/gem5/src/arch/riscv/decoder.hh
/gem5/src/arch/riscv/interrupts.hh
/gem5/src/arch/riscv/isa.hh
/gem5/src/arch/riscv/locked_mem.hh
/gem5/src/arch/riscv/pagetable.hh
/gem5/src/arch/riscv/process.cc
/gem5/src/arch/riscv/pseudo_inst.hh
/gem5/src/arch/sparc/isa/includes.isa
/gem5/src/arch/sparc/mt.hh
/gem5/src/arch/sparc/pagetable.hh
/gem5/src/arch/sparc/process.cc
/gem5/src/arch/sparc/pseudo_inst.hh
/gem5/src/arch/sparc/tlb.hh
/gem5/src/arch/sparc/utility.hh
intelmp.cc
/gem5/src/arch/x86/decoder.cc
/gem5/src/arch/x86/decoder.hh
/gem5/src/arch/x86/emulenv.cc
/gem5/src/arch/x86/faults.hh
/gem5/src/arch/x86/isa/includes.isa
/gem5/src/arch/x86/process.cc
/gem5/src/arch/x86/regs/int.hh
/gem5/src/base/SConscript
/gem5/src/base/addr_range.hh
/gem5/src/base/bigint.hh
/gem5/src/base/bmpwriter.cc
/gem5/src/base/circlebuf.hh
/gem5/src/base/debug.cc
/gem5/src/base/hostinfo.cc
/gem5/src/base/imgwriter.cc
/gem5/src/base/intmath.hh
/gem5/src/base/loader/ecoff_object.cc
/gem5/src/base/loader/elf_object.cc
/gem5/src/base/loader/object_file.hh
/gem5/src/base/loader/symtab.cc
/gem5/src/base/logging.cc
/gem5/src/base/logging.hh
/gem5/src/base/misc.cc
/gem5/src/base/misc.hh
/gem5/src/base/output.cc
/gem5/src/base/pngwriter.cc
/gem5/src/base/pollevent.cc
/gem5/src/base/random.cc
/gem5/src/base/socket.cc
/gem5/src/base/statistics.cc
/gem5/src/base/stats/text.cc
/gem5/src/base/time.cc
/gem5/src/base/trace.cc
/gem5/src/base/trie.hh
/gem5/src/base/vnc/vncinput.cc
/gem5/src/base/vnc/vncserver.cc
/gem5/src/cpu/base.cc
/gem5/src/cpu/func_unit.cc
/gem5/src/cpu/intr_control.hh
/gem5/src/cpu/kvm/device.cc
/gem5/src/cpu/kvm/perfevent.cc
/gem5/src/cpu/kvm/timer.cc
/gem5/src/cpu/minor/buffers.hh
/gem5/src/cpu/o3/free_list.hh
/gem5/src/cpu/o3/store_set.cc
/gem5/src/cpu/pc_event.hh
/gem5/src/cpu/pred/2bit_local.cc
/gem5/src/cpu/pred/btb.hh
/gem5/src/cpu/pred/ltage.cc
/gem5/src/cpu/pred/sat_counter.hh
/gem5/src/cpu/simple/base.cc
/gem5/src/cpu/static_inst.hh
/gem5/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc
/gem5/src/cpu/testers/rubytest/RubyTester.cc
/gem5/src/cpu/thread_context.cc
/gem5/src/dev/intel_8254_timer.cc
/gem5/src/dev/mc146818.hh
/gem5/src/dev/net/dist_iface.hh
/gem5/src/dev/net/etherbus.cc
/gem5/src/dev/net/etherdump.cc
/gem5/src/dev/net/etherint.cc
/gem5/src/dev/net/etherpkt.cc
/gem5/src/dev/net/ethertap.cc
/gem5/src/dev/net/pktfifo.cc
/gem5/src/dev/net/pktfifo.hh
/gem5/src/dev/pci/device.cc
/gem5/src/dev/platform.cc
/gem5/src/dev/ps2.cc
/gem5/src/dev/serial/serial.cc
/gem5/src/dev/serial/terminal.cc
/gem5/src/dev/storage/disk_image.cc
/gem5/src/dev/storage/simple_disk.cc
/gem5/src/gpu-compute/brig_object.cc
/gem5/src/gpu-compute/gpu_tlb.hh
/gem5/src/gpu-compute/hsa_object.cc
/gem5/src/gpu-compute/misc.hh
/gem5/src/gpu-compute/of_scheduling_policy.hh
/gem5/src/gpu-compute/rr_scheduling_policy.hh
/gem5/src/gpu-compute/simple_pool_manager.cc
/gem5/src/gpu-compute/tlb_coalescer.hh
/gem5/src/gpu-compute/vector_register_file.cc
/gem5/src/gpu-compute/wavefront.hh
/gem5/src/kern/operatingsystem.cc
/gem5/src/mem/cache/base.hh
/gem5/src/mem/cache/cache.cc
/gem5/src/mem/cache/cache.hh
/gem5/src/mem/cache/mshr.cc
/gem5/src/mem/cache/tags/fa_lru.cc
/gem5/src/mem/cache/write_queue_entry.cc
/gem5/src/mem/coherent_xbar.cc
/gem5/src/mem/dramsim2_wrapper.cc
/gem5/src/mem/mem_checker.hh
/gem5/src/mem/noncoherent_xbar.cc
/gem5/src/mem/packet.cc
/gem5/src/mem/packet.hh
/gem5/src/mem/request.hh
/gem5/src/mem/ruby/common/Set.hh
/gem5/src/mem/ruby/network/MessageBuffer.cc
/gem5/src/mem/ruby/network/Network.cc
/gem5/src/mem/ruby/network/fault_model/FaultModel.cc
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
/gem5/src/mem/ruby/structures/AbstractReplacementPolicy.cc
/gem5/src/mem/ruby/system/GPUCoalescer.cc
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/VIPERCoalescer.cc
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/mem/slicc/symbols/Type.py
/gem5/src/mem/snoop_filter.cc
/gem5/src/mem/xbar.cc
/gem5/src/proto/protoio.cc
/gem5/src/python/pybind11/core.cc
/gem5/src/python/pybind11/event.cc
/gem5/src/sim/clocked_object.cc
/gem5/src/sim/drain.cc
/gem5/src/sim/dvfs_handler.cc
/gem5/src/sim/eventq.cc
/gem5/src/sim/faults.cc
/gem5/src/sim/fd_array.cc
/gem5/src/sim/init.cc
/gem5/src/sim/init_signals.cc
/gem5/src/sim/mathexpr.cc
/gem5/src/sim/microcode_rom.cc
/gem5/src/sim/root.cc
/gem5/src/sim/serialize.cc
/gem5/src/sim/sim_object.cc
/gem5/src/sim/simulate.cc
/gem5/src/sim/syscall_emul.hh
/gem5/src/unittest/cprintftest.cc
/gem5/src/unittest/nmtest.cc
/gem5/src/unittest/stattest.cc
/gem5/util/systemc/sc_module.cc
11793:ef606668d247 09-Nov-2016 Brandon Potter <brandon.potter@amd.com>

style: [patch 1/22] use /r/3648/ to reorganize includes


/gem5/src/arch/alpha/faults.cc
/gem5/src/arch/alpha/freebsd/system.cc
/gem5/src/arch/alpha/idle_event.cc
/gem5/src/arch/alpha/ipr.cc
/gem5/src/arch/alpha/isa.cc
/gem5/src/arch/alpha/kernel_stats.cc
/gem5/src/arch/alpha/linux/process.cc
/gem5/src/arch/alpha/linux/system.cc
/gem5/src/arch/alpha/pagetable.cc
/gem5/src/arch/alpha/process.cc
/gem5/src/arch/alpha/remote_gdb.cc
/gem5/src/arch/alpha/stacktrace.cc
/gem5/src/arch/alpha/system.cc
/gem5/src/arch/alpha/utility.cc
/gem5/src/arch/alpha/vtophys.cc
/gem5/src/arch/arm/faults.cc
/gem5/src/arch/arm/insts/macromem.cc
/gem5/src/arch/arm/insts/mem.cc
/gem5/src/arch/arm/insts/mem64.cc
/gem5/src/arch/arm/insts/misc.cc
/gem5/src/arch/arm/insts/pseudo.cc
/gem5/src/arch/arm/insts/static_inst.cc
/gem5/src/arch/arm/interrupts.cc
/gem5/src/arch/arm/isa.cc
/gem5/src/arch/arm/kvm/base_cpu.cc
/gem5/src/arch/arm/linux/process.cc
/gem5/src/arch/arm/linux/system.cc
/gem5/src/arch/arm/miscregs.cc
/gem5/src/arch/arm/nativetrace.cc
/gem5/src/arch/arm/process.cc
/gem5/src/arch/arm/remote_gdb.cc
/gem5/src/arch/arm/stacktrace.cc
/gem5/src/arch/arm/stage2_lookup.cc
/gem5/src/arch/arm/system.cc
/gem5/src/arch/arm/tlb.cc
/gem5/src/arch/arm/utility.cc
/gem5/src/arch/arm/vtophys.cc
/gem5/src/arch/generic/decode_cache.cc
/gem5/src/arch/generic/mmapped_ipr.cc
/gem5/src/arch/generic/pseudo_inst.cc
/gem5/src/arch/mips/bare_iron/system.cc
/gem5/src/arch/mips/dsp.cc
/gem5/src/arch/mips/faults.cc
/gem5/src/arch/mips/idle_event.cc
/gem5/src/arch/mips/interrupts.cc
/gem5/src/arch/mips/isa.cc
/gem5/src/arch/mips/linux/process.cc
/gem5/src/arch/mips/linux/system.cc
/gem5/src/arch/mips/pagetable.cc
/gem5/src/arch/mips/process.cc
/gem5/src/arch/mips/remote_gdb.cc
/gem5/src/arch/mips/stacktrace.cc
/gem5/src/arch/mips/system.cc
/gem5/src/arch/mips/tlb.cc
/gem5/src/arch/mips/utility.cc
/gem5/src/arch/mips/vtophys.cc
/gem5/src/arch/power/insts/branch.cc
/gem5/src/arch/power/insts/mem.cc
/gem5/src/arch/power/insts/static_inst.cc
/gem5/src/arch/power/isa.cc
/gem5/src/arch/power/linux/process.cc
/gem5/src/arch/power/pagetable.cc
/gem5/src/arch/power/process.cc
/gem5/src/arch/power/stacktrace.cc
/gem5/src/arch/power/tlb.cc
/gem5/src/arch/power/utility.cc
/gem5/src/arch/sparc/faults.cc
/gem5/src/arch/sparc/isa.cc
/gem5/src/arch/sparc/linux/process.cc
/gem5/src/arch/sparc/nativetrace.cc
/gem5/src/arch/sparc/pagetable.cc
/gem5/src/arch/sparc/process.cc
/gem5/src/arch/sparc/remote_gdb.cc
/gem5/src/arch/sparc/solaris/process.cc
/gem5/src/arch/sparc/system.cc
/gem5/src/arch/sparc/tlb.cc
/gem5/src/arch/sparc/ua2005.cc
/gem5/src/arch/sparc/utility.cc
/gem5/src/arch/sparc/vtophys.cc
acpi.cc
e820.cc
intelmp.cc
smbios.cc
/gem5/src/arch/x86/cpuid.cc
/gem5/src/arch/x86/decoder.cc
/gem5/src/arch/x86/emulenv.cc
/gem5/src/arch/x86/faults.cc
/gem5/src/arch/x86/insts/badmicroop.cc
/gem5/src/arch/x86/insts/microfpop.cc
/gem5/src/arch/x86/insts/microldstop.cc
/gem5/src/arch/x86/insts/micromediaop.cc
/gem5/src/arch/x86/insts/microop.cc
/gem5/src/arch/x86/insts/microregop.cc
/gem5/src/arch/x86/insts/static_inst.cc
/gem5/src/arch/x86/interrupts.cc
/gem5/src/arch/x86/isa.cc
/gem5/src/arch/x86/linux/process.cc
/gem5/src/arch/x86/linux/system.cc
/gem5/src/arch/x86/nativetrace.cc
/gem5/src/arch/x86/pagetable.cc
/gem5/src/arch/x86/pagetable_walker.cc
/gem5/src/arch/x86/process.cc
/gem5/src/arch/x86/pseudo_inst.cc
/gem5/src/arch/x86/remote_gdb.cc
/gem5/src/arch/x86/stacktrace.cc
/gem5/src/arch/x86/system.cc
/gem5/src/arch/x86/tlb.cc
/gem5/src/arch/x86/types.cc
/gem5/src/arch/x86/utility.cc
/gem5/src/arch/x86/vtophys.cc
/gem5/src/base/atomicio.cc
/gem5/src/base/bigint.cc
/gem5/src/base/cp_annotate.cc
/gem5/src/base/cprintf.cc
/gem5/src/base/debug.cc
/gem5/src/base/hostinfo.cc
/gem5/src/base/inet.cc
/gem5/src/base/inifile.cc
/gem5/src/base/loader/aout_object.cc
/gem5/src/base/loader/dtb_object.cc
/gem5/src/base/loader/ecoff_object.cc
/gem5/src/base/loader/hex_file.cc
/gem5/src/base/loader/object_file.cc
/gem5/src/base/loader/raw_object.cc
/gem5/src/base/loader/symtab.cc
/gem5/src/base/match.cc
/gem5/src/base/misc.cc
/gem5/src/base/output.cc
/gem5/src/base/pollevent.cc
/gem5/src/base/random.cc
/gem5/src/base/remote_gdb.cc
/gem5/src/base/socket.cc
/gem5/src/base/statistics.cc
/gem5/src/base/stats/text.cc
/gem5/src/base/str.cc
/gem5/src/base/time.cc
/gem5/src/base/trace.cc
/gem5/src/base/vnc/vncinput.cc
/gem5/src/base/vnc/vncserver.cc
/gem5/src/cpu/activity.cc
/gem5/src/cpu/base.cc
/gem5/src/cpu/checker/cpu.cc
/gem5/src/cpu/dummy_checker.cc
/gem5/src/cpu/exetrace.cc
/gem5/src/cpu/func_unit.cc
/gem5/src/cpu/inteltrace.cc
/gem5/src/cpu/intr_control.cc
/gem5/src/cpu/kvm/base.cc
/gem5/src/cpu/kvm/perfevent.cc
/gem5/src/cpu/kvm/timer.cc
/gem5/src/cpu/kvm/vm.cc
/gem5/src/cpu/kvm/x86_cpu.cc
/gem5/src/cpu/minor/activity.cc
/gem5/src/cpu/minor/cpu.cc
/gem5/src/cpu/minor/decode.cc
/gem5/src/cpu/minor/dyn_inst.cc
/gem5/src/cpu/minor/execute.cc
/gem5/src/cpu/minor/fetch1.cc
/gem5/src/cpu/minor/fetch2.cc
/gem5/src/cpu/minor/func_unit.cc
/gem5/src/cpu/minor/lsq.cc
/gem5/src/cpu/minor/pipeline.cc
/gem5/src/cpu/minor/scoreboard.cc
/gem5/src/cpu/nativetrace.cc
/gem5/src/cpu/o3/base_dyn_inst.cc
/gem5/src/cpu/o3/checker.cc
/gem5/src/cpu/o3/cpu.cc
/gem5/src/cpu/o3/deriv.cc
/gem5/src/cpu/o3/free_list.cc
/gem5/src/cpu/o3/fu_pool.cc
/gem5/src/cpu/o3/probe/simple_trace.cc
/gem5/src/cpu/o3/regfile.cc
/gem5/src/cpu/o3/rename_map.cc
/gem5/src/cpu/o3/scoreboard.cc
/gem5/src/cpu/o3/store_set.cc
/gem5/src/cpu/o3/thread_context.cc
/gem5/src/cpu/pc_event.cc
/gem5/src/cpu/pred/2bit_local.cc
/gem5/src/cpu/pred/bi_mode.cc
/gem5/src/cpu/pred/btb.cc
/gem5/src/cpu/pred/tournament.cc
/gem5/src/cpu/profile.cc
/gem5/src/cpu/quiesce_event.cc
/gem5/src/cpu/simple/atomic.cc
/gem5/src/cpu/simple/base.cc
/gem5/src/cpu/simple/probes/simpoint.cc
/gem5/src/cpu/simple/timing.cc
/gem5/src/cpu/simple_thread.cc
/gem5/src/cpu/static_inst.cc
/gem5/src/cpu/testers/directedtest/DirectedGenerator.cc
/gem5/src/cpu/testers/directedtest/InvalidateGenerator.cc
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.cc
/gem5/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
/gem5/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc
/gem5/src/cpu/testers/memtest/memtest.cc
/gem5/src/cpu/testers/rubytest/Check.cc
/gem5/src/cpu/testers/rubytest/CheckTable.cc
/gem5/src/cpu/testers/rubytest/RubyTester.cc
/gem5/src/cpu/thread_context.cc
/gem5/src/cpu/thread_state.cc
/gem5/src/cpu/timing_expr.cc
/gem5/src/dev/alpha/backdoor.cc
/gem5/src/dev/alpha/tsunami.cc
/gem5/src/dev/alpha/tsunami_cchip.cc
/gem5/src/dev/alpha/tsunami_io.cc
/gem5/src/dev/arm/a9scu.cc
/gem5/src/dev/arm/amba_device.cc
/gem5/src/dev/arm/amba_fake.cc
/gem5/src/dev/arm/energy_ctrl.cc
/gem5/src/dev/arm/gic_pl390.cc
/gem5/src/dev/arm/hdlcd.cc
/gem5/src/dev/arm/kmi.cc
/gem5/src/dev/arm/pl011.cc
/gem5/src/dev/arm/pl111.cc
/gem5/src/dev/arm/realview.cc
/gem5/src/dev/arm/rtc_pl031.cc
/gem5/src/dev/arm/timer_cpulocal.cc
/gem5/src/dev/arm/timer_sp804.cc
/gem5/src/dev/arm/vgic.cc
/gem5/src/dev/baddev.cc
/gem5/src/dev/intel_8254_timer.cc
/gem5/src/dev/io_device.cc
/gem5/src/dev/isa_fake.cc
/gem5/src/dev/mc146818.cc
/gem5/src/dev/mips/malta.cc
/gem5/src/dev/mips/malta_cchip.cc
/gem5/src/dev/mips/malta_io.cc
/gem5/src/dev/pci/device.cc
/gem5/src/dev/pci/host.cc
/gem5/src/dev/platform.cc
/gem5/src/dev/ps2.cc
/gem5/src/dev/ps2.hh
/gem5/src/dev/sparc/dtod.cc
/gem5/src/dev/sparc/iob.cc
/gem5/src/dev/sparc/mm_disk.cc
/gem5/src/dev/sparc/t1000.cc
/gem5/src/dev/uart.cc
/gem5/src/dev/uart8250.cc
/gem5/src/dev/virtio/base.cc
/gem5/src/dev/virtio/block.cc
/gem5/src/dev/virtio/console.cc
/gem5/src/dev/virtio/fs9p.cc
/gem5/src/dev/virtio/pci.cc
/gem5/src/dev/x86/cmos.cc
/gem5/src/dev/x86/i8042.cc
/gem5/src/dev/x86/i82094aa.cc
/gem5/src/dev/x86/i8237.cc
/gem5/src/dev/x86/i8254.cc
/gem5/src/dev/x86/i8259.cc
/gem5/src/dev/x86/pc.cc
/gem5/src/dev/x86/south_bridge.cc
/gem5/src/dev/x86/speaker.cc
/gem5/src/kern/linux/linux.cc
/gem5/src/kern/linux/printk.cc
/gem5/src/kern/operatingsystem.cc
/gem5/src/kern/system_events.cc
/gem5/src/mem/abstract_mem.cc
/gem5/src/mem/bridge.cc
/gem5/src/mem/cache/prefetch/base.cc
/gem5/src/mem/cache/prefetch/queued.cc
/gem5/src/mem/cache/prefetch/stride.cc
/gem5/src/mem/coherent_xbar.cc
/gem5/src/mem/comm_monitor.cc
/gem5/src/mem/dram_ctrl.cc
/gem5/src/mem/drampower.cc
/gem5/src/mem/dramsim2.cc
/gem5/src/mem/dramsim2_wrapper.cc
/gem5/src/mem/external_master.cc
/gem5/src/mem/external_slave.cc
/gem5/src/mem/fs_translating_port_proxy.cc
/gem5/src/mem/hmc_controller.cc
/gem5/src/mem/mem_checker.cc
/gem5/src/mem/mem_checker_monitor.cc
/gem5/src/mem/noncoherent_xbar.cc
/gem5/src/mem/packet.cc
/gem5/src/mem/packet_queue.cc
/gem5/src/mem/page_table.cc
/gem5/src/mem/physical.cc
/gem5/src/mem/port.cc
/gem5/src/mem/port_proxy.cc
/gem5/src/mem/probes/base.cc
/gem5/src/mem/ruby/common/Histogram.cc
/gem5/src/mem/ruby/common/NetDest.cc
/gem5/src/mem/ruby/common/SubBlock.cc
/gem5/src/mem/ruby/filters/BlockBloomFilter.cc
/gem5/src/mem/ruby/filters/BulkBloomFilter.cc
/gem5/src/mem/ruby/filters/H3BloomFilter.cc
/gem5/src/mem/ruby/filters/LSB_CountingBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiGrainBloomFilter.cc
/gem5/src/mem/ruby/filters/NonCountingBloomFilter.cc
/gem5/src/mem/ruby/network/MessageBuffer.cc
/gem5/src/mem/ruby/network/Network.cc
/gem5/src/mem/ruby/network/Topology.cc
/gem5/src/mem/ruby/network/simple/PerfectSwitch.cc
/gem5/src/mem/ruby/network/simple/PerfectSwitch.hh
/gem5/src/mem/ruby/network/simple/SimpleNetwork.cc
/gem5/src/mem/ruby/network/simple/Switch.cc
/gem5/src/mem/ruby/network/simple/Throttle.cc
/gem5/src/mem/ruby/profiler/AccessTraceForAddress.cc
/gem5/src/mem/ruby/profiler/AddressProfiler.cc
/gem5/src/mem/ruby/profiler/StoreTrace.cc
/gem5/src/mem/ruby/slicc_interface/AbstractController.cc
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/slicc_interface/RubyRequest.cc
/gem5/src/mem/ruby/structures/BankedArray.cc
/gem5/src/mem/ruby/structures/CacheMemory.cc
/gem5/src/mem/ruby/structures/DirectoryMemory.cc
/gem5/src/mem/ruby/structures/LRUPolicy.cc
/gem5/src/mem/ruby/structures/Prefetcher.cc
/gem5/src/mem/ruby/structures/PseudoLRUPolicy.cc
/gem5/src/mem/ruby/structures/WireBuffer.cc
/gem5/src/mem/ruby/system/CacheRecorder.cc
/gem5/src/mem/ruby/system/DMASequencer.cc
/gem5/src/mem/ruby/system/RubyPort.cc
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/se_translating_port_proxy.cc
/gem5/src/mem/serial_link.cc
/gem5/src/mem/simple_mem.cc
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/mem/snoop_filter.cc
/gem5/src/mem/tport.cc
/gem5/src/mem/xbar.cc
/gem5/src/proto/protoio.cc
/gem5/src/python/swig/pyevent.cc
/gem5/src/python/swig/pyevent.hh
/gem5/src/python/swig/pyobject.cc
/gem5/src/sim/arguments.cc
/gem5/src/sim/backtrace_glibc.cc
/gem5/src/sim/clock_domain.cc
/gem5/src/sim/core.cc
/gem5/src/sim/cxx_manager.cc
/gem5/src/sim/debug.cc
/gem5/src/sim/dvfs_handler.cc
/gem5/src/sim/faults.cc
/gem5/src/sim/init.cc
/gem5/src/sim/probe/probe.cc
/gem5/src/sim/process.cc
/gem5/src/sim/pseudo_inst.cc
/gem5/src/sim/py_interact.cc
/gem5/src/sim/root.cc
/gem5/src/sim/serialize.cc
/gem5/src/sim/sim_events.cc
/gem5/src/sim/sim_object.cc
/gem5/src/sim/simulate.cc
/gem5/src/sim/stat_control.cc
/gem5/src/sim/stat_control.hh
/gem5/src/sim/sub_system.cc
/gem5/src/sim/syscall_emul.cc
/gem5/src/sim/system.cc
/gem5/src/sim/voltage_domain.cc
/gem5/src/unittest/circlebuf.cc
/gem5/src/unittest/unittest.cc
11481:fc247b9c42b6 19-May-2016 Bjoern A. Zeeb <baz21@cam.ac.uk>

config, x86: Properly space pad the X86IntelMPBus Entry descriptions

According to the Intel Multi Processor Specification rev 1.4 (-006) (*),
section 4.3.2 Bus Entries, Bus type strings are >>6-character ASCII
(blank-filled) strings<<.
This patch properly pads the entries with the missing spaces at the end.

(*) http://www.intel.com/design/pentium/datashts/24201606.pdf

Committed by Jason Lowe-Power <power.jg@gmail.com>

11321:02e930db812d 06-Feb-2016 Steve Reinhardt <steve.reinhardt@amd.com>

style: fix missing spaces in control statements

Result of running 'hg m5style --skip-all --fix-control -a'.


/gem5/src/arch/alpha/process.cc
/gem5/src/arch/arm/insts/macromem.cc
/gem5/src/arch/arm/insts/vfp.hh
/gem5/src/arch/arm/kvm/arm_cpu.cc
/gem5/src/arch/arm/linux/system.cc
/gem5/src/arch/arm/tlb.cc
/gem5/src/arch/generic/tlb.cc
/gem5/src/arch/mips/isa.cc
intelmp.cc
/gem5/src/arch/x86/cpuid.cc
/gem5/src/arch/x86/decoder.cc
/gem5/src/arch/x86/insts/microldstop.cc
/gem5/src/arch/x86/insts/microregop.cc
/gem5/src/arch/x86/insts/static_inst.cc
/gem5/src/arch/x86/insts/static_inst.hh
/gem5/src/arch/x86/nativetrace.cc
/gem5/src/arch/x86/pagetable_walker.cc
/gem5/src/arch/x86/process.cc
/gem5/src/arch/x86/types.hh
/gem5/src/base/atomicio.hh
/gem5/src/base/cp_annotate.cc
/gem5/src/base/fenv.c
/gem5/src/base/loader/elf_object.cc
/gem5/src/base/statistics.cc
/gem5/src/cpu/base.cc
/gem5/src/cpu/kvm/perfevent.cc
/gem5/src/cpu/kvm/x86_cpu.cc
/gem5/src/cpu/minor/decode.cc
/gem5/src/cpu/nativetrace.cc
/gem5/src/cpu/nativetrace.hh
/gem5/src/cpu/o3/inst_queue_impl.hh
/gem5/src/cpu/o3/rename_impl.hh
/gem5/src/cpu/pred/bpred_unit.cc
/gem5/src/cpu/simple/atomic.cc
/gem5/src/cpu/simple/base.cc
/gem5/src/cpu/simple/timing.cc
/gem5/src/dev/alpha/tsunami_cchip.cc
/gem5/src/dev/arm/flash_device.cc
/gem5/src/dev/arm/ufs_device.cc
/gem5/src/dev/intel_8254_timer.cc
/gem5/src/dev/mips/malta_cchip.cc
/gem5/src/dev/virtio/base.cc
/gem5/src/mem/bridge.cc
/gem5/src/mem/cache/prefetch/stride.cc
/gem5/src/mem/dram_ctrl.cc
/gem5/src/mem/physical.cc
/gem5/src/mem/port.cc
/gem5/src/mem/ruby/filters/BulkBloomFilter.cc
/gem5/src/mem/ruby/filters/H3BloomFilter.cc
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiGrainBloomFilter.cc
/gem5/src/mem/ruby/filters/NonCountingBloomFilter.cc
/gem5/src/mem/ruby/network/MessageBuffer.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/simple/PerfectSwitch.cc
/gem5/src/mem/ruby/profiler/AccessTraceForAddress.cc
/gem5/src/mem/ruby/slicc_interface/AbstractController.cc
/gem5/src/mem/ruby/structures/AbstractReplacementPolicy.cc
/gem5/src/mem/ruby/structures/BankedArray.cc
/gem5/src/mem/ruby/structures/CacheMemory.cc
/gem5/src/mem/ruby/structures/PseudoLRUPolicy.cc
/gem5/src/mem/ruby/structures/RubyMemoryControl.cc
/gem5/src/mem/ruby/structures/TBETable.hh
/gem5/src/mem/ruby/system/GPUCoalescer.cc
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/VIPERCoalescer.cc
/gem5/src/mem/ruby/system/WeightedLRUPolicy.cc
/gem5/src/mem/serial_link.cc
/gem5/src/mem/stack_dist_calc.cc
/gem5/src/python/swig/pyobject.cc
/gem5/src/sim/backtrace_glibc.cc
/gem5/src/sim/dvfs_handler.cc
/gem5/src/sim/serialize.hh
/gem5/src/sim/syscall_emul.hh
/gem5/tests/test-progs/gpu-hello/src/gpu-hello-kernel.cl
/gem5/tests/test-progs/gpu-hello/src/gpu-hello.cpp
/gem5/tests/test-progs/mwait/mwait.c
/gem5/util/statetrace/arch/amd64/tracechild.cc
/gem5/util/statetrace/arch/arm/tracechild.cc
/gem5/util/statetrace/arch/sparc/tracechild.cc
/gem5/util/tlm/main.cc
/gem5/util/tlm/sc_mm.cc
/gem5/util/tlm/sc_port.cc
/gem5/util/tlm/sc_target.cc
10292:933dfb9d8279 26-Aug-2014 Andreas Sandberg <Andreas.Sandberg@ARM.com>

base: Replace the internal varargs stuff with C++11 constructs

We currently use our own home-baked support for type-safe variadic
functions. This is confusing and somewhat limited (e.g., cprintf only
supports a limited number of arguments). This changeset converts all
uses of our internal varargs support to use C++11 variadic macros.

9554:406fbcf60223 19-Feb-2013 Andreas Hansson <andreas.hansson@arm.com>

scons: Add warning for missing declarations

This patch enables warnings for missing declarations. To avoid issues
with SWIG-generated code, the warning is only applied to non-SWIG
code.

9338:97b4a2be1e5b 02-Nov-2012 Andreas Sandberg <Andreas.Sandberg@arm.com>

sim: Include object header files in SWIG interfaces

When casting objects in the generated SWIG interfaces, SWIG uses
classical C-style casts ( (Foo *)bar; ). In some cases, this can
degenerate into the equivalent of a reinterpret_cast (mainly if only a
forward declaration of the type is available). This usually works for
most compilers, but it is known to break if multiple inheritance is
used anywhere in the object hierarchy.

This patch introduces the cxx_header attribute to Python SimObject
definitions, which should be used to specify a header to include in
the SWIG interface. The header should include the declaration of the
wrapped object. We currently don't enforce header the use of the
header attribute, but a warning will be generated for objects that do
not use it.


/gem5/src/SConscript
/gem5/src/arch/alpha/AlphaInterrupts.py
/gem5/src/arch/alpha/AlphaSystem.py
/gem5/src/arch/alpha/AlphaTLB.py
/gem5/src/arch/arm/ArmInterrupts.py
/gem5/src/arch/arm/ArmNativeTrace.py
/gem5/src/arch/arm/ArmSystem.py
/gem5/src/arch/arm/ArmTLB.py
/gem5/src/arch/mips/MipsInterrupts.py
/gem5/src/arch/mips/MipsSystem.py
/gem5/src/arch/mips/MipsTLB.py
/gem5/src/arch/power/PowerInterrupts.py
/gem5/src/arch/power/PowerTLB.py
/gem5/src/arch/sparc/SparcInterrupts.py
/gem5/src/arch/sparc/SparcNativeTrace.py
/gem5/src/arch/sparc/SparcSystem.py
/gem5/src/arch/sparc/SparcTLB.py
/gem5/src/arch/x86/X86LocalApic.py
/gem5/src/arch/x86/X86NativeTrace.py
/gem5/src/arch/x86/X86System.py
/gem5/src/arch/x86/X86TLB.py
ACPI.py
E820.py
IntelMP.py
SMBios.py
/gem5/src/base/CPA.py
/gem5/src/base/vnc/Vnc.py
/gem5/src/cpu/BaseCPU.py
/gem5/src/cpu/CheckerCPU.py
/gem5/src/cpu/ExeTracer.py
/gem5/src/cpu/FuncUnit.py
/gem5/src/cpu/IntelTrace.py
/gem5/src/cpu/IntrControl.py
/gem5/src/cpu/LegionTrace.py
/gem5/src/cpu/NativeTrace.py
/gem5/src/cpu/inorder/InOrderCPU.py
/gem5/src/cpu/inorder/InOrderTrace.py
/gem5/src/cpu/inteltrace.hh
/gem5/src/cpu/o3/FUPool.py
/gem5/src/cpu/simple/AtomicSimpleCPU.py
/gem5/src/cpu/simple/BaseSimpleCPU.py
/gem5/src/cpu/simple/TimingSimpleCPU.py
/gem5/src/cpu/static_inst.hh
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.py
/gem5/src/cpu/testers/memtest/MemTest.py
/gem5/src/cpu/testers/networktest/NetworkTest.py
/gem5/src/cpu/testers/rubytest/RubyTester.py
/gem5/src/cpu/testers/traffic_gen/TrafficGen.py
/gem5/src/dev/BadDevice.py
/gem5/src/dev/CopyEngine.py
/gem5/src/dev/Device.py
/gem5/src/dev/DiskImage.py
/gem5/src/dev/Ethernet.py
/gem5/src/dev/Ide.py
/gem5/src/dev/Pci.py
/gem5/src/dev/Platform.py
/gem5/src/dev/SimpleDisk.py
/gem5/src/dev/Terminal.py
/gem5/src/dev/Uart.py
/gem5/src/dev/alpha/AlphaBackdoor.py
/gem5/src/dev/alpha/Tsunami.py
/gem5/src/dev/alpha/tsunami_io.hh
/gem5/src/dev/arm/RealView.py
/gem5/src/dev/arm/pl011.hh
/gem5/src/dev/arm/realview.hh
/gem5/src/dev/arm/timer_cpulocal.hh
/gem5/src/dev/copy_engine.hh
/gem5/src/dev/mips/Malta.py
/gem5/src/dev/mips/malta_io.hh
/gem5/src/dev/sparc/T1000.py
/gem5/src/dev/x86/Cmos.py
/gem5/src/dev/x86/I8042.py
/gem5/src/dev/x86/I82094AA.py
/gem5/src/dev/x86/I8237.py
/gem5/src/dev/x86/I8254.py
/gem5/src/dev/x86/I8259.py
/gem5/src/dev/x86/Pc.py
/gem5/src/dev/x86/PcSpeaker.py
/gem5/src/dev/x86/SouthBridge.py
/gem5/src/dev/x86/X86IntPin.py
/gem5/src/dev/x86/speaker.hh
/gem5/src/mem/AbstractMemory.py
/gem5/src/mem/AddrMapper.py
/gem5/src/mem/Bridge.py
/gem5/src/mem/Bus.py
/gem5/src/mem/CommMonitor.py
/gem5/src/mem/MemObject.py
/gem5/src/mem/SimpleDRAM.py
/gem5/src/mem/SimpleMemory.py
/gem5/src/mem/cache/BaseCache.py
/gem5/src/mem/cache/prefetch/Prefetcher.py
/gem5/src/mem/cache/tags/iic_repl/Repl.py
/gem5/src/mem/ruby/network/BasicLink.py
/gem5/src/mem/ruby/network/BasicRouter.py
/gem5/src/mem/ruby/network/Network.py
/gem5/src/mem/ruby/network/fault_model/FaultModel.py
/gem5/src/mem/ruby/network/garnet/BaseGarnetNetwork.py
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.py
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetRouter_d.py
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.py
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.py
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetRouter.py
/gem5/src/mem/ruby/network/simple/SimpleLink.py
/gem5/src/mem/ruby/network/simple/SimpleNetwork.py
/gem5/src/mem/ruby/profiler/Profiler.py
/gem5/src/mem/ruby/slicc_interface/Controller.py
/gem5/src/mem/ruby/system/Cache.py
/gem5/src/mem/ruby/system/DirectoryMemory.py
/gem5/src/mem/ruby/system/MemoryControl.py
/gem5/src/mem/ruby/system/RubyMemoryControl.py
/gem5/src/mem/ruby/system/RubySystem.py
/gem5/src/mem/ruby/system/Sequencer.py
/gem5/src/mem/ruby/system/WireBuffer.py
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/python/m5/SimObject.py
/gem5/src/sim/BaseTLB.py
/gem5/src/sim/ClockedObject.py
/gem5/src/sim/InstTracer.py
/gem5/src/sim/Process.py
/gem5/src/sim/Root.py
/gem5/src/sim/System.py
8902:75b524b64c28 19-Mar-2012 Andreas Hansson <andreas.hansson@arm.com>

gcc: Clean-up of non-C++0x compliant code, first steps

This patch cleans up a number of minor issues aiming to get closer to
compliance with the C++0x standard as interpreted by gcc and clang
(compile with std=c++0x and -pedantic-errors). In particular, the
patch cleans up enums where the last item was succeded by a comma,
namespaces closed by a curcly brace followed by a semi-colon, and the
use of the GNU-extension typeof (replaced by templated functions). It
does not address variable-length arrays, zero-size arrays, anonymous
structs, range expressions in switch statements, and the use of long
long. The generated CPU code also has a large number of issues that
remain to be fixed, mainly related to overflows in implicit constant
conversion (due to shifts).


/gem5/src/arch/alpha/isa/main.isa
/gem5/src/arch/alpha/isa_traits.hh
/gem5/src/arch/alpha/types.hh
/gem5/src/arch/arm/intregs.hh
/gem5/src/arch/arm/isa/templates/neon.isa
/gem5/src/arch/arm/linux/atag.hh
/gem5/src/arch/arm/miscregs.cc
/gem5/src/arch/arm/miscregs.hh
/gem5/src/arch/arm/nativetrace.cc
/gem5/src/arch/arm/pagetable.hh
/gem5/src/arch/arm/predecoder.hh
/gem5/src/arch/arm/table_walker.hh
/gem5/src/arch/arm/utility.hh
/gem5/src/arch/arm/vtophys.hh
e820.hh
/gem5/src/arch/x86/emulenv.hh
/gem5/src/arch/x86/faults.hh
/gem5/src/arch/x86/isa/macroop.isa
/gem5/src/arch/x86/isa_traits.hh
/gem5/src/arch/x86/locked_mem.hh
/gem5/src/arch/x86/mmapped_ipr.hh
/gem5/src/arch/x86/nativetrace.cc
/gem5/src/arch/x86/predecoder.hh
/gem5/src/arch/x86/regs/float.hh
/gem5/src/arch/x86/regs/int.hh
/gem5/src/arch/x86/regs/misc.hh
/gem5/src/arch/x86/regs/segment.hh
/gem5/src/arch/x86/tlb.cc
/gem5/src/arch/x86/types.hh
/gem5/src/arch/x86/utility.hh
/gem5/src/arch/x86/vtophys.hh
/gem5/src/base/bitmap.cc
/gem5/src/base/callback.cc
/gem5/src/base/range.cc
/gem5/src/base/range_map.hh
/gem5/src/base/str.cc
/gem5/src/base/vnc/convert.hh
/gem5/src/cpu/base_dyn_inst.hh
/gem5/src/cpu/exetrace.cc
/gem5/src/cpu/inorder/inorder_dyn_inst.hh
/gem5/src/cpu/inorder/pipeline_traits.hh
/gem5/src/cpu/inorder/resource.hh
/gem5/src/cpu/inteltrace.cc
/gem5/src/cpu/o3/dyn_inst.hh
/gem5/src/cpu/o3/thread_context.hh
/gem5/src/cpu/simple_thread.hh
/gem5/src/cpu/static_inst.hh
/gem5/src/cpu/thread_context.hh
/gem5/src/cpu/thread_state.hh
/gem5/src/dev/i8254xGBe.hh
/gem5/src/dev/ide_atareg.h
/gem5/src/dev/sinicreg.hh
/gem5/src/python/m5/params.py
/gem5/src/sim/byteswap.hh
/gem5/src/sim/eventq.hh
/gem5/src/sim/serialize.hh
8852:c744483edfcf 24-Feb-2012 Andreas Hansson <andreas.hansson@arm.com>

MEM: Make port proxies use references rather than pointers

This patch is adding a clearer design intent to all objects that would
not be complete without a port proxy by making the proxies members
rathen than dynamically allocated. In essence, if NULL would not be a
valid value for the proxy, then we avoid using a pointer to make this
clear.

The same approach is used for the methods using these proxies, such as
loadSections, that now use references rather than pointers to better
reflect the fact that NULL would not be an acceptable value (in fact
the code would break and that is how this patch started out).

Overall the concept of "using a reference to express unconditional
composition where a NULL pointer is never valid" could be done on a
much broader scale throughout the code base, but for now it is only
done in the locations affected by the proxies.


/gem5/src/arch/alpha/freebsd/system.cc
/gem5/src/arch/alpha/linux/system.cc
/gem5/src/arch/alpha/linux/threadinfo.hh
/gem5/src/arch/alpha/process.cc
/gem5/src/arch/alpha/stacktrace.cc
/gem5/src/arch/alpha/system.cc
/gem5/src/arch/alpha/tru64/system.cc
/gem5/src/arch/alpha/utility.cc
/gem5/src/arch/alpha/vtophys.cc
/gem5/src/arch/alpha/vtophys.hh
/gem5/src/arch/arm/linux/process.cc
/gem5/src/arch/arm/linux/system.cc
/gem5/src/arch/arm/process.cc
/gem5/src/arch/arm/stacktrace.cc
/gem5/src/arch/arm/system.cc
/gem5/src/arch/arm/utility.cc
/gem5/src/arch/arm/vtophys.cc
/gem5/src/arch/mips/linux/threadinfo.hh
/gem5/src/arch/mips/process.cc
/gem5/src/arch/mips/stacktrace.cc
/gem5/src/arch/power/process.cc
/gem5/src/arch/sparc/process.cc
/gem5/src/arch/sparc/utility.cc
/gem5/src/arch/sparc/vtophys.cc
e820.cc
e820.hh
intelmp.cc
intelmp.hh
smbios.cc
smbios.hh
/gem5/src/arch/x86/linux/syscalls.cc
/gem5/src/arch/x86/linux/system.cc
/gem5/src/arch/x86/process.cc
/gem5/src/arch/x86/stacktrace.cc
/gem5/src/arch/x86/system.cc
/gem5/src/base/loader/elf_object.cc
/gem5/src/base/loader/elf_object.hh
/gem5/src/base/loader/hex_file.cc
/gem5/src/base/loader/hex_file.hh
/gem5/src/base/loader/object_file.cc
/gem5/src/base/loader/object_file.hh
/gem5/src/base/remote_gdb.cc
/gem5/src/cpu/checker/thread_context.hh
/gem5/src/cpu/inorder/thread_context.cc
/gem5/src/cpu/inorder/thread_context.hh
/gem5/src/cpu/o3/thread_context.hh
/gem5/src/cpu/o3/thread_context_impl.hh
/gem5/src/cpu/ozone/cpu.hh
/gem5/src/cpu/simple_thread.hh
/gem5/src/cpu/thread_context.hh
/gem5/src/cpu/thread_state.cc
/gem5/src/cpu/thread_state.hh
/gem5/src/dev/simple_disk.cc
/gem5/src/kern/tru64/tru64.hh
/gem5/src/mem/fs_translating_port_proxy.cc
/gem5/src/mem/se_translating_port_proxy.hh
/gem5/src/sim/process.cc
/gem5/src/sim/process.hh
/gem5/src/sim/process_impl.hh
/gem5/src/sim/syscall_emul.cc
/gem5/src/sim/syscall_emul.hh
/gem5/src/sim/system.cc
/gem5/src/sim/system.hh
/gem5/src/sim/vptr.hh
8768:314eb1e2fa94 30-Oct-2011 Gabe Black <gblack@eecs.umich.edu>

X86: Get rid of more uses of FULL_SYSTEM.

8737:770ccf3af571 31-Jan-2012 Koan-Sin Tan <koansin.tan@gmail.com>

clang: Enable compiling gem5 using clang 2.9 and 3.0

This patch adds the necessary flags to the SConstruct and SConscript
files for compiling using clang 2.9 and later (on Ubuntu et al and OSX
XCode 4.2), and also cleans up a bunch of compiler warnings found by
clang. Most of the warnings are related to hidden virtual functions,
comparisons with unsigneds >= 0, and if-statements with empty
bodies. A number of mismatches between struct and class are also
fixed. clang 2.8 is not working as it has problems with class names
that occur in multiple namespaces (e.g. Statistics in
kernel_stats.hh).

clang has a bug (http://llvm.org/bugs/show_bug.cgi?id=7247) which
causes confusion between the container std::set and the function
Packet::set, and this is currently addressed by not including the
entire namespace std, but rather selecting e.g. "using std::vector" in
the appropriate places.


/gem5/SConstruct
/gem5/ext/libelf/SConscript
/gem5/src/SConscript
/gem5/src/arch/alpha/tlb.cc
/gem5/src/arch/alpha/tlb.hh
/gem5/src/arch/arm/insts/static_inst.hh
/gem5/src/arch/arm/insts/vfp.hh
/gem5/src/arch/arm/isa/templates/basic.isa
/gem5/src/arch/arm/miscregs.cc
/gem5/src/arch/generic/memhelpers.hh
/gem5/src/arch/mips/faults.cc
/gem5/src/arch/mips/faults.hh
acpi.hh
intelmp.cc
intelmp.hh
smbios.hh
/gem5/src/base/fast_alloc.cc
/gem5/src/base/range_map.hh
/gem5/src/base/remote_gdb.hh
/gem5/src/base/stl_helpers.hh
/gem5/src/cpu/base.cc
/gem5/src/cpu/base.hh
/gem5/src/cpu/func_unit.hh
/gem5/src/cpu/inorder/cpu.cc
/gem5/src/cpu/inorder/cpu.hh
/gem5/src/cpu/inorder/resource.cc
/gem5/src/cpu/inorder/resource.hh
/gem5/src/cpu/inorder/resource_pool.cc
/gem5/src/cpu/inorder/resource_pool.hh
/gem5/src/cpu/inorder/resources/cache_unit.hh
/gem5/src/cpu/inorder/thread_context.cc
/gem5/src/cpu/nativetrace.hh
/gem5/src/cpu/o3/bpred_unit.hh
/gem5/src/cpu/o3/commit.hh
/gem5/src/cpu/o3/cpu.cc
/gem5/src/cpu/o3/cpu.hh
/gem5/src/cpu/o3/decode.hh
/gem5/src/cpu/o3/decode_impl.hh
/gem5/src/cpu/o3/fetch.hh
/gem5/src/cpu/o3/fu_pool.cc
/gem5/src/cpu/o3/fu_pool.hh
/gem5/src/cpu/o3/iew.hh
/gem5/src/cpu/o3/iew_impl.hh
/gem5/src/cpu/o3/inst_queue.hh
/gem5/src/cpu/o3/inst_queue_impl.hh
/gem5/src/cpu/o3/lsq.hh
/gem5/src/cpu/o3/lsq_unit.hh
/gem5/src/cpu/o3/mem_dep_unit.cc
/gem5/src/cpu/o3/mem_dep_unit.hh
/gem5/src/cpu/o3/rename.hh
/gem5/src/cpu/o3/sat_counter.hh
/gem5/src/cpu/quiesce_event.hh
/gem5/src/cpu/sched_list.hh
/gem5/src/cpu/simple/atomic.cc
/gem5/src/cpu/simple/atomic.hh
/gem5/src/cpu/simple/base.cc
/gem5/src/cpu/simple/base.hh
/gem5/src/cpu/simple/timing.cc
/gem5/src/cpu/simple/timing.hh
/gem5/src/cpu/static_inst.hh
/gem5/src/dev/alpha/tsunami_cchip.cc
/gem5/src/dev/alpha/tsunami_io.cc
/gem5/src/dev/arm/pl111.cc
/gem5/src/dev/arm/pl111.hh
/gem5/src/dev/copy_engine.cc
/gem5/src/dev/disk_image.cc
/gem5/src/dev/disk_image.hh
/gem5/src/dev/ide_ctrl.cc
/gem5/src/dev/ns_gige.cc
/gem5/src/dev/pciconfigall.cc
/gem5/src/dev/pcidev.cc
/gem5/src/mem/cache/base.hh
/gem5/src/mem/cache/tags/iic.cc
/gem5/src/mem/cache/tags/iic_repl/gen.cc
/gem5/src/mem/cache/tags/iic_repl/gen.hh
/gem5/src/mem/cache/tags/iic_repl/repl.hh
/gem5/src/mem/packet.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc
/gem5/src/mem/ruby/system/Sequencer.hh
/gem5/src/python/m5/SimObject.py
/gem5/src/sim/core.hh
/gem5/src/sim/process.cc
/gem5/src/sim/process.hh
/gem5/src/sim/process_impl.hh
/gem5/src/sim/serialize.cc
/gem5/src/sim/sim_object.cc
/gem5/src/sim/sim_object.hh
/gem5/src/sim/syscall_emul.hh
8706:b1838faf3bcc 17-Jan-2012 Andreas Hansson <andreas.hansson@arm.com>

MEM: Add port proxies instead of non-structural ports

Port proxies are used to replace non-structural ports, and thus enable
all ports in the system to correspond to a structural entity. This has
the advantage of accessing memory through the normal memory subsystem
and thus allowing any constellation of distributed memories, address
maps, etc. Most accesses are done through the "system port" that is
used for loading binaries, debugging etc. For the entities that belong
to the CPU, e.g. threads and thread contexts, they wrap the CPU data
port in a port proxy.

The following replacements are made:
FunctionalPort > PortProxy
TranslatingPort > SETranslatingPortProxy
VirtualPort > FSTranslatingPortProxy


/gem5/configs/common/FSConfig.py
/gem5/configs/example/se.py
/gem5/configs/ruby/Ruby.py
/gem5/src/arch/alpha/freebsd/system.cc
/gem5/src/arch/alpha/linux/process.cc
/gem5/src/arch/alpha/linux/system.cc
/gem5/src/arch/alpha/linux/system.hh
/gem5/src/arch/alpha/linux/threadinfo.hh
/gem5/src/arch/alpha/remote_gdb.cc
/gem5/src/arch/alpha/stacktrace.cc
/gem5/src/arch/alpha/system.cc
/gem5/src/arch/alpha/system.hh
/gem5/src/arch/alpha/tru64/process.cc
/gem5/src/arch/alpha/tru64/system.cc
/gem5/src/arch/alpha/utility.cc
/gem5/src/arch/alpha/vtophys.cc
/gem5/src/arch/alpha/vtophys.hh
/gem5/src/arch/arm/linux/process.cc
/gem5/src/arch/arm/linux/system.cc
/gem5/src/arch/arm/process.cc
/gem5/src/arch/arm/stacktrace.cc
/gem5/src/arch/arm/system.cc
/gem5/src/arch/arm/system.hh
/gem5/src/arch/arm/utility.cc
/gem5/src/arch/arm/vtophys.cc
/gem5/src/arch/mips/linux/process.cc
/gem5/src/arch/mips/linux/system.cc
/gem5/src/arch/mips/linux/threadinfo.hh
/gem5/src/arch/mips/stacktrace.cc
/gem5/src/arch/mips/utility.cc
/gem5/src/arch/power/linux/process.cc
/gem5/src/arch/power/process.cc
/gem5/src/arch/sparc/linux/syscalls.cc
/gem5/src/arch/sparc/process.cc
/gem5/src/arch/sparc/solaris/process.cc
/gem5/src/arch/sparc/system.cc
/gem5/src/arch/sparc/system.hh
/gem5/src/arch/sparc/utility.cc
/gem5/src/arch/sparc/vtophys.cc
intelmp.cc
intelmp.hh
smbios.cc
smbios.hh
/gem5/src/arch/x86/linux/syscalls.cc
/gem5/src/arch/x86/linux/system.cc
/gem5/src/arch/x86/process.cc
/gem5/src/arch/x86/stacktrace.cc
/gem5/src/arch/x86/system.cc
/gem5/src/base/loader/elf_object.cc
/gem5/src/base/loader/elf_object.hh
/gem5/src/base/loader/hex_file.cc
/gem5/src/base/loader/hex_file.hh
/gem5/src/base/loader/object_file.cc
/gem5/src/base/loader/object_file.hh
/gem5/src/base/remote_gdb.cc
/gem5/src/cpu/checker/thread_context.hh
/gem5/src/cpu/inorder/cpu.cc
/gem5/src/cpu/inorder/cpu.hh
/gem5/src/cpu/inorder/resources/cache_unit.cc
/gem5/src/cpu/inorder/resources/cache_unit.hh
/gem5/src/cpu/inorder/thread_context.cc
/gem5/src/cpu/inorder/thread_context.hh
/gem5/src/cpu/o3/cpu.cc
/gem5/src/cpu/o3/cpu.hh
/gem5/src/cpu/o3/lsq.hh
/gem5/src/cpu/o3/lsq_impl.hh
/gem5/src/cpu/o3/thread_context.hh
/gem5/src/cpu/o3/thread_context_impl.hh
/gem5/src/cpu/ozone/cpu.hh
/gem5/src/cpu/ozone/cpu_impl.hh
/gem5/src/cpu/simple/atomic.cc
/gem5/src/cpu/simple/atomic.hh
/gem5/src/cpu/simple/timing.cc
/gem5/src/cpu/simple/timing.hh
/gem5/src/cpu/simple_thread.cc
/gem5/src/cpu/simple_thread.hh
/gem5/src/cpu/thread_context.hh
/gem5/src/cpu/thread_state.cc
/gem5/src/cpu/thread_state.hh
/gem5/src/dev/simple_disk.cc
/gem5/src/kern/tru64/tru64.hh
/gem5/src/kern/tru64/tru64_events.cc
/gem5/src/mem/SConscript
/gem5/src/mem/fs_translating_port_proxy.cc
/gem5/src/mem/fs_translating_port_proxy.hh
/gem5/src/mem/port.hh
/gem5/src/mem/port_impl.hh
/gem5/src/mem/port_proxy.hh
/gem5/src/mem/ruby/system/RubyPort.cc
/gem5/src/mem/ruby/system/RubyPortProxy.cc
/gem5/src/mem/ruby/system/RubyPortProxy.hh
/gem5/src/mem/ruby/system/SConscript
/gem5/src/mem/ruby/system/Sequencer.py
/gem5/src/mem/se_translating_port_proxy.cc
/gem5/src/mem/se_translating_port_proxy.hh
/gem5/src/mem/translating_port.cc
/gem5/src/mem/translating_port.hh
/gem5/src/mem/vport.cc
/gem5/src/mem/vport.hh
/gem5/src/sim/arguments.hh
/gem5/src/sim/process.cc
/gem5/src/sim/process.hh
/gem5/src/sim/process_impl.hh
/gem5/src/sim/syscall_emul.cc
/gem5/src/sim/syscall_emul.hh
/gem5/src/sim/system.cc
/gem5/src/sim/system.hh
/gem5/src/sim/vptr.hh
/gem5/tests/configs/inorder-timing.py
/gem5/tests/configs/memtest-ruby.py
/gem5/tests/configs/memtest.py
/gem5/tests/configs/o3-timing-mp.py
/gem5/tests/configs/o3-timing.py
/gem5/tests/configs/rubytest-ruby.py
/gem5/tests/configs/simple-atomic-mp.py
/gem5/tests/configs/simple-atomic.py
/gem5/tests/configs/simple-timing-mp-ruby.py
/gem5/tests/configs/simple-timing-mp.py
/gem5/tests/configs/simple-timing-ruby.py
/gem5/tests/configs/simple-timing.py
8323:fd20dcf1a9aa 23-May-2011 Steve Reinhardt <steve.reinhardt@amd.com>

config: revamp x86 config to avoid appending to SimObjectVectors
A significant contributor to the need for adoptOrphanParams()
is the practice of appending to SimObjectVectors which have
already been assigned as children. This practice sidesteps the
assignment operation for those appended SimObjects, which is
where parent/child relationships are typically established.

This patch reworks the config scripts that use append() on
SimObjectVectors, which all happen to be in the x86 system
configuration. At some point in the future, I hope to make
SimObjectVectors immutable (by deriving from tuple rather than
list), at which time this patch will be necessary for correct
operation. For now, it just avoids some of the warning
messages that get printed in adoptOrphanParams().

8229:78bf55f23338 15-Apr-2011 Nathan Binkert <nate@binkert.org>

includes: sort all includes


/gem5/src/arch/alpha/faults.cc
/gem5/src/arch/alpha/isa.hh
/gem5/src/arch/alpha/isa/main.isa
/gem5/src/arch/alpha/linux/system.cc
/gem5/src/arch/alpha/mt.hh
/gem5/src/arch/alpha/process.cc
/gem5/src/arch/alpha/remote_gdb.cc
/gem5/src/arch/alpha/remote_gdb.hh
/gem5/src/arch/alpha/tlb.cc
/gem5/src/arch/alpha/tru64/process.cc
/gem5/src/arch/alpha/types.hh
/gem5/src/arch/alpha/utility.hh
/gem5/src/arch/arm/faults.cc
/gem5/src/arch/arm/faults.hh
/gem5/src/arch/arm/insts/macromem.cc
/gem5/src/arch/arm/insts/static_inst.cc
/gem5/src/arch/arm/insts/vfp.hh
/gem5/src/arch/arm/intregs.hh
/gem5/src/arch/arm/isa/includes.isa
/gem5/src/arch/arm/linux/atag.hh
/gem5/src/arch/arm/linux/linux.cc
/gem5/src/arch/arm/linux/process.cc
/gem5/src/arch/arm/linux/process.hh
/gem5/src/arch/arm/linux/system.cc
/gem5/src/arch/arm/locked_mem.hh
/gem5/src/arch/arm/pagetable.hh
/gem5/src/arch/arm/predecoder.hh
/gem5/src/arch/arm/process.hh
/gem5/src/arch/arm/registers.hh
/gem5/src/arch/arm/remote_gdb.cc
/gem5/src/arch/arm/system.cc
/gem5/src/arch/arm/system.hh
/gem5/src/arch/arm/table_walker.cc
/gem5/src/arch/arm/table_walker.hh
/gem5/src/arch/arm/tlb.hh
/gem5/src/arch/arm/vtophys.hh
/gem5/src/arch/generic/debugfaults.hh
/gem5/src/arch/generic/types.hh
/gem5/src/arch/mips/dsp.cc
/gem5/src/arch/mips/dsp.hh
/gem5/src/arch/mips/isa.cc
/gem5/src/arch/mips/isa.hh
/gem5/src/arch/mips/isa/includes.isa
/gem5/src/arch/mips/isa_traits.hh
/gem5/src/arch/mips/linux/linux.cc
/gem5/src/arch/mips/linux/process.cc
/gem5/src/arch/mips/linux/process.hh
/gem5/src/arch/mips/linux/system.cc
/gem5/src/arch/mips/mt.hh
/gem5/src/arch/mips/process.cc
/gem5/src/arch/mips/process.hh
/gem5/src/arch/mips/system.cc
/gem5/src/arch/mips/system.hh
/gem5/src/arch/mips/tlb.cc
/gem5/src/arch/mips/tlb.hh
/gem5/src/arch/mips/utility.cc
/gem5/src/arch/mips/utility.hh
/gem5/src/arch/mips/vtophys.hh
/gem5/src/arch/power/insts/floating.hh
/gem5/src/arch/power/insts/integer.hh
/gem5/src/arch/power/isa/includes.isa
/gem5/src/arch/power/linux/linux.cc
/gem5/src/arch/power/linux/process.cc
/gem5/src/arch/power/linux/process.hh
/gem5/src/arch/power/process.hh
/gem5/src/arch/power/tlb.hh
/gem5/src/arch/power/vtophys.hh
/gem5/src/arch/sparc/isa.hh
/gem5/src/arch/sparc/isa/includes.isa
/gem5/src/arch/sparc/isa_traits.hh
/gem5/src/arch/sparc/linux/linux.cc
/gem5/src/arch/sparc/linux/process.cc
/gem5/src/arch/sparc/locked_mem.hh
/gem5/src/arch/sparc/mmapped_ipr.hh
/gem5/src/arch/sparc/nativetrace.cc
/gem5/src/arch/sparc/process.cc
/gem5/src/arch/sparc/process.hh
/gem5/src/arch/sparc/remote_gdb.cc
/gem5/src/arch/sparc/remote_gdb.hh
/gem5/src/arch/sparc/solaris/process.cc
/gem5/src/arch/sparc/solaris/solaris.cc
/gem5/src/arch/sparc/system.cc
/gem5/src/arch/sparc/tlb.cc
/gem5/src/arch/sparc/tlb_map.hh
/gem5/src/arch/sparc/types.hh
/gem5/src/arch/sparc/utility.hh
/gem5/src/arch/sparc/vtophys.cc
acpi.cc
intelmp.hh
/gem5/src/arch/x86/emulenv.hh
/gem5/src/arch/x86/faults.hh
/gem5/src/arch/x86/insts/badmicroop.cc
/gem5/src/arch/x86/insts/macroop.hh
/gem5/src/arch/x86/insts/microfpop.cc
/gem5/src/arch/x86/insts/microldstop.cc
/gem5/src/arch/x86/insts/micromediaop.cc
/gem5/src/arch/x86/interrupts.cc
/gem5/src/arch/x86/interrupts.hh
/gem5/src/arch/x86/isa.hh
/gem5/src/arch/x86/isa/includes.isa
/gem5/src/arch/x86/linux/linux.cc
/gem5/src/arch/x86/linux/process.cc
/gem5/src/arch/x86/linux/process.hh
/gem5/src/arch/x86/linux/syscalls.cc
/gem5/src/arch/x86/linux/system.cc
/gem5/src/arch/x86/linux/system.hh
/gem5/src/arch/x86/microcode_rom.hh
/gem5/src/arch/x86/nativetrace.cc
/gem5/src/arch/x86/pagetable_walker.cc
/gem5/src/arch/x86/pagetable_walker.hh
/gem5/src/arch/x86/predecoder.hh
/gem5/src/arch/x86/process.cc
/gem5/src/arch/x86/process.hh
/gem5/src/arch/x86/registers.hh
/gem5/src/arch/x86/remote_gdb.cc
/gem5/src/arch/x86/system.cc
/gem5/src/arch/x86/tlb.cc
/gem5/src/arch/x86/tlb.hh
/gem5/src/base/cp_annotate.cc
/gem5/src/base/cp_annotate.hh
/gem5/src/base/cprintf.hh
/gem5/src/base/debug.cc
/gem5/src/base/fast_alloc.hh
/gem5/src/base/fenv.c
/gem5/src/base/hostinfo.cc
/gem5/src/base/inet.hh
/gem5/src/base/inifile.cc
/gem5/src/base/loader/aout_object.cc
/gem5/src/base/loader/elf_object.cc
/gem5/src/base/loader/elf_object.hh
/gem5/src/base/loader/hex_file.cc
/gem5/src/base/loader/object_file.cc
/gem5/src/base/loader/symtab.cc
/gem5/src/base/misc.cc
/gem5/src/base/mysql.hh
/gem5/src/base/output.cc
/gem5/src/base/pollevent.cc
/gem5/src/base/pollevent.hh
/gem5/src/base/range_map.hh
/gem5/src/base/remote_gdb.cc
/gem5/src/base/remote_gdb.hh
/gem5/src/base/socket.cc
/gem5/src/base/statistics.cc
/gem5/src/base/statistics.hh
/gem5/src/base/stats/info.hh
/gem5/src/base/stats/mysql.cc
/gem5/src/base/stats/output.cc
/gem5/src/base/stats/text.cc
/gem5/src/base/stats/text.hh
/gem5/src/base/str.hh
/gem5/src/base/time.hh
/gem5/src/base/trace.cc
/gem5/src/base/vnc/convert.cc
/gem5/src/base/vnc/vncserver.cc
/gem5/src/base/vnc/vncserver.hh
/gem5/src/cpu/activity.cc
/gem5/src/cpu/activity.hh
/gem5/src/cpu/base.cc
/gem5/src/cpu/base.hh
/gem5/src/cpu/base_dyn_inst_impl.hh
/gem5/src/cpu/checker/cpu.cc
/gem5/src/cpu/checker/cpu.hh
/gem5/src/cpu/checker/cpu_impl.hh
/gem5/src/cpu/cpuevent.hh
/gem5/src/cpu/exetrace.cc
/gem5/src/cpu/func_unit.hh
/gem5/src/cpu/inorder/cpu.cc
/gem5/src/cpu/inorder/cpu.hh
/gem5/src/cpu/inorder/first_stage.cc
/gem5/src/cpu/inorder/first_stage.hh
/gem5/src/cpu/inorder/inorder_cpu_builder.cc
/gem5/src/cpu/inorder/inorder_dyn_inst.cc
/gem5/src/cpu/inorder/inorder_dyn_inst.hh
/gem5/src/cpu/inorder/inorder_trace.cc
/gem5/src/cpu/inorder/pipeline_stage.cc
/gem5/src/cpu/inorder/pipeline_stage.hh
/gem5/src/cpu/inorder/pipeline_traits.5stage.cc
/gem5/src/cpu/inorder/pipeline_traits.5stage.hh
/gem5/src/cpu/inorder/pipeline_traits.9stage.cc
/gem5/src/cpu/inorder/pipeline_traits.9stage.hh
/gem5/src/cpu/inorder/pipeline_traits.9stage.smt2.cc
/gem5/src/cpu/inorder/pipeline_traits.9stage.smt2.hh
/gem5/src/cpu/inorder/pipeline_traits.hh
/gem5/src/cpu/inorder/reg_dep_map.cc
/gem5/src/cpu/inorder/resource.cc
/gem5/src/cpu/inorder/resource.hh
/gem5/src/cpu/inorder/resource_pool.9stage.cc
/gem5/src/cpu/inorder/resource_pool.cc
/gem5/src/cpu/inorder/resource_pool.hh
/gem5/src/cpu/inorder/resource_sked.cc
/gem5/src/cpu/inorder/resource_sked.hh
/gem5/src/cpu/inorder/resources/agen_unit.hh
/gem5/src/cpu/inorder/resources/bpred_unit.hh
/gem5/src/cpu/inorder/resources/branch_predictor.hh
/gem5/src/cpu/inorder/resources/cache_unit.cc
/gem5/src/cpu/inorder/resources/cache_unit.hh
/gem5/src/cpu/inorder/resources/decode_unit.hh
/gem5/src/cpu/inorder/resources/execution_unit.cc
/gem5/src/cpu/inorder/resources/execution_unit.hh
/gem5/src/cpu/inorder/resources/fetch_seq_unit.hh
/gem5/src/cpu/inorder/resources/fetch_unit.cc
/gem5/src/cpu/inorder/resources/fetch_unit.hh
/gem5/src/cpu/inorder/resources/graduation_unit.hh
/gem5/src/cpu/inorder/resources/inst_buffer.cc
/gem5/src/cpu/inorder/resources/inst_buffer.hh
/gem5/src/cpu/inorder/resources/mem_dep_unit.hh
/gem5/src/cpu/inorder/resources/mult_div_unit.cc
/gem5/src/cpu/inorder/resources/mult_div_unit.hh
/gem5/src/cpu/inorder/resources/resource_list.hh
/gem5/src/cpu/inorder/resources/tlb_unit.cc
/gem5/src/cpu/inorder/resources/tlb_unit.hh
/gem5/src/cpu/inorder/resources/use_def.cc
/gem5/src/cpu/inorder/resources/use_def.hh
/gem5/src/cpu/inorder/thread_context.cc
/gem5/src/cpu/inorder/thread_context.hh
/gem5/src/cpu/inorder/thread_state.cc
/gem5/src/cpu/intr_control.cc
/gem5/src/cpu/intr_control.hh
/gem5/src/cpu/nativetrace.hh
/gem5/src/cpu/o3/base_dyn_inst.cc
/gem5/src/cpu/o3/bpred_unit.hh
/gem5/src/cpu/o3/bpred_unit_impl.hh
/gem5/src/cpu/o3/checker_builder.cc
/gem5/src/cpu/o3/commit.cc
/gem5/src/cpu/o3/commit.hh
/gem5/src/cpu/o3/commit_impl.hh
/gem5/src/cpu/o3/cpu.cc
/gem5/src/cpu/o3/cpu.hh
/gem5/src/cpu/o3/cpu_policy.hh
/gem5/src/cpu/o3/decode.cc
/gem5/src/cpu/o3/dyn_inst.hh
/gem5/src/cpu/o3/fetch.cc
/gem5/src/cpu/o3/fetch.hh
/gem5/src/cpu/o3/fetch_impl.hh
/gem5/src/cpu/o3/free_list.cc
/gem5/src/cpu/o3/fu_pool.hh
/gem5/src/cpu/o3/iew.cc
/gem5/src/cpu/o3/iew.hh
/gem5/src/cpu/o3/iew_impl.hh
/gem5/src/cpu/o3/impl.hh
/gem5/src/cpu/o3/inst_queue.cc
/gem5/src/cpu/o3/inst_queue.hh
/gem5/src/cpu/o3/isa_specific.hh
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/gem5/src/dev/sparc/mm_disk.cc
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/gem5/src/dev/terminal.cc
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/gem5/src/dev/x86/i8042.hh
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/gem5/src/kern/tru64/dump_mbuf.cc
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/gem5/src/mem/packet.cc
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/gem5/src/mem/page_table.cc
/gem5/src/mem/physical.cc
/gem5/src/mem/ruby/buffers/MessageBuffer.hh
/gem5/src/mem/ruby/common/NetDest.cc
/gem5/src/mem/ruby/common/Set.hh
/gem5/src/mem/ruby/filters/GenericBloomFilter.hh
/gem5/src/mem/ruby/network/Network.cc
/gem5/src/mem/ruby/network/garnet/BaseGarnetNetwork.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/OutVcState_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/OutVcState_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/RoutingUnit_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/RoutingUnit_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/SWallocator_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/SWallocator_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/VCallocator_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/VCallocator_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/VirtualChannel_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/flitBuffer_d.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/FlexibleConsumer.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/Router.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/Router.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/VCarbiter.cc
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/gem5/src/mem/ruby/network/garnet/flexible-pipeline/flitBuffer.hh
/gem5/src/mem/ruby/network/orion/Allocator/Arbiter.cc
/gem5/src/mem/ruby/network/orion/Allocator/MatrixArbiter.hh
/gem5/src/mem/ruby/network/orion/Allocator/RRArbiter.cc
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/gem5/src/mem/ruby/network/orion/Allocator/SWAllocator.cc
/gem5/src/mem/ruby/network/orion/Allocator/VCAllocator.cc
/gem5/src/mem/ruby/network/orion/Buffer/Buffer.cc
/gem5/src/mem/ruby/network/orion/Buffer/DecoderUnit.hh
/gem5/src/mem/ruby/network/orion/Buffer/OutdrvUnit.cc
/gem5/src/mem/ruby/network/orion/Buffer/PrechargeUnit.cc
/gem5/src/mem/ruby/network/orion/Buffer/Register.cc
/gem5/src/mem/ruby/network/orion/Buffer/SRAM.cc
/gem5/src/mem/ruby/network/orion/Buffer/SRAM.hh
/gem5/src/mem/ruby/network/orion/Buffer/WordlineUnit.cc
/gem5/src/mem/ruby/network/orion/Clock.cc
/gem5/src/mem/ruby/network/orion/ConfigFile.hh
/gem5/src/mem/ruby/network/orion/Crossbar/Crossbar.cc
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/gem5/src/mem/ruby/network/orion/FlipFlop.cc
/gem5/src/mem/ruby/network/orion/NetworkPower.cc
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/gem5/src/mem/ruby/network/orion/OrionConfig.cc
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/gem5/src/mem/ruby/network/orion/OrionLink.cc
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/gem5/src/mem/ruby/network/orion/TechParameter.cc
/gem5/src/mem/ruby/network/orion/Wire.cc
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/gem5/src/mem/ruby/system/CacheMemory.hh
/gem5/src/mem/ruby/system/RubyPort.cc
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/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/Sequencer.hh
/gem5/src/mem/ruby/system/WireBuffer.hh
/gem5/src/mem/slicc/symbols/StateMachine.py
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/gem5/src/mem/translating_port.cc
/gem5/src/mem/vport.hh
/gem5/src/python/swig/core.i
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/gem5/src/python/swig/sim_object.i
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/gem5/src/python/swig/system.i
/gem5/src/sim/faults.cc
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/gem5/src/sim/init.cc
/gem5/src/sim/process.cc
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/gem5/src/sim/pseudo_inst.cc
/gem5/src/sim/serialize.cc
/gem5/src/sim/serialize.hh
/gem5/src/sim/stat_control.cc
/gem5/src/sim/syscall_emul.cc
/gem5/src/sim/syscall_emul.hh
/gem5/src/sim/system.cc
/gem5/src/sim/tlb.cc
/gem5/src/sim/vptr.hh
/gem5/src/unittest/cprintftest.cc
/gem5/src/unittest/cprintftime.cc
/gem5/src/unittest/initest.cc
/gem5/src/unittest/rangemaptest.cc
/gem5/src/unittest/stattest.cc
/gem5/src/unittest/symtest.cc
/gem5/util/ccdrv/devtime.c
/gem5/util/m5/m5.c
/gem5/util/statetrace/arch/amd64/tracechild.cc
/gem5/util/statetrace/arch/amd64/tracechild.hh
/gem5/util/statetrace/arch/arm/tracechild.cc
/gem5/util/statetrace/arch/arm/tracechild.hh
/gem5/util/statetrace/arch/i686/tracechild.cc
/gem5/util/statetrace/arch/i686/tracechild.hh
/gem5/util/statetrace/arch/sparc/tracechild.cc
/gem5/util/statetrace/arch/sparc/tracechild.hh
/gem5/util/statetrace/base/regstate.hh
/gem5/util/statetrace/base/statetrace.cc
/gem5/util/statetrace/base/tracechild.cc
/gem5/util/tap/tap.cc
/gem5/util/term/term.c
7799:5d0f62927d75 20-Dec-2010 Gabe Black <gblack@eecs.umich.edu>

Style: Replace some tabs with spaces.

7088:84bd4089958b 25-May-2010 Nathan Binkert <nate@binkert.org>

x86: put back code that I accidentally deleted

7087:fb8d5786ff30 24-May-2010 Nathan Binkert <nate@binkert.org>

copyright: Change HP copyright on x86 code to be more friendly


/gem5/src/arch/x86/SConscript
/gem5/src/arch/x86/X86System.py
/gem5/src/arch/x86/X86TLB.py
/gem5/src/arch/x86/arguments.hh
ACPI.py
E820.py
IntelMP.py
SConscript
SMBios.py
acpi.cc
acpi.hh
e820.cc
e820.hh
intelmp.cc
intelmp.hh
smbios.cc
smbios.hh
/gem5/src/arch/x86/emulenv.cc
/gem5/src/arch/x86/emulenv.hh
/gem5/src/arch/x86/faults.cc
/gem5/src/arch/x86/faults.hh
/gem5/src/arch/x86/floatregs.hh
/gem5/src/arch/x86/insts/macroop.hh
/gem5/src/arch/x86/insts/microfpop.cc
/gem5/src/arch/x86/insts/microfpop.hh
/gem5/src/arch/x86/insts/microldstop.cc
/gem5/src/arch/x86/insts/microldstop.hh
/gem5/src/arch/x86/insts/microop.cc
/gem5/src/arch/x86/insts/microop.hh
/gem5/src/arch/x86/insts/microregop.cc
/gem5/src/arch/x86/insts/microregop.hh
/gem5/src/arch/x86/insts/static_inst.cc
/gem5/src/arch/x86/insts/static_inst.hh
/gem5/src/arch/x86/interrupts.cc
/gem5/src/arch/x86/interrupts.hh
/gem5/src/arch/x86/intregs.hh
/gem5/src/arch/x86/isa/bitfields.isa
/gem5/src/arch/x86/isa/decoder/decoder.isa
/gem5/src/arch/x86/isa/decoder/one_byte_opcodes.isa
/gem5/src/arch/x86/isa/decoder/two_byte_opcodes.isa
/gem5/src/arch/x86/isa/decoder/x87.isa
/gem5/src/arch/x86/isa/formats/basic.isa
/gem5/src/arch/x86/isa/formats/cpuid.isa
/gem5/src/arch/x86/isa/formats/error.isa
/gem5/src/arch/x86/isa/formats/formats.isa
/gem5/src/arch/x86/isa/formats/multi.isa
/gem5/src/arch/x86/isa/formats/string.isa
/gem5/src/arch/x86/isa/formats/syscall.isa
/gem5/src/arch/x86/isa/formats/unimp.isa
/gem5/src/arch/x86/isa/formats/unknown.isa
/gem5/src/arch/x86/isa/includes.isa
/gem5/src/arch/x86/isa/insts/__init__.py
/gem5/src/arch/x86/isa/insts/general_purpose/__init__.py
/gem5/src/arch/x86/isa/insts/general_purpose/arithmetic/__init__.py
/gem5/src/arch/x86/isa/insts/general_purpose/arithmetic/add_and_subtract.py
/gem5/src/arch/x86/isa/insts/general_purpose/arithmetic/increment_and_decrement.py
/gem5/src/arch/x86/isa/insts/general_purpose/arithmetic/multiply_and_divide.py
/gem5/src/arch/x86/isa/insts/general_purpose/cache_and_memory_management.py
/gem5/src/arch/x86/isa/insts/general_purpose/compare_and_test/__init__.py
/gem5/src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_scan.py
/gem5/src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_test.py
/gem5/src/arch/x86/isa/insts/general_purpose/compare_and_test/bounds.py
/gem5/src/arch/x86/isa/insts/general_purpose/compare_and_test/compare.py
/gem5/src/arch/x86/isa/insts/general_purpose/compare_and_test/set_byte_on_condition.py
/gem5/src/arch/x86/isa/insts/general_purpose/compare_and_test/test.py
/gem5/src/arch/x86/isa/insts/general_purpose/control_transfer/__init__.py
/gem5/src/arch/x86/isa/insts/general_purpose/control_transfer/call.py
/gem5/src/arch/x86/isa/insts/general_purpose/control_transfer/conditional_jump.py
/gem5/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py
/gem5/src/arch/x86/isa/insts/general_purpose/control_transfer/jump.py
/gem5/src/arch/x86/isa/insts/general_purpose/control_transfer/loop.py
/gem5/src/arch/x86/isa/insts/general_purpose/control_transfer/xreturn.py
/gem5/src/arch/x86/isa/insts/general_purpose/data_conversion/__init__.py
/gem5/src/arch/x86/isa/insts/general_purpose/data_conversion/ascii_adjust.py
/gem5/src/arch/x86/isa/insts/general_purpose/data_conversion/bcd_adjust.py
/gem5/src/arch/x86/isa/insts/general_purpose/data_conversion/endian_conversion.py
/gem5/src/arch/x86/isa/insts/general_purpose/data_conversion/extract_sign_mask.py
/gem5/src/arch/x86/isa/insts/general_purpose/data_conversion/sign_extension.py
/gem5/src/arch/x86/isa/insts/general_purpose/data_conversion/translate.py
/gem5/src/arch/x86/isa/insts/general_purpose/data_transfer/__init__.py
/gem5/src/arch/x86/isa/insts/general_purpose/data_transfer/conditional_move.py
/gem5/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py
/gem5/src/arch/x86/isa/insts/general_purpose/data_transfer/stack_operations.py
/gem5/src/arch/x86/isa/insts/general_purpose/data_transfer/xchg.py
/gem5/src/arch/x86/isa/insts/general_purpose/flags/__init__.py
/gem5/src/arch/x86/isa/insts/general_purpose/flags/load_and_store.py
/gem5/src/arch/x86/isa/insts/general_purpose/flags/push_and_pop.py
/gem5/src/arch/x86/isa/insts/general_purpose/flags/set_and_clear.py
/gem5/src/arch/x86/isa/insts/general_purpose/input_output/__init__.py
/gem5/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py
/gem5/src/arch/x86/isa/insts/general_purpose/input_output/string_io.py
/gem5/src/arch/x86/isa/insts/general_purpose/load_effective_address.py
/gem5/src/arch/x86/isa/insts/general_purpose/load_segment_registers.py
/gem5/src/arch/x86/isa/insts/general_purpose/logical.py
/gem5/src/arch/x86/isa/insts/general_purpose/no_operation.py
/gem5/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/__init__.py
/gem5/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/rotate.py
/gem5/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/shift.py
/gem5/src/arch/x86/isa/insts/general_purpose/semaphores.py
/gem5/src/arch/x86/isa/insts/general_purpose/string/__init__.py
/gem5/src/arch/x86/isa/insts/general_purpose/string/compare_strings.py
/gem5/src/arch/x86/isa/insts/general_purpose/string/load_string.py
/gem5/src/arch/x86/isa/insts/general_purpose/string/move_string.py
/gem5/src/arch/x86/isa/insts/general_purpose/string/scan_string.py
/gem5/src/arch/x86/isa/insts/general_purpose/string/store_string.py
/gem5/src/arch/x86/isa/insts/general_purpose/system_calls.py
/gem5/src/arch/x86/isa/insts/simd128/__init__.py
/gem5/src/arch/x86/isa/insts/simd128/floating_point/__init__.py
/gem5/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/__init__.py
/gem5/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/addition.py
/gem5/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/division.py
/gem5/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/horizontal_addition.py
/gem5/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/horizontal_subtraction.py
/gem5/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/multiplication.py
/gem5/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/reciprocal_estimation.py
/gem5/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/reciprocal_square_root.py
/gem5/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/simultaneous_addition_and_subtraction.py
/gem5/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/square_root.py
/gem5/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/subtraction.py
/gem5/src/arch/x86/isa/insts/simd128/floating_point/compare/__init__.py
/gem5/src/arch/x86/isa/insts/simd128/floating_point/compare/compare_and_write_mask.py
/gem5/src/arch/x86/isa/insts/simd128/floating_point/compare/compare_and_write_minimum_or_maximum.py
/gem5/src/arch/x86/isa/insts/simd128/floating_point/compare/compare_and_write_rflags.py
/gem5/src/arch/x86/isa/insts/simd128/floating_point/data_conversion/__init__.py
/gem5/src/arch/x86/isa/insts/simd128/floating_point/data_conversion/convert_floating_point_to_floating_point.py
/gem5/src/arch/x86/isa/insts/simd128/floating_point/data_conversion/convert_floating_point_to_gpr_integer.py
/gem5/src/arch/x86/isa/insts/simd128/floating_point/data_conversion/convert_floating_point_to_mmx_integer.py
/gem5/src/arch/x86/isa/insts/simd128/floating_point/data_conversion/convert_floating_point_to_xmm_integer.py
/gem5/src/arch/x86/isa/insts/simd128/floating_point/data_reordering/__init__.py
/gem5/src/arch/x86/isa/insts/simd128/floating_point/data_reordering/shuffle.py
/gem5/src/arch/x86/isa/insts/simd128/floating_point/data_reordering/unpack_and_interleave.py
/gem5/src/arch/x86/isa/insts/simd128/floating_point/data_transfer/__init__.py
/gem5/src/arch/x86/isa/insts/simd128/floating_point/data_transfer/move.py
/gem5/src/arch/x86/isa/insts/simd128/floating_point/data_transfer/move_mask.py
/gem5/src/arch/x86/isa/insts/simd128/floating_point/data_transfer/move_non_temporal.py
/gem5/src/arch/x86/isa/insts/simd128/floating_point/data_transfer/move_with_duplication.py
/gem5/src/arch/x86/isa/insts/simd128/floating_point/logical/__init__.py
/gem5/src/arch/x86/isa/insts/simd128/floating_point/logical/andp.py
/gem5/src/arch/x86/isa/insts/simd128/floating_point/logical/exclusive_or.py
/gem5/src/arch/x86/isa/insts/simd128/floating_point/logical/orp.py
/gem5/src/arch/x86/isa/insts/simd128/integer/__init__.py
/gem5/src/arch/x86/isa/insts/simd128/integer/arithmetic/__init__.py
/gem5/src/arch/x86/isa/insts/simd128/integer/arithmetic/addition.py
/gem5/src/arch/x86/isa/insts/simd128/integer/arithmetic/average.py
/gem5/src/arch/x86/isa/insts/simd128/integer/arithmetic/multiplication.py
/gem5/src/arch/x86/isa/insts/simd128/integer/arithmetic/multiply_add.py
/gem5/src/arch/x86/isa/insts/simd128/integer/arithmetic/subtraction.py
/gem5/src/arch/x86/isa/insts/simd128/integer/arithmetic/sum_of_absolute_differences.py
/gem5/src/arch/x86/isa/insts/simd128/integer/compare/__init__.py
/gem5/src/arch/x86/isa/insts/simd128/integer/compare/compare_and_write_mask.py
/gem5/src/arch/x86/isa/insts/simd128/integer/compare/compare_and_write_minimum_or_maximum.py
/gem5/src/arch/x86/isa/insts/simd128/integer/data_conversion/__init__.py
/gem5/src/arch/x86/isa/insts/simd128/integer/data_conversion/convert_gpr_integer_to_floating_point.py
/gem5/src/arch/x86/isa/insts/simd128/integer/data_conversion/convert_integer_to_floating_point.py
/gem5/src/arch/x86/isa/insts/simd128/integer/data_conversion/convert_mmx_integer_to_floating_point.py
/gem5/src/arch/x86/isa/insts/simd128/integer/data_reordering/__init__.py
/gem5/src/arch/x86/isa/insts/simd128/integer/data_reordering/extract_and_insert.py
/gem5/src/arch/x86/isa/insts/simd128/integer/data_reordering/pack_with_saturation.py
/gem5/src/arch/x86/isa/insts/simd128/integer/data_reordering/shuffle.py
/gem5/src/arch/x86/isa/insts/simd128/integer/data_reordering/unpack_and_interleave.py
/gem5/src/arch/x86/isa/insts/simd128/integer/data_transfer/__init__.py
/gem5/src/arch/x86/isa/insts/simd128/integer/data_transfer/move.py
/gem5/src/arch/x86/isa/insts/simd128/integer/data_transfer/move_mask.py
/gem5/src/arch/x86/isa/insts/simd128/integer/data_transfer/move_non_temporal.py
/gem5/src/arch/x86/isa/insts/simd128/integer/logical/__init__.py
/gem5/src/arch/x86/isa/insts/simd128/integer/logical/exclusive_or.py
/gem5/src/arch/x86/isa/insts/simd128/integer/logical/pand.py
/gem5/src/arch/x86/isa/insts/simd128/integer/logical/por.py
/gem5/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/__init__.py
/gem5/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_control_and_status.py
/gem5/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_state.py
/gem5/src/arch/x86/isa/insts/simd128/integer/shift/__init__.py
/gem5/src/arch/x86/isa/insts/simd128/integer/shift/left_logical_shift.py
/gem5/src/arch/x86/isa/insts/simd128/integer/shift/right_arithmetic_shift.py
/gem5/src/arch/x86/isa/insts/simd128/integer/shift/right_logical_shift.py
/gem5/src/arch/x86/isa/insts/simd64/__init__.py
/gem5/src/arch/x86/isa/insts/simd64/floating_point/__init__.py
/gem5/src/arch/x86/isa/insts/simd64/floating_point/arithmetic/__init__.py
/gem5/src/arch/x86/isa/insts/simd64/floating_point/arithmetic/accumulation.py
/gem5/src/arch/x86/isa/insts/simd64/floating_point/arithmetic/addition.py
/gem5/src/arch/x86/isa/insts/simd64/floating_point/arithmetic/multiplication.py
/gem5/src/arch/x86/isa/insts/simd64/floating_point/arithmetic/reciprocal_estimation.py
/gem5/src/arch/x86/isa/insts/simd64/floating_point/arithmetic/reciprocal_square_root.py
/gem5/src/arch/x86/isa/insts/simd64/floating_point/arithmetic/subtraction.py
/gem5/src/arch/x86/isa/insts/simd64/floating_point/compare/__init__.py
/gem5/src/arch/x86/isa/insts/simd64/floating_point/compare/compare_and_write_mask.py
/gem5/src/arch/x86/isa/insts/simd64/floating_point/compare/compare_and_write_minimum_or_maximum.py
/gem5/src/arch/x86/isa/insts/simd64/floating_point/data_conversion.py
/gem5/src/arch/x86/isa/insts/simd64/integer/__init__.py
/gem5/src/arch/x86/isa/insts/simd64/integer/arithmetic/__init__.py
/gem5/src/arch/x86/isa/insts/simd64/integer/arithmetic/addition.py
/gem5/src/arch/x86/isa/insts/simd64/integer/arithmetic/average.py
/gem5/src/arch/x86/isa/insts/simd64/integer/arithmetic/multiplication.py
/gem5/src/arch/x86/isa/insts/simd64/integer/arithmetic/multiply_add.py
/gem5/src/arch/x86/isa/insts/simd64/integer/arithmetic/subtraction.py
/gem5/src/arch/x86/isa/insts/simd64/integer/arithmetic/sum_of_absolute_differences.py
/gem5/src/arch/x86/isa/insts/simd64/integer/compare/__init__.py
/gem5/src/arch/x86/isa/insts/simd64/integer/compare/compare_and_write_mask.py
/gem5/src/arch/x86/isa/insts/simd64/integer/compare/compare_and_write_minimum_or_maximum.py
/gem5/src/arch/x86/isa/insts/simd64/integer/data_conversion.py
/gem5/src/arch/x86/isa/insts/simd64/integer/data_reordering/__init__.py
/gem5/src/arch/x86/isa/insts/simd64/integer/data_reordering/extract_and_insert.py
/gem5/src/arch/x86/isa/insts/simd64/integer/data_reordering/pack_with_saturation.py
/gem5/src/arch/x86/isa/insts/simd64/integer/data_reordering/shuffle_and_swap.py
/gem5/src/arch/x86/isa/insts/simd64/integer/data_reordering/unpack_and_interleave.py
/gem5/src/arch/x86/isa/insts/simd64/integer/data_transfer/__init__.py
/gem5/src/arch/x86/isa/insts/simd64/integer/data_transfer/move.py
/gem5/src/arch/x86/isa/insts/simd64/integer/data_transfer/move_mask.py
/gem5/src/arch/x86/isa/insts/simd64/integer/data_transfer/move_non_temporal.py
/gem5/src/arch/x86/isa/insts/simd64/integer/exit_media_state.py
/gem5/src/arch/x86/isa/insts/simd64/integer/logical/__init__.py
/gem5/src/arch/x86/isa/insts/simd64/integer/logical/exclusive_or.py
/gem5/src/arch/x86/isa/insts/simd64/integer/logical/pand.py
/gem5/src/arch/x86/isa/insts/simd64/integer/logical/por.py
/gem5/src/arch/x86/isa/insts/simd64/integer/save_and_restore_state.py
/gem5/src/arch/x86/isa/insts/simd64/integer/shift/__init__.py
/gem5/src/arch/x86/isa/insts/simd64/integer/shift/left_logical_shift.py
/gem5/src/arch/x86/isa/insts/simd64/integer/shift/right_arithmetic_shift.py
/gem5/src/arch/x86/isa/insts/simd64/integer/shift/right_logical_shift.py
/gem5/src/arch/x86/isa/insts/system/__init__.py
/gem5/src/arch/x86/isa/insts/system/halt.py
/gem5/src/arch/x86/isa/insts/system/invlpg.py
/gem5/src/arch/x86/isa/insts/system/msrs.py
/gem5/src/arch/x86/isa/insts/system/segmentation.py
/gem5/src/arch/x86/isa/insts/system/undefined_operation.py
/gem5/src/arch/x86/isa/insts/x87/__init__.py
/gem5/src/arch/x86/isa/insts/x87/arithmetic/__init__.py
/gem5/src/arch/x86/isa/insts/x87/arithmetic/addition.py
/gem5/src/arch/x86/isa/insts/x87/arithmetic/change_sign.py
/gem5/src/arch/x86/isa/insts/x87/arithmetic/division.py
/gem5/src/arch/x86/isa/insts/x87/arithmetic/multiplication.py
/gem5/src/arch/x86/isa/insts/x87/arithmetic/partial_remainder.py
/gem5/src/arch/x86/isa/insts/x87/arithmetic/round.py
/gem5/src/arch/x86/isa/insts/x87/arithmetic/square_root.py
/gem5/src/arch/x86/isa/insts/x87/arithmetic/subtraction.py
/gem5/src/arch/x86/isa/insts/x87/compare_and_test/__init__.py
/gem5/src/arch/x86/isa/insts/x87/compare_and_test/classify.py
/gem5/src/arch/x86/isa/insts/x87/compare_and_test/floating_point_ordered_compare.py
/gem5/src/arch/x86/isa/insts/x87/compare_and_test/floating_point_unordered_compare.py
/gem5/src/arch/x86/isa/insts/x87/compare_and_test/integer_compare.py
/gem5/src/arch/x86/isa/insts/x87/compare_and_test/test.py
/gem5/src/arch/x86/isa/insts/x87/control/__init__.py
/gem5/src/arch/x86/isa/insts/x87/control/clear_exceptions.py
/gem5/src/arch/x86/isa/insts/x87/control/initialize.py
/gem5/src/arch/x86/isa/insts/x87/control/save_and_restore_x87_control_word.py
/gem5/src/arch/x86/isa/insts/x87/control/save_and_restore_x87_environment.py
/gem5/src/arch/x86/isa/insts/x87/control/save_x87_status_word.py
/gem5/src/arch/x86/isa/insts/x87/control/wait_for_exceptions.py
/gem5/src/arch/x86/isa/insts/x87/data_transfer_and_conversion/__init__.py
/gem5/src/arch/x86/isa/insts/x87/data_transfer_and_conversion/conditional_move.py
/gem5/src/arch/x86/isa/insts/x87/data_transfer_and_conversion/convert_and_load_or_store_bcd.py
/gem5/src/arch/x86/isa/insts/x87/data_transfer_and_conversion/convert_and_load_or_store_integer.py
/gem5/src/arch/x86/isa/insts/x87/data_transfer_and_conversion/exchange.py
/gem5/src/arch/x86/isa/insts/x87/data_transfer_and_conversion/extract.py
/gem5/src/arch/x86/isa/insts/x87/data_transfer_and_conversion/load_or_store_floating_point.py
/gem5/src/arch/x86/isa/insts/x87/load_constants/__init__.py
/gem5/src/arch/x86/isa/insts/x87/load_constants/load_0_1_or_pi.py
/gem5/src/arch/x86/isa/insts/x87/load_constants/load_logarithm.py
/gem5/src/arch/x86/isa/insts/x87/no_operation.py
/gem5/src/arch/x86/isa/insts/x87/stack_management/__init__.py
/gem5/src/arch/x86/isa/insts/x87/stack_management/clear_state.py
/gem5/src/arch/x86/isa/insts/x87/stack_management/stack_control.py
/gem5/src/arch/x86/isa/insts/x87/transcendental_functions/__init__.py
/gem5/src/arch/x86/isa/insts/x87/transcendental_functions/logarithmic_functions.py
/gem5/src/arch/x86/isa/insts/x87/transcendental_functions/trigonometric_functions.py
/gem5/src/arch/x86/isa/macroop.isa
/gem5/src/arch/x86/isa/main.isa
/gem5/src/arch/x86/isa/microasm.isa
/gem5/src/arch/x86/isa/microops/base.isa
/gem5/src/arch/x86/isa/microops/debug.isa
/gem5/src/arch/x86/isa/microops/fpop.isa
/gem5/src/arch/x86/isa/microops/ldstop.isa
/gem5/src/arch/x86/isa/microops/limmop.isa
/gem5/src/arch/x86/isa/microops/microops.isa
/gem5/src/arch/x86/isa/microops/regop.isa
/gem5/src/arch/x86/isa/microops/seqop.isa
/gem5/src/arch/x86/isa/microops/specop.isa
/gem5/src/arch/x86/isa/operands.isa
/gem5/src/arch/x86/isa/outputblock.isa
/gem5/src/arch/x86/isa/specialize.isa
/gem5/src/arch/x86/isa_traits.hh
/gem5/src/arch/x86/kernel_stats.hh
/gem5/src/arch/x86/linux/linux.cc
/gem5/src/arch/x86/linux/linux.hh
/gem5/src/arch/x86/linux/process.cc
/gem5/src/arch/x86/linux/process.hh
/gem5/src/arch/x86/linux/syscalls.cc
/gem5/src/arch/x86/linux/system.cc
/gem5/src/arch/x86/linux/system.hh
/gem5/src/arch/x86/miscregs.hh
/gem5/src/arch/x86/mmaped_ipr.hh
/gem5/src/arch/x86/pagetable.cc
/gem5/src/arch/x86/pagetable.hh
/gem5/src/arch/x86/pagetable_walker.cc
/gem5/src/arch/x86/pagetable_walker.hh
/gem5/src/arch/x86/predecoder.cc
/gem5/src/arch/x86/predecoder.hh
/gem5/src/arch/x86/predecoder_tables.cc
/gem5/src/arch/x86/process.cc
/gem5/src/arch/x86/process.hh
/gem5/src/arch/x86/registers.hh
/gem5/src/arch/x86/remote_gdb.cc
/gem5/src/arch/x86/remote_gdb.hh
/gem5/src/arch/x86/segmentregs.hh
/gem5/src/arch/x86/system.cc
/gem5/src/arch/x86/system.hh
/gem5/src/arch/x86/tlb.cc
/gem5/src/arch/x86/tlb.hh
/gem5/src/arch/x86/types.hh
/gem5/src/arch/x86/utility.cc
/gem5/src/arch/x86/utility.hh
/gem5/src/arch/x86/vtophys.cc
/gem5/src/arch/x86/vtophys.hh
/gem5/src/arch/x86/x86_traits.hh
6216:2f4020838149 17-May-2009 Nathan Binkert <nate@binkert.org>

includes: sort includes again


/gem5/src/arch/alpha/isa_traits.hh
/gem5/src/arch/alpha/predecoder.hh
/gem5/src/arch/arm/utility.hh
/gem5/src/arch/mips/dsp.hh
/gem5/src/arch/mips/isa_traits.hh
/gem5/src/arch/mips/utility.hh
/gem5/src/arch/sparc/isa_traits.hh
/gem5/src/arch/sparc/predecoder.hh
/gem5/src/arch/sparc/regfile.hh
acpi.hh
e820.hh
intelmp.cc
smbios.cc
smbios.hh
/gem5/src/arch/x86/intmessage.hh
/gem5/src/arch/x86/miscregfile.hh
/gem5/src/arch/x86/pagetable.hh
/gem5/src/arch/x86/pagetable_walker.hh
/gem5/src/arch/x86/predecoder.cc
/gem5/src/arch/x86/regfile.hh
/gem5/src/arch/x86/utility.hh
/gem5/src/arch/x86/x86_traits.hh
/gem5/src/base/cp_annotate.hh
/gem5/src/base/crc.cc
/gem5/src/base/inet.cc
/gem5/src/base/inet.hh
/gem5/src/base/intmath.hh
/gem5/src/base/misc.cc
/gem5/src/base/pollevent.cc
/gem5/src/base/res_list.hh
/gem5/src/base/statistics.hh
/gem5/src/base/stats/mysql.cc
/gem5/src/base/stats/output.cc
/gem5/src/cpu/exetrace.hh
/gem5/src/cpu/inorder/comm.hh
/gem5/src/cpu/inorder/inorder_trace.hh
/gem5/src/cpu/inteltrace.hh
/gem5/src/cpu/legiontrace.hh
/gem5/src/cpu/nativetrace.hh
/gem5/src/cpu/o3/2bit_local_pred.hh
/gem5/src/cpu/o3/bpred_unit.hh
/gem5/src/cpu/o3/comm.hh
/gem5/src/cpu/o3/fetch_impl.hh
/gem5/src/cpu/o3/inst_queue.hh
/gem5/src/cpu/o3/ras.hh
/gem5/src/cpu/o3/store_set.hh
/gem5/src/cpu/o3/tournament_pred.hh
/gem5/src/cpu/ozone/ea_list.hh
/gem5/src/cpu/ozone/inst_queue.hh
/gem5/src/cpu/ozone/null_predictor.hh
/gem5/src/cpu/simple/base.cc
/gem5/src/cpu/simple_thread.hh
/gem5/src/cpu/static_inst.hh
/gem5/src/cpu/thread_context.hh
/gem5/src/dev/alpha/backdoor.hh
/gem5/src/dev/etherlink.hh
/gem5/src/dev/etherpkt.hh
/gem5/src/dev/intel_8254_timer.hh
/gem5/src/dev/mips/backdoor.hh
/gem5/src/dev/ns_gige.cc
/gem5/src/dev/sinic.cc
/gem5/src/dev/x86/intdev.hh
/gem5/src/dev/x86/south_bridge.cc
/gem5/src/kern/tru64/dump_mbuf.cc
/gem5/src/kern/tru64/mbuf.hh
/gem5/src/mem/bus.hh
/gem5/src/mem/cache/cache_impl.hh
/gem5/src/mem/cache/mshr.cc
/gem5/src/mem/cache/tags/fa_lru.cc
/gem5/src/mem/cache/tags/fa_lru.hh
/gem5/src/mem/cache/tags/iic_repl/gen.cc
/gem5/src/mem/cache/tags/iic_repl/repl.hh
/gem5/src/mem/cache/tags/lru.hh
/gem5/src/mem/gems_common/util.cc
/gem5/src/mem/packet.hh
/gem5/src/mem/page_table.hh
/gem5/src/mem/physical.cc
/gem5/src/mem/ruby/common/Debug.hh
/gem5/src/mem/ruby/common/Global.hh
/gem5/src/mem/ruby/network/orion/power_ll.cc
/gem5/src/mem/ruby/network/orion/power_utils.cc
/gem5/src/mem/rubymem.cc
/gem5/src/mem/slicc/slicc_global.hh
/gem5/src/python/swig/core.i
/gem5/src/python/swig/event.i
/gem5/src/python/swig/pyobject.hh
/gem5/src/python/swig/sim_object.i
/gem5/src/sim/arguments.hh
/gem5/src/sim/eventq.hh
/gem5/src/sim/init.cc
/gem5/src/sim/insttracer.hh
/gem5/src/sim/sim_object.cc
/gem5/src/sim/simulate.cc
/gem5/src/sim/syscall_emul.hh
/gem5/src/unittest/rangemaptest.cc
/gem5/src/unittest/rangemultimaptest.cc
/gem5/util/statetrace/arch/tracechild_amd64.hh
/gem5/util/statetrace/arch/tracechild_i386.hh
/gem5/util/statetrace/arch/tracechild_sparc.hh
6214:1ec0ec8933ae 17-May-2009 Nathan Binkert <nate@binkert.org>

types: Move stuff for global types into src/base/types.hh


/gem5/src/arch/alpha/isa_traits.hh
/gem5/src/arch/alpha/miscregfile.hh
/gem5/src/arch/alpha/predecoder.hh
/gem5/src/arch/alpha/types.hh
/gem5/src/arch/arm/isa_traits.hh
/gem5/src/arch/arm/predecoder.hh
/gem5/src/arch/arm/types.hh
/gem5/src/arch/arm/utility.hh
/gem5/src/arch/mips/dsp.hh
/gem5/src/arch/mips/isa_traits.hh
/gem5/src/arch/mips/predecoder.hh
/gem5/src/arch/mips/types.hh
/gem5/src/arch/mips/utility.hh
/gem5/src/arch/sparc/isa_traits.hh
/gem5/src/arch/sparc/predecoder.hh
/gem5/src/arch/sparc/regfile.hh
acpi.hh
e820.hh
intelmp.cc
smbios.cc
smbios.hh
/gem5/src/arch/x86/intmessage.hh
/gem5/src/arch/x86/isa_traits.hh
/gem5/src/arch/x86/miscregfile.hh
/gem5/src/arch/x86/pagetable.hh
/gem5/src/arch/x86/pagetable_walker.hh
/gem5/src/arch/x86/predecoder.cc
/gem5/src/arch/x86/predecoder.hh
/gem5/src/arch/x86/regfile.hh
/gem5/src/arch/x86/utility.hh
/gem5/src/arch/x86/vtophys.hh
/gem5/src/arch/x86/x86_traits.hh
/gem5/src/base/cp_annotate.hh
/gem5/src/base/crc.cc
/gem5/src/base/crc.hh
/gem5/src/base/fast_alloc.hh
/gem5/src/base/hashmap.hh
/gem5/src/base/hostinfo.cc
/gem5/src/base/hostinfo.hh
/gem5/src/base/inet.cc
/gem5/src/base/inet.hh
/gem5/src/base/intmath.hh
/gem5/src/base/loader/hex_file.hh
/gem5/src/base/loader/object_file.hh
/gem5/src/base/loader/symtab.cc
/gem5/src/base/loader/symtab.hh
/gem5/src/base/misc.cc
/gem5/src/base/pollevent.cc
/gem5/src/base/random.hh
/gem5/src/base/socket.cc
/gem5/src/base/statistics.hh
/gem5/src/base/stats/events.cc
/gem5/src/base/stats/mysql.cc
/gem5/src/base/stats/mysql_run.hh
/gem5/src/base/stats/output.cc
/gem5/src/base/stats/types.hh
/gem5/src/base/stats/visit.hh
/gem5/src/base/trace.hh
/gem5/src/base/types.hh
/gem5/src/cpu/exetrace.hh
/gem5/src/cpu/inorder/comm.hh
/gem5/src/cpu/inorder/inorder_trace.hh
/gem5/src/cpu/inteltrace.hh
/gem5/src/cpu/legiontrace.hh
/gem5/src/cpu/nativetrace.hh
/gem5/src/cpu/o3/2bit_local_pred.hh
/gem5/src/cpu/o3/bpred_unit.hh
/gem5/src/cpu/o3/btb.hh
/gem5/src/cpu/o3/comm.hh
/gem5/src/cpu/o3/fetch_impl.hh
/gem5/src/cpu/o3/inst_queue.hh
/gem5/src/cpu/o3/ras.hh
/gem5/src/cpu/o3/sat_counter.hh
/gem5/src/cpu/o3/store_set.hh
/gem5/src/cpu/o3/tournament_pred.hh
/gem5/src/cpu/ozone/ea_list.hh
/gem5/src/cpu/ozone/inst_queue.hh
/gem5/src/cpu/ozone/null_predictor.hh
/gem5/src/cpu/pc_event.hh
/gem5/src/cpu/profile.hh
/gem5/src/cpu/simple/base.cc
/gem5/src/cpu/simple_thread.hh
/gem5/src/cpu/static_inst.hh
/gem5/src/cpu/thread_context.hh
/gem5/src/dev/alpha/backdoor.hh
/gem5/src/dev/etherlink.hh
/gem5/src/dev/etherpkt.hh
/gem5/src/dev/intel_8254_timer.hh
/gem5/src/dev/mips/backdoor.hh
/gem5/src/dev/ns_gige.cc
/gem5/src/dev/sinic.cc
/gem5/src/kern/tru64/dump_mbuf.cc
/gem5/src/kern/tru64/mbuf.hh
/gem5/src/kern/tru64/printf.cc
/gem5/src/mem/cache/cache_impl.hh
/gem5/src/mem/cache/mshr.cc
/gem5/src/mem/cache/tags/iic_repl/gen.cc
/gem5/src/mem/cache/tags/iic_repl/repl.hh
/gem5/src/mem/packet.hh
/gem5/src/mem/page_table.hh
/gem5/src/mem/physical.cc
/gem5/src/mem/request.hh
/gem5/src/mem/rubymem.cc
/gem5/src/python/m5/params.py
/gem5/src/python/swig/core.i
/gem5/src/python/swig/debug.i
/gem5/src/python/swig/event.i
/gem5/src/python/swig/pyobject.hh
/gem5/src/python/swig/random.i
/gem5/src/python/swig/range.i
/gem5/src/python/swig/sim_object.i
/gem5/src/python/swig/trace.i
/gem5/src/sim/arguments.hh
/gem5/src/sim/byteswap.hh
/gem5/src/sim/core.hh
/gem5/src/sim/debug.hh
/gem5/src/sim/eventq.hh
/gem5/src/sim/host.hh
/gem5/src/sim/init.cc
/gem5/src/sim/insttracer.hh
/gem5/src/sim/process.hh
/gem5/src/sim/pseudo_inst.hh
/gem5/src/sim/serialize.hh
/gem5/src/sim/sim_exit.hh
/gem5/src/sim/sim_object.cc
/gem5/src/sim/simulate.cc
/gem5/src/sim/simulate.hh
/gem5/src/sim/syscall_emul.hh
/gem5/src/unittest/rangemaptest.cc
/gem5/src/unittest/rangemultimaptest.cc
/gem5/src/unittest/stattest.cc
5838:47ada83a8958 01-Feb-2009 Gabe Black <gblack@eecs.umich.edu>

X86: Add extended Intel MP entries correctly.

5825:da5f7e97958c 01-Feb-2009 Gabe Black <gblack@eecs.umich.edu>

X86: Set/correct some default values for x86 parameters.

5770:03c07a62074f 06-Dec-2008 Gabe Black <gblack@eecs.umich.edu>

X86: Add add_entry back in.

5702:bf84e2fa05f7 20-Oct-2008 Ali Saidi <saidi@eecs.umich.edu>

O3CPU: Undo Gabe's changes to remove hwrei and simpalcheck from O3 CPU. Removing hwrei causes
the instruction after the hwrei to be fetched before the ITB/DTB_CM register is updated in a call pal
call sys and thus the translation fails because the user is attempting to access a super page address.

Minimally, it seems as though some sort of fetch stall or refetch after a hwrei is required. I think
this works currently because the hwrei uses the exec context interface, and the o3 stalls when that occurs.

Additionally, these changes don't update the LOCK register and probably break ll/sc. Both o3 changes were
removed since a great deal of manual patching would be required to only remove the hwrei change.

5641:51b7b8cf8083 11-Oct-2008 Gabe Black <gblack@eecs.umich.edu>

X86: Add an Intel MP table to the simulation.

5627:31eac202dbd1 11-Oct-2008 Gabe Black <gblack@eecs.umich.edu>

X86: Create SimObjects in python and C++ to represent the ACPI system description tables.

5625:ea7d3676ac8d 11-Oct-2008 Gabe Black <gblack@eecs.umich.edu>

X86: Create SimObjects in python and C++ to represent the Intel MP tables.

5615:1c4b9b1aa500 10-Oct-2008 Gabe Black <gblack@eecs.umich.edu>

X86: Turn SMBios structures into simobjects.

5614:2e7dbd0c4a2b 10-Oct-2008 Gabe Black <gblack@eecs.umich.edu>

X86: Add a couple comments to the bios SConscript

5612:1bd333953e49 10-Oct-2008 Gabe Black <gblack@eecs.umich.edu>

X86: Move the smbios objects into a folder for BIOS objects.

5610:0e1e9c186769 10-Oct-2008 Nathan Binkert <nate@binkert.org>

SimObjects: Clean up handling of C++ namespaces.
Make them easier to express by only having the cxx_type parameter which
has the full namespace name, and drop the cxx_namespace thing.
Add support for multiple levels of namespace.

5450:25e395a87745 12-Jun-2008 Gabe Black <gblack@eecs.umich.edu>

X86: Make the e820 table manually or automatically configurable from python.