History log of /gem5/src/arch/power/isa/
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13801:e18de9c80ce3 30-Jan-2019 Sandipan Das <sandipan@linux.ibm.com>

arch-power: Rename program counter registers

The Power ISA specification lists the Program Counter (PC) and
the Next Program Counter (NPC) registers as Current Instruction
Address (CIA) and Next Instruction Address (NIA). This applies
the ISA naming convention for these two registers.

Change-Id: I8b9094ab1c809f4dfdb4d7330c17f360adf063e9
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16603
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

13800:cffc4c0fc94e 30-Jan-2019 Sandipan Das <sandipan@linux.ibm.com>

arch-power: Simplify doubleword operand types

Currently, 'sq' and 'uq' are used to represent signed and
unsigned doublewords respectively. Since all recent Power
ISA specifications list 128-bit quadwords as a valid data
type, it may be misleading to use the current terminology
in case support for such operands are added in the future.
So, to simplify this, 'sd' and 'ud' are used to represent
signed and unsigned doublewords respectively.

Change-Id: Ie7831c596fc8f9ddfdf3b652c37cfe26484ebe01
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16602
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

12692:1eaaa1d75080 04-May-2018 Matt Sinclair <mattdsinclair@gmail.com>

arch-x86, arch-power: fix calls to bits and insertBits

The bits and insertBits assume the first bit is the larger bit and the last
bit is the smaller bit. This commit fixes several X86 and Power calls to
these functions that incorrectly assumed that first was the smaller bit.

Change-Id: I2b5354d1b9ca66e3436c4a72042416a6ce6dec01
Reviewed-on: https://gem5-review.googlesource.com/10241
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

12616:4b463b4dc098 23-Mar-2018 Gabe Black <gabeblack@google.com>

arch: Fix all override related warnings.

Clang has started(?) reporting override related warnings, something gcc
apparently did before, but was disabled in the SConstruct. Rather than
disable the warnings in for clang as well, this change fixes the
warnings. A future change will re-enable the warnings for gcc.

Change-Id: I3cc79e45749b2ae0f9bebb1acadc56a3d3a942da
Reviewed-on: https://gem5-review.googlesource.com/9343
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>


/gem5/src/arch/alpha/isa/branch.isa
/gem5/src/arch/alpha/isa/fp.isa
/gem5/src/arch/alpha/isa/int.isa
/gem5/src/arch/alpha/isa/main.isa
/gem5/src/arch/alpha/isa/mem.isa
/gem5/src/arch/alpha/isa/opcdec.isa
/gem5/src/arch/alpha/isa/pal.isa
/gem5/src/arch/alpha/isa/unimp.isa
/gem5/src/arch/arm/insts/branch64.hh
/gem5/src/arch/arm/insts/data64.hh
/gem5/src/arch/arm/insts/macromem.hh
/gem5/src/arch/arm/insts/mem.hh
/gem5/src/arch/arm/insts/mem64.hh
/gem5/src/arch/arm/insts/misc.hh
/gem5/src/arch/arm/insts/misc64.hh
/gem5/src/arch/arm/insts/pred_inst.hh
/gem5/src/arch/arm/insts/pseudo.hh
/gem5/src/arch/arm/insts/static_inst.hh
/gem5/src/arch/arm/insts/vfp.hh
/gem5/src/arch/arm/isa/formats/breakpoint.isa
/gem5/src/arch/arm/isa/templates/basic.isa
/gem5/src/arch/arm/isa/templates/branch.isa
/gem5/src/arch/arm/isa/templates/branch64.isa
/gem5/src/arch/arm/isa/templates/data64.isa
/gem5/src/arch/arm/isa/templates/macromem.isa
/gem5/src/arch/arm/isa/templates/mem.isa
/gem5/src/arch/arm/isa/templates/mem64.isa
/gem5/src/arch/arm/isa/templates/misc.isa
/gem5/src/arch/arm/isa/templates/misc64.isa
/gem5/src/arch/arm/isa/templates/mult.isa
/gem5/src/arch/arm/isa/templates/neon.isa
/gem5/src/arch/arm/isa/templates/neon64.isa
/gem5/src/arch/arm/isa/templates/pred.isa
/gem5/src/arch/arm/isa/templates/vfp.isa
/gem5/src/arch/arm/isa/templates/vfp64.isa
/gem5/src/arch/mips/isa/base.isa
/gem5/src/arch/mips/isa/formats/basic.isa
/gem5/src/arch/mips/isa/formats/branch.isa
/gem5/src/arch/mips/isa/formats/control.isa
/gem5/src/arch/mips/isa/formats/fp.isa
/gem5/src/arch/mips/isa/formats/int.isa
/gem5/src/arch/mips/isa/formats/mem.isa
/gem5/src/arch/mips/isa/formats/mt.isa
/gem5/src/arch/mips/isa/formats/noop.isa
/gem5/src/arch/mips/isa/formats/tlbop.isa
/gem5/src/arch/mips/isa/formats/trap.isa
/gem5/src/arch/mips/isa/formats/unimp.isa
/gem5/src/arch/mips/isa/formats/unknown.isa
/gem5/src/arch/power/insts/branch.hh
/gem5/src/arch/power/insts/condition.hh
/gem5/src/arch/power/insts/floating.hh
/gem5/src/arch/power/insts/integer.hh
/gem5/src/arch/power/insts/mem.hh
/gem5/src/arch/power/insts/misc.hh
/gem5/src/arch/power/insts/static_inst.hh
formats/basic.isa
formats/mem.isa
formats/unimp.isa
formats/unknown.isa
/gem5/src/arch/riscv/insts/static_inst.hh
/gem5/src/arch/sparc/insts/nop.cc
/gem5/src/arch/sparc/insts/priv.hh
/gem5/src/arch/sparc/insts/static_inst.hh
/gem5/src/arch/sparc/isa/formats/basic.isa
/gem5/src/arch/sparc/isa/formats/mem/basicmem.isa
/gem5/src/arch/sparc/isa/formats/mem/blockmem.isa
12420:f5c80f4ed41f 05-Jan-2018 Gabe Black <gabeblack@google.com>

cpu, power: Get rid of the remnants of the EA computation insts.

Get rid of some remnants of a system which was intended to separate
address computation into its own instruction object.

Change-Id: I23f9ffd70fcb89a8ea5bbb934507fb00da9a0b7f
Reviewed-on: https://gem5-review.googlesource.com/7122
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

12236:126ac9da6050 04-Nov-2017 Gabe Black <gabeblack@google.com>

alpha,arm,mips,power,riscv,sparc,x86: Merge exec decl templates.

In the ISA instruction definitions, some classes were declared with
execute, etc., functions outside of the main template because they
had CPU specific signatures and would need to be duplicated with
each CPU plugged into them. Now that the instructions always just
use an ExecContext, there's no reason for those templates to be
separate. This change folds those templates together.

Change-Id: I13bda247d3d1cc07c0ea06968e48aa5b4aace7fa
Reviewed-on: https://gem5-review.googlesource.com/5401
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Alec Roelke <ar4jc@virginia.edu>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>


/gem5/src/arch/alpha/isa/main.isa
/gem5/src/arch/alpha/isa/mem.isa
/gem5/src/arch/alpha/isa/opcdec.isa
/gem5/src/arch/alpha/isa/unimp.isa
/gem5/src/arch/arm/insts/pred_inst.hh
/gem5/src/arch/arm/isa/formats/breakpoint.isa
/gem5/src/arch/arm/isa/insts/fp.isa
/gem5/src/arch/arm/isa/templates/basic.isa
/gem5/src/arch/arm/isa/templates/branch.isa
/gem5/src/arch/arm/isa/templates/branch64.isa
/gem5/src/arch/arm/isa/templates/data64.isa
/gem5/src/arch/arm/isa/templates/macromem.isa
/gem5/src/arch/arm/isa/templates/mem.isa
/gem5/src/arch/arm/isa/templates/mem64.isa
/gem5/src/arch/arm/isa/templates/misc.isa
/gem5/src/arch/arm/isa/templates/misc64.isa
/gem5/src/arch/arm/isa/templates/mult.isa
/gem5/src/arch/arm/isa/templates/neon.isa
/gem5/src/arch/arm/isa/templates/neon64.isa
/gem5/src/arch/arm/isa/templates/pred.isa
/gem5/src/arch/arm/isa/templates/vfp.isa
/gem5/src/arch/arm/isa/templates/vfp64.isa
/gem5/src/arch/mips/isa/formats/basic.isa
/gem5/src/arch/mips/isa/formats/mem.isa
/gem5/src/arch/mips/isa/formats/noop.isa
/gem5/src/arch/mips/isa/formats/unimp.isa
/gem5/src/arch/mips/isa/formats/unknown.isa
formats/basic.isa
formats/mem.isa
formats/unimp.isa
formats/unknown.isa
/gem5/src/arch/riscv/isa/base.isa
/gem5/src/arch/riscv/isa/formats/amo.isa
/gem5/src/arch/riscv/isa/formats/basic.isa
/gem5/src/arch/riscv/isa/formats/mem.isa
/gem5/src/arch/riscv/isa/formats/standard.isa
/gem5/src/arch/riscv/isa/formats/unknown.isa
/gem5/src/arch/riscv/isa/includes.isa
/gem5/src/arch/riscv/isa/main.isa
/gem5/src/arch/riscv/isa/micro.isa
/gem5/src/arch/riscv/static_inst.hh
/gem5/src/arch/sparc/isa/formats/basic.isa
/gem5/src/arch/sparc/isa/formats/mem/basicmem.isa
/gem5/src/arch/sparc/isa/formats/mem/blockmem.isa
/gem5/src/arch/sparc/isa/formats/mem/util.isa
/gem5/src/arch/sparc/isa/formats/micro.isa
/gem5/src/arch/sparc/isa/formats/nop.isa
/gem5/src/arch/sparc/isa/formats/unimp.isa
/gem5/src/arch/sparc/isa/formats/unknown.isa
/gem5/src/arch/x86/isa/formats/basic.isa
/gem5/src/arch/x86/isa/formats/monitor_mwait.isa
/gem5/src/arch/x86/isa/formats/unimp.isa
/gem5/src/arch/x86/isa/formats/unknown.isa
/gem5/src/arch/x86/isa/macroop.isa
/gem5/src/arch/x86/isa/microops/debug.isa
/gem5/src/arch/x86/isa/microops/fpop.isa
/gem5/src/arch/x86/isa/microops/ldstop.isa
/gem5/src/arch/x86/isa/microops/limmop.isa
/gem5/src/arch/x86/isa/microops/mediaop.isa
/gem5/src/arch/x86/isa/microops/regop.isa
/gem5/src/arch/x86/isa/microops/seqop.isa
/gem5/src/arch/x86/isa/microops/specop.isa
12234:78ece221f9f5 02-Nov-2017 Gabe Black <gabeblack@google.com>

alpha,arm,mips,power,riscv,sparc,x86,isa: De-specialize ExecContexts.

The ISA parser used to generate different copies of exec functions
for each exec context class a particular CPU wanted to use. That's
since been changed so that those functions take a pointer to the base
ExecContext, so the code which would generate those extra functions
can be removed, and some functions which used to be templated on an
ExecContext subclass can be untemplated, or minimally less templated.

Now that some functions aren't going to be instantiated multiple times
with different signatures, there are also opportunities to collapse
templates and make many instruction definitions simpler within the
parser. Since those changes will be less mechanical, they're left for
later changes and will probably be done in smaller increments.

Change-Id: I0015307bb02dfb9c60380b56d2a820f12169ebea
Reviewed-on: https://gem5-review.googlesource.com/5381
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>


/gem5/src/arch/alpha/isa/fp.isa
/gem5/src/arch/alpha/isa/main.isa
/gem5/src/arch/alpha/isa/mem.isa
/gem5/src/arch/alpha/isa/opcdec.isa
/gem5/src/arch/alpha/isa/unimp.isa
/gem5/src/arch/alpha/isa/unknown.isa
/gem5/src/arch/arm/insts/static_inst.hh
/gem5/src/arch/arm/isa/formats/breakpoint.isa
/gem5/src/arch/arm/isa/templates/basic.isa
/gem5/src/arch/arm/isa/templates/macromem.isa
/gem5/src/arch/arm/isa/templates/mem.isa
/gem5/src/arch/arm/isa/templates/mem64.isa
/gem5/src/arch/arm/isa/templates/neon.isa
/gem5/src/arch/arm/isa/templates/neon64.isa
/gem5/src/arch/arm/isa/templates/pred.isa
/gem5/src/arch/isa_parser.py
/gem5/src/arch/mips/isa/formats/basic.isa
/gem5/src/arch/mips/isa/formats/control.isa
/gem5/src/arch/mips/isa/formats/dsp.isa
/gem5/src/arch/mips/isa/formats/fp.isa
/gem5/src/arch/mips/isa/formats/int.isa
/gem5/src/arch/mips/isa/formats/mem.isa
/gem5/src/arch/mips/isa/formats/mt.isa
/gem5/src/arch/mips/isa/formats/noop.isa
/gem5/src/arch/mips/isa/formats/tlbop.isa
/gem5/src/arch/mips/isa/formats/trap.isa
/gem5/src/arch/mips/isa/formats/unimp.isa
/gem5/src/arch/mips/isa/formats/unknown.isa
formats/basic.isa
formats/mem.isa
formats/misc.isa
formats/unimp.isa
formats/unknown.isa
/gem5/src/arch/riscv/isa/formats/amo.isa
/gem5/src/arch/riscv/isa/formats/basic.isa
/gem5/src/arch/riscv/isa/formats/fp.isa
/gem5/src/arch/riscv/isa/formats/mem.isa
/gem5/src/arch/riscv/isa/formats/standard.isa
/gem5/src/arch/riscv/isa/formats/unknown.isa
/gem5/src/arch/riscv/isa/micro.isa
/gem5/src/arch/sparc/isa/base.isa
/gem5/src/arch/sparc/isa/formats/basic.isa
/gem5/src/arch/sparc/isa/formats/branch.isa
/gem5/src/arch/sparc/isa/formats/integerop.isa
/gem5/src/arch/sparc/isa/formats/mem/swap.isa
/gem5/src/arch/sparc/isa/formats/mem/util.isa
/gem5/src/arch/sparc/isa/formats/micro.isa
/gem5/src/arch/sparc/isa/formats/nop.isa
/gem5/src/arch/sparc/isa/formats/priv.isa
/gem5/src/arch/sparc/isa/formats/trap.isa
/gem5/src/arch/sparc/isa/formats/unimp.isa
/gem5/src/arch/sparc/isa/formats/unknown.isa
/gem5/src/arch/x86/isa/formats/basic.isa
/gem5/src/arch/x86/isa/formats/cpuid.isa
/gem5/src/arch/x86/isa/formats/monitor_mwait.isa
/gem5/src/arch/x86/isa/formats/nop.isa
/gem5/src/arch/x86/isa/formats/syscall.isa
/gem5/src/arch/x86/isa/formats/unimp.isa
/gem5/src/arch/x86/isa/formats/unknown.isa
/gem5/src/arch/x86/isa/macroop.isa
/gem5/src/arch/x86/isa/microops/debug.isa
/gem5/src/arch/x86/isa/microops/fpop.isa
/gem5/src/arch/x86/isa/microops/ldstop.isa
/gem5/src/arch/x86/isa/microops/limmop.isa
/gem5/src/arch/x86/isa/microops/mediaop.isa
/gem5/src/arch/x86/isa/microops/regop.isa
/gem5/src/arch/x86/isa/microops/seqop.isa
/gem5/src/arch/x86/isa/microops/specop.isa
/gem5/src/arch/x86/memhelpers.hh
11877:5ea85692a53e 20-Jul-2015 Brandon Potter <brandon.potter@amd.com>

syscall_emul: [patch 13/22] add system call retry capability

This changeset adds functionality that allows system calls to retry without
affecting thread context state such as the program counter or register values
for the associated thread context (when system calls return with a retry
fault).

This functionality is needed to solve problems with blocking system calls
in multi-process or multi-threaded simulations where information is passed
between processes/threads. Blocking system calls can cause deadlock because
the simulator itself is single threaded. There is only a single thread
servicing the event queue which can cause deadlock if the thread hits a
blocking system call instruction.

To illustrate the problem, consider two processes using the producer/consumer
sharing model. The processes can use file descriptors and the read and write
calls to pass information to one another. If the consumer calls the blocking
read system call before the producer has produced anything, the call will
block the event queue (while executing the system call instruction) and
deadlock the simulation.

The solution implemented in this changeset is to recognize that the system
calls will block and then generate a special retry fault. The fault will
be sent back up through the function call chain until it is exposed to the
cpu model's pipeline where the fault becomes visible. The fault will trigger
the cpu model to replay the instruction at a future tick where the call has
a chance to succeed without actually going into a blocking state.

In subsequent patches, we recognize that a syscall will block by calling a
non-blocking poll (from inside the system call implementation) and checking
for events. When events show up during the poll, it signifies that the call
would not have blocked and the syscall is allowed to proceed (calling an
underlying host system call if necessary). If no events are returned from the
poll, we generate the fault and try the instruction for the thread context
at a distant tick. Note that retrying every tick is not efficient.

As an aside, the simulator has some multi-threading support for the event
queue, but it is not used by default and needs work. Even if the event queue
was completely multi-threaded, meaning that there is a hardware thread on
the host servicing a single simulator thread contexts with a 1:1 mapping
between them, it's still possible to run into deadlock due to the event queue
barriers on quantum boundaries. The solution of replaying at a later tick
is the simplest solution and solves the problem generally.

11327:1e7b883dffc6 06-Feb-2016 Steve Reinhardt <steve.reinhardt@amd.com>

arch: get rid of dummy var init

MemOperand variables were being initialized to 0
"to avoid 'uninitialized variable' errors" but these
no longer seem to be a problem (with the exception of
one use case in POWER that is arguably broken and
easily fixed here).

Getting rid of the initialization is necessary to
set up a subsequent patch which extends memory
operands to possibly not be scalars, making the
'= 0' initialization no longer feasible.

11303:f694764d656d 17-Jan-2016 Steve Reinhardt <steve.reinhardt@amd.com>

cpu. arch: add initiateMemRead() to ExecContext interface

For historical reasons, the ExecContext interface had a single
function, readMem(), that did two different things depending on
whether the ExecContext supported atomic memory mode (i.e.,
AtomicSimpleCPU) or timing memory mode (all the other models).
In the former case, it actually performed a memory read; in the
latter case, it merely initiated a read access, and the read
completion did not happen until later when a response packet
arrived from the memory system.

This led to some confusing things, including timing accesses
being required to provide a pointer for the return data even
though that pointer was only used in atomic mode.

This patch splits this interface, adding a new initiateMemRead()
function to the ExecContext interface to replace the timing-mode
use of readMem().

For consistency and clarity, the readMemTiming() helper function
in the ISA definitions is renamed to initiateMemRead() as well.
For x86, where the access size is passed in explicitly, we can
also get rid of the data parameter at this level. For other ISAs,
where the access size is determined from the type of the data
parameter, we have to keep the parameter for that purpose.

10474:799c8ee4ecba 16-Oct-2014 Andreas Hansson <andreas.hansson@arm.com>

arch: Use shared_ptr for all Faults

This patch takes quite a large step in transitioning from the ad-hoc
RefCountingPtr to the c++11 shared_ptr by adopting its use for all
Faults. There are no changes in behaviour, and the code modifications
are mostly just replacing "new" with "make_shared".


/gem5/src/arch/alpha/ev5.cc
/gem5/src/arch/alpha/faults.hh
/gem5/src/arch/alpha/interrupts.hh
/gem5/src/arch/alpha/isa/decoder.isa
/gem5/src/arch/alpha/isa/fp.isa
/gem5/src/arch/alpha/isa/opcdec.isa
/gem5/src/arch/alpha/isa/unimp.isa
/gem5/src/arch/alpha/isa/unknown.isa
/gem5/src/arch/alpha/tlb.cc
/gem5/src/arch/alpha/tlb.hh
/gem5/src/arch/arm/insts/static_inst.hh
/gem5/src/arch/arm/interrupts.hh
/gem5/src/arch/arm/isa/formats/breakpoint.isa
/gem5/src/arch/arm/isa/formats/unimp.isa
/gem5/src/arch/arm/isa/insts/branch.isa
/gem5/src/arch/arm/isa/insts/branch64.isa
/gem5/src/arch/arm/isa/insts/data64.isa
/gem5/src/arch/arm/isa/insts/fp.isa
/gem5/src/arch/arm/isa/insts/macromem.isa
/gem5/src/arch/arm/isa/insts/misc.isa
/gem5/src/arch/arm/isa/insts/misc64.isa
/gem5/src/arch/arm/isa/insts/neon.isa
/gem5/src/arch/arm/isa/insts/neon64.isa
/gem5/src/arch/arm/isa/insts/neon64_mem.isa
/gem5/src/arch/arm/isa/insts/swap.isa
/gem5/src/arch/arm/isa/templates/mem64.isa
/gem5/src/arch/arm/isa/templates/neon.isa
/gem5/src/arch/arm/isa/templates/vfp.isa
/gem5/src/arch/arm/table_walker.cc
/gem5/src/arch/arm/table_walker.hh
/gem5/src/arch/arm/tlb.cc
/gem5/src/arch/arm/tlb.hh
/gem5/src/arch/arm/utility.cc
/gem5/src/arch/generic/memhelpers.hh
/gem5/src/arch/mips/interrupts.cc
/gem5/src/arch/mips/isa.hh
/gem5/src/arch/mips/isa/decoder.isa
/gem5/src/arch/mips/isa/formats/control.isa
/gem5/src/arch/mips/isa/formats/dsp.isa
/gem5/src/arch/mips/isa/formats/fp.isa
/gem5/src/arch/mips/isa/formats/int.isa
/gem5/src/arch/mips/isa/formats/mt.isa
/gem5/src/arch/mips/isa/formats/trap.isa
/gem5/src/arch/mips/isa/formats/unimp.isa
/gem5/src/arch/mips/isa/formats/unknown.isa
/gem5/src/arch/mips/mt.hh
/gem5/src/arch/mips/tlb.hh
formats/unimp.isa
formats/unknown.isa
/gem5/src/arch/power/tlb.cc
/gem5/src/arch/power/tlb.hh
/gem5/src/arch/sparc/interrupts.hh
/gem5/src/arch/sparc/isa/base.isa
/gem5/src/arch/sparc/isa/decoder.isa
/gem5/src/arch/sparc/isa/formats/mem/util.isa
/gem5/src/arch/sparc/isa/formats/priv.isa
/gem5/src/arch/sparc/isa/formats/trap.isa
/gem5/src/arch/sparc/isa/formats/unknown.isa
/gem5/src/arch/sparc/tlb.cc
/gem5/src/arch/sparc/tlb.hh
/gem5/src/arch/sparc/utility.cc
/gem5/src/arch/sparc/utility.hh
/gem5/src/arch/x86/interrupts.cc
/gem5/src/arch/x86/isa/formats/string.isa
/gem5/src/arch/x86/isa/formats/unknown.isa
/gem5/src/arch/x86/isa/insts/general_purpose/compare_and_test/bounds.py
/gem5/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py
/gem5/src/arch/x86/isa/insts/general_purpose/control_transfer/jump.py
/gem5/src/arch/x86/isa/insts/system/undefined_operation.py
/gem5/src/arch/x86/isa/insts/x87/arithmetic/addition.py
/gem5/src/arch/x86/isa/insts/x87/arithmetic/subtraction.py
/gem5/src/arch/x86/isa/insts/x87/data_transfer_and_conversion/exchange.py
/gem5/src/arch/x86/isa/microops/debug.isa
/gem5/src/arch/x86/isa/microops/regop.isa
/gem5/src/arch/x86/memhelpers.hh
/gem5/src/arch/x86/pagetable_walker.cc
/gem5/src/arch/x86/tlb.cc
/gem5/src/arch/x86/tlb.hh
/gem5/src/arch/x86/vtophys.cc
/gem5/src/base/types.hh
/gem5/src/cpu/base_dyn_inst.hh
/gem5/src/cpu/exec_context.hh
/gem5/src/cpu/inorder/inorder_dyn_inst.cc
/gem5/src/cpu/inorder/inorder_dyn_inst.hh
/gem5/src/cpu/o3/dyn_inst_impl.hh
/gem5/src/cpu/o3/lsq_unit.hh
/gem5/src/cpu/o3/lsq_unit_impl.hh
/gem5/src/cpu/static_inst.hh
/gem5/src/sim/fault_fwd.hh
/gem5/src/sim/faults.hh
/gem5/src/sim/tlb.hh
10196:be0e1724eb39 09-May-2014 Curtis Dunham <Curtis.Dunham@arm.com>

arch: teach ISA parser how to split code across files

This patch encompasses several interrelated and interdependent changes
to the ISA generation step. The end goal is to reduce the size of the
generated compilation units for instruction execution and decoding so
that batch compilation can proceed with all CPUs active without
exhausting physical memory.

The ISA parser (src/arch/isa_parser.py) has been improved so that it can
accept 'split [output_type];' directives at the top level of the grammar
and 'split(output_type)' python calls within 'exec {{ ... }}' blocks.
This has the effect of "splitting" the files into smaller compilation
units. I use air-quotes around "splitting" because the files themselves
are not split, but preprocessing directives are inserted to have the same
effect.

Architecturally, the ISA parser has had some changes in how it works.
In general, it emits code sooner. It doesn't generate per-CPU files,
and instead defers to the C preprocessor to create the duplicate copies
for each CPU type. Likewise there are more files emitted and the C
preprocessor does more substitution that used to be done by the ISA parser.

Finally, the build system (SCons) needs to be able to cope with a
dynamic list of source files coming out of the ISA parser. The changes
to the SCons{cript,truct} files support this. In broad strokes, the
targets requested on the command line are hidden from SCons until all
the build dependencies are determined, otherwise it would try, realize
it can't reach the goal, and terminate in failure. Since build steps
(i.e. running the ISA parser) must be taken to determine the file list,
several new build stages have been inserted at the very start of the
build. First, the build dependencies from the ISA parser will be emitted
to arch/$ISA/generated/inc.d, which is then read by a new SCons builder
to finalize the dependencies. (Once inc.d exists, the ISA parser will not
need to be run to complete this step.) Once the dependencies are known,
the 'Environments' are made by the makeEnv() function. This function used
to be called before the build began but now happens during the build.
It is easy to see that this step is quite slow; this is a known issue
and it's important to realize that it was already slow, but there was
no obvious cause to attribute it to since nothing was displayed to the
terminal. Since new steps that used to be performed serially are now in a
potentially-parallel build phase, the pathname handling in the SCons scripts
has been tightened up to deal with chdir() race conditions. In general,
pathnames are computed earlier and more likely to be stored, passed around,
and processed as absolute paths rather than relative paths. In the end,
some of these issues had to be fixed by inserting serializing dependencies
in the build.

Minor note:
For the null ISA, we just provide a dummy inc.d so SCons is never
compelled to try to generate it. While it seems slightly wrong to have
anything in src/arch/*/generated (i.e. a non-generated 'generated' file),
it's by far the simplest solution.


/gem5/SConstruct
/gem5/src/SConscript
/gem5/src/arch/SConscript
/gem5/src/arch/alpha/SConscript
/gem5/src/arch/alpha/isa/fp.isa
/gem5/src/arch/alpha/isa/main.isa
/gem5/src/arch/alpha/isa/mem.isa
/gem5/src/arch/alpha/isa/opcdec.isa
/gem5/src/arch/alpha/isa/unimp.isa
/gem5/src/arch/alpha/isa/unknown.isa
/gem5/src/arch/arm/SConscript
/gem5/src/arch/arm/isa/formats/breakpoint.isa
/gem5/src/arch/arm/isa/formats/unimp.isa
/gem5/src/arch/arm/isa/templates/basic.isa
/gem5/src/arch/arm/isa/templates/macromem.isa
/gem5/src/arch/arm/isa/templates/mem.isa
/gem5/src/arch/arm/isa/templates/mem64.isa
/gem5/src/arch/arm/isa/templates/neon.isa
/gem5/src/arch/arm/isa/templates/neon64.isa
/gem5/src/arch/arm/isa/templates/pred.isa
/gem5/src/arch/isa_parser.py
/gem5/src/arch/mips/SConscript
/gem5/src/arch/mips/isa/formats/basic.isa
/gem5/src/arch/mips/isa/formats/control.isa
/gem5/src/arch/mips/isa/formats/dsp.isa
/gem5/src/arch/mips/isa/formats/fp.isa
/gem5/src/arch/mips/isa/formats/int.isa
/gem5/src/arch/mips/isa/formats/mem.isa
/gem5/src/arch/mips/isa/formats/mt.isa
/gem5/src/arch/mips/isa/formats/noop.isa
/gem5/src/arch/mips/isa/formats/tlbop.isa
/gem5/src/arch/mips/isa/formats/trap.isa
/gem5/src/arch/mips/isa/formats/unimp.isa
/gem5/src/arch/mips/isa/formats/unknown.isa
/gem5/src/arch/null/generated/inc.d
/gem5/src/arch/power/SConscript
formats/basic.isa
formats/mem.isa
formats/misc.isa
formats/unimp.isa
formats/unknown.isa
/gem5/src/arch/sparc/SConscript
/gem5/src/arch/sparc/isa/base.isa
/gem5/src/arch/sparc/isa/formats/basic.isa
/gem5/src/arch/sparc/isa/formats/branch.isa
/gem5/src/arch/sparc/isa/formats/integerop.isa
/gem5/src/arch/sparc/isa/formats/mem/swap.isa
/gem5/src/arch/sparc/isa/formats/mem/util.isa
/gem5/src/arch/sparc/isa/formats/nop.isa
/gem5/src/arch/sparc/isa/formats/priv.isa
/gem5/src/arch/sparc/isa/formats/trap.isa
/gem5/src/arch/sparc/isa/formats/unimp.isa
/gem5/src/arch/sparc/isa/formats/unknown.isa
/gem5/src/arch/x86/SConscript
/gem5/src/arch/x86/isa/formats/basic.isa
/gem5/src/arch/x86/isa/formats/cpuid.isa
/gem5/src/arch/x86/isa/formats/nop.isa
/gem5/src/arch/x86/isa/formats/syscall.isa
/gem5/src/arch/x86/isa/formats/unimp.isa
/gem5/src/arch/x86/isa/formats/unknown.isa
/gem5/src/arch/x86/isa/microops/debug.isa
/gem5/src/arch/x86/isa/microops/fpop.isa
/gem5/src/arch/x86/isa/microops/ldstop.isa
/gem5/src/arch/x86/isa/microops/limmop.isa
/gem5/src/arch/x86/isa/microops/mediaop.isa
/gem5/src/arch/x86/isa/microops/regop.isa
/gem5/src/arch/x86/isa/microops/seqop.isa
/gem5/src/arch/x86/isa/microops/specop.isa
/gem5/tests/SConscript
10184:bbfa3152bdea 09-May-2014 Curtis Dunham <Curtis.Dunham@arm.com>

arch: remove inline specifiers on all inst constrs, all ISAs

With (upcoming) separate compilation, they are useless. Only
link-time optimization could re-inline them, but ideally
feedback-directed optimization would choose to do so only for
profitable (i.e. common) instructions.

9022:bb25e7646c41 25-May-2012 Gabe Black <gblack@eecs.umich.edu>

ISA: Make the decode function part of the ISA's decoder.

8946:fb6c89334b86 14-Apr-2012 Andreas Hansson <andreas.hansson@arm.com>

clang/gcc: Fix compilation issues with clang 3.0 and gcc 4.6

This patch addresses a number of minor issues that cause problems when
compiling with clang >= 3.0 and gcc >= 4.6. Most importantly, it
avoids using the deprecated ext/hash_map and instead uses
unordered_map (and similarly so for the hash_set). To make use of the
new STL containers, g++ and clang has to be invoked with "-std=c++0x",
and this is now added for all gcc versions >= 4.6, and for clang >=
3.0. For gcc >= 4.3 and <= 4.5 and clang <= 3.0 we use the tr1
unordered_map to avoid the deprecation warning.

The addition of c++0x in turn causes a few problems, as the
compiler is more stringent and adds a number of new warnings. Below,
the most important issues are enumerated:

1) the use of namespaces is more strict, e.g. for isnan, and all
headers opening the entire namespace std are now fixed.

2) another other issue caused by the more stringent compiler is the
narrowing of the embedded python, which used to be a char array,
and is now unsigned char since there were values larger than 128.

3) a particularly odd issue that arose with the new c++0x behaviour is
found in range.hh, where the operator< causes gcc to complain about
the template type parsing (the "<" is interpreted as the beginning
of a template argument), and the problem seems to be related to the
begin/end members introduced for the range-type iteration, which is
a new feature in c++11.

As a minor update, this patch also fixes the build flags for the clang
debug target that used to be shared with gcc and incorrectly use
"-ggdb".

8917:a16ba72db7d0 26-Mar-2012 Andreas Hansson <andreas.hansson@arm.com>

Power: Change bitfield name to avoid conflicts with range_map

This patch changes the name of a bitfield from W to W_FIELD to avoid
clashes with W being used as a class (typename) in the templatized
range_map. It also changes L to L_FIELD to avoid future problems. The
problem manifestes itself when the CPU includes a header that in turn
includes range_map.hh. The relevant parts of the decoder are updated.

8607:5fb918115c07 31-Oct-2011 Gabe Black <gblack@eecs.umich.edu>

GCC: Get everything working with gcc 4.6.1.

And by "everything" I mean all the quick regressions.

8588:ef28ed90449d 27-Sep-2011 Gabe Black <gblack@eecs.umich.edu>

ISA parser: Use '_' instead of '.' to delimit type modifiers on operands.

By using an underscore, the "." is still available and can unambiguously be
used to refer to members of a structure if an operand is a structure, class,
etc. This change mostly just replaces the appropriate "."s with "_"s, but
there were also a few places where the ISA descriptions where handling the
extensions themselves and had their own regular expressions to update. The
regular expressions in the isa parser were updated as well. It also now
looks for one of the defined type extensions specifically after connecting "_"
where before it would look for any sequence of characters after a "."
following an operand name and try to use it as the extension. This helps to
disambiguate cases where a "_" may legitimately be part of an operand name but
not separate the name from the type suffix.

Because leaving the "_" and suffix on the variable name still leaves a valid
C++ identifier and all extensions need to be consistent in a given context, I
considered leaving them on as a breadcrumb that would show what the intended
type was for that operand. Unfortunately the operands can be referred to in
code templates, the Mem operand in particular, and since the exact type of Mem
can be different for different uses of the same template, that broke things.

8450:40e10746b049 05-Jul-2011 Gabe Black <gblack@eecs.umich.edu>

ISAs: Streamline some spots where Mem is used in the ISA descriptions.

8449:4be49ad47c74 05-Jul-2011 Gabe Black <gblack@eecs.umich.edu>

ISA parser: Define operand types with a ctype directly.

8448:86ed97566b23 05-Jul-2011 Gabe Black <gblack@eecs.umich.edu>

ISA parser: Simplify operand type handling.

This change simplifies the code surrounding operand type handling and makes it
depend only on the ctype that goes with each operand type. Future changes will
allow defining operand types by their ctypes directly, convert the ISAs over
to that style of definition, and then remove support for the old style. These
changes are to make it easier to use non-builtin types like classes or
structures as the type for operands.

8442:b1f3dfae06f1 03-Jul-2011 Gabe Black <gblack@eecs.umich.edu>

ISA: Use readBytes/writeBytes for all instruction level memory operations.

8230:845c8eb5ac49 15-Apr-2011 Nathan Binkert <nate@binkert.org>

includes: fix up code after sorting

8229:78bf55f23338 15-Apr-2011 Nathan Binkert <nate@binkert.org>

includes: sort all includes


/gem5/src/arch/alpha/faults.cc
/gem5/src/arch/alpha/isa.hh
/gem5/src/arch/alpha/isa/main.isa
/gem5/src/arch/alpha/linux/system.cc
/gem5/src/arch/alpha/mt.hh
/gem5/src/arch/alpha/process.cc
/gem5/src/arch/alpha/remote_gdb.cc
/gem5/src/arch/alpha/remote_gdb.hh
/gem5/src/arch/alpha/tlb.cc
/gem5/src/arch/alpha/tru64/process.cc
/gem5/src/arch/alpha/types.hh
/gem5/src/arch/alpha/utility.hh
/gem5/src/arch/arm/faults.cc
/gem5/src/arch/arm/faults.hh
/gem5/src/arch/arm/insts/macromem.cc
/gem5/src/arch/arm/insts/static_inst.cc
/gem5/src/arch/arm/insts/vfp.hh
/gem5/src/arch/arm/intregs.hh
/gem5/src/arch/arm/isa/includes.isa
/gem5/src/arch/arm/linux/atag.hh
/gem5/src/arch/arm/linux/linux.cc
/gem5/src/arch/arm/linux/process.cc
/gem5/src/arch/arm/linux/process.hh
/gem5/src/arch/arm/linux/system.cc
/gem5/src/arch/arm/locked_mem.hh
/gem5/src/arch/arm/pagetable.hh
/gem5/src/arch/arm/predecoder.hh
/gem5/src/arch/arm/process.hh
/gem5/src/arch/arm/registers.hh
/gem5/src/arch/arm/remote_gdb.cc
/gem5/src/arch/arm/system.cc
/gem5/src/arch/arm/system.hh
/gem5/src/arch/arm/table_walker.cc
/gem5/src/arch/arm/table_walker.hh
/gem5/src/arch/arm/tlb.hh
/gem5/src/arch/arm/vtophys.hh
/gem5/src/arch/generic/debugfaults.hh
/gem5/src/arch/generic/types.hh
/gem5/src/arch/mips/dsp.cc
/gem5/src/arch/mips/dsp.hh
/gem5/src/arch/mips/isa.cc
/gem5/src/arch/mips/isa.hh
/gem5/src/arch/mips/isa/includes.isa
/gem5/src/arch/mips/isa_traits.hh
/gem5/src/arch/mips/linux/linux.cc
/gem5/src/arch/mips/linux/process.cc
/gem5/src/arch/mips/linux/process.hh
/gem5/src/arch/mips/linux/system.cc
/gem5/src/arch/mips/mt.hh
/gem5/src/arch/mips/process.cc
/gem5/src/arch/mips/process.hh
/gem5/src/arch/mips/system.cc
/gem5/src/arch/mips/system.hh
/gem5/src/arch/mips/tlb.cc
/gem5/src/arch/mips/tlb.hh
/gem5/src/arch/mips/utility.cc
/gem5/src/arch/mips/utility.hh
/gem5/src/arch/mips/vtophys.hh
/gem5/src/arch/power/insts/floating.hh
/gem5/src/arch/power/insts/integer.hh
includes.isa
/gem5/src/arch/power/linux/linux.cc
/gem5/src/arch/power/linux/process.cc
/gem5/src/arch/power/linux/process.hh
/gem5/src/arch/power/process.hh
/gem5/src/arch/power/tlb.hh
/gem5/src/arch/power/vtophys.hh
/gem5/src/arch/sparc/isa.hh
/gem5/src/arch/sparc/isa/includes.isa
/gem5/src/arch/sparc/isa_traits.hh
/gem5/src/arch/sparc/linux/linux.cc
/gem5/src/arch/sparc/linux/process.cc
/gem5/src/arch/sparc/locked_mem.hh
/gem5/src/arch/sparc/mmapped_ipr.hh
/gem5/src/arch/sparc/nativetrace.cc
/gem5/src/arch/sparc/process.cc
/gem5/src/arch/sparc/process.hh
/gem5/src/arch/sparc/remote_gdb.cc
/gem5/src/arch/sparc/remote_gdb.hh
/gem5/src/arch/sparc/solaris/process.cc
/gem5/src/arch/sparc/solaris/solaris.cc
/gem5/src/arch/sparc/system.cc
/gem5/src/arch/sparc/tlb.cc
/gem5/src/arch/sparc/tlb_map.hh
/gem5/src/arch/sparc/types.hh
/gem5/src/arch/sparc/utility.hh
/gem5/src/arch/sparc/vtophys.cc
/gem5/src/arch/x86/bios/acpi.cc
/gem5/src/arch/x86/bios/intelmp.hh
/gem5/src/arch/x86/emulenv.hh
/gem5/src/arch/x86/faults.hh
/gem5/src/arch/x86/insts/badmicroop.cc
/gem5/src/arch/x86/insts/macroop.hh
/gem5/src/arch/x86/insts/microfpop.cc
/gem5/src/arch/x86/insts/microldstop.cc
/gem5/src/arch/x86/insts/micromediaop.cc
/gem5/src/arch/x86/interrupts.cc
/gem5/src/arch/x86/interrupts.hh
/gem5/src/arch/x86/isa.hh
/gem5/src/arch/x86/isa/includes.isa
/gem5/src/arch/x86/linux/linux.cc
/gem5/src/arch/x86/linux/process.cc
/gem5/src/arch/x86/linux/process.hh
/gem5/src/arch/x86/linux/syscalls.cc
/gem5/src/arch/x86/linux/system.cc
/gem5/src/arch/x86/linux/system.hh
/gem5/src/arch/x86/microcode_rom.hh
/gem5/src/arch/x86/nativetrace.cc
/gem5/src/arch/x86/pagetable_walker.cc
/gem5/src/arch/x86/pagetable_walker.hh
/gem5/src/arch/x86/predecoder.hh
/gem5/src/arch/x86/process.cc
/gem5/src/arch/x86/process.hh
/gem5/src/arch/x86/registers.hh
/gem5/src/arch/x86/remote_gdb.cc
/gem5/src/arch/x86/system.cc
/gem5/src/arch/x86/tlb.cc
/gem5/src/arch/x86/tlb.hh
/gem5/src/base/cp_annotate.cc
/gem5/src/base/cp_annotate.hh
/gem5/src/base/cprintf.hh
/gem5/src/base/debug.cc
/gem5/src/base/fast_alloc.hh
/gem5/src/base/fenv.c
/gem5/src/base/hostinfo.cc
/gem5/src/base/inet.hh
/gem5/src/base/inifile.cc
/gem5/src/base/loader/aout_object.cc
/gem5/src/base/loader/elf_object.cc
/gem5/src/base/loader/elf_object.hh
/gem5/src/base/loader/hex_file.cc
/gem5/src/base/loader/object_file.cc
/gem5/src/base/loader/symtab.cc
/gem5/src/base/misc.cc
/gem5/src/base/mysql.hh
/gem5/src/base/output.cc
/gem5/src/base/pollevent.cc
/gem5/src/base/pollevent.hh
/gem5/src/base/range_map.hh
/gem5/src/base/remote_gdb.cc
/gem5/src/base/remote_gdb.hh
/gem5/src/base/socket.cc
/gem5/src/base/statistics.cc
/gem5/src/base/statistics.hh
/gem5/src/base/stats/info.hh
/gem5/src/base/stats/mysql.cc
/gem5/src/base/stats/output.cc
/gem5/src/base/stats/text.cc
/gem5/src/base/stats/text.hh
/gem5/src/base/str.hh
/gem5/src/base/time.hh
/gem5/src/base/trace.cc
/gem5/src/base/vnc/convert.cc
/gem5/src/base/vnc/vncserver.cc
/gem5/src/base/vnc/vncserver.hh
/gem5/src/cpu/activity.cc
/gem5/src/cpu/activity.hh
/gem5/src/cpu/base.cc
/gem5/src/cpu/base.hh
/gem5/src/cpu/base_dyn_inst_impl.hh
/gem5/src/cpu/checker/cpu.cc
/gem5/src/cpu/checker/cpu.hh
/gem5/src/cpu/checker/cpu_impl.hh
/gem5/src/cpu/cpuevent.hh
/gem5/src/cpu/exetrace.cc
/gem5/src/cpu/func_unit.hh
/gem5/src/cpu/inorder/cpu.cc
/gem5/src/cpu/inorder/cpu.hh
/gem5/src/cpu/inorder/first_stage.cc
/gem5/src/cpu/inorder/first_stage.hh
/gem5/src/cpu/inorder/inorder_cpu_builder.cc
/gem5/src/cpu/inorder/inorder_dyn_inst.cc
/gem5/src/cpu/inorder/inorder_dyn_inst.hh
/gem5/src/cpu/inorder/inorder_trace.cc
/gem5/src/cpu/inorder/pipeline_stage.cc
/gem5/src/cpu/inorder/pipeline_stage.hh
/gem5/src/cpu/inorder/pipeline_traits.5stage.cc
/gem5/src/cpu/inorder/pipeline_traits.5stage.hh
/gem5/src/cpu/inorder/pipeline_traits.9stage.cc
/gem5/src/cpu/inorder/pipeline_traits.9stage.hh
/gem5/src/cpu/inorder/pipeline_traits.9stage.smt2.cc
/gem5/src/cpu/inorder/pipeline_traits.9stage.smt2.hh
/gem5/src/cpu/inorder/pipeline_traits.hh
/gem5/src/cpu/inorder/reg_dep_map.cc
/gem5/src/cpu/inorder/resource.cc
/gem5/src/cpu/inorder/resource.hh
/gem5/src/cpu/inorder/resource_pool.9stage.cc
/gem5/src/cpu/inorder/resource_pool.cc
/gem5/src/cpu/inorder/resource_pool.hh
/gem5/src/cpu/inorder/resource_sked.cc
/gem5/src/cpu/inorder/resource_sked.hh
/gem5/src/cpu/inorder/resources/agen_unit.hh
/gem5/src/cpu/inorder/resources/bpred_unit.hh
/gem5/src/cpu/inorder/resources/branch_predictor.hh
/gem5/src/cpu/inorder/resources/cache_unit.cc
/gem5/src/cpu/inorder/resources/cache_unit.hh
/gem5/src/cpu/inorder/resources/decode_unit.hh
/gem5/src/cpu/inorder/resources/execution_unit.cc
/gem5/src/cpu/inorder/resources/execution_unit.hh
/gem5/src/cpu/inorder/resources/fetch_seq_unit.hh
/gem5/src/cpu/inorder/resources/fetch_unit.cc
/gem5/src/cpu/inorder/resources/fetch_unit.hh
/gem5/src/cpu/inorder/resources/graduation_unit.hh
/gem5/src/cpu/inorder/resources/inst_buffer.cc
/gem5/src/cpu/inorder/resources/inst_buffer.hh
/gem5/src/cpu/inorder/resources/mem_dep_unit.hh
/gem5/src/cpu/inorder/resources/mult_div_unit.cc
/gem5/src/cpu/inorder/resources/mult_div_unit.hh
/gem5/src/cpu/inorder/resources/resource_list.hh
/gem5/src/cpu/inorder/resources/tlb_unit.cc
/gem5/src/cpu/inorder/resources/tlb_unit.hh
/gem5/src/cpu/inorder/resources/use_def.cc
/gem5/src/cpu/inorder/resources/use_def.hh
/gem5/src/cpu/inorder/thread_context.cc
/gem5/src/cpu/inorder/thread_context.hh
/gem5/src/cpu/inorder/thread_state.cc
/gem5/src/cpu/intr_control.cc
/gem5/src/cpu/intr_control.hh
/gem5/src/cpu/nativetrace.hh
/gem5/src/cpu/o3/base_dyn_inst.cc
/gem5/src/cpu/o3/bpred_unit.hh
/gem5/src/cpu/o3/bpred_unit_impl.hh
/gem5/src/cpu/o3/checker_builder.cc
/gem5/src/cpu/o3/commit.cc
/gem5/src/cpu/o3/commit.hh
/gem5/src/cpu/o3/commit_impl.hh
/gem5/src/cpu/o3/cpu.cc
/gem5/src/cpu/o3/cpu.hh
/gem5/src/cpu/o3/cpu_policy.hh
/gem5/src/cpu/o3/decode.cc
/gem5/src/cpu/o3/dyn_inst.hh
/gem5/src/cpu/o3/fetch.cc
/gem5/src/cpu/o3/fetch.hh
/gem5/src/cpu/o3/fetch_impl.hh
/gem5/src/cpu/o3/free_list.cc
/gem5/src/cpu/o3/fu_pool.hh
/gem5/src/cpu/o3/iew.cc
/gem5/src/cpu/o3/iew.hh
/gem5/src/cpu/o3/iew_impl.hh
/gem5/src/cpu/o3/impl.hh
/gem5/src/cpu/o3/inst_queue.cc
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7791:762276cd3cc7 08-Dec-2010 Gabe Black <gblack@eecs.umich.edu>

POWER: Take advantage of new PCState syntax.

7720:65d338a8dba4 31-Oct-2010 Gabe Black <gblack@eecs.umich.edu>

ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.



This change is a low level and pervasive reorganization of how PCs are managed
in M5. Back when Alpha was the only ISA, there were only 2 PCs to worry about,
the PC and the NPC, and the lsb of the PC signaled whether or not you were in
PAL mode. As other ISAs were added, we had to add an NNPC, micro PC and next
micropc, x86 and ARM introduced variable length instruction sets, and ARM
started to keep track of mode bits in the PC. Each CPU model handled PCs in
its own custom way that needed to be updated individually to handle the new
dimensions of variability, or, in the case of ARMs mode-bit-in-the-pc hack,
the complexity could be hidden in the ISA at the ISA implementation's expense.
Areas like the branch predictor hadn't been updated to handle branch delay
slots or micropcs, and it turns out that had introduced a significant (10s of
percent) performance bug in SPARC and to a lesser extend MIPS. Rather than
perpetuate the problem by reworking O3 again to handle the PC features needed
by x86, this change was introduced to rework PC handling in a more modular,
transparent, and hopefully efficient way.


PC type:

Rather than having the superset of all possible elements of PC state declared
in each of the CPU models, each ISA defines its own PCState type which has
exactly the elements it needs. A cross product of canned PCState classes are
defined in the new "generic" ISA directory for ISAs with/without delay slots
and microcode. These are either typedef-ed or subclassed by each ISA. To read
or write this structure through a *Context, you use the new pcState() accessor
which reads or writes depending on whether it has an argument. If you just
want the address of the current or next instruction or the current micro PC,
you can get those through read-only accessors on either the PCState type or
the *Contexts. These are instAddr(), nextInstAddr(), and microPC(). Note the
move away from readPC. That name is ambiguous since it's not clear whether or
not it should be the actual address to fetch from, or if it should have extra
bits in it like the PAL mode bit. Each class is free to define its own
functions to get at whatever values it needs however it needs to to be used in
ISA specific code. Eventually Alpha's PAL mode bit could be moved out of the
PC and into a separate field like ARM.

These types can be reset to a particular pc (where npc = pc +
sizeof(MachInst), nnpc = npc + sizeof(MachInst), upc = 0, nupc = 1 as
appropriate), printed, serialized, and compared. There is a branching()
function which encapsulates code in the CPU models that checked if an
instruction branched or not. Exactly what that means in the context of branch
delay slots which can skip an instruction when not taken is ambiguous, and
ideally this function and its uses can be eliminated. PCStates also generally
know how to advance themselves in various ways depending on if they point at
an instruction, a microop, or the last microop of a macroop. More on that
later.

Ideally, accessing all the PCs at once when setting them will improve
performance of M5 even though more data needs to be moved around. This is
because often all the PCs need to be manipulated together, and by getting them
all at once you avoid multiple function calls. Also, the PCs of a particular
thread will have spatial locality in the cache. Previously they were grouped
by element in arrays which spread out accesses.


Advancing the PC:

The PCs were previously managed entirely by the CPU which had to know about PC
semantics, try to figure out which dimension to increment the PC in, what to
set NPC/NNPC, etc. These decisions are best left to the ISA in conjunction
with the PC type itself. Because most of the information about how to
increment the PC (mainly what type of instruction it refers to) is contained
in the instruction object, a new advancePC virtual function was added to the
StaticInst class. Subclasses provide an implementation that moves around the
right element of the PC with a minimal amount of decision making. In ISAs like
Alpha, the instructions always simply assign NPC to PC without having to worry
about micropcs, nnpcs, etc. The added cost of a virtual function call should
be outweighed by not having to figure out as much about what to do with the
PCs and mucking around with the extra elements.

One drawback of making the StaticInsts advance the PC is that you have to
actually have one to advance the PC. This would, superficially, seem to
require decoding an instruction before fetch could advance. This is, as far as
I can tell, realistic. fetch would advance through memory addresses, not PCs,
perhaps predicting new memory addresses using existing ones. More
sophisticated decisions about control flow would be made later on, after the
instruction was decoded, and handed back to fetch. If branching needs to
happen, some amount of decoding needs to happen to see that it's a branch,
what the target is, etc. This could get a little more complicated if that gets
done by the predecoder, but I'm choosing to ignore that for now.


Variable length instructions:

To handle variable length instructions in x86 and ARM, the predecoder now
takes in the current PC by reference to the getExtMachInst function. It can
modify the PC however it needs to (by setting NPC to be the PC + instruction
length, for instance). This could be improved since the CPU doesn't know if
the PC was modified and always has to write it back.


ISA parser:

To support the new API, all PC related operand types were removed from the
parser and replaced with a PCState type. There are two warts on this
implementation. First, as with all the other operand types, the PCState still
has to have a valid operand type even though it doesn't use it. Second, using
syntax like PCS.npc(target) doesn't work for two reasons, this looks like the
syntax for operand type overriding, and the parser can't figure out if you're
reading or writing. Instructions that use the PCS operand (which I've
consistently called it) need to first read it into a local variable,
manipulate it, and then write it back out.


Return address stack:

The return address stack needed a little extra help because, in the presence
of branch delay slots, it has to merge together elements of the return PC and
the call PC. To handle that, a buildRetPC utility function was added. There
are basically only two versions in all the ISAs, but it didn't seem short
enough to put into the generic ISA directory. Also, the branch predictor code
in O3 and InOrder were adjusted so that they always store the PC of the actual
call instruction in the RAS, not the next PC. If the call instruction is a
microop, the next PC refers to the next microop in the same macroop which is
probably not desirable. The buildRetPC function advances the PC intelligently
to the next macroop (in an ISA specific way) so that that case works.


Change in stats:

There were no change in stats except in MIPS and SPARC in the O3 model. MIPS
runs in about 9% fewer ticks. SPARC runs with 30%-50% fewer ticks, which could
likely be improved further by setting call/return instruction flags and taking
advantage of the RAS.


TODO:

Add != operators to the PCState classes, defined trivially to be !(a==b).
Smooth out places where PCs are split apart, passed around, and put back
together later. I think this might happen in SPARC's fault code. Add ISA
specific constructors that allow setting PC elements without calling a bunch
of accessors. Try to eliminate the need for the branching() function. Factor
out Alpha's PAL mode pc bit into a separate flag field, and eliminate places
where it's blindly masked out or tested in the PC.


/gem5/src/arch/alpha/ev5.cc
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/gem5/src/arch/alpha/isa/branch.isa
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/gem5/src/arch/arm/linux/system.cc
/gem5/src/arch/arm/nativetrace.cc
/gem5/src/arch/arm/predecoder.cc
/gem5/src/arch/arm/predecoder.hh
/gem5/src/arch/arm/process.cc
/gem5/src/arch/arm/system.hh
/gem5/src/arch/arm/table_walker.cc
/gem5/src/arch/arm/tlb.cc
/gem5/src/arch/arm/types.hh
/gem5/src/arch/arm/utility.cc
/gem5/src/arch/arm/utility.hh
/gem5/src/arch/generic/types.hh
/gem5/src/arch/isa_parser.py
/gem5/src/arch/mips/isa/base.isa
/gem5/src/arch/mips/isa/decoder.isa
/gem5/src/arch/mips/isa/formats/branch.isa
/gem5/src/arch/mips/isa/includes.isa
/gem5/src/arch/mips/isa/operands.isa
/gem5/src/arch/mips/mt.hh
/gem5/src/arch/mips/predecoder.hh
/gem5/src/arch/mips/process.cc
/gem5/src/arch/mips/types.hh
/gem5/src/arch/mips/utility.cc
/gem5/src/arch/mips/utility.hh
/gem5/src/arch/power/insts/branch.cc
/gem5/src/arch/power/insts/branch.hh
/gem5/src/arch/power/insts/static_inst.hh
decoder.isa
formats/branch.isa
formats/unknown.isa
operands.isa
/gem5/src/arch/power/predecoder.hh
/gem5/src/arch/power/process.cc
/gem5/src/arch/power/types.hh
/gem5/src/arch/power/utility.cc
/gem5/src/arch/power/utility.hh
/gem5/src/arch/sparc/faults.cc
/gem5/src/arch/sparc/isa/base.isa
/gem5/src/arch/sparc/isa/decoder.isa
/gem5/src/arch/sparc/isa/formats/branch.isa
/gem5/src/arch/sparc/isa/formats/micro.isa
/gem5/src/arch/sparc/isa/operands.isa
/gem5/src/arch/sparc/nativetrace.cc
/gem5/src/arch/sparc/predecoder.hh
/gem5/src/arch/sparc/process.cc
/gem5/src/arch/sparc/remote_gdb.cc
/gem5/src/arch/sparc/types.hh
/gem5/src/arch/sparc/utility.cc
/gem5/src/arch/sparc/utility.hh
/gem5/src/arch/x86/faults.cc
/gem5/src/arch/x86/insts/macroop.hh
/gem5/src/arch/x86/insts/microop.hh
/gem5/src/arch/x86/insts/static_inst.hh
/gem5/src/arch/x86/isa/decoder/two_byte_opcodes.isa
/gem5/src/arch/x86/isa/formats/unknown.isa
/gem5/src/arch/x86/isa/microops/regop.isa
/gem5/src/arch/x86/isa/microops/seqop.isa
/gem5/src/arch/x86/isa/operands.isa
/gem5/src/arch/x86/nativetrace.cc
/gem5/src/arch/x86/predecoder.hh
/gem5/src/arch/x86/process.cc
/gem5/src/arch/x86/system.cc
/gem5/src/arch/x86/tlb.cc
/gem5/src/arch/x86/types.hh
/gem5/src/arch/x86/utility.cc
/gem5/src/arch/x86/utility.hh
/gem5/src/base/remote_gdb.cc
/gem5/src/base/types.hh
/gem5/src/cpu/base_dyn_inst.hh
/gem5/src/cpu/base_dyn_inst_impl.hh
/gem5/src/cpu/checker/cpu.hh
/gem5/src/cpu/exetrace.cc
/gem5/src/cpu/exetrace.hh
/gem5/src/cpu/inorder/comm.hh
/gem5/src/cpu/inorder/cpu.cc
/gem5/src/cpu/inorder/cpu.hh
/gem5/src/cpu/inorder/first_stage.cc
/gem5/src/cpu/inorder/inorder_dyn_inst.cc
/gem5/src/cpu/inorder/inorder_dyn_inst.hh
/gem5/src/cpu/inorder/inorder_trace.cc
/gem5/src/cpu/inorder/inorder_trace.hh
/gem5/src/cpu/inorder/pipeline_stage.cc
/gem5/src/cpu/inorder/pipeline_stage.hh
/gem5/src/cpu/inorder/resources/bpred_unit.cc
/gem5/src/cpu/inorder/resources/bpred_unit.hh
/gem5/src/cpu/inorder/resources/branch_predictor.cc
/gem5/src/cpu/inorder/resources/cache_unit.cc
/gem5/src/cpu/inorder/resources/execution_unit.cc
/gem5/src/cpu/inorder/resources/fetch_seq_unit.cc
/gem5/src/cpu/inorder/resources/fetch_seq_unit.hh
/gem5/src/cpu/inorder/resources/tlb_unit.hh
/gem5/src/cpu/inorder/thread_context.cc
/gem5/src/cpu/inorder/thread_context.hh
/gem5/src/cpu/inorder/thread_state.hh
/gem5/src/cpu/inteltrace.cc
/gem5/src/cpu/inteltrace.hh
/gem5/src/cpu/legiontrace.cc
/gem5/src/cpu/legiontrace.hh
/gem5/src/cpu/nativetrace.hh
/gem5/src/cpu/o3/bpred_unit.hh
/gem5/src/cpu/o3/bpred_unit_impl.hh
/gem5/src/cpu/o3/comm.hh
/gem5/src/cpu/o3/commit.hh
/gem5/src/cpu/o3/commit_impl.hh
/gem5/src/cpu/o3/cpu.cc
/gem5/src/cpu/o3/cpu.hh
/gem5/src/cpu/o3/decode_impl.hh
/gem5/src/cpu/o3/dep_graph.hh
/gem5/src/cpu/o3/dyn_inst.hh
/gem5/src/cpu/o3/dyn_inst_impl.hh
/gem5/src/cpu/o3/fetch.hh
/gem5/src/cpu/o3/fetch_impl.hh
/gem5/src/cpu/o3/iew_impl.hh
/gem5/src/cpu/o3/inst_queue_impl.hh
/gem5/src/cpu/o3/lsq_unit.hh
/gem5/src/cpu/o3/lsq_unit_impl.hh
/gem5/src/cpu/o3/mem_dep_unit_impl.hh
/gem5/src/cpu/o3/rename_impl.hh
/gem5/src/cpu/o3/rob_impl.hh
/gem5/src/cpu/o3/thread_context.hh
/gem5/src/cpu/o3/thread_context_impl.hh
/gem5/src/cpu/pc_event.cc
/gem5/src/cpu/pred/btb.cc
/gem5/src/cpu/pred/btb.hh
/gem5/src/cpu/pred/ras.cc
/gem5/src/cpu/pred/ras.hh
/gem5/src/cpu/simple/atomic.cc
/gem5/src/cpu/simple/base.cc
/gem5/src/cpu/simple/base.hh
/gem5/src/cpu/simple/timing.cc
/gem5/src/cpu/simple_thread.cc
/gem5/src/cpu/simple_thread.hh
/gem5/src/cpu/static_inst.cc
/gem5/src/cpu/static_inst.hh
/gem5/src/cpu/thread_context.cc
/gem5/src/cpu/thread_context.hh
/gem5/src/kern/system_events.cc
/gem5/src/kern/tru64/tru64.hh
/gem5/src/sim/faults.cc
/gem5/src/sim/insttracer.hh
/gem5/src/sim/syscall_emul.cc
/gem5/src/sim/syscall_emul.hh
7712:7733c562e5e3 22-Oct-2010 Gabe Black <gblack@eecs.umich.edu>

ISA: Simplify various implementations of completeAcc.

7045:e21fe6a62b1c 23-Mar-2010 Steve Reinhardt <steve.reinhardt@amd.com>

cpu: fix exec tracing memory corruption bug
Accessing traceData (to call setAddress() and/or setData())
after initiating a timing translation was causing crashes,
since a failed translation could delete the traceData
object before returning.

It turns out that there was never a need to access traceData
after initiating the translation, as the traced data was
always available earlier; this ordering was merely
historical. Furthermore, traceData->setAddress() and
traceData->setData() were being called both from the CPU
model and the ISA definition, often redundantly.

This patch standardizes all setAddress and setData calls
for memory instructions to be in the CPU models and not
in the ISA definition. It also moves those calls above
the translation calls to eliminate the crashes.

6691:cd68b6ecd68d 27-Oct-2009 Timothy M. Jones <tjones1@inf.ed.ac.uk>

POWER: Add support for the Power ISA

This adds support for the 32-bit, big endian Power ISA. This supports both
integer and floating point instructions based on the Power ISA Book I v2.06.


/gem5/build_opts/POWER_SE
/gem5/src/arch/isa_parser.py
/gem5/src/arch/power/PowerTLB.py
/gem5/src/arch/power/SConscript
/gem5/src/arch/power/SConsopts
/gem5/src/arch/power/faults.hh
/gem5/src/arch/power/insts/branch.cc
/gem5/src/arch/power/insts/branch.hh
/gem5/src/arch/power/insts/condition.cc
/gem5/src/arch/power/insts/condition.hh
/gem5/src/arch/power/insts/floating.cc
/gem5/src/arch/power/insts/floating.hh
/gem5/src/arch/power/insts/integer.cc
/gem5/src/arch/power/insts/integer.hh
/gem5/src/arch/power/insts/mem.cc
/gem5/src/arch/power/insts/mem.hh
/gem5/src/arch/power/insts/misc.cc
/gem5/src/arch/power/insts/misc.hh
/gem5/src/arch/power/insts/static_inst.cc
/gem5/src/arch/power/insts/static_inst.hh
/gem5/src/arch/power/isa.hh
bitfields.isa
decoder.isa
formats/basic.isa
formats/branch.isa
formats/condition.isa
formats/formats.isa
formats/fp.isa
formats/integer.isa
formats/mem.isa
formats/misc.isa
formats/unimp.isa
formats/unknown.isa
formats/util.isa
includes.isa
main.isa
operands.isa
/gem5/src/arch/power/isa_traits.hh
/gem5/src/arch/power/linux/linux.cc
/gem5/src/arch/power/linux/linux.hh
/gem5/src/arch/power/linux/process.cc
/gem5/src/arch/power/linux/process.hh
/gem5/src/arch/power/locked_mem.hh
/gem5/src/arch/power/microcode_rom.hh
/gem5/src/arch/power/miscregs.hh
/gem5/src/arch/power/mmaped_ipr.hh
/gem5/src/arch/power/pagetable.cc
/gem5/src/arch/power/pagetable.hh
/gem5/src/arch/power/predecoder.hh
/gem5/src/arch/power/process.cc
/gem5/src/arch/power/process.hh
/gem5/src/arch/power/registers.hh
/gem5/src/arch/power/remote_gdb.hh
/gem5/src/arch/power/stacktrace.hh
/gem5/src/arch/power/tlb.cc
/gem5/src/arch/power/tlb.hh
/gem5/src/arch/power/types.hh
/gem5/src/arch/power/utility.hh
/gem5/src/arch/power/vtophys.hh
/gem5/src/base/loader/elf_object.cc
/gem5/src/base/loader/object_file.hh
/gem5/src/cpu/BaseCPU.py
/gem5/src/sim/process.cc