Cross Reference: /gem5/src/arch/arm/tracers/

History log of /gem5/src/arch/arm/tracers/
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13915:24ae4ea846c9	29-Apr-2019	Gabe Black <gabeblack@google.com>	arch: Stop using TheISA within the ISAs. We know for sure what the ISA is, so there's no need for the indirection. Change-Id: I73ff04c50890d40a4c7f40caeee746b68b846cb3 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18488 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> /gem5/src/arch/alpha/utility.cc /gem5/src/arch/arm/isa/insts/fp64.isa /gem5/src/arch/arm/isa/insts/ldr64.isa /gem5/src/arch/arm/isa/insts/neon64_mem.isa /gem5/src/arch/arm/isa/insts/sve.isa /gem5/src/arch/arm/isa/operands.isa tarmac_base.cc tarmac_base.hh tarmac_parser.cc tarmac_parser.hh tarmac_record.hh tarmac_record_v8.cc tarmac_record_v8.hh tarmac_tracer.cc tarmac_tracer.hh /gem5/src/arch/mips/utility.cc /gem5/src/arch/power/stacktrace.hh /gem5/src/arch/riscv/stacktrace.hh /gem5/src/arch/sparc/utility.cc /gem5/src/arch/x86/process.cc
13665:9c7fe3811b88	25-Jan-2019	Andreas Sandberg <andreas.sandberg@arm.com>	python: Don't assume SimObjects live in the global namespace The importer in Python 3 doesn't like the way we import SimObjects from the global namespace. Convert the existing SimObject declarations to import from m5.objects. As a side-effect, this makes these files consistent with configuration files. Change-Id: I11153502b430822130722839e1fa767b82a027aa Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15981 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> /gem5/src/arch/alpha/AlphaSystem.py /gem5/src/arch/alpha/AlphaTLB.py /gem5/src/arch/arm/ArmISA.py /gem5/src/arch/arm/ArmNativeTrace.py /gem5/src/arch/arm/ArmPMU.py /gem5/src/arch/arm/ArmSemihosting.py /gem5/src/arch/arm/ArmSystem.py /gem5/src/arch/arm/ArmTLB.py TarmacTrace.py /gem5/src/arch/mips/MipsSystem.py /gem5/src/arch/mips/MipsTLB.py /gem5/src/arch/power/PowerTLB.py /gem5/src/arch/riscv/RiscvSystem.py /gem5/src/arch/riscv/RiscvTLB.py /gem5/src/arch/sparc/SparcNativeTrace.py /gem5/src/arch/sparc/SparcSystem.py /gem5/src/arch/sparc/SparcTLB.py /gem5/src/arch/x86/X86LocalApic.py /gem5/src/arch/x86/X86NativeTrace.py /gem5/src/arch/x86/X86System.py /gem5/src/arch/x86/X86TLB.py /gem5/src/base/vnc/Vnc.py /gem5/src/cpu/BaseCPU.py /gem5/src/cpu/CPUTracers.py /gem5/src/cpu/CheckerCPU.py /gem5/src/cpu/DummyChecker.py /gem5/src/cpu/InstPBTrace.py /gem5/src/cpu/kvm/BaseKvmCPU.py /gem5/src/cpu/kvm/X86KvmCPU.py /gem5/src/cpu/minor/MinorCPU.py /gem5/src/cpu/o3/FUPool.py /gem5/src/cpu/o3/FuncUnitConfig.py /gem5/src/cpu/o3/O3CPU.py /gem5/src/cpu/o3/O3Checker.py /gem5/src/cpu/o3/probe/ElasticTrace.py /gem5/src/cpu/o3/probe/SimpleTrace.py /gem5/src/cpu/simple/AtomicSimpleCPU.py /gem5/src/cpu/simple/BaseSimpleCPU.py /gem5/src/cpu/simple/NonCachingSimpleCPU.py /gem5/src/cpu/simple/TimingSimpleCPU.py /gem5/src/cpu/simple/probes/SimPoint.py /gem5/src/cpu/testers/directedtest/RubyDirectedTester.py /gem5/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.py /gem5/src/cpu/testers/memtest/MemTest.py /gem5/src/cpu/testers/rubytest/RubyTester.py /gem5/src/cpu/testers/traffic_gen/BaseTrafficGen.py /gem5/src/cpu/testers/traffic_gen/PyTrafficGen.py /gem5/src/cpu/testers/traffic_gen/TrafficGen.py /gem5/src/cpu/trace/TraceCPU.py /gem5/src/dev/BadDevice.py /gem5/src/dev/Device.py /gem5/src/dev/Platform.py /gem5/src/dev/alpha/AlphaBackdoor.py /gem5/src/dev/alpha/Tsunami.py /gem5/src/dev/arm/EnergyCtrl.py /gem5/src/dev/arm/FlashDevice.py /gem5/src/dev/arm/Gic.py /gem5/src/dev/arm/NoMali.py /gem5/src/dev/arm/RealView.py /gem5/src/dev/arm/UFSHostDevice.py /gem5/src/dev/arm/VirtIOMMIO.py /gem5/src/dev/i2c/I2C.py /gem5/src/dev/mips/Malta.py /gem5/src/dev/net/Ethernet.py /gem5/src/dev/pci/CopyEngine.py /gem5/src/dev/pci/PciDevice.py /gem5/src/dev/pci/PciHost.py /gem5/src/dev/serial/Terminal.py /gem5/src/dev/serial/Uart.py /gem5/src/dev/sparc/T1000.py /gem5/src/dev/storage/Ide.py /gem5/src/dev/virtio/VirtIO.py /gem5/src/dev/virtio/VirtIO9P.py /gem5/src/dev/virtio/VirtIOBlock.py /gem5/src/dev/virtio/VirtIOConsole.py /gem5/src/dev/x86/Cmos.py /gem5/src/dev/x86/I8042.py /gem5/src/dev/x86/I82094AA.py /gem5/src/dev/x86/I8237.py /gem5/src/dev/x86/I8254.py /gem5/src/dev/x86/I8259.py /gem5/src/dev/x86/Pc.py /gem5/src/dev/x86/PcSpeaker.py /gem5/src/dev/x86/SouthBridge.py /gem5/src/gpu-compute/GPU.py /gem5/src/gpu-compute/LdsState.py /gem5/src/learning_gem5/part2/SimpleCache.py /gem5/src/learning_gem5/part2/SimpleMemobj.py /gem5/src/mem/AbstractMemory.py /gem5/src/mem/AddrMapper.py /gem5/src/mem/Bridge.py /gem5/src/mem/CommMonitor.py /gem5/src/mem/DRAMCtrl.py /gem5/src/mem/ExternalMaster.py /gem5/src/mem/ExternalSlave.py /gem5/src/mem/HMCController.py /gem5/src/mem/MemChecker.py /gem5/src/mem/MemDelay.py /gem5/src/mem/MemObject.py /gem5/src/mem/SerialLink.py /gem5/src/mem/SimpleMemory.py /gem5/src/mem/XBar.py /gem5/src/mem/cache/Cache.py /gem5/src/mem/cache/prefetch/Prefetcher.py /gem5/src/mem/cache/tags/Tags.py /gem5/src/mem/probes/MemFootprintProbe.py /gem5/src/mem/probes/MemTraceProbe.py /gem5/src/mem/probes/StackDistProbe.py /gem5/src/mem/qos/QoSMemCtrl.py /gem5/src/mem/qos/QoSMemSinkCtrl.py /gem5/src/mem/ruby/network/BasicRouter.py /gem5/src/mem/ruby/network/Network.py /gem5/src/mem/ruby/network/garnet2.0/GarnetLink.py /gem5/src/mem/ruby/network/garnet2.0/GarnetNetwork.py /gem5/src/mem/ruby/network/simple/SimpleLink.py /gem5/src/mem/ruby/network/simple/SimpleNetwork.py /gem5/src/mem/ruby/slicc_interface/Controller.py /gem5/src/mem/ruby/structures/LRUReplacementPolicy.py /gem5/src/mem/ruby/structures/PseudoLRUReplacementPolicy.py /gem5/src/mem/ruby/structures/RubyCache.py /gem5/src/mem/ruby/structures/RubyPrefetcher.py /gem5/src/mem/ruby/system/GPUCoalescer.py /gem5/src/mem/ruby/system/RubySystem.py /gem5/src/mem/ruby/system/Sequencer.py /gem5/src/mem/ruby/system/VIPERCoalescer.py /gem5/src/mem/ruby/system/WeightedLRUReplacementPolicy.py /gem5/src/mem/slicc/symbols/StateMachine.py /gem5/src/sim/System.py /gem5/src/sim/TickedObject.py /gem5/src/sim/power/MathExprPowerModel.py /gem5/src/sim/power/ThermalModel.py
13611:c8b7847b4171	19-Nov-2018	Gabe Black <gabeblack@google.com>	arch: cpu: Rename FloatRegBits to FloatReg. Now that there's no plain FloatReg, there's no reason to distinguish FloatRegBits with a special suffix since it's the only way to read or write FP registers. Change-Id: I3a60168c1d4302aed55223ea8e37b421f21efded Reviewed-on: https://gem5-review.googlesource.com/c/14460 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Gabe Black <gabeblack@google.com> /gem5/src/arch/alpha/ev5.cc /gem5/src/arch/alpha/registers.hh /gem5/src/arch/alpha/remote_gdb.cc /gem5/src/arch/alpha/utility.cc /gem5/src/arch/arm/kvm/arm_cpu.cc /gem5/src/arch/arm/kvm/armv8_cpu.cc tarmac_parser.cc tarmac_record.cc /gem5/src/arch/arm/utility.cc /gem5/src/arch/mips/isa/formats/fp.isa /gem5/src/arch/mips/registers.hh /gem5/src/arch/mips/remote_gdb.cc /gem5/src/arch/mips/utility.cc /gem5/src/arch/null/registers.hh /gem5/src/arch/power/registers.hh /gem5/src/arch/power/remote_gdb.cc /gem5/src/arch/power/utility.cc /gem5/src/arch/riscv/registers.hh /gem5/src/arch/riscv/remote_gdb.cc /gem5/src/arch/riscv/remote_gdb.hh /gem5/src/arch/sparc/utility.cc /gem5/src/arch/x86/insts/micromediaop.hh /gem5/src/arch/x86/isa/microops/mediaop.isa /gem5/src/arch/x86/nativetrace.cc /gem5/src/arch/x86/registers.hh /gem5/src/arch/x86/utility.cc /gem5/src/cpu/checker/cpu.hh /gem5/src/cpu/checker/cpu_impl.hh /gem5/src/cpu/checker/thread_context.hh /gem5/src/cpu/kvm/x86_cpu.cc /gem5/src/cpu/minor/exec_context.hh /gem5/src/cpu/o3/cpu.cc /gem5/src/cpu/o3/cpu.hh /gem5/src/cpu/o3/dyn_inst.hh /gem5/src/cpu/o3/regfile.hh /gem5/src/cpu/o3/thread_context.hh /gem5/src/cpu/o3/thread_context_impl.hh /gem5/src/cpu/simple/base.cc /gem5/src/cpu/simple/exec_context.hh /gem5/src/cpu/simple_thread.hh /gem5/src/cpu/thread_context.cc /gem5/src/cpu/thread_context.hh
13500:6e0a2a7c6d8c	19-Nov-2018	Gabe Black <gabeblack@google.com>	arch, cpu: Remove float type accessors. Use the binary accessors instead. Change-Id: Iff1877e92c79df02b3d13635391a8c2f025776a2 Reviewed-on: https://gem5-review.googlesource.com/c/14457 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Gabe Black <gabeblack@google.com> /gem5/src/arch/alpha/ev5.cc tarmac_record.cc /gem5/src/arch/arm/utility.cc /gem5/src/arch/mips/utility.cc /gem5/src/cpu/base_dyn_inst.hh /gem5/src/cpu/checker/cpu.hh /gem5/src/cpu/checker/cpu_impl.hh /gem5/src/cpu/checker/thread_context.hh /gem5/src/cpu/exec_context.hh /gem5/src/cpu/kvm/x86_cpu.cc /gem5/src/cpu/minor/exec_context.hh /gem5/src/cpu/o3/cpu.cc /gem5/src/cpu/o3/cpu.hh /gem5/src/cpu/o3/dyn_inst.hh /gem5/src/cpu/o3/regfile.hh /gem5/src/cpu/o3/thread_context.hh /gem5/src/cpu/o3/thread_context_impl.hh /gem5/src/cpu/simple/base.cc /gem5/src/cpu/simple/exec_context.hh /gem5/src/cpu/simple_thread.hh /gem5/src/cpu/thread_context.hh
13116:d3c3e2533928	25-Sep-2018	Giacomo Travaglini <giacomo.travaglini@arm.com>	arch-arm: Implement AArch64 ID_AA64MMFR2_EL1 register This patch implements AArch64 Memory Model Feature Register 2 (from ARMv8.2) Change-Id: I16d9acaf620fac6d1206e208bd143daec1657daf Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/13066 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> /gem5/src/arch/arm/ArmISA.py /gem5/src/arch/arm/isa.cc /gem5/src/arch/arm/miscregs.cc /gem5/src/arch/arm/miscregs.hh tarmac_parser.cc /gem5/src/arch/arm/utility.cc
12749:223c83ed9979	04-Jun-2018	Giacomo Travaglini <giacomo.travaglini@arm.com>	misc: Using smart pointers for memory Requests This patch is changing the underlying type for RequestPtr from Request* to shared_ptr<Request>. Having memory requests being managed by smart pointers will simplify the code; it will also prevent memory leakage and dangling pointers. Change-Id: I7749af38a11ac8eb4d53d8df1252951e0890fde3 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10996 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> /gem5/ext/sst/ExtMaster.cc /gem5/ext/sst/ExtSlave.cc /gem5/src/arch/alpha/locked_mem.hh /gem5/src/arch/alpha/tlb.cc /gem5/src/arch/alpha/tlb.hh /gem5/src/arch/arm/isa.cc /gem5/src/arch/arm/locked_mem.hh /gem5/src/arch/arm/stage2_lookup.cc /gem5/src/arch/arm/stage2_lookup.hh /gem5/src/arch/arm/stage2_mmu.cc /gem5/src/arch/arm/stage2_mmu.hh /gem5/src/arch/arm/table_walker.cc /gem5/src/arch/arm/table_walker.hh /gem5/src/arch/arm/tlb.cc /gem5/src/arch/arm/tlb.hh tarmac_parser.cc tarmac_parser.hh /gem5/src/arch/arm/vtophys.cc /gem5/src/arch/generic/locked_mem.hh /gem5/src/arch/generic/tlb.cc /gem5/src/arch/generic/tlb.hh /gem5/src/arch/hsail/insts/mem.hh /gem5/src/arch/mips/locked_mem.hh /gem5/src/arch/mips/tlb.cc /gem5/src/arch/mips/tlb.hh /gem5/src/arch/power/tlb.cc /gem5/src/arch/power/tlb.hh /gem5/src/arch/riscv/locked_mem.hh /gem5/src/arch/riscv/tlb.cc /gem5/src/arch/riscv/tlb.hh /gem5/src/arch/sparc/tlb.cc /gem5/src/arch/sparc/tlb.hh /gem5/src/arch/x86/intmessage.hh /gem5/src/arch/x86/pagetable_walker.cc /gem5/src/arch/x86/pagetable_walker.hh /gem5/src/arch/x86/tlb.cc /gem5/src/arch/x86/tlb.hh /gem5/src/cpu/base.cc /gem5/src/cpu/base_dyn_inst.hh /gem5/src/cpu/base_dyn_inst_impl.hh /gem5/src/cpu/checker/cpu.cc /gem5/src/cpu/checker/cpu.hh /gem5/src/cpu/checker/cpu_impl.hh /gem5/src/cpu/kvm/base.cc /gem5/src/cpu/kvm/x86_cpu.cc /gem5/src/cpu/minor/fetch1.cc /gem5/src/cpu/minor/fetch1.hh /gem5/src/cpu/minor/lsq.cc /gem5/src/cpu/minor/lsq.hh /gem5/src/cpu/o3/cpu.hh /gem5/src/cpu/o3/fetch.hh /gem5/src/cpu/o3/fetch_impl.hh /gem5/src/cpu/o3/lsq.hh /gem5/src/cpu/o3/lsq_impl.hh /gem5/src/cpu/o3/lsq_unit.hh /gem5/src/cpu/o3/lsq_unit_impl.hh /gem5/src/cpu/simple/atomic.cc /gem5/src/cpu/simple/atomic.hh /gem5/src/cpu/simple/base.cc /gem5/src/cpu/simple/base.hh /gem5/src/cpu/simple/timing.cc /gem5/src/cpu/simple/timing.hh /gem5/src/cpu/testers/directedtest/InvalidateGenerator.cc /gem5/src/cpu/testers/directedtest/RubyDirectedTester.cc /gem5/src/cpu/testers/directedtest/SeriesRequestGenerator.cc /gem5/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc /gem5/src/cpu/testers/memtest/memtest.cc /gem5/src/cpu/testers/rubytest/Check.cc /gem5/src/cpu/testers/rubytest/RubyTester.cc /gem5/src/cpu/testers/traffic_gen/base_gen.cc /gem5/src/cpu/testers/traffic_gen/traffic_gen.cc /gem5/src/cpu/trace/trace_cpu.cc /gem5/src/cpu/translation.hh /gem5/src/dev/dma_device.cc /gem5/src/dev/x86/i82094aa.cc /gem5/src/gpu-compute/compute_unit.cc /gem5/src/gpu-compute/fetch_unit.cc /gem5/src/gpu-compute/gpu_tlb.cc /gem5/src/gpu-compute/gpu_tlb.hh /gem5/src/gpu-compute/shader.cc /gem5/src/gpu-compute/shader.hh /gem5/src/learning_gem5/part2/simple_cache.cc /gem5/src/mem/abstract_mem.cc /gem5/src/mem/abstract_mem.hh /gem5/src/mem/cache/base.cc /gem5/src/mem/cache/blk.hh /gem5/src/mem/cache/cache.cc /gem5/src/mem/cache/mshr.cc /gem5/src/mem/cache/noncoherent_cache.cc /gem5/src/mem/cache/prefetch/queued.cc /gem5/src/mem/packet.hh /gem5/src/mem/page_table.cc /gem5/src/mem/page_table.hh /gem5/src/mem/port.cc /gem5/src/mem/port_proxy.cc /gem5/src/mem/request.hh /gem5/src/mem/ruby/slicc_interface/AbstractController.cc /gem5/src/mem/ruby/system/CacheRecorder.cc /gem5/src/mem/ruby/system/GPUCoalescer.cc /gem5/src/mem/ruby/system/GPUCoalescer.hh /gem5/src/mem/ruby/system/RubyPort.cc /gem5/src/mem/ruby/system/Sequencer.cc /gem5/util/tlm/src/sc_master_port.cc
12642:d0ce95094a54	14-Mar-2018	Giacomo Travaglini <giacomo.travaglini@arm.com>	arch-arm: Add support for Tarmac trace generation This patch introduces the TarmacTracer: an instruction tracer which allows to dump a gem5 execution trace in Tarmac format [1]. The new tracer is supporting either Tarmac and TarmacV8 format specifications. Not every traceable information has been implemented: Implemented Trace Type: Instruction Trace Register Trace Processor Memory Access Trace Unimplemented Trace Type: Program Flow Trace Event Trace Memory Bus Trace [1]: https://developer.arm.com/docs/dui0845/f/tarmac-trace-file-format Change-Id: I8799d8e5852e868673f728971db3fe8c63961f5e Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9382 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> SConscript TarmacTrace.py tarmac_record.cc tarmac_record.hh tarmac_record_v8.cc tarmac_record_v8.hh tarmac_tracer.cc tarmac_tracer.hh
12641:4c67bbebe381	14-Mar-2018	Giacomo Travaglini <giacomo.travaglini@arm.com>	arch-arm: Add support for Tarmac trace-based simulation A new InstTracer (TarmacParser) has been implemented. This tracer is parsing a pre-existing Tarmac trace file [1] while gem5 is running; it is comparing execution data together with trace data and it is dumping differences. This allows to use Tarmac format as a glue between heterogeneous simuators speaking the same Tarmac language. Kudos to Giacomo Gabrielli for writing the original tracer. [1]: https://developer.arm.com/docs/dui0845/f/tarmac-trace-file-format Change-Id: I9b92204a149813166166adba4a7c61a248bdcac3 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9381 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> SConscript TarmacTrace.py tarmac_base.cc tarmac_base.hh tarmac_parser.cc tarmac_parser.hh