cpu, mem: Changing AtomicOpFunctor* for unique_ptr<AtomicOpFunctor>

This change is based on modify the way we move the AtomicOpFunctor*
through gem5 in order to mantain proper ownership of the object and
ensuring its destruction when it is no longer used.

Doing that we fix at the same time a memory leak in Request.hh
where we were assigning a new AtomicOpFunctor* without destroying the
previous one.

This change creates a new type AtomicOpFunctor_ptr as a
std::unique_ptr<AtomicOpFunctor> and move its ownership as needed. Except
for its only usage when AtomicOpFunc() is called.

Change-Id: Ic516f9d8217cb1ae1f0a19500e5da0336da9fd4f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20919
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

x86: Templatize the IntMasterPort.

This makes the IntMasterPort usable with any class, making it possible
to avoid inheriting from IntDevice.

It also makes IntMasterPort inherit directly from QueuedMasterPort,
skipping over MessageMasterPort.

Change-Id: I9d218556c838ea567ced5f6fa4d57a3ec9d28d31
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20821
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

x86: Templatize IntSlavePort.

This makes the device IntSlavePort calls back into based on a template
parameter so that IntDevice doesn't have to be in the inheritance
hierarchy to use it.

It also makes IntSlavePort inherit from SimpleTimingPort directly,
skipping over MessageSlavePort.

Change-Id: Ic3213edc9c3ed5e506ee1e9f5e082cd47d7c7998
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20820
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

x86: Turn the local APIC into a PioDevice instead of a BasicPioDevice.

This will let us accept several address ranges through our pio port
instead of just one, and that will in turn let us accept interrupt
requests and pio requests through the same port.

Change-Id: I70b78c8cd0edca7fe58b3d4cd241e41d9e0f2c20
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20819
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-x86: ignore non-temporal hint for movntps/movntpd SSE insts

Making the implementation of movntps/movntpd consistent with other
non-temporal instructions. We are ignoring the hint here, and
implementing those instructions as cacheable instructions.

This change adds a warning to let user know about this workaround.
Also, this change add the address check for second part of move.

Change-Id: I811652b24cf39ca2f5c5d4c9e9e417f69190b55c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20408
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-x86: Change warn to warn_once for NT instructions

Change-Id: I50353716f2a913b9b106b140644d95991879f662
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21039
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: PSTATE.PAN changes should inval cached regs in TLB

Change-Id: Id94e355fec345d2e952539a7dce7fbd21ed220c6
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20983
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Fix Data Abort ISS when caused by Atomic operation

Data Aborts caused by an atomic instruction have a special rule for
their syndrome:
From a ISS point of view they count as read if a read to that address
would generate a fault; they count as writes otherwise (ISS.WnR bit)
This patch is implementing this in the TLB. For permission faults we
need to explicitly check if a read would trigger a fault
(e.g. checking for the AP bits) since permissions can allow read-only
accesses.
For other MMU exceptions (like translation faults) we are confident the
nature of the access doesn't affect the genration of a fault.
This means that if the access is atomic, we treat it as a read from an
ISS.WnR point of view.

Change-Id: Ia524aa6ae07f81513cdc26c516b5fd9b01a931c3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20981
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: ISV bit in DataAbort should check for translation stage

According to the ESR spec, the ISV bit is set to 1 only for stage 2
aborts.

Change-Id: Id524ef36e82184f741e968ddba04ca8ccdd4ad58
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20980
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: PSTATE.PAN affecting EL2 only when HCR_EL2.E2H=1

Change-Id: I6df0cdcbadca17f30d3de3bed887f75c739b00f0
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20979
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch, x86: Rework the debug faults and microops.

This makes the non-fatal microops advance the PC, and adds missing
functions. The *_once Faults now also can be run once per *something*.
They would previously be run once per Fault invoke function which is
common to all M5WarnOnceFaults. The warn_once microop will now warn
once per message.

Change-Id: I05974b93f3b2700077a411b243679c2ff0e8c2cb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20739
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sparc: Fix a warning/error in tlb.cc.

gcc has started to not like memseting an ojbect to zero in some cases.
Cast the TlbEntry pointer to a void * before memsetting it to placate
gcc.

Change-Id: Iccb3c326fdb82f1f111329ff1a80bb6719cace47
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20830
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

arch-arm, dev-arm: MISCREG_ICC_IGRPEN1_EL1 using AA64 banking

Change-Id: Ic08ac1e7f3ebef408a83aa068ce15e9dfe2aa3cd
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20628
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm, dev-arm: MISCREG_ICC_AP1R0_EL1 using AA64 banking

Change-Id: Ide93464f62288fbe8f409f718487a15512c01295
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20627
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm, dev-arm: MISCREG_ICC_CTLR_EL1 using AA64 banking

Change-Id: Ib1691f1cba08251a36ceb959849b61c33cc3e93b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20626
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: MISCREG_ICC_BPR1_EL1 using AA64 banking

Change-Id: Ib30c7a49490f05f88ddfd7572dd360cb92647f81
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20625
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Add explicit AArch64 MiscReg banking

Change-Id: I89836d14491a51b1573f45c8012e3ad12b107d24
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20623
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Use same template across all MSR inst

Change-Id: Ifb9f1db288e401761b71ccf426e370c475e5663f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20622
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: SySDC64 Instructions (CMO) using MiscRegIndex

Change-Id: Ia66d6abf965b1d33579e8fa048608d99c93ff2ce
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20621
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: fix GDB stub after SVE

The SVE patches made registers longer by increasing NumVecElemPerVecReg,
but the GDB XML was not updated to account for that, and as a result GDB
connections were failing with:

Remote 'g' packet reply is too long

This commit introduces NumVecElemPerSimdVecReg which counts only the SIMD
register sizes to get it back working. SVE GDB support is not added here.

Change-Id: I4191b9f1999ae02b0308863db4cc9b5b16a27d6d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20468
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: SGI registers undecoded in AArch32

Change-Id: I64d3e639e1beaa507263637d59499aafeb5a19f8
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20612
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Fix read/setMiscReg for AArch32 GICv3 ICC regs

The readMiscReg/setMiscReg methods were not forwarding register
reads/writes to the cpu interface when in AArch32.

Change-Id: Ide983e793b8033a88d31fe6ea87eaeffe9b093f5
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20611
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-x86: Adding warning for movnti

We are ignoring the non-temporal hint here, and implementing this
instruction as a cacheable instruction.

This change adds a warning to let user know about this workaround.

Change-Id: I2e40437a44282fe9cf7772a25a8870bd8729a6ed
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20428
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

arch-x86: implement movntq/movntdq instructions

Non-temporal quadword/double-quadword move instructions.
This change ignores the non-temporal hint and instructions are
implemented to send cacheable request to memory.
This would have some "performance" impact (i.e. having some cache
pollution) to get better "correctness" in behavior.

Change-Id: I2052ac0970f61a54bafb7332762debcb7103202d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20288
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

arm,kvm: Fix python imports from global namespace

Change-Id: I31bd3563c2427efd7e520f714b1ca6f480fa4e85
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20491
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem: Eliminate the Base(Slave|Master)Port classes.

The Port class has assumed all the duties of the less generic
Base*Port classes, making them unnecessary. Since they don't add
anything but make the code more complex, this change eliminates them.

Change-Id: Ibb9c56def04465f353362595c1f1c5ac5083e5e9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20236
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

arch-riscv: fix GDB register cache

Fixes the definition of the RISC-V GDB register cache. The latest
version, of RISC-V gdb, commit c3eb4078520dad8234ffd7fbf893ac0da23ad3c8,
appears to only accept the 32 integer registers + the PC in the 'g'
packet.

This functions with the Linux toolchain (riscv64-unknown-linux-gnu-*),
but works best with the Newlib toolchain (riscv64-unknown-elf-*).

Change-Id: Ie35ea89a45870fb634e6c68236261bde27c86e41
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20028
Reviewed-by: Alec Roelke <alec.roelke@gmail.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Alec Roelke <alec.roelke@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-riscv: Update register file

This patch adds mcounteren, scounteren according to Risc-V
Privileged Architectures V1.10.

Change-Id: I6e138a50710bc0a1e9d9c38a11fc7fcc09ed500e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20128
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Alec Roelke <alec.roelke@gmail.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Alec Roelke <alec.roelke@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm, cpu: fix ARM ubsan build on GCC 7.4.0

In src/cpu/reg_class.hh, numPinnedWrites was unset because the
constructors were not well factored out.

Change-Id: Ib2fc8d34a1adf5c48826d257a31dd24dfa64a08a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20048
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Fix implicit fallthrough build errors

1942b21713 introduced implicit-fallthrough errors when compiled with
GCC 8. This change adds M5_UNREACHABLE in the default case.

Change-Id: I220f2b3fe39b5c3a65c0dd390915bffeafb28962
Signed-off-by: Chun-Chen TK Hsu <chunchenhsu@google.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20268
Reviewed-by: Jordi Vaquero <jordi.vaquero@metempsy.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Replace occ of opModeToEL(currOpMode/cpsr) with currEL

Change-Id: I739a9be03ea5caa63540c62fd110eee86a058c4c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20252
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Replace direct use cpsr.el with currEL helper

The patch is replacing it in places where the current EL could be using
AArch32, hence leading to an incorrect ExceptionLevel.

Change-Id: I99b75af2668f2c38fd88bec62e985ab7dbea80dc
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20251
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Overload currEL helper with CPSR argument

Change-Id: I1edabc61637ecb9d30bca34b5dbcf1de12b35fe0
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20250
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Rewrite the currEL helper method to use opModeToEL

Direct use of cpsr.el should be discouraged: it should be used when
in AArch64 only; when in AArch32 it won't return the matching EL.

Eg: when in Supervisor Mode (EL1), CPSR.M<3,0> (mode) is 0b0011,
and cpsr.el will return 0 (EL0)

Change-Id: I5504bd1f59980f79b2607cce435ea09245de12e5
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20249
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

x86: Stop CPUID from claiming we support xsave.

xsave is a fairly complex feature which we don't support in gem5, but
we do report that we support it through CPUID. It looks like I confused
it with FXSAVE which is an instruction related to SSE. This change
turns that bit back off again.

Change-Id: I00fc79168c5f7095b5241e870a4c8782e4385425
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20169
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

x86: Make unsuccessful CPUID instructions zero the result.

The previous implementation left the registers unmodified which is
technically correct since there is no defined behavior in that case or
a fault to raise. That would make what happened when the following code
consumed the result unpredictable because it would depend on what junk
values were left in the registers. This was originally not a problem
since the space of supported functions were tightly packed, but someone
added a new function with a gap without adjusting this behavior.

This change makes CPUID zero out RAX, RBX, RCX, and RDX when it fails.
That should be more predictable and cause less flakey failures.

Change-Id: If6ffb17c2969d34aff1600c0ffc32333d0b9be44
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20168
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Added LD/ST<op> atomic instruction family and SWP instrs

Adding LD/ST/SWP family of instructions, LD/ST include a set of
operations like ADD/CLR/EOR/SET/UMAX/UMIN/SMAX/SMIN
This commit includes:
+ Instruction decode
+ Instruction functional code
+ New set of skeletons for Ex/Com/Ini/Constructor and declaration.

Change-Id: Ieea8d4256807e004d2f8aca8f421b3df8d76b116
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19812
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

arch-arm: Adding CAS/CASP AMO instr including new TypedAtomic func

CAS/CASP atomic instruction implementation
This change includes:
+ Instructions decode
+ new amo64.isa file where CAS/CASP main functional code is implemented
+ mem64.isa include Execute/complete/initiatie skeletons,
contructor and declarator
+ Added TypedAtomic function for pair register CASP instruction

Change-Id: I4a4acdec4ab1c8b888f10ef5dc1e896be8c432bf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19811
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

x86: Move some fixed or dummy config information into X86LocalApic.py.

The X86 local APIC doesn't actually use the pio_addr set in the config
and instead computes what address it will respond to based on the
initial ID of the CPU it's attached to. gem5's BasicPioDevice, which
the X86LocalApic class inherits from, does not provide a default value
for that parameter and will complain if *something* isn't set. The
value used, 0x2000000000000000, is a dummy value which is the base of
the region of the physical address space set aside for messages to
local APICs from the CPU and from other local APICs.

Also, the clock for the local APIC's timer is defined to be the bus
clock. The assumption seems to be that this has a 16:1 ratio with the
CPU clock, and I vaguely remember finding that that was more or less
unofficially true, even if it isn't necessary stringently defined to
be that.

Since we were already just assuming that that ratio was correct and
always setting up the local APICs clock that way, we can do that in
the X86LocalApic class definition and remove some special x86 specific
setup that we'd otherwise need for the x86 version of the Interrupt
class. If that's not correct, it can still be overridden somewhere else
in the config.

Change-Id: I50e84f899f44b1191c2ad79d05803b44f07001f9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19968
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch: Bump MaxVecRegLenInBytes to 4096

The GPU model uses the generic vector register
containers, however the maximum vector register
length is fixed at 256, which is an invalid assumption
for the GPU model as it can operate on vectors up
to 4096B.

Change-Id: Id85e0ed45c9a9c1a4bb6e712c44eaeec2d628fce
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17908
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Add TypeAtomicOp class to be used by new atomic instructions

Creating a new object TypeAtomicOp that will be used by the atomic
instructions following gem5 AMO feature.

Change-Id: If082b596fb37d7a1cb569a4320c23505591df6a5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19810
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: adding register control flags enabling LSE implementation

Added changes on arch-arm architecture to accept Atomic instructions
following ARM v8.1 documentation. That includes enabling atomic bit
in ID registers and add have_lse variable into arm system.

Change-Id: Ic28d3215d74ff129142fb51cb2fa217d3b1482de
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19809
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim-se: add new getpgrp system call

This changeset adds new (relatively simple) system call
support. The getpgrp call returns a thread context's
pgid.

Change-Id: I361bdbfb9c01b761ddd5a4923d23f86971f8d614
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17111
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>

sim-se: adding pipe2 syscall

pipe2 builds on top of the pipe syscall implementation by
adding some extra flags for the files (to avoid have to
make separate calls to fcntl).

Change-Id: I88cf6f1387b9d14e60b33a32db412da9ed93a3e6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12310
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Implement ARMv8.1-PAN, Privileged access never

ARMv8.1-PAN adds a new bit to PSTATE. When the value of this PAN state
bit is 1, any privileged data access from EL1 or EL2 to a virtual memory
address that is accessible at EL0 generates a Permission fault.
This feature is mandatory in ARMv8.1 implementations.
This feature is supported in AArch64 and AArch32 states.
The ID_AA64MMFR1_EL1.PAN, ID_MMFR3_EL1.PAN, and ID_MMFR3.PAN fields
identify the support for ARMv8.1-PAN.

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I94a76311711739dd2394c72944d88ba9321fd159
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19729
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Rewrite MSR immediate instruction class

MSR <pstatefield>, #imm is used for setting a PSTATE field using an
immediate. Current implementation has the following flaws:

* There is no base MSR immediate definition: all the existing
PSTATE fields have a different class definition
* Those implementation make use of a generic data64 base class
which results in a wrong disassembly (pstate register is printed as an
integer register).

This patch is fixing this by defining a new base class (MiscRegImmOp64)
and new related templates. In this way, we aim to ease addition of new
PSTATE fields (in ARMv8.x)

Change-Id: I71b630ff32abe1b105bbb3ab5781c6589b67d419
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19728
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Fix reg dependency for SVE gather microops

The first microop of an SVE gather creates a copy of the
source vecreg into AA64FpUreg0. The subsequent microops
must refer to this copy as a source in order to establish
the correct register dependencies.

Change-Id: I84d8c331f9f9ebca609948a15f686a7cde67dc31
Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com>
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19172
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Fix tracing code for SVE gather

Printing the entire contents of the dest vecreg for each gather
microop is suboptimal as it creates false positive differences
between Atomic and O3 traces. This fix prints only the memory
data which a microop loads from memory.

Change-Id: Idd8e0b26a96f9c9cc0b69360174bedf6a9f6dcb5
Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com>
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19171
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Add SVE LD1RQ[BHWD]

Add both scalar+scalar and scalar+immediate versions.

Change-Id: If5fa1a71ab0dab93f9d35b544ea0899ece858bea
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19170
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Fix decoding for SVE memory instructions

Some SVE memory instructions are missing the makeSP function for
register operands that can be the SP register. This leads to
segmentation faults on the application side as the wrong register is
decoded.

Change-Id: Ic71abc845e0786a60d665231b5f7b024d2955f4b
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19169
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

arch-arm: Add support for SVE load/store structures

Change-Id: I4d9cde18dfc3d478eacc156de6a4a9721eb9e2ff
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13524
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-x86: Don't free PTW state with inflight requests

If a page table walk is squashed, the walker state is being deleted
in the squash code. If there are in flight requests, the deleted
walker state values may be clobbered, leading to undefined behavior.
This adds a squashed boolean to the walker state which is set if a
walk is squashed while requests are still in flight. When packets
for the in flight request return, we check if the walk was squashed
and return that the walk is complete once the number of in flight
requests reaches zero. The walker state is then freed by the PTW.

Change-Id: I57a64b1548b83a8a9e8441fc9d6f33e9842df2b3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19568
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Implement ARMv8.1-HPD, Hierarchical permission disable

According to the armarm:
ARMv8.1-HPD introduces the facility to disable the hierarchical
attributes, APTable, PXNTable, and UXNTable, in the translation tables.
This disable has no effect on the NSTable bit. This feature is
mandatory in ARMv8.1 implementations.

This feature is added only to the VMSAv8-64 translation regimes. ARMv8.2
extends this to the AArch32 translation regimes, see ARMv8.2-AA32HPD.

The ID_AA64MMFR1_EL1.HPDS field identifies the support for ARMv8.1-HPD.

Change-Id: Ibbf589b82f2c1e4437b43252f8f633e8f6fb0b80
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19610
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Add HPD bit for TCR_EL2/EL3

This is controlling Hierarchical Permissions for EL3 and for EL2 when
HCR_EL2.E2H = 0.

Change-Id: I9d6615ff4980cc56a28dc32088cf1524155f0fa4
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19609
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Clean Fault generation when processing Long Descriptor

A new shared method has been introduced: generateLongDescFault

Change-Id: I7eb6fa1347a6c2cf9cb11fd9f2137d983c4f7a40
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19608
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Add first-/non-faulting load instructions

First-/non-faulting loads are part of Arm SVE.

Change-Id: I93dfd6d1d74791653927e99098ddb651150a8ef7
Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19177
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Use ExceptionLevel type in TlbEntry

Replacing uint8_t with ExceptionLevel type in the arm TlbEntry. The
variable is representing the translation regime it is targeting.

Change-Id: Ifcd6e86c5d73f752e8476a2b7fda9ea74a0c7a3b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19488
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-x86: add unconditional tag to calls/returns

The branch predictor checks whether an instruction is unconditional
branch before adding it or checking the RAS. With this change, the
RAS is significantly more effective for short running x86 workloads.

Change-Id: I60af5f2f583b898ad77f79f4b0478d6cda88fc21
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19448
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>

arch, arm: Update miscRegs in getTE

Normally, a translation will start via translateTiming/functional
which will check if the miscRegs have been updated and if so,
will update the TLB state accordingly. However, in a 2 stage
system, if there is a hit in stage 1, the resulting IPA will be
sent to the S2-TLB for translation via a getTE() function call
(via the stage2_lookup object). This will cause the state of the
S2-TLB to be out of sync.

Change-Id: I117e4032fc76d7d31f4f999887b5573a7e5811e6
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/14995
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

arch-arm: Move the memacc_code before op_wb in fp loads

This is trying to fix the bug that arises when a memory exception
is generated during a fp flavoured load (A memory load targeting
a SIMD & FP register).
With the previous template a fault was not stopping the register
value to be modified (wrong)

if (fault == NoFault) {
fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags);
%(memacc_code)s;
}

if (fault == NoFault) {
%(op_wb)s;
}

The patch introduces a Load64FpExecute template which is moving the
register write (memacc_code) just before the op_wb

Change-Id: I1c89c525dfa7a4ef489abe0872cd7baacdd6ce3c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19228
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: implement VMINNM scalar thumb

VMINNM was implemented at Iabbbca2932557cf6c98ce36690c385c3ddf39ed8 but
the thumb scalar encoding was missing. This patch implements it.

Change-Id: Ia29ec77dbd82f6be6b3d040a0e737794f52c33bf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19108
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Fix WalkerState,Descriptors default constructor

Those POD strutures are not initializing all members at construction.
This could lead to undefined behaviour

Change-Id: Iaa8afb126382b6bfbef686883a026262f24d5ca1
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Javier Setoain <javier.setoain@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19149
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

x86: fix movsd bug on %xmm register

The movsd instruction should zero out half the register, but
does not do it. This changeset adds the necessary microop to
the instruction to cause correct behavior.

Change-Id: I5278da3634c78a97ed0586f687a36c6dc5a34c60
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19068
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Michael LeBeane <Michael.Lebeane@amd.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arm: Fix decoding of CRC32 instructions in thumb32

The CRC32 and CRC32C instructions are incorrectly decoded in thumb32
mode according to the latest manual:
https://developer.arm.com/docs/ddi0597/latest/top-level-encodings-for-t32/16-bit#dpint_2r

Change-Id: I9c6684f1ec7fe14d3b4cdf13f117a9819e046578
Signed-off-by: Chun-Chen TK Hsu
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19028
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Treat SVE prefetch instructions as no-ops

Change-Id: Ife0424e274dd65d6dc4f6e5cc5e37d17b03be0d8
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13522
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Add initial support for SVE gather/scatter loads/stores

Change-Id: I891623015b47a39f61ed616f8896f32a7134c8e2
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13521
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch: Add include guards to auto-gen. decode header

Change-Id: I03bfc9035b82bc1a42e799cf645d43cb5dafb4cb
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18911
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch, base, cpu, gpu, sim: Merge getMemProxy and getVirtProxy.

These two functions were performing the same function but had two
different names for historical reasons. This change merges them
together, keeping the getVirtProxy name to be consistent with the
getPhysProxy method used to get a non-translating proxy port.

Change-Id: Idd83c6b899f9343795075b030ccbc723a79e52a4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18581
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch, base, sim: Demote (SE|FS)TranslatingPortProxy &s to PortProxy &s.

Al(most) all of the interesting differences between the two classes
have been removed. There are some control methods which are still
specific to each type which may require treating them as their true
type, but most code that consumes them doesn't need to worry about
which is which.

Change-Id: Ie592676f1e496c7940605b66e55cd7fae18e59d6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18577
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch, base, sim: Replace Copy(String)?(In|Out) with equivalent code.

This expands those functions into code which extracts the virt proxy
and then uses the appropriate method on it. This has two benefits.
First, the Copy* functions where mostly redundant wrappers around the
methods the proxy port already had. Second, using them forced a
particular port which might not actually be what the user wanted.

Change-Id: I62084631dd080061e3c74997125164f40da2d77c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18575
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim-se: add a release parameter to Process.py

Set the default release to that single value for all ISAs.

glibc has checks for the kernel version based on uname, and refuses
to start any syscall emulation programs if those checks don't pass with
error:

FATAL: kernel too old

The ideal solution to this problem is to actually implement all missing
system calls for the required kernel version and bumping the release
accordingly.

However, it is very hard to implement all missing syscalls and verify
compliance.

Previously, we have simply bumped the version manually from time to
time when major glibc versions started breaking.

This commit alleviates the problem in two ways.

Firstly, having a single kernel version for all versions means that it is
easier to bump all versions at once.

Secondly, it makes it is possible to set the release with a parameter,
which in turn can be set from the command line with:

se.py --param 'system.cpu[:].workload[:].release = "4.18.0"'

Change-Id: I9e3c31073bfe68735f7b0775c8e299aa62b98222
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17849
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch, base, dev, sim: Remove now unnecessary casts from PortProxy methods.

Change-Id: Ia73b2d86a10d02fa09c924a4571477bb5f200eb7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18572
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

arm, mem: Move the SecurePortProxy subclass into it's own file.

The idea of a "secure" memory area/access is specific to ARM and
shouldn't be in the common mem directory, although it's built in to the
generic memory protocol at this point.

Regardless, it should minimially be in its own file like the virtual
and physical port proxy classes are.

Change-Id: I140d4566ee2deded784adb04bcf6f11755a85c0c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18569
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Fix fallthrough when trapping at EL2

This had been caused by the introduction of GICv3 registers trapping in
commit 32a23114c14cebc5ec0067ac739144b50e412219

Change-Id: I5073e2891f3ff5c5a9e05d3456dad6f4f8ffba0d
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18909
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Trap virtual accesses to GICv3 SGI registers

According to GICv3 documentation, a virtual write (which means
HCR.IMO/FMO = 1) to ICC_SGI0R_EL1, ICC_SGI1R_EL1, ICC_ASGI1R_EL1 should
trap to EL2.

Change-Id: Ie7a952c2ff08590bb0c6e3854df567d714c2dc94
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17990
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Expose haveGicv3CPUInterface to the ISA interface

Change-Id: I36232b7618ad875983f34b741c51f12ddb9ae166
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17989
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Change mcrMrc15TrapToHyp signature

This patch is moving MiscRegs reading inside the mcrMrc15TrapToHyp
helper function. Rather than passing registers as arguments,
we are just passing a ThreadContext pointer

Change-Id: I6636dd3a4f92f757479d8a8d2c47de050a0b9eae
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17988
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim-se: remove comment for code that moved

The page table code must have moved from this class, because
the comment no longer accurately reflects upon any of the
surrounding code.

Change-Id: If08a4298c1237a541d9875ddeaf3d3ecfd98e9db
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12300
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

sim-se: change syscall function signature

The system calls had four parameters. One of the parameters
is ThreadContext and another is Process. The ThreadContext
holds the value of the current process so the Process parameter
is redundant since the system call functions already have
indirect access.

With the old API, it is possible to call into the functions with
the wrong supplied Process which could end up being a confusing
error.

This patch removes the redundancy by forcing access through the
ThreadContext field within each system call.

Change-Id: Ib43d3f65824f6d425260dfd9f67de1892b6e8b7c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12299
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

x86: Add an object file loader for linux.

Change-Id: I283dd1f52fd020ad3c226eb00fc9216ee034c67f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18630
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sparc: Add an object file loader for linux and solaris.

Change-Id: I76bcbc06714f7d538f03a8311994a868de3640f1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18629
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

riscv: Add an object file loader for linux.

Change-Id: I3accca91cc4e02fa8e3a1169590cbe6696cf05e2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18628
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Alec Roelke <alec.roelke@gmail.com>
Maintainer: Alec Roelke <alec.roelke@gmail.com>

power: Add an object file loader for linux.

Change-Id: I64ce81e98a6dc96754554d0fdcd7d16b8a2752d4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18587
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Sandipan Das <sandipan@linux.ibm.com>

mips: Add an object file loader for linux.

Change-Id: Icae6430a210076117cf2ceadce52d6efbe58a5f3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18586
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arm: Add an object file loader for linux and freebsd.

Change-Id: Ie5fd187a4897aa608ffc12278b23d3ee8c0f323c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18585
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

alpha: Add an object file loader for linux.

Change-Id: I91c4019567bdf74b2517fda597121a6ad107cb86
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18584
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch, base, cpu, dev, mem, sim: Remove #if 0-ed out code.

This code will be preserved through version control, but otherwise
creates clutter and will rot in place since it's never compiled.

Change-Id: Id265f6deac445116843956ea5cf1210d8127274e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18608
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: implement VMINNM and VMAXNM scalar version

ARMv8.2 16-bit versions have not yet been implemented, but a placeholders
were created for them.

Refactor the nearby decoding tree to closely match the ARM spec A32 decode
table.

That piece of the tree can also be called from thumb which decodes it in
the same way, although the thumb decode table has a different terminology

The old code didn't match neither A32 or T32 terminologies, so it is
better to at least match one of them to help verify correctness.

Change-Id: Iabbbca2932557cf6c98ce36690c385c3ddf39ed8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18690
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: implement VMINNM and VMAXNM SIMD version

This instruction is backported from aarch64.

In order to use the existing fplibMinNum backend, we first move
VMIN and VPMIN to use fplib. Adding VMINNM is then trivial.

Change-Id: I404daabeb6079f60e51a648a06d5b3e54f1c24a9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18689
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: rename operands to match spec in isa/formats/fp.isa

Matches ARM DDI 0487D.a decoding tables.

Change-Id: I48338ef956a04308d55d1022229ebe0962a8fe5d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18688
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Do not check MustBeOne flag for TLB requests from the prefetcher

Allow TLB requests generated from prefetchers to override the
MustBeOne arch flag. This allows the prefetchers to issue requests
without having to know architecutre-specific flags.

Change-Id: Id83e0c93f3d1a614da11c4f344ab4dc594423672
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18768
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Add initial support for SVE contiguous loads/stores

Thanks to Pau Cabre and Adria Armejach Sanosa for their contribution
of bugfixes.

Change-Id: If8983cf85d95cddb187c90967a94ddfe2414bc46
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13519
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

x86: Mark translation as delayed in case of a hw page table walk

This information is used by the LSQ in the O3 cpu (since commit
"51becd2... cpu-o3: O3 LSQ Generalisation")

Change-Id: I35fe7e2f8428641d863af0e79e28b0b259fb0b00
Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18508
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-riscv: Implement MHARTID CSR

This patch implements the MHARTID CSR by intercepting attempts to access
it, similar to the way accesses to the performance counters are
intercepted, to return the thread's context ID.

Change-Id: Ie14a31036fbe0e49fb3347ac0c3c508d9427a10d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16988
Reviewed-by: Alec Roelke <alec.roelke@gmail.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Alec Roelke <alec.roelke@gmail.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim-se: add eventfd system call

Change-Id: I7aeb4fe808d0c8f2fb8041e3662d330d8458f09c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12125
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>

arch-riscv,isa: Fix for compressed jump (c_j) imm

c_j(al) has a special format, called CJ.
The jump offset format is instbits[12:2] --> offset[11|4|9:8|10|6|7|3:1|5]
Currently in decoder.isa, c_j format is JOp, the imm and branchTarget are incorrect
In the execute section (decoder.isa:228), the imm fields is ignored and the offset is calculated correctlly.
As a result, we get decoder flush for each c_j instance
I've added CJOp format in compressed.isa, and use it in execute section.
In addition, c_j is mappped to jal zero, cj_imm, and actually is neither indirect control nor a function call
I fixed the flags accordently.
I'll fix all IsRet, IsCall and IsIndirectControl flags for rest of (c_)jal(r) in my next commit.
I ran coremark -O0 before my fix and I got 37.7% branch miss-rate, after the fix the branch miss-rate is <13%

Change-Id: I608d5894a78a1ebefe36f21e21aaea68b42bccfc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17808
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Alec Roelke <alec.roelke@gmail.com>

arch: Stop using TheISA within the ISAs.

We know for sure what the ISA is, so there's no need for the
indirection.

Change-Id: I73ff04c50890d40a4c7f40caeee746b68b846cb3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18488
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

x86: Get rid of some unnecessary TheISA-es in x86.

The X86ISA namespace is already available.

Change-Id: I5774968fdfb30b01eba52cdec5e6ef2c75cb66e4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18471
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sparc: Move translation constants from isa_traits.hh into tlb.hh.

These aren't used outside of SPARC. Also get rid of some unused
constants.

Change-Id: Icfe119f88189348245a6f225a61e62dfa93ea951
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18470
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sparc: Move the interrupt types out of isa_traits.hh into interrupts.hh.

Those types aren't generic or used outside of SPARC.

Change-Id: I9bb154920a9625f12388c3d295dc933ab51fadde
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18469
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch: Remove the mt.hh switching header.

This header was only useful in MIPS and is only used internally within
MIPS. It doesn't need to be a switching header file.

Change-Id: Id7005f73b95e122f9ab83b3b657cae3391682f26
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18468
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: alpha: Delete all occurrances of the simPalCheck function.

This is now handled within the ISA description.

Change-Id: Ie409bb46d102e59d4eb41408d9196fe235626d32
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18434
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

alpha: Implement simPalCheck within the ISA description.

This doesn't need to be plumbed through generic interfaces. If the
function/instruction got more complex in the future (unlikely since
Alpha doesn't really see development these days), it could be moved to
a helper function defined within Alpha files.

Change-Id: Ib746fad7bb13c5cc9c6ee555c3a46ce686771c12
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18433
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

cpu: Remove hwrei from the generic interfaces.

This mechanism is specific to Alpha and doesn't belong sprinkled around
the CPU's generic mechanisms.

Change-Id: I87904d1a08df2b03eb770205e2c4b94db25201a1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18432
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch: cpu: Track kernel stats using the base ISA agnostic type.

Then cast to the ISA specific type when necessary. This removes
(mostly) an ISA specific aspect to some of the interfaces. The ISA
specific version of the kernel stats still needs to be constructed and
stored in a few places which means that kernel_stats.hh still needs to
be a switching arch header, for instance.

In the future, I'd like to make the kernel its own object like the
Process objects in SE mode, and then it would be able to instantiate
and maintain its own stats.

Change-Id: I8309d49019124f6bea1482aaea5b5b34e8c97433
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18429
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

alpha: Implement HWREI in the ISA.

This moves it out of generic interfaces and the CPU implementations.

Change-Id: I6767d6b26d0ae128b5bdad5830dce838be74e256
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18431
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

alpha: Add some control registers to the ISA operands list.

These will be used in the in-ISA HWREI implementation.

Change-Id: Ia9f7bf1aa2dbd764c878911c2cba680840397c62
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18430
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mips: Implement readRegOtherThread and setRegOtherThread directly.

These accessors can be implemented as helper functions within MIPS
without having to plumb them through a bunch of common interfaces.
There are a few problems with the way they were implemented which are
carried forward to this new implementation as well. That includes
hiding the register accesses from the ISA parser and therefore the
CPU's dependency tracking, potentially panicing or accessing a non
existent thread based on a possible set of input values, and modifying
register values even if an instruction is being executed speculatively.

Fixing these problems would be fairly involved and require changing how
dependencies are tracked in all the CPUs so that they can act across
threads, and also how registers are handled in the ISA description
itself.

The original implementation just punted on making this work in CPUs
other than the minor CPU (and potentially one or more CPU models that
were not and/or are not in the code base). Where as that implementation
might have paniced if these methods were called, this will attempt to
work, but may have incorrect behavior based on the limitations
described above. I'd consider this an acceptable tradeoff, at least for
the time being.

Change-Id: I94adceafb9812a8641c76ea3518c3285c31baf51
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18435
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Faults DebugFlag now printing inst opcode if available

This makes it easier to debug unimplemented instructions.

Change-Id: Iaaa288037326722f07251299fd68eacb2e295376
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18396
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Report real instruction encoding when Undefined

When dumping the opcode that caused an Undefined Instruction, we just
want to dump the real instruction encoding, and not the extended version
with metabits (like thumb, bigThumb etc). This was not appening when
panicking in SE mode.

The patch is also replacing custom masking in the Unknown(64) disassembler
in favour of ArmStaticInstruction::encoding() helper.

Change-Id: I9eb6fd145d02b4b07bb51f0bd89ca014d6d5a6de
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18395
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch, sim: Simplify the AuxVector type.

The AuxVector type has a bunch of accessors which just give access to
the underlying variables through references. We might as well just make
those members accessible directly.

Also, the AuxVector doesn't need to handle endianness flips itself. We
can tell the byteswap mechanism how to flip an AuxVector, and let it
handle that for us.

This gets rid of the entire .cc file which was complicated by trying
to both hide the ISA specific endianness translations, and instantiate
templated functions in a .cc.

Change-Id: I433cd61e73e0b067b6d628fba31be4a4ec1c4cf0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18373
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

mem: Remove the ISA specialized versions of port proxy's read/write.

These selected their behavior based on ifdefs and had to be disabled
when on the NULL ISA. The versions which take an explicit endianness
have been renamed to just read/write instead of readGtoH and writeHtoG
since the direction of the translation is obvious from context.

Change-Id: I6cfbfda6c4481962d442d3370534e50532d41814
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18372
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem: Minimize the use of MemObject.

MemObject doesn't provide anything beyond its base ClockedObject any
more, so this change removes it from most inheritance hierarchies.
Occasionally MemObject is replaced with SimObject when I was fairly
confident that the extra functionality of ClockedObject wasn't needed.

Change-Id: Ic014ab61e56402e62548e8c831eb16e26523fdce
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18289
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>

arch-arm: updateMiscReg not setting isHyp in aarch64

The isHyp flag should be set for a TLB::NormalTran when in EL2. This
was happening in aarch32 only, where the CPSR mode is checked, while
aarch64 was only using it for explicit EL2 translations, like for AT
instructions.

Change-Id: I54605811e9dde75b5cf8868190b0f4c2a8d46570
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18394
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arm: Factor some repetition out of the ProcessInfo constructor.

Change-Id: I34f952d1097886704d37304478de125a915b2615
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18371
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

arm: Fix some style issues in stacktrace.cc.

De-indent the ArmISA namespace, and wrap some overly long lines.

Change-Id: Idc02b025bdfda483ddbd27d662e2314a5cbcb23c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18370
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

x86: Refactor the ProcessInfo constructor.

That function had a lot of repetition which is easily factored out
into its own function.

Change-Id: I3b7a522de2ba808856bb59df75b80efde6780e3f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18369
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

x86: Fix some style issues in stacktrace.cc.

De-indent the X86ISA namespace, and wrap some overly long lines.

Change-Id: I01a6b66a1cf721e16e4ed4dd1c3469ee112e9177
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18368
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Remove un-needed hyp flag in TLBI operations

The hyp flag was probably a legacy pre-v8 flag distinguishing
invalidation targeting PL2 translation regime (hyp mode).
Since the introduction of target_el parameter, hyp boolean is not needed
anymore. The patch works by setting the hyp flag in the flush* methods
in the TLB automatically by checking if target_el == EL2.

Change-Id: I798009e09ff24a383dea871e348188bae2685e8e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jan-Peter Larsson <jan-peter.larsson@arm.com>
Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18389
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Correct target EL field in TLBI operations

Some TLB Invalidation operations affecting the EL2 translation regime
were marked as targeting EL1 instead of EL2

Change-Id: I77821eec7a409e9df6a6814855f9a375832ffe74
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jan-Peter Larsson <jan-peter.larsson@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18388
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim-se: Enhance clone for X86KvmCPU

This changeset enables clone to work with X86KvmCPU model, which
will allow running multi-threaded applications at near hardware
speeds. Even though the application is multi-threaded, the KvmCPU
model uses one event queue, therefore, only one hardware thread
will be used, through KVM, to simulate multiple application threads.

Change-Id: I2b2a7b1edb1c56eeb9c4fa0553cd236029cd53f8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18268
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Eliminate the ProxyThreadContext class.

Replace it with direct inheritance from the ThreadContext class in the
SimpleThread class which was the only place it was used.

Also take the opportunity to use some specialized types instead of
ints, etc., add some consts, and fix some style issues.

Change-Id: I5d2cfa87b20dc43615e33e6755c9d016564e9c0e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18048
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Enable PMSELR_EL0 read in PMU

Change-Id: Ic1ec1d03464a7ce42295cee8a9f4ebcd3e90def1
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17948
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

misc: Removed inconsistency in O3* debug msgs

Added consistency in the DEBUG message form, to allow a better parsing.
Fixed sn/tid type parameter.
Removed some annoying newlines

Change-Id: I4761c49fc12b874a7d8b46779475b606865cad4b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17248
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

dev-arm: Make GICv3 maintenance interrupt an ArmInterrupt

Change-Id: I88e2b72849cdf3f69026c62517303837e7d3d551
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17629
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

dev-arm: Correct cast of template parameter

Clang with -Wconstant-conversion is _very_ restrictive on casting.
The shift operator results in an incorrect promotion.

This patch add a compile-time static cast that remove the error
when clang is used.

Change-Id: I3aa1e77da2565799feadc32317d5faa111b2de86
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17308
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Fix use of bitwise operators on booleans

Change-Id: I3762b2921f1d00a9104d8dc11a19dc0a219581e5
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17288
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Fix index generation for VecElem operands

Current operand generation is not providing VecElems with the right
vector index and element index.
The bug was covered when registers were 128 bit wide, but with SVE we
have augmented the vector register size and the bug has been exposed.

E.g. With dest = 2,

FpDestP2 = (vec_index = 0, elem_index = 4)

whereas it should be

FpDestP2 = (vec_index = 1, elem_index = 0)

Change-Id: Iad02fb477afd0d3dd3d437bf2ca4338fbd142107
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17710

arch-arm: Add missing fall-through defaults

Change-Id: Ie64b83d754c4719a77c7788879be71304a9b786e
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17289
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andrea Mondelli <Andrea.Mondelli@ucf.edu>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

arch-power: Rename program counter registers

The Power ISA specification lists the Program Counter (PC) and
the Next Program Counter (NPC) registers as Current Instruction
Address (CIA) and Next Instruction Address (NIA). This applies
the ISA naming convention for these two registers.

Change-Id: I8b9094ab1c809f4dfdb4d7330c17f360adf063e9
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16603
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

arch-power: Simplify doubleword operand types

Currently, 'sq' and 'uq' are used to represent signed and
unsigned doublewords respectively. Since all recent Power
ISA specifications list 128-bit quadwords as a valid data
type, it may be misleading to use the current terminology
in case support for such operands are added in the future.
So, to simplify this, 'sd' and 'ud' are used to represent
signed and unsigned doublewords respectively.

Change-Id: Ie7831c596fc8f9ddfdf3b652c37cfe26484ebe01
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16602
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

sim-se: Fixed initialization array size

Doubled the size of the zeroed auxiliary vector since 2 * intSize on
aarch64 > sizeof(uint64).

Change-Id: I5196b000a696e9ea3f2b5daa5d5bb071794369aa
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17088
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>

dev-arm: ambiguous use of getPort()

The recent introduction of getPort() creates a conflict with
the existing method used in arm MMU.

This patch rename the old getPort() in getDMAPort() according
to the returned value (DmaPort class type)

Change-Id: Ief3d83650fd6b08490522341631244be06e380ce
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17469
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch, cpu, dev, gpu, mem, sim, python: start using getPort.

Replace the getMasterPort, getSlavePort, and getEthPort functions
with getPort, and remove extraneous mechanisms that are no longer
necessary.

Change-Id: Iab7e3c02d2f3a0cf33e7e824e18c28646b5bc318
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17040
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm,cpu: Add initial support for Arm SVE

This changeset adds initial support for the Arm Scalable Vector Extension
(SVE) by implementing:
- support for most data-processing instructions (no loads/stores yet);
- basic system-level support.

Additional authors:
- Javier Setoain <javier.setoain@arm.com>
- Gabor Dozsa <gabor.dozsa@arm.com>
- Giacomo Travaglini <giacomo.travaglini@arm.com>

Thanks to Pau Cabre for his contribution of bugfixes.

Change-Id: I1808b5ff55b401777eeb9b99c9a1129e0d527709
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13515
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-hsail: changed gen.py shebang from python(3) to python2.7

gen.py includes code_formatter from m5.util. code_formatter uses the
python2 __metaclass__ attribute, which is ignored by python3, causing
the code_formatter.pattern attribute to be unset.

This prevented scons from building against HSAIL_X86

Signed-off-by: Ryan Gambord
<gambordr@oregonstate.edu>

Change-Id: I5a8bf9e730fd629eb7f9a7ac2dce928235a0dae4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17008
Reviewed-by: Andrea Mondelli <Andrea.Mondelli@ucf.edu>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

arch-arm: Fixing implicit fallthrough build errors

2c242d6 introduced implicit-fallthrough errors when building against
ARM.

Added "default: return new Unknown(machInst);" to offending switch
statements; please verify this is the corret behavior

Signed-off-by: Ryan Gambord

Change-Id: I5f5e3661ec562d4a3b2699e07d1195e6877ff959
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17071
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

mem-cache: alias to mem::getMasterPort in TLB class

TLB:getMasterPort is used to obtain the PageWalkMasterPort if present and
hides the BaseTLB::getMasterPort().

The TLB::getMasterPort() is renamed according to the expected behavior.

Change-Id: If4f61189094a706d59805cd10f4f814e5830eda8
Reviewed-on: https://gem5-review.googlesource.com/c/16648
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: implement floating point aarch32 VCVTA family

These instructions round floating point to integer, and were added to
aarch32 as an extension to ARMv7.

Change-Id: I62d1705badc95a4e8954a5ad62b2b6bc9e4ffe00
Reviewed-on: https://gem5-review.googlesource.com/c/16788
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

python: Enforce absolute imports for Python 3 compatibility

Change-Id: Ia88d7fd472f7aed9b97df81468211384981bf6c6
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15983
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

x86: Call the base class's regStats in X86ISA::TLB

When I try to build x86 architecture and run the se.py sample script
with helloworld example, there is a panic warning stated "Not all stats
have been initialized. You may need to add <ParentClass>::regStats() to
a new SimObject's regStats() function."

I see that in x86 tlb.cc, there is no initialization in regStats() function
that causes memory allocation error in some machine which make gem5 exit
abnormally. I add the BaseTLB::regStats(); on TLB::regStats() method and
can solve the problem

Change-Id: I8b62bebc15f896c3136ff4f8253dabbf998f618f
Reviewed-on: https://gem5-review.googlesource.com/c/16522
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

arch-generic: Making base TLB class a MemObject

Allow configuring a TLB hierarchy using ports

Change-Id: I1f791829d4e072a9104e67eacf69a69de9543634
Reviewed-on: https://gem5-review.googlesource.com/c/14117
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Move GICv3 detection at startup time

At the moment the haveGicV3 parameter is used only to signal its
presence when reading the MISCREG_ID_AA64PFR0_EL1 register. It depends
on the system->getGIC pointing to a GICv3 model. However this pointer
is set in the System only at init time (after construction), which means
that the haveGICv3CPUInterface will always be false.
This patch is fixing this by moving the parameter initialization at
startup time, together with the cpu interface registration.

Change-Id: I8da6711ea741ecd0f78ec8ca60a8c3ae3bca2421
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/16483
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

sim-se: update the arm kernel version

This change is needed to run cpu tests with ARM binaries
compiled with newer linux kernel headers

Change-Id: I6cbf132c38d4b18f971ee32272ddb6a5a791a625
Signed-off-by: Ayaz Akram <yazakram@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/15855
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

python: Replace dict.has_key with 'key in dict'

Python 3 has removed dict.has_key in favour of 'key in dict'.

Change-Id: I9852a5f57d672bea815308eb647a0ce45624fad5
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15987
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

python: Don't assume SimObjects live in the global namespace

The importer in Python 3 doesn't like the way we import SimObjects
from the global namespace. Convert the existing SimObject declarations
to import from m5.objects. As a side-effect, this makes these files
consistent with configuration files.

Change-Id: I11153502b430822130722839e1fa767b82a027aa
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15981
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

arch-mips: Remove unused Python file

Change-Id: I7155915fccdec1d9f116f2a8617474188a91165b
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/16302
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

riscv: fix AMO, LR and SC instructions

(1) Atomic Memory Operation (AMO)

This patch changes how RISC-V AMO instructions are implemented. For each
AMO, instead of issuing a locking load and an unlocking store request to
downstream memory system, this patch issues a single memory request that
contains a corresponding AtomicOpFunctor to the memory system. Once the
memory system receives the request, the atomic operation is executed in
one single step.

This patch also changes how AMO instructions handle acquire and release
flags in AMOs (e.g., amoadd.aq and amoadd.rl). If an AMO is associated
with an acquire flag, a memory fence is inserted after the AMO completes
as a micro-op. If an AMO is associated with a release flag, another
memory fence is inserted before the AMO executes. If both flags are
specified, the AMO is broken down into a sequence of 3 micro-ops:
mem fence -> atomic RMW -> mem fence. This change makes this AMO
implementation comply to the release consistency model.

(2) Load-Reserved (LR) and Store-Conditional (SC)

Addresses locked by LR instructions are tracked in a stack data
structure. LR instruction pushes its target address to the stack, and SC
instruction pops the top address from the stack. As specified by RISC-V
ISA, a SC fails if its target address does not match with the most recent
LR.

Previously, there was a single stack for all hardware thread contexts.
A shared stack between thread contexts can lead to a infinite sequence
of failed SCs if LRs from other threads keep pushing new addresses to
this stack.

This patch gives each context its private stack to address the problem.

This patch also adds extra memory fence micro-ops to lr/sc to guarantee
a correct execution order of memory instructions with respect to release
consistency model.

Change-Id: I1e95900367c89dd866ba872a5203f63359ac51ae
Reviewed-on: https://gem5-review.googlesource.com/c/8189
Reviewed-by: Alec Roelke <ar4jc@virginia.edu>
Maintainer: Alec Roelke <ar4jc@virginia.edu>

riscv: fixed syscall return value

In case of failure, a syscall returns a negative value encoding the
error code. This patch makes the risc-v implementation returns the
encoded value instead of its absolute value upon a failure of a syscall.

Change-Id: I6032b0337fe1cff5b326dbc6bb3b87a415f03300
Reviewed-on: https://gem5-review.googlesource.com/c/9627
Reviewed-by: Alec Roelke <ar4jc@virginia.edu>
Maintainer: Alec Roelke <ar4jc@virginia.edu>

riscv: ignore nanosleep syscall

Change-Id: I564a09564da668a5db3e75f15b33efaca363d71a
Reviewed-on: https://gem5-review.googlesource.com/c/9624
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

arch-riscv: initialize RISC-V's thread pointer register in clone syscall

This patch initializes thread pointer register to Thread Local Storage
(TLS)'s pointer given to a clone system call.

Change-Id: I03e2cf4763e6a0ed31f357772a513a05e1e3461b
Reviewed-on: https://gem5-review.googlesource.com/c/9622
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>

arch-arm: Fix Virtual interrupts in AArch64

Checking if cpsr.mode is equal to MODE_HYP doesn't work for AArch64.
This is because AArch64 is using different modes when in EL2, like EL2T
and EL2H.
This made Virtual Interrupts to be triggered even when executing in EL2
(hypervisor) whereas they should interrupt the scheduled VM only
(Non-Secure EL0 and EL1). This patch is fixing this by using the generic
currEL() helper for getting the exception level, which is working for
both AArch32 and AArch64.

Change-Id: I08640050ef06261f280ba1e63ca9f32c805af845
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/16202
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Fix extra comma in b7ce897f1e9545785bde982f72d04830c19d9a30

Change-Id: I649f8507ccb6c814b46b0b9b7e39dc912ecd9006
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/16242

arch-arm: Allow ArmPPI usage for PMU

Differently from ArmSPIs, ArmPPI interrupts need to be instantiated by
giving a ThreadContext pointer in the ArmPPIGen::get() method. Since the
PMU is registering the ThreadContext only at ISA startup time, ArmPPI
generation in deferred until the PMU has a non NULL pointer.

Change-Id: I17daa6f0e355363b8778d707b440cab9f75aaea2
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/16204
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Fix initialization of PMU counters

A version of Linux kernel initializes counters before enabling them.
Without this change, gem5 overwrites the value of counter, which causes
incorrect counter values derived by kernel.

Change-Id: If0c515111103018d5f65f74434d7711a67aeaee4
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/16203
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-riscv: Enable support for riscv 32-bit in SE mode.

This patch splits up the riscv SE mode support for 32 and 64-bit.
A future patch will add support for decoding rv32 instructions.

Change-Id: Ia79ae19f753caf94dc7e5830a6630efb94b419d7
Signed-off-by: Austin Harris <austinharris@utexas.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/15355
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Alec Roelke <alec.roelke@gmail.com>
Maintainer: Alec Roelke <alec.roelke@gmail.com>

riscv: remove NonSpeculative flag from fence inst

Fence instruction origially had two flags NonSpeculative and
MemBarrier. In O3 model, MemBarrier instructions are inserted
into the instruction queue by the InstructionQueue::insertBarrier (at
src/cpu/o3/iew_impl.hh:1083). Barrier instructions are implicitly
assumed to be non-speculative.

Adding NonSpeculative flag to fence instruction makes it inserted into
the instruction queue twice (at src/cpu/o3/iew_impl.hh:1083 and :1111).
This can lead to a deadlock if both pointers to the instruction are not
cleared from the queue when the instruction retires.

This patch removes NonSpeculative flag from the fence inst.

Change-Id: I26573d12a0b52f43b73c0e51158286dc98d05ea4
Reviewed-on: https://gem5-review.googlesource.com/c/8183
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Alec Roelke <ar4jc@virginia.edu>
Maintainer: Alec Roelke <ar4jc@virginia.edu>

arch-riscv: Initialize interrupt mask

This patch initializes RISCV interrupt mask to 0.

Change-Id: I56289d9f3f319e239e305befea006a0ad4d86b75
Reviewed-on: https://gem5-review.googlesource.com/c/16162
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

misc: added missing override specifier

Added missing specifier for various virtual functions.

Change-Id: I4783e92d78789a9ae182fad79aadceafb00b2458
Reviewed-on: https://gem5-review.googlesource.com/c/16103
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

riscv: Get rid of ISA specific register types in Interrupts.

Change-Id: I5542649c6af27a286f276a289b86c40dd7e32abc
Signed-off-by: Austin Harris <austinharris@utexas.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/16122
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

cpu, arch: Replace the CCReg type with RegVal.

Most architectures weren't using the CCReg type, and in x86 and arm
it was already a uint64_t.

Change-Id: I0b3d5e690e6b31db6f2627f449c89bde0f6750a6
Reviewed-on: https://gem5-review.googlesource.com/c/14515
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

power: Get rid of some ISA specific register types.

Change-Id: If63acb10705a9f442255680917d16630748ca8e1
Reviewed-on: https://gem5-review.googlesource.com/c/14465
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

null: Get rid of some register type definitions.

These are no longer used.

Change-Id: Ic6a35e8a7e25eab9d21a3eef683914e01508c6d7
Reviewed-on: https://gem5-review.googlesource.com/c/14463
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

mips: Stop using architecture specific register types.

Change-Id: I764f6eea214ba4e03cc0fe19a21abcb0ebd04408
Reviewed-on: https://gem5-review.googlesource.com/c/14462
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

alpha: Stop using architecture specific register types.

Change-Id: I4052000014c9f6f9ecefd3f37e58595c61599484
Reviewed-on: https://gem5-review.googlesource.com/c/14461
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

x86: Stop using/defining some ISA specific register types.

These have been replaced with the generic RegVal type.

Change-Id: I75c1134212067dea43aa0903d813633e06f3d6c6
Reviewed-on: https://gem5-review.googlesource.com/c/14476
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

riscv: Get rid of some ISA specific register types.

Change-Id: Ie812cf1d42536094273ba2ec731c16cca38db100
Reviewed-on: https://gem5-review.googlesource.com/c/14466
Reviewed-by: Alec Roelke <alec.roelke@gmail.com>
Maintainer: Alec Roelke <alec.roelke@gmail.com>

arch: cpu: Rename *FloatRegBits* to *FloatReg*.

Now that there's no plain FloatReg, there's no reason to distinguish
FloatRegBits with a special suffix since it's the only way to read or
write FP registers.

Change-Id: I3a60168c1d4302aed55223ea8e37b421f21efded
Reviewed-on: https://gem5-review.googlesource.com/c/14460
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

arch,cpu: Add vector predicate registers

Latest-gen. vector/SIMD extensions, including the Arm Scalable Vector
Extension (SVE), introduce the notion of a predicate register file.
This changeset adds this feature across architectures and CPU models.

Change-Id: Iebcadbad89c0a582ff8b1b70de353305db603946
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13715
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

arch-arm, configs: Create single instance of DTB autogeneration

This patch is rewriting the DTB autogeneration functions available in
fs_bigLITTLE.py and fs.py as a single method in the GenericArmSystem
so that other configuration scripts can make use of it.

Change-Id: I492bbf77e6b0ac5c5fbdbc75c0eecba29bd63bda
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15958
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Remove floatReg operand type

Change-Id: I87553257ce9c42d0e2514d5a1f010bc6e2e7f21e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15604
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Use VecElem instead of FloatReg for FP instruction

SIMD & FP Operations use FloatRegs in AArch32 mode and VecRegs in
AArch64 mode. The usage of two different register pools breaks
interprocessing between A32 and A64. This patch is changing definition
of arm operands so that they are backed by VecElems in A32, which are
mapped to the same storage as A64 VecRegs.

Change-Id: I54e2ea0ef1ae61d29aca57ab09acb589d82c1217
Reviewed-on: https://gem5-review.googlesource.com/c/15603
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch: Fix VecElem Operand generation in ISA parser

Fixes include:

* Change of reg_class: VecElemClass in lieau of non-existing
VectorElemClass.
* Removal of unused regId in operand constructor
* makeRead and makeWrite are using VecElem (which is a typedef
of uint32_t) as a source/destination type, regardless of the real
operand type (which is specified by ctype)

Change-Id: I4588e1120e1fc8fdb68b2b2f05d5e3692c55b2e8
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15602
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

cpu, arch, arch-arm: Wire unused VecElem code in the O3 model

VecElem code had been introduced in order to simulate change of renaming
for vector registers. Most of the work is happening on the rename_map
switchRenameMode. Change of renaming can happen after a squash in the
pipeline.
This patch is also changing the interface to the ISA part so that
a PCState is used instead of ISA in order to check if rename mode
has changed.

Change-Id: I8af795d771b958e0a0d459abfeceff5f16b4b5d4
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15601

arch-arm: Inital vector rename mode depending on A32/A64

Change-Id: I6b99833641b0ab6534471d5ff3ca5d3791285481
Reviewed-on: https://gem5-review.googlesource.com/c/15599
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Remove unused float operands

Removing FaP1 and FDest2 since they are not currently used by any ARM
instruction.

Change-Id: I4251dfcdd3f4434caaf0bdab507c1c3bd53fb5d2
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15596
Reviewed-by: Ciro Santilli <ciro.santilli@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch: Provide traceback when parsing ISA code

There is no line information When the ISA code is executed inside the
isa_parser environment and an error is encountered. The build stops and
reports the line of the let block containing the error.
This patch is enhacing the error reporting by printing the traceback of
the faulting ISA code.

Change-Id: I3acd17f0d78b2feb8fe6e48808a094c5b81624e6
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15595
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

hsail: Remove the MiscReg type.

It has been replaced by the ISA agnostic RegVal.

Change-Id: I563ea3852e37b5c1cf51eb0ac9a6f2a827ba89cf
Reviewed-on: https://gem5-review.googlesource.com/c/14464
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>

base: arch: Get rid of the now unused FloatRegVal type.

This type is no longer used since FP registers are accessed as integer
bit patterns.

Change-Id: I1070f9443d6247165fd64c6bc041811c28287e9f
Reviewed-on: https://gem5-review.googlesource.com/c/14459
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

arch-arm: Implement LoadAcquire/StoreRelease in AArch32

This patch is implementing LoadAcquire/StoreRelease instructions in
AArch32, which were added in ARMv8-A only and where not present in
ARMv7.

Change-Id: I5e26459971d0b183a955cd7b0c9c7eaffef453be
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15817
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: IsStoreConditional flag set depending on flavor

This patch is aligning A32 with A64 where the IsStoreConditional flag
doesn't have to be specified manually in the instruction implementation,
but will be automatically added to any exclusive store.

Change-Id: Id02ed6fc2beeca6d125017393714a7c6eb3d8a33
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15816
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Remove SWP and SWPB instructions

The SWP and SWPB instructions have been removed from AArch32. It was
previously (ARMv7) possible to enable them with the ID_ISAR0.Swap bits,
which are now hardcoded to 0b0000 (SWP and SWPB not implemented)

Change-Id: Ic32b534454a7e0f7494a6f0b5e11182c65b3fe24
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15815
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arm: Replace MiscReg with RegVal in utility.(hh|cc).

These uses snuck in after the previous pass which made this switch in
the rest of these files.

Change-Id: Ie891c6ec393a65f1c57c54301f0a2bb920d38bb0
Reviewed-on: https://gem5-review.googlesource.com/c/15795
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

sparc: Get rid of some register type definitions.

These are IntReg, FloatReg, FloatRegBits, and MiscReg. These have been
supplanted by the global types RegVal and FloatRegVal.

Change-Id: I956abfc7b439b083403e1a0d01e0bb35020bde44
Reviewed-on: https://gem5-review.googlesource.com/c/13627
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

arch: cpu: Stop passing around misc registers by reference.

These values are all basic integers (specifically uint64_t now), and
so passing them by const & is actually less efficient since there's a
extra level of indirection and an extra value, and the same sized value
(a 64 bit pointer vs. a 64 bit int) is being passed around.

Change-Id: Ie9956b8dc4c225068ab1afaba233ec2b42b76da3
Reviewed-on: https://gem5-review.googlesource.com/c/13626
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

arm: Get rid of some register type definitions.

These are IntReg, FloatReg, FloatRegBits, and MiscReg. These have been
supplanted by the global types RegVal and FloatRegVal.

Change-Id: Ief1cd85d0eff7156282ddb1ce168a2a5677f7435
Reviewed-on: https://gem5-review.googlesource.com/c/13625
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

arch-arm: implement the GDB XML target description for ARM

The supported registers are essentially the same as before this patch,
but it is now trivial to make new registers visible in future commits.

Change-Id: Id15b7aeccca824c342e49a626d2877179474f3d4
Reviewed-on: https://gem5-review.googlesource.com/c/15138
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Move AArch32 IMPLEMENTATION DEFINED registers

Moving AArch32 instruction accessing IMPLEMENTATION DEFINED registers
from pseudo.[cc/hh] to misc.[cc/hh] in order to symmetrically match
with AArch64 implementation.

Change-Id: I27b0d65925d7965589b765269ae54129426e4c88
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15735
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

sim-se add readv and modifies writev

Change-Id: I6cbce4389d5697da34058dc910306394e48c6582
Reviewed-on: https://gem5-review.googlesource.com/c/12117
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

sim-se: add ability to get/set sock metadata

Add getsockopt, getsockname, setsockname, and getpeername
system calls.

Change-Id: Ifa1d9a95f15b4fb12859dbfd3c4bd248de2e3d32
Reviewed-on: https://gem5-review.googlesource.com/c/12116
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

sim-se: add syscalls related to polling

Fix poll so that it will use the syscall retry capability
instead of causing a blocking call.

Add the accept and wait4 system calls.

Add polling to read to remove deadlocks that occur in the
event queue that are caused by blocking system calls.

Modify the write system call to return an error number in
case of error.

Change-Id: I0b4091a2e41e4187ebf69d63e0088f988f37d5da
Reviewed-on: https://gem5-review.googlesource.com/c/12115
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

sim-se: add calls for network transmissions

Add recvfrom, sendto, recvmsg, and sendmsg system calls.

Change-Id: I2eb50ea7823c8af57d99b3b8d443d2099418c06c
Reviewed-on: https://gem5-review.googlesource.com/c/12114
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

sim-se: add socket-based functionality

Add socket, socketpair, bind, list, connect and shutdown
system calls.

Change-Id: I635af3fca410f96fe28f8fe497e3d457a9dbc470
Reviewed-on: https://gem5-review.googlesource.com/c/12113
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

cpu: dev: sim: gpu-compute: Banish some ISA specific register types.

These types are IntReg, FloatReg, FloatRegBits, and MiscReg. There are
some remaining types, specifically the vector registers and the CCReg.
I'm less familiar with these new types of registers, and so will look
at getting rid of them at some later time.

Change-Id: Ide8f76b15c531286f61427330053b44074b8ac9b
Reviewed-on: https://gem5-review.googlesource.com/c/13624
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

arch: Make the ISA register types aliases for the global types.

The ISA specific types can thus be phased out.

Change-Id: I8ea531a099fad140a4ec9c91cd972fe044111d60
Reviewed-on: https://gem5-review.googlesource.com/c/13623
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

arm: Make the fp register types 64 bits.

This matches the other ISAs.

Change-Id: I84de91efde2529f4aecc7b26b84266d97459738c
Reviewed-on: https://gem5-review.googlesource.com/c/13622
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

arch-arm: Read VMPIDR instead of MPIDR when EL2 is Enabled

Trying to read MPIDR(_EL1) from EL1, should return the value of
VMPIDR_EL2 if EL2 is enabled. This patch is modifying the utility
function for reading MPIDR in order to match this behaviour for both
AArch32 and AArch64.

Change-Id: I32c2d4d5052f509e6e0542a5314844164221c6a3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15617
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Added TLBI_ALL EL2 instruction

This patch is adding TLBI_ALLE2(IS) operations to the arm ISA.

Change-Id: I8e35cff9a2cc414f4c5fbbc5aa0cfe5023a3f011
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15616
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-riscv: Add interrupt handling

Implement the Interrupts SimObject for RISC-V. This basically just
handles setting and getting the values of the interrupt-pending and
interrupt-enable CSRs according to the privileged ISA reference chapter
3.1.14. Note that it does NOT implement the PLIC as defined in chapter
7, as that is used for handling external interrupts which are defined
based on peripherals that are available.

Change-Id: Ia1321430f870ff5a3950217266fde0511332485b
Reviewed-on: https://gem5-review.googlesource.com/c/14377
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

arch-riscv: Fix reset function and style

In addition to fixing some style issues with resetting, this patch fixes
what happens on reset. The RISC-V privileged ISA reference manual says
that,
on reset:
1. Privilege mode is set to M
2. mstatus.mie <- 0; mstatus.mprv <- 0
3. PC <- reset vector
4. mcause <- reset cause (0 if there is no distinguishing causes)
5. Everything else is undefined
Because of 5, everything else will be left alone

Change-Id: I81bdf7a88b08874e3c3d5fc6c7f3ca2d796496b8
Reviewed-on: https://gem5-review.googlesource.com/c/14376
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

arch-arm: Fix usage of RegId constructor for VecElem

RegId() constructor requires three arguments in case of a VecElem
register: the class, the vector index and the element index inside the
vector, otherwise it panics.

Change-Id: Ic842df4dcddaffa83b211aa6e1dd1953cafa4951
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15615
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arm: Stop using the FloatReg and FloatRegBits types.

This will let us make those types 64 bits to be in line with the other
architectures.

Change-Id: I5aef5199f4d2d5bb1558afedac5c6c92bf95c021
Reviewed-on: https://gem5-review.googlesource.com/c/13621
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

sim-se, arch-arm: Add support for getdents64

Change-Id: Ib27950144d4c9802ffb842db98aec9e433ccbfc5
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Cc: Giacomo Travaglini <giacomo.travaglini@arm.com>
Cc: Javier Setoain <javier.setoain@arm.com>
Cc: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15438
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

arch-arm, sim-se: Add support for TLS in clone

Change-Id: I1f78dce05a48a2e3adfaf027cd38ab55507b9611
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Cc: Giacomo Travaglini <giacomo.travaglini@arm.com>
Cc: Javier Setoain <javier.setoain@arm.com>
Cc: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15437
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>

arch-arm, sim-se: Fix incorrect SP handling in clone

The clone syscall is currently broken on aarch64 since the aarch64
code uses an incorrect SP register. Fix this by storing the new stack
pointer in SP_EL0 instead of R13.

Change-Id: Ie17990b4f359608e3b53e5bf625eca53769a6653
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Cc: Giacomo Travaglini <giacomo.travaglini@arm.com>
Cc: Javier Setoain <javier.setoain@arm.com>
Cc: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15436
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>

sim-se: Refactor clone to avoid most ifdefs

Some parts of clone are architecture dependent. In some cases, we are
able to use architecture-specific helper functions or register
aliases. However, there is still some architecture-specific that is
protected by ifdefs in the common clone implementation.

Move these architecture-specific bits to the architecture-specific OS
class instead to avoid these ifdefs and make the code a bit more
readable.

Change-Id: Ia0903d738d0ba890863bddfa77e3b717db7f45de
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Cc: Giacomo Travaglini <giacomo.travaglini@arm.com>
Cc: Javier Setoain <javier.setoain@arm.com>
Cc: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15435
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>

arch-arm, sim-se: Wire up syscalls needed for pthreads

Change-Id: I8da5e3e0d7dc5d31ac82ed2045109d6d73cbf99d
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Cc: Giacomo Travaglini <giacomo.travaglini@arm.com>
Cc: Javier Setoain <javier.setoain@arm.com>
Cc: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15415
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>

dev-arm: Add a GICv3 model

Change-Id: Ib0067fc743f84ff7be9f12d2fc33ddf63736bdd1
Reviewed-on: https://gem5-review.googlesource.com/c/13436
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

arch-arm: Additional bits in misc ARM registers to use with the TLB and page walker

Change-Id: I71a6360709b35ad788d8c88fba1a7a2761233dbd
Reviewed-on: https://gem5-review.googlesource.com/c/14555
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arm: properly handle RES0/1 for SCTLRs

They were being treated as RAZ/RAO, which is incorrect.
Put the access masks in the register metadatabase now that we have one.

Also fix this for HVBAR.

Change-Id: I097c847e35be2d59fb8235fc621bb061ef514cfb
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/10401
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch, cpu: Remove float type accessors.

Use the binary accessors instead.

Change-Id: Iff1877e92c79df02b3d13635391a8c2f025776a2
Reviewed-on: https://gem5-review.googlesource.com/c/14457
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

arch-arm: Add Crypto in SE mode

This patch is also enabling AArch32 crypto instructions by setting the
ID_ISAR5 register accordingly.

Change-Id: Id412585b39b78570a65bd3047199c84e9db76cda
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15155
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch: Make the ISA parser always use binary floating point accessors.

Any operands which use read_code or write_code would need to start
using the floatToBits and bitsToFloat, but only ARM is using that
mechanism, and not on float operands.

Also I notice that the "predicate" mechanism for operands ignores the
read_code and write_code mechanism, and using both will not work
correctly. This change makes no attempt to fix that problem, but
shouldn't contribute to it either.

Change-Id: I0e3a7f78ed28f40cb66958ef12c32e862950fde0
Reviewed-on: https://gem5-review.googlesource.com/c/14456
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>

arch-x86: Add sys/syscall.h to x86 process.cc/syscall_emul.cc

Change a66d12c guards the selection of getdents()
in x86's process.cc file with SYS_getdents, however
process.cc does not include the right header for
SYS_getdents, which leads to x86 choosing the
unimplemented call. This change adds sys/syscall.h to
address the problem.

This change also adds sys/syscall.hh to syscall_emu.cc,
which only includes syscall.hh and may not be supported on
all systems.

Change-Id: If1adcf41e9e455de5f2827ba98c542fdcacdc22e
Reviewed-on: https://gem5-review.googlesource.com/c/14775
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>

arch-arm: correctly set floats from GDB on aarch64

aarch64 floating point registers are now stored as vector type, but this
was not updated in the stub.

Change-Id: I4a2bc1cea0eec9beeb5bbd49e2a868b9d5ed0a42
Reviewed-on: https://gem5-review.googlesource.com/c/14498
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

arch-arm: only change the pc address when GDB registers are set

The entire pcState was being reset, which made the simulation incorrectly
switch to aarch32 from aarch64.

Change-Id: I9ba7dd0ed95bc6120d94393bba272e0cb8c081c5
Reviewed-on: https://gem5-review.googlesource.com/c/14496
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

arch-arm: fix the aarch64 GDB stub

The main change is to remove vector registers from the GDB stub.

Those registers were intended for SVE, which is a new architecture feature
and not yet treated by default on the GDB present in Ubuntu 18.04, and
possibly not even on GDB master.

As a result, aarch64 GDB stub connections would fail with:

Remote 'g' packet reply is too long

The correct way to support those registers is to send XML GDB target
description files to the client. This feature is not yet available for
any architecture, and should be implemented in future patches.

Other smaller fixes are:

* cpsr is uint32_t in aarch64 as well as arm
* use M5_ATTR_PACKED on the register structs since they are being cast and
sent as byte arrays

Change-Id: I77cd8a98e322ecc60799e5b11fe5cd414d893cc7
Reviewed-on: https://gem5-review.googlesource.com/c/14495
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

arch-arm: Add missing template declaration

The lack of a template declaration for IllegalInstSetStateFault was
causing errors when compiling with clang.

Change-Id: If7f19d7e879330226c80df2baca73d88d818f673
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14618
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

cpu,arch-arm: Initialise data members

The value that is not initialized has a bogus value that manifests when
using some debug-flags what makes the usage of tracediff a bit more
challenging.

In addition, while debugging with other techniques, it introduces the
problem of understanding if the value of a field is 'intended' or just
an effect of the lack of initialisation.

Change-Id: Ied88caa77479c6f1d5166d80d1a1a057503cb106
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13125
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

arch-arm: clang compilation fixes

Fix 1: std::pair constructor is not a constexpr in clang implementation
Fix 2: static const templates need to be defined in their
translation unit

Change-Id: I3d9b9b47e1d148e44555f40e2e2aeff06707ff8f
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14617
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

hsail: Fix a warning/build failure for HSAIL_X86.

The Bitselect operation definition used ~ to invert the bits of a mask
value, but if that mask value is of type bool, that generates a
warning. This change casts that value to a uint64_t so that it can
always have ~ applied to it.

Change-Id: I7fbfc6ff264bc32a265f2724c772b8fae08590f7
Reviewed-on: https://gem5-review.googlesource.com/c/14655
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>

arch, base, cpu, gpu, mem: Replace assert(0 or false with panic.

Neither assert(0) nor assert(false) give any hint as to why control
getting to them is bad, and their more descriptive versions,
assert(0 && "description") and assert(false && "description"), jury
rig assert to add an error message when the utility function panic()
already does that directly with better formatting options.

This change replaces that flavor of call to assert with panic, except
in the actual code which processes the formatting that panic uses (to
avoid infinitely recurring error handling), and in some *.sm files
since I don't know what rules those have to follow and don't want to
accidentaly break them.

Change-Id: I8addfbfaf77eaed94ec8191f2ae4efb477cefdd0
Reviewed-on: https://gem5-review.googlesource.com/c/14636
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

sim-se: only implement getdentsFunc on supported hosts

The implementation of the getdents syscall relies on SYS_getdents, which
is not available on all archs, because the getdents syscall has been
superseded by getdents64, and does not exist on newer archs such as
aarch64.

This leads the build to break on aarch64 hosts with error:

error: 'SYS_getdents' was not declared in this scope

Change-Id: I8701fb5b61c0418b14a9463ef135a391a7f7a9ba
Reviewed-on: https://gem5-review.googlesource.com/c/14596
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>

x86: Get rid of a problematic DPRINTF in PremFp.

This DPRINTF shouldn't be necessary since it shows the operands and
results of the instruction which the trace should already make
available. Also by passing the destination register to DPRINTF, the ISA
parser will assume that it's also a source when tracking dependencies.

Change-Id: I820387c82578bdbb8d2e3d91652a6c0185077f54
Reviewed-on: https://gem5-review.googlesource.com/c/14475
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

arch-arm: Print register name when warning on AT instructions

With this patch we don't print anymore the enum value when warning
on any AT instruction usage, but we print the sys reg name instead

Change-Id: Ic6831b98ad6b0582be69883dc9519a9d3324da30
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14316
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Deprecate usage of legacy bootloader patching

This patch is implicitly deprecating the usage of bootloader patching,
which is injecting instructions from gem5 into the bootloader
binary. This was probably meant to provide a dynamic bootloader
entry point.
This is not needed in ARMv8.0, since we can simply update the
ArmSystem::resetAddress with the bootloader entry point.

Change-Id: I0c469873b8d69f7b49a7383e0754468bc1f2bd72
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14001
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: ArmSystem::resetAddr64 renamed to be used in AArch32

ARMv8 differs from ARMv7 with the presence of RVBAR register, which
contains the implementation defined reset address when EL3 is not
implemented.
The entry 0x0 in the AArch32 vector table, once used for the Reset
Vector, is now marked as "Not used", stating that it is now IMPLEMENTATION
DEFINED. An implementation might still use this vector table entry to
hold the Reset vector, but having a Reset address != than the general
vector table (for any other exception) is allowed.

At the moment any Reset exception is still using 0 as a vector table
base address. This patch is extending the ArmSystem::resetAddr64 to
ArmSystem::resetAddr so that it can be used for initializing
MVBAR/RVBAR. In order to do so, we are providing a specialized behavior
for the Reset exception when evaluating the vector base address.

Change-Id: I051a730dc089e194db3b107bbed19251c661f87e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14000
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Implement AArch32 RVBAR

RVBAR has been added to the system register list since ARMv8.0-A. It is
implemented only if the highest Exception Level is different (minor)
than EL3. If that's not the case, MVBAR is used. Since the two
registers are mutually exclusive (depending on the presence of EL3),
they share the same coprocessor numbers:

p15, 0, c12, c0, 1

Rather than introducing a new register alias, we overload MVBAR so that
it is treated as RVBAR if ArmSystem::highestEL() < EL3. This patch is
changing the MiscReg info so that EL1 or EL2 access MVBAR (as RVBAR).

N.B MVBAR is RW, whereas RVBAR is RO

Change-Id: Ida3070413fd151ce79c446e99a2a389298d5f5bd
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13999
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Remove SCTLR.VE bit

ARMv8 has removed SCTLR.VE bit which is now hardcoded to 0. We are
removing it from gem5 since we were not handling it anyway.

Change-Id: Ibde2db45c7f8add4a3188f2cb8c23701a6088d03
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13998
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Refactor ISA::clear by adding a ISA::clear32 method

The patch is also moving some initialization code to be used
by AArch64 as well since the registers are mapped to AArch64 ones.

Change-Id: I0089df25275434172c6e0e9cb125ee535c04d1b8
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13997
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Remove MISCREG commented numbers

Having an enum number might be useful in case we wanted to know how many
miscregs we have, but on the other hand it makes it tedious to update
the register list, since every commented number must be bumped. This
patch is removing the comments holding the MISCREG numbers

Change-Id: Ic5aba93885e4b8d6cb3bd6a4c49900b9e5474276
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13996
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

mips: Change the integer and fp register widths to be 64 bits.

This makes them more consistent with the other architectures, helping
to facilitate having a single, unified type across ISAs in the future.

Change-Id: I65efb10e39d453281b8429eeedbb46fa6b023a2b
Reviewed-on: https://gem5-review.googlesource.com/c/13620
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mips: Clean up type overrides for operands.

For operands which default to uw (uint32_t), there's no reason to
explicitly specify that all over the place. Also, when assigning to a
32 bit value which is supposed to be the full width of the resulting
register, there's no reason to override the value to be signed. If the
value is expanded into a larger value, then extra bits may get set
unintentionally through sign extension. Even if an instruction
produces a value which should be interpreted as signed, it will still
only produce a value of a certain predefined width, even if that answer
ends up stored in a larger variable.

Change-Id: I048d68c5dd08a1d40e8117ae9d36d70e05ec21c8
Reviewed-on: https://gem5-review.googlesource.com/c/13618
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

mips: Explicitly truncate the syscall return value down to 32 bits.

The IntReg type is 32 bits, and using it to cast the syscall return
value is appropriate, but we're attempting to get rid of the ISA
specific register types.

Change-Id: I42496dd2cc086a6b718e1ce087fef81bb897d02f
Reviewed-on: https://gem5-review.googlesource.com/c/13619
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

null: Claim to use 64 bit floating point registers.

The NULL ISA doesn't actually have registers, so this setting doesn't
matter. By making it 64 bits the ISA is more compatible with the other
ISAs.

Change-Id: I2c9b6d9a6f612719b8b00eb9dbed55fa2159e9b5
Reviewed-on: https://gem5-review.googlesource.com/c/13617
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

sparc: Switch the FloatReg and FloatRegBits types to be 64 bit.

These types aren't used by the ISA itself since they're defined to be
particular primitive types in the ISA description. This just affects
code outside of the ISA which work with those types of registers.

Change-Id: I4f62ab8fe04184cc23845090c82b250145a71747
Reviewed-on: https://gem5-review.googlesource.com/c/13616
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

arch, arm: Return s1Req upon fault in s2Lookup

When a s2Lookup object is created, a new request is created, based
upon the original, stage 1 request sent out by the CPU. When a fault
occurs during the second stage of translation, this new request is
returned. This can lead to issues with the O3 CPU. The O3 fetch stage
will not acknowledge the fault as it is a different request than the
one it sent out and does not contain a contextID. This commit
rectifies this.

Change-Id: I21cb7377a59aed9d90d99f048b2106eaf219e93a
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13782
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch, arm: Effect of AT instructions on descriptor handling

Some address translation instructions will stop translation after
the 1st stage and intercept the IPA, even in the presence of
stage 2 (eg AT S1E1). However, in the case of a TLB miss, the
table descriptors still need to be translated from IPA to PA to
avoid fetching the wrong addresses. This commit splits whether
IPA->PA translation is required for the VA and/or for the table
descriptors.

Change-Id: Ie53cdc00585f116150256f1d833460931b3bfb7d
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13781
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

syscall_emul: implement arm openat

This is especially important because the Ubuntu 18.04 packaged
arm-linux-gnueabihf-gcc uses the system call on the program initialization,
which leads all programs to fail with:

fatal: syscall openat (#322) unimplemented.

Change-Id: I5596162ad19644df7b6d21f2a46acc07030001ae
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13004
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: FIXUP for the add PRFM PST instruction commit

Change-Id: I898e5b565c6591f88ae732b24713aeae2c827cbd
Reviewed-on: https://gem5-review.googlesource.com/c/13815
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: We add PRFM PST instruction for arm

Note current PRFM supports only PLD, but PST (prefetch for store) is
also important for latency hiding. We also bug fix in disassembler to
display prfop correctly.

Change-Id: I9144e7233900aa2d555e1c1a6a2c2e41d837aa13
Signed-off-by: Yuetsu Kodama <yuetsu.kodama@riken.jp>
Reviewed-on: https://gem5-review.googlesource.com/c/13675
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>