---------- Begin Simulation Statistics ---------- sim_seconds 1.196225 # Number of seconds simulated sim_ticks 1196225147500 # Number of ticks simulated final_tick 1196225147500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks host_inst_rate 669591 # Simulator instruction rate (inst/s) host_op_rate 853186 # Simulator op (including micro ops) rate (op/s) host_tick_rate 13029857543 # Simulator tick rate (ticks/s) host_mem_usage 426076 # Number of bytes of host memory used host_seconds 91.81 # Real time elapsed on the host sim_insts 61472758 # Number of instructions simulated sim_ops 78327958 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::cpu1.inst 40 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::total 57 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu1.inst 40 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::total 57 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.inst 378508 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 4532924 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 337988 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 4964984 # Number of bytes read from this memory system.physmem.bytes_read::total 62119428 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 378508 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 337988 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 716496 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4092288 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory system.physmem.bytes_written::total 7119632 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.inst 12142 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 70901 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 5372 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 77606 # Number of read requests responded to by this memory system.physmem.num_reads::total 6654093 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 63942 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory system.physmem.num_writes::total 820778 # Number of write requests responded to by this memory system.physmem.bw_read::realview.clcd 43390253 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 54 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 161 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.inst 316419 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.data 3789357 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 214 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.inst 282545 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.data 4150543 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 51929545 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu0.inst 316419 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu1.inst 282545 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 598964 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 3421001 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 14211 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 2516536 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 5951749 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 3421001 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.clcd 43390253 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 54 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 161 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.inst 316419 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.data 3803568 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 214 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.inst 282545 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.data 6667079 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 57881294 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 6654093 # Number of read requests accepted system.physmem.writeReqs 820778 # Number of write requests accepted system.physmem.readBursts 6654093 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 820778 # Number of DRAM write bursts, including those merged in the write queue system.physmem.bytesReadDRAM 425823936 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 38016 # Total number of bytes read from write queue system.physmem.bytesWritten 7142848 # Total number of bytes written to DRAM system.physmem.bytesReadSys 62119428 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 7119632 # Total written bytes from the system interface side system.physmem.servicedByWrQ 594 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 709146 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 11979 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 415258 # Per bank write bursts system.physmem.perBankRdBursts::1 415304 # Per bank write bursts system.physmem.perBankRdBursts::2 415298 # Per bank write bursts system.physmem.perBankRdBursts::3 415715 # Per bank write bursts system.physmem.perBankRdBursts::4 422332 # Per bank write bursts system.physmem.perBankRdBursts::5 415542 # Per bank write bursts system.physmem.perBankRdBursts::6 415821 # Per bank write bursts system.physmem.perBankRdBursts::7 415579 # Per bank write bursts system.physmem.perBankRdBursts::8 415943 # Per bank write bursts system.physmem.perBankRdBursts::9 415582 # Per bank write bursts system.physmem.perBankRdBursts::10 415396 # Per bank write bursts system.physmem.perBankRdBursts::11 414885 # Per bank write bursts system.physmem.perBankRdBursts::12 414891 # Per bank write bursts system.physmem.perBankRdBursts::13 415396 # Per bank write bursts system.physmem.perBankRdBursts::14 415532 # Per bank write bursts system.physmem.perBankRdBursts::15 415025 # Per bank write bursts system.physmem.perBankWrBursts::0 6797 # Per bank write bursts system.physmem.perBankWrBursts::1 6838 # Per bank write bursts system.physmem.perBankWrBursts::2 6874 # Per bank write bursts system.physmem.perBankWrBursts::3 7108 # Per bank write bursts system.physmem.perBankWrBursts::4 7245 # Per bank write bursts system.physmem.perBankWrBursts::5 7088 # Per bank write bursts system.physmem.perBankWrBursts::6 7332 # Per bank write bursts system.physmem.perBankWrBursts::7 7150 # Per bank write bursts system.physmem.perBankWrBursts::8 7392 # Per bank write bursts system.physmem.perBankWrBursts::9 7114 # Per bank write bursts system.physmem.perBankWrBursts::10 7008 # Per bank write bursts system.physmem.perBankWrBursts::11 6578 # Per bank write bursts system.physmem.perBankWrBursts::12 6732 # Per bank write bursts system.physmem.perBankWrBursts::13 6801 # Per bank write bursts system.physmem.perBankWrBursts::14 7004 # Per bank write bursts system.physmem.perBankWrBursts::15 6546 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry system.physmem.totGap 1196220625500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 6849 # Read request sizes (log2) system.physmem.readPktSize::3 6488064 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) system.physmem.readPktSize::6 159180 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 756836 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 63942 # Write request sizes (log2) system.physmem.rdQLenPdf::0 568386 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 406756 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 406740 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 413202 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 408903 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 410926 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1188562 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1189774 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1562236 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 22558 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 14685 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 15166 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 13714 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 12546 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 9828 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 9386 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 119 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 2656 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 2719 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 3656 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 5124 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 5129 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 5125 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 5127 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 5169 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 5182 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 5159 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 6206 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 5353 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 5316 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 6283 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 5251 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 5231 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 5217 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 5137 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 1141 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 1090 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 1087 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 1087 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 1076 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 1076 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 1074 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 1072 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 1074 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 1072 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 1070 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 1069 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 1069 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 1067 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 1067 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 1065 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 1065 # What write queue length does an incoming req see system.physmem.wrQLenPdf::50 1064 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 1064 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 1064 # What write queue length does an incoming req see system.physmem.wrQLenPdf::53 1064 # What write queue length does an incoming req see system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 427748 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 996.884371 # Bytes accessed per row activation system.physmem.bytesPerActivate::gmean 962.233746 # Bytes accessed per row activation system.physmem.bytesPerActivate::stdev 147.681447 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 5003 1.17% 1.17% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 3928 0.92% 2.09% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 2092 0.49% 2.58% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 1312 0.31% 2.88% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 1079 0.25% 3.14% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 787 0.18% 3.32% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 742 0.17% 3.49% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 447 0.10% 3.60% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 412358 96.40% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 427748 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 5121 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::mean 1299.254638 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::stdev 29808.283067 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-65535 5114 99.86% 99.86% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-262143 3 0.06% 99.92% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::589824-655359 1 0.02% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::786432-851967 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::983040-1.04858e+06 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1.57286e+06-1.6384e+06 1 0.02% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 5121 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 5121 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::mean 21.793986 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::gmean 20.383938 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::stdev 9.006526 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::16 2131 41.61% 41.61% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::17 296 5.78% 47.39% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::18 286 5.58% 52.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::19 1314 25.66% 78.64% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::20 15 0.29% 78.93% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::21 5 0.10% 79.03% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::22 2 0.04% 79.07% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::24 2 0.04% 79.11% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::25 1 0.02% 79.13% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::28 3 0.06% 79.18% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::34 1 0.02% 79.20% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::35 1 0.02% 79.22% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::39 953 18.61% 97.83% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::40 61 1.19% 99.02% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::41 17 0.33% 99.36% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::42 33 0.64% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 5121 # Writes before turning the bus around for reads system.physmem.totQLat 249828830750 # Total ticks spent queuing system.physmem.totMemAccLat 297299498250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 33267495000 # Total ticks spent in databus transfers system.physmem.totBankLat 14203172500 # Total ticks spent accessing banks system.physmem.avgQLat 37548.49 # Average queueing delay per DRAM burst system.physmem.avgBankLat 2134.69 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst system.physmem.avgMemAccLat 44683.18 # Average memory access latency per DRAM burst system.physmem.avgRdBW 355.97 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 5.97 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 51.93 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 5.95 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.83 # Data bus utilization in percentage system.physmem.busUtilRead 2.78 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 4.56 # Average read queue length when enqueuing system.physmem.avgWrQLen 29.44 # Average write queue length when enqueuing system.physmem.readRowHits 6202256 # Number of row buffer hits during reads system.physmem.writeRowHits 93908 # Number of row buffer hits during writes system.physmem.readRowHitRate 93.22 # Row buffer hit rate for reads system.physmem.writeRowHitRate 84.12 # Row buffer hit rate for writes system.physmem.avgGap 160032.28 # Average gap between requests system.physmem.pageHitRate 93.07 # Row buffer hit rate, read and write combined system.physmem.prechargeAllPercent 6.14 # Percentage of time for which DRAM has all the banks in precharge state system.membus.throughput 59898120 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 7703395 # Transaction distribution system.membus.trans_dist::ReadResp 7703395 # Transaction distribution system.membus.trans_dist::WriteReq 767585 # Transaction distribution system.membus.trans_dist::WriteResp 767585 # Transaction distribution system.membus.trans_dist::Writeback 63942 # Transaction distribution system.membus.trans_dist::UpgradeReq 31730 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 17317 # Transaction distribution system.membus.trans_dist::UpgradeResp 11979 # Transaction distribution system.membus.trans_dist::ReadExReq 137317 # Transaction distribution system.membus.trans_dist::ReadExResp 136921 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382690 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 10302 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 914 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1971094 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::total 4365038 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12976128 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 12976128 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 17341166 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390070 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 20604 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1828 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17334548 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::total 19747126 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 51904512 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 51904512 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::total 71651638 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 71651638 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 1224825500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 18000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) system.membus.reqLayer2.occupancy 9234000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) system.membus.reqLayer5.occupancy 786000 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) system.membus.reqLayer6.occupancy 9208108500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.8 # Layer utilization (%) system.membus.respLayer1.occupancy 5075173558 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) system.membus.respLayer2.occupancy 16181474500 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.4 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.l2c.tags.replacements 69062 # number of replacements system.l2c.tags.tagsinuse 52959.899517 # Cycle average of tags in use system.l2c.tags.total_refs 1674433 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 134270 # Sample count of references to valid blocks. system.l2c.tags.avg_refs 12.470641 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.l2c.tags.occ_blocks::writebacks 40142.433744 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000410 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.003238 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.inst 3707.808501 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.data 4231.213775 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.742447 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.inst 2816.465022 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.data 2059.232379 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.612525 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.inst 0.056577 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.data 0.064563 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.inst 0.042976 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.data 0.031421 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.808104 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id system.l2c.tags.occ_task_id_blocks::1024 65203 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::2 1924 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::3 7908 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::4 55276 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1024 0.994919 # Percentage of cache occupancy per task id system.l2c.tags.tag_accesses 17240213 # Number of tag accesses system.l2c.tags.data_accesses 17240213 # Number of data accesses system.l2c.ReadReq_hits::cpu0.dtb.walker 2997 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 1656 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.inst 349452 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.data 169925 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.dtb.walker 6371 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.itb.walker 1905 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.inst 535287 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.data 180837 # number of ReadReq hits system.l2c.ReadReq_hits::total 1248430 # number of ReadReq hits system.l2c.Writeback_hits::writebacks 572475 # number of Writeback hits system.l2c.Writeback_hits::total 572475 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 1043 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 587 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 1630 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu0.data 220 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu1.data 84 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 304 # number of SCUpgradeReq hits system.l2c.ReadExReq_hits::cpu0.data 47236 # number of ReadExReq hits system.l2c.ReadExReq_hits::cpu1.data 62412 # number of ReadExReq hits system.l2c.ReadExReq_hits::total 109648 # number of ReadExReq hits system.l2c.demand_hits::cpu0.dtb.walker 2997 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.itb.walker 1656 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.inst 349452 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.data 217161 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.dtb.walker 6371 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.itb.walker 1905 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.inst 535287 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.data 243249 # number of demand (read+write) hits system.l2c.demand_hits::total 1358078 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.dtb.walker 2997 # number of overall hits system.l2c.overall_hits::cpu0.itb.walker 1656 # number of overall hits system.l2c.overall_hits::cpu0.inst 349452 # number of overall hits system.l2c.overall_hits::cpu0.data 217161 # number of overall hits system.l2c.overall_hits::cpu1.dtb.walker 6371 # number of overall hits system.l2c.overall_hits::cpu1.itb.walker 1905 # number of overall hits system.l2c.overall_hits::cpu1.inst 535287 # number of overall hits system.l2c.overall_hits::cpu1.data 243249 # number of overall hits system.l2c.overall_hits::total 1358078 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.inst 5500 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.data 7825 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 4 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.inst 5275 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.data 3652 # number of ReadReq misses system.l2c.ReadReq_misses::total 22260 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu0.data 3753 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu1.data 4772 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 8525 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu0.data 571 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 460 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 1031 # number of SCUpgradeReq misses system.l2c.ReadExReq_misses::cpu0.data 63889 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 75455 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 139344 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.inst 5500 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.data 71714 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 4 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.inst 5275 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.data 79107 # number of demand (read+write) misses system.l2c.demand_misses::total 161604 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses system.l2c.overall_misses::cpu0.inst 5500 # number of overall misses system.l2c.overall_misses::cpu0.data 71714 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 4 # number of overall misses system.l2c.overall_misses::cpu1.inst 5275 # number of overall misses system.l2c.overall_misses::cpu1.data 79107 # number of overall misses system.l2c.overall_misses::total 161604 # number of overall misses system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 32000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.itb.walker 224500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.inst 385138750 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.data 587705249 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 334500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.inst 381420250 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.data 283658250 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::total 1638513499 # number of ReadReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu0.data 11041523 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu1.data 13954898 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::total 24996421 # number of UpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1841422 # number of SCUpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2322900 # number of SCUpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::total 4164322 # number of SCUpgradeReq miss cycles system.l2c.ReadExReq_miss_latency::cpu0.data 4291032858 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::cpu1.data 5578462720 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::total 9869495578 # number of ReadExReq miss cycles system.l2c.demand_miss_latency::cpu0.dtb.walker 32000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.itb.walker 224500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.inst 385138750 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.data 4878738107 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.dtb.walker 334500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.inst 381420250 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.data 5862120970 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::total 11508009077 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu0.dtb.walker 32000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.itb.walker 224500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.inst 385138750 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.data 4878738107 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.dtb.walker 334500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.inst 381420250 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.data 5862120970 # number of overall miss cycles system.l2c.overall_miss_latency::total 11508009077 # number of overall miss cycles system.l2c.ReadReq_accesses::cpu0.dtb.walker 2998 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.itb.walker 1659 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.inst 354952 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.data 177750 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.dtb.walker 6375 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.itb.walker 1905 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.inst 540562 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.data 184489 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::total 1270690 # number of ReadReq accesses(hits+misses) system.l2c.Writeback_accesses::writebacks 572475 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 572475 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 4796 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 5359 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 10155 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu0.data 791 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu1.data 544 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 1335 # number of SCUpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.data 111125 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1.data 137867 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 248992 # number of ReadExReq accesses(hits+misses) system.l2c.demand_accesses::cpu0.dtb.walker 2998 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.itb.walker 1659 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.inst 354952 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.data 288875 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.dtb.walker 6375 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.itb.walker 1905 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.inst 540562 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.data 322356 # number of demand (read+write) accesses system.l2c.demand_accesses::total 1519682 # number of demand (read+write) accesses system.l2c.overall_accesses::cpu0.dtb.walker 2998 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.itb.walker 1659 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.inst 354952 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.data 288875 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.dtb.walker 6375 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.itb.walker 1905 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.inst 540562 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.data 322356 # number of overall (read+write) accesses system.l2c.overall_accesses::total 1519682 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000334 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001808 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.inst 0.015495 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.data 0.044023 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000627 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.inst 0.009758 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.data 0.019795 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::total 0.017518 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.782527 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 0.890465 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 0.839488 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.721871 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.845588 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::total 0.772285 # miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 0.574929 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 0.547303 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::total 0.559632 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000334 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.itb.walker 0.001808 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.inst 0.015495 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.248253 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000627 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.009758 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.data 0.245403 # miss rate for demand accesses system.l2c.demand_miss_rate::total 0.106341 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000334 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.itb.walker 0.001808 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.inst 0.015495 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.data 0.248253 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000627 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.009758 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.data 0.245403 # miss rate for overall accesses system.l2c.overall_miss_rate::total 0.106341 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 32000 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 74833.333333 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.inst 70025.227273 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.data 75106.102109 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 83625 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72307.156398 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.data 77672.029025 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total 73607.973899 # average ReadReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2942.052491 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2924.329003 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total 2932.131496 # average UpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3224.907180 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5049.782609 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::total 4039.109602 # average SCUpgradeReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu0.data 67163.875753 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu1.data 73930.988271 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total 70828.278060 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 32000 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.itb.walker 74833.333333 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.inst 70025.227273 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.data 68030.483685 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 83625 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.inst 72307.156398 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.data 74103.694616 # average overall miss latency system.l2c.demand_avg_miss_latency::total 71211.164804 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 32000 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.itb.walker 74833.333333 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.inst 70025.227273 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.data 68030.483685 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 83625 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.inst 72307.156398 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.data 74103.694616 # average overall miss latency system.l2c.overall_avg_miss_latency::total 71211.164804 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed system.l2c.writebacks::writebacks 63942 # number of writebacks system.l2c.writebacks::total 63942 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu0.inst 1 # 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number of SCUpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 460 # number of SCUpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::total 1031 # number of SCUpgradeReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu0.data 63889 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu1.data 75455 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::total 139344 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu0.dtb.walker 1 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 3 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.inst 5499 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.data 71714 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.dtb.walker 4 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.inst 5275 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.data 79107 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::total 161603 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu0.dtb.walker 1 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 3 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.inst 5499 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.data 71714 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.dtb.walker 4 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.inst 5275 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.data 79107 # number of overall MSHR misses system.l2c.overall_mshr_misses::total 161603 # number of overall MSHR misses system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 20000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 187500 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 315394500 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.data 490118749 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 284500 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 314655750 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.data 238278250 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::total 1358939249 # number of ReadReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 37548751 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 47763765 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::total 85312516 # number of UpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 5717068 # number of SCUpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4604958 # number of SCUpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::total 10322026 # number of SCUpgradeReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3469064140 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4618288780 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::total 8087352920 # number of ReadExReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 20000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 187500 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.inst 315394500 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.data 3959182889 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 284500 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.inst 314655750 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.data 4856567030 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::total 9446292169 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 20000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 187500 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.inst 315394500 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.data 3959182889 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 284500 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.inst 314655750 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.data 4856567030 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::total 9446292169 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 352326000 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 11221595994 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5508250 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 155529668246 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::total 167109098490 # number of ReadReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1041121994 # number of WriteReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 15728911223 # number of WriteReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency::total 16770033217 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 352326000 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.data 12262717988 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5508250 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.data 171258579469 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::total 183879131707 # number of overall MSHR uncacheable cycles system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000334 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001808 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015492 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.044023 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000627 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009758 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.019795 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total 0.017517 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.782527 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.890465 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total 0.839488 # mshr miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.721871 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.845588 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.772285 # mshr miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.574929 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.547303 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total 0.559632 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000334 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001808 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015492 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.data 0.248253 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000627 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009758 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.data 0.245403 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total 0.106340 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000334 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001808 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015492 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.data 0.248253 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000627 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009758 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.data 0.245403 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total 0.106340 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 20000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 57354.882706 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 62634.983898 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 71125 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 59650.379147 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65245.961117 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::total 61051.226425 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10004.996270 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10009.171207 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10007.333255 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10012.378284 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10010.778261 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10011.664403 # average SCUpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 54298.300803 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61205.868133 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::total 58038.759616 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 20000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 57354.882706 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.data 55207.949480 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 71125 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59650.379147 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61392.380320 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::total 58453.693118 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 20000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 57354.882706 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.data 55207.949480 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 71125 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59650.379147 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61392.380320 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::total 58453.693118 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.toL2Bus.throughput 119642613 # Throughput (bytes/s) system.toL2Bus.trans_dist::ReadReq 2536412 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 2536412 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 767585 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 767585 # Transaction distribution system.toL2Bus.trans_dist::Writeback 572475 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 30937 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 17621 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 48558 # Transaction distribution system.toL2Bus.trans_dist::ReadExReq 260776 # Transaction distribution system.toL2Bus.trans_dist::ReadExResp 260776 # Transaction distribution system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 723469 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1059051 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 4339 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 7907 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1082141 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4772543 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 7929 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 20256 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count::total 7677635 # Packet count per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 22743520 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 35146882 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 6636 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 11992 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 34596404 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 46050592 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 7620 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 25500 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size::total 138589146 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.data_through_bus 138589146 # Total data (bytes) system.toL2Bus.snoop_data_through_bus 4530356 # Total snoop data (bytes) system.toL2Bus.reqLayer0.occupancy 4766758175 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) system.toL2Bus.respLayer0.occupancy 1607753214 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) system.toL2Bus.respLayer1.occupancy 1517597206 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.toL2Bus.respLayer2.occupancy 2680000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) system.toL2Bus.respLayer3.occupancy 4909499 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.toL2Bus.respLayer6.occupancy 2437223968 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.2 # Layer utilization (%) system.toL2Bus.respLayer7.occupancy 3163938724 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 0.3 # Layer utilization (%) system.toL2Bus.respLayer8.occupancy 6024000 # Layer occupancy (ticks) system.toL2Bus.respLayer8.utilization 0.0 # Layer utilization (%) system.toL2Bus.respLayer9.occupancy 13881500 # Layer occupancy (ticks) system.toL2Bus.respLayer9.utilization 0.0 # Layer utilization (%) system.iobus.throughput 45388263 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 7671442 # Transaction distribution system.iobus.trans_dist::ReadResp 7671442 # Transaction distribution system.iobus.trans_dist::WriteReq 7967 # Transaction distribution system.iobus.trans_dist::WriteResp 7967 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30566 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8070 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 742 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 494 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 2382690 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12976128 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 12976128 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::total 15358818 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40335 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16140 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1484 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 271 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::total 2390070 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 51904512 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 51904512 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::total 54294582 # Cumulative packet size per connected master and slave (bytes) system.iobus.data_through_bus 54294582 # Total data (bytes) system.iobus.reqLayer0.occupancy 21430000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 4041000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 377000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 297000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.1 # Layer utilization (%) system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 6488064000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%) system.iobus.respLayer0.occupancy 2374723000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.2 # Layer utilization (%) system.iobus.respLayer1.occupancy 16195242500 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.4 # Layer utilization (%) system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses system.cpu0.dtb.read_hits 5879584 # DTB read hits system.cpu0.dtb.read_misses 2138 # DTB read misses system.cpu0.dtb.write_hits 4838515 # DTB write hits system.cpu0.dtb.write_misses 406 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID system.cpu0.dtb.flush_entries 1387 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.dtb.prefetch_faults 88 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 203 # Number of TLB faults due to permissions restrictions system.cpu0.dtb.read_accesses 5881722 # DTB read accesses system.cpu0.dtb.write_accesses 4838921 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses system.cpu0.dtb.hits 10718099 # DTB hits system.cpu0.dtb.misses 2544 # DTB misses system.cpu0.dtb.accesses 10720643 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.itb.inst_hits 24773464 # ITB inst hits system.cpu0.itb.inst_misses 1350 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID system.cpu0.itb.flush_entries 963 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses system.cpu0.itb.inst_accesses 24774814 # ITB inst accesses system.cpu0.itb.hits 24773464 # DTB hits system.cpu0.itb.misses 1350 # DTB misses system.cpu0.itb.accesses 24774814 # DTB accesses system.cpu0.numCycles 2391604989 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.committedInsts 24375312 # Number of instructions committed system.cpu0.committedOps 31460856 # Number of ops (including micro ops) committed system.cpu0.num_int_alu_accesses 28085533 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 4364 # Number of float alu accesses system.cpu0.num_func_calls 1070699 # number of times a function call or return occured system.cpu0.num_conditional_control_insts 3751745 # number of instructions that are conditional controls system.cpu0.num_int_insts 28085533 # number of integer instructions system.cpu0.num_fp_insts 4364 # number of float instructions system.cpu0.num_int_register_reads 162520351 # number of times the integer registers were read system.cpu0.num_int_register_writes 30535592 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3980 # number of times the floating registers were read system.cpu0.num_fp_register_writes 384 # number of times the floating registers were written system.cpu0.num_mem_refs 11309766 # number of memory refs system.cpu0.num_load_insts 6158982 # Number of load instructions system.cpu0.num_store_insts 5150784 # Number of store instructions system.cpu0.num_idle_cycles 2265857607.135565 # Number of idle cycles system.cpu0.num_busy_cycles 125747381.864435 # Number of busy cycles system.cpu0.not_idle_fraction 0.052579 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.947421 # Percentage of idle cycles system.cpu0.Branches 4778581 # Number of branches fetched system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 39137 # number of quiesce instructions executed system.cpu0.icache.tags.replacements 354708 # number of replacements system.cpu0.icache.tags.tagsinuse 509.352361 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 24418226 # Total number of references to valid blocks. system.cpu0.icache.tags.sampled_refs 355220 # Sample count of references to valid blocks. system.cpu0.icache.tags.avg_refs 68.741135 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 76254991000 # Cycle when the warmup percentage was hit. system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.352361 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994829 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.994829 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 464 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 47 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu0.icache.tags.tag_accesses 25128668 # Number of tag accesses system.cpu0.icache.tags.data_accesses 25128668 # Number of data accesses system.cpu0.icache.ReadReq_hits::cpu0.inst 24418226 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 24418226 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 24418226 # number of demand (read+write) hits system.cpu0.icache.demand_hits::total 24418226 # number of demand (read+write) hits system.cpu0.icache.overall_hits::cpu0.inst 24418226 # number of overall hits system.cpu0.icache.overall_hits::total 24418226 # number of overall hits system.cpu0.icache.ReadReq_misses::cpu0.inst 355221 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 355221 # number of ReadReq misses system.cpu0.icache.demand_misses::cpu0.inst 355221 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 355221 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 355221 # number of overall misses system.cpu0.icache.overall_misses::total 355221 # number of overall misses system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 4963623214 # number of ReadReq miss cycles system.cpu0.icache.ReadReq_miss_latency::total 4963623214 # number of ReadReq miss cycles system.cpu0.icache.demand_miss_latency::cpu0.inst 4963623214 # number of demand (read+write) miss cycles system.cpu0.icache.demand_miss_latency::total 4963623214 # number of demand (read+write) miss cycles system.cpu0.icache.overall_miss_latency::cpu0.inst 4963623214 # number of overall miss cycles system.cpu0.icache.overall_miss_latency::total 4963623214 # number of overall miss cycles system.cpu0.icache.ReadReq_accesses::cpu0.inst 24773447 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::total 24773447 # number of ReadReq accesses(hits+misses) system.cpu0.icache.demand_accesses::cpu0.inst 24773447 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::total 24773447 # number of demand (read+write) accesses system.cpu0.icache.overall_accesses::cpu0.inst 24773447 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::total 24773447 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014339 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::total 0.014339 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014339 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total 0.014339 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014339 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.014339 # miss rate for overall accesses system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13973.338327 # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::total 13973.338327 # average ReadReq miss latency system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13973.338327 # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::total 13973.338327 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13973.338327 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::total 13973.338327 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 355221 # number of ReadReq MSHR misses system.cpu0.icache.ReadReq_mshr_misses::total 355221 # number of ReadReq MSHR misses system.cpu0.icache.demand_mshr_misses::cpu0.inst 355221 # number of demand (read+write) MSHR misses system.cpu0.icache.demand_mshr_misses::total 355221 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 355221 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 355221 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4251043786 # number of ReadReq MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_latency::total 4251043786 # number of ReadReq MSHR miss cycles system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4251043786 # number of demand (read+write) MSHR miss cycles system.cpu0.icache.demand_mshr_miss_latency::total 4251043786 # number of demand (read+write) MSHR miss cycles system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4251043786 # number of overall MSHR miss cycles system.cpu0.icache.overall_mshr_miss_latency::total 4251043786 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 443885000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 443885000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 443885000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 443885000 # number of overall MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014339 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014339 # mshr miss rate for ReadReq accesses system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014339 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total 0.014339 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014339 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.014339 # mshr miss rate for overall accesses system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11967.321149 # average ReadReq mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11967.321149 # average ReadReq mshr miss latency system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11967.321149 # average overall mshr miss latency system.cpu0.icache.demand_avg_mshr_miss_latency::total 11967.321149 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11967.321149 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::total 11967.321149 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.tags.replacements 278858 # number of replacements system.cpu0.dcache.tags.tagsinuse 453.142717 # Cycle average of tags in use system.cpu0.dcache.tags.total_refs 10319958 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 279247 # Sample count of references to valid blocks. system.cpu0.dcache.tags.avg_refs 36.956379 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 673996250 # Cycle when the warmup percentage was hit. system.cpu0.dcache.tags.occ_blocks::cpu0.data 453.142717 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.885044 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.885044 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 389 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 379 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 0.759766 # Percentage of cache occupancy per task id system.cpu0.dcache.tags.tag_accesses 42855830 # Number of tag accesses system.cpu0.dcache.tags.data_accesses 42855830 # Number of data accesses system.cpu0.dcache.ReadReq_hits::cpu0.data 5473702 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 5473702 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 4567964 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::total 4567964 # number of WriteReq hits system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 129389 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 129389 # number of LoadLockedReq hits system.cpu0.dcache.StoreCondReq_hits::cpu0.data 130155 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 130155 # number of StoreCondReq hits system.cpu0.dcache.demand_hits::cpu0.data 10041666 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::total 10041666 # number of demand (read+write) hits system.cpu0.dcache.overall_hits::cpu0.data 10041666 # number of overall hits system.cpu0.dcache.overall_hits::total 10041666 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.data 191503 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 191503 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::cpu0.data 126416 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::total 126416 # number of WriteReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8708 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 8708 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7742 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 7742 # number of StoreCondReq misses system.cpu0.dcache.demand_misses::cpu0.data 317919 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::total 317919 # number of demand (read+write) misses system.cpu0.dcache.overall_misses::cpu0.data 317919 # number of overall misses system.cpu0.dcache.overall_misses::total 317919 # number of overall misses system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2845005745 # number of ReadReq miss cycles system.cpu0.dcache.ReadReq_miss_latency::total 2845005745 # number of ReadReq miss cycles system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5278408391 # number of WriteReq miss cycles system.cpu0.dcache.WriteReq_miss_latency::total 5278408391 # number of WriteReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 82648500 # number of LoadLockedReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::total 82648500 # number of LoadLockedReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 45599070 # number of StoreCondReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::total 45599070 # number of StoreCondReq miss cycles system.cpu0.dcache.demand_miss_latency::cpu0.data 8123414136 # number of demand (read+write) miss cycles system.cpu0.dcache.demand_miss_latency::total 8123414136 # number of demand (read+write) miss cycles system.cpu0.dcache.overall_miss_latency::cpu0.data 8123414136 # number of overall miss cycles system.cpu0.dcache.overall_miss_latency::total 8123414136 # number of overall miss cycles system.cpu0.dcache.ReadReq_accesses::cpu0.data 5665205 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 5665205 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 4694380 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::total 4694380 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 138097 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 138097 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 137897 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 137897 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.demand_accesses::cpu0.data 10359585 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::total 10359585 # number of demand (read+write) accesses system.cpu0.dcache.overall_accesses::cpu0.data 10359585 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 10359585 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033803 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.033803 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.026929 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::total 0.026929 # miss rate for WriteReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.063057 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.063057 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.056143 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.056143 # miss rate for StoreCondReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.030688 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total 0.030688 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.030688 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total 0.030688 # miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14856.194133 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::total 14856.194133 # average ReadReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 41754.274704 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::total 41754.274704 # average WriteReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9491.100138 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9491.100138 # average LoadLockedReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5889.830793 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5889.830793 # average StoreCondReq miss latency system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25551.835958 # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::total 25551.835958 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 25551.835958 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::total 25551.835958 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 257140 # number of writebacks system.cpu0.dcache.writebacks::total 257140 # number of writebacks system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 191503 # number of ReadReq MSHR misses system.cpu0.dcache.ReadReq_mshr_misses::total 191503 # number of ReadReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 126416 # number of WriteReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::total 126416 # number of WriteReq MSHR misses system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8708 # number of LoadLockedReq MSHR misses system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8708 # number of LoadLockedReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7738 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::total 7738 # number of StoreCondReq MSHR misses system.cpu0.dcache.demand_mshr_misses::cpu0.data 317919 # number of demand (read+write) MSHR misses system.cpu0.dcache.demand_mshr_misses::total 317919 # number of demand (read+write) MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu0.data 317919 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 317919 # number of overall MSHR misses system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2460118255 # number of ReadReq MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2460118255 # number of ReadReq MSHR miss cycles system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4997663609 # number of WriteReq MSHR miss cycles system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4997663609 # number of WriteReq MSHR miss cycles system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 65185500 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 65185500 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 30121930 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 30121930 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7457781864 # number of demand (read+write) MSHR miss cycles system.cpu0.dcache.demand_mshr_miss_latency::total 7457781864 # number of demand (read+write) MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7457781864 # number of overall MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_latency::total 7457781864 # number of overall MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 12214482000 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 12214482000 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1164635000 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1164635000 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 13379117000 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_latency::total 13379117000 # number of overall MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033803 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033803 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.026929 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.026929 # mshr miss rate for WriteReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.063057 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.063057 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.056114 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.056114 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030688 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total 0.030688 # mshr miss rate for demand accesses system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030688 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.030688 # mshr miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12846.369274 # average ReadReq mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12846.369274 # average ReadReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39533.473682 # average WriteReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39533.473682 # average WriteReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7485.702802 # average LoadLockedReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7485.702802 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3892.728095 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3892.728095 # average StoreCondReq mshr miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23458.119408 # average overall mshr miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23458.119408 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23458.119408 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23458.119408 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses system.cpu1.dtb.read_hits 9507781 # DTB read hits system.cpu1.dtb.read_misses 5255 # DTB read misses system.cpu1.dtb.write_hits 6647969 # DTB write hits system.cpu1.dtb.write_misses 1834 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID system.cpu1.dtb.flush_entries 2187 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.dtb.prefetch_faults 188 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 249 # Number of TLB faults due to permissions restrictions system.cpu1.dtb.read_accesses 9513036 # DTB read accesses system.cpu1.dtb.write_accesses 6649803 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses system.cpu1.dtb.hits 16155750 # DTB hits system.cpu1.dtb.misses 7089 # DTB misses system.cpu1.dtb.accesses 16162839 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.itb.inst_hits 38008437 # ITB inst hits system.cpu1.itb.inst_misses 3017 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID system.cpu1.itb.flush_entries 1485 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses system.cpu1.itb.inst_accesses 38011454 # ITB inst accesses system.cpu1.itb.hits 38008437 # DTB hits system.cpu1.itb.misses 3017 # DTB misses system.cpu1.itb.accesses 38011454 # DTB accesses system.cpu1.numCycles 2392450295 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.committedInsts 37097446 # Number of instructions committed system.cpu1.committedOps 46867102 # Number of ops (including micro ops) committed system.cpu1.num_int_alu_accesses 42687988 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 5457 # Number of float alu accesses system.cpu1.num_func_calls 1134316 # number of times a function call or return occured system.cpu1.num_conditional_control_insts 4357000 # number of instructions that are conditional controls system.cpu1.num_int_insts 42687988 # number of integer instructions system.cpu1.num_fp_insts 5457 # number of float instructions system.cpu1.num_int_register_reads 248074220 # number of times the integer registers were read system.cpu1.num_int_register_writes 45509439 # number of times the integer registers were written system.cpu1.num_fp_register_reads 3577 # number of times the floating registers were read system.cpu1.num_fp_register_writes 1884 # number of times the floating registers were written system.cpu1.num_mem_refs 16770062 # number of memory refs system.cpu1.num_load_insts 9887948 # Number of load instructions system.cpu1.num_store_insts 6882114 # Number of store instructions system.cpu1.num_idle_cycles 1855714829.552449 # Number of idle cycles system.cpu1.num_busy_cycles 536735465.447551 # Number of busy cycles system.cpu1.not_idle_fraction 0.224346 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.775654 # Percentage of idle cycles system.cpu1.Branches 5771094 # Number of branches fetched system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 52097 # number of quiesce instructions executed system.cpu1.icache.tags.replacements 540849 # number of replacements system.cpu1.icache.tags.tagsinuse 478.554171 # Cycle average of tags in use system.cpu1.icache.tags.total_refs 37467072 # Total number of references to valid blocks. system.cpu1.icache.tags.sampled_refs 541361 # Sample count of references to valid blocks. system.cpu1.icache.tags.avg_refs 69.209034 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 94011084500 # Cycle when the warmup percentage was hit. system.cpu1.icache.tags.occ_blocks::cpu1.inst 478.554171 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.934676 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.934676 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::1 244 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 203 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu1.icache.tags.tag_accesses 38549794 # Number of tag accesses system.cpu1.icache.tags.data_accesses 38549794 # Number of data accesses system.cpu1.icache.ReadReq_hits::cpu1.inst 37467072 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 37467072 # number of ReadReq hits system.cpu1.icache.demand_hits::cpu1.inst 37467072 # number of demand (read+write) hits system.cpu1.icache.demand_hits::total 37467072 # number of demand (read+write) hits system.cpu1.icache.overall_hits::cpu1.inst 37467072 # number of overall hits system.cpu1.icache.overall_hits::total 37467072 # number of overall hits system.cpu1.icache.ReadReq_misses::cpu1.inst 541361 # number of ReadReq misses system.cpu1.icache.ReadReq_misses::total 541361 # number of ReadReq misses system.cpu1.icache.demand_misses::cpu1.inst 541361 # number of demand (read+write) misses system.cpu1.icache.demand_misses::total 541361 # number of demand (read+write) misses system.cpu1.icache.overall_misses::cpu1.inst 541361 # number of overall misses system.cpu1.icache.overall_misses::total 541361 # number of overall misses system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7383473218 # number of ReadReq miss cycles system.cpu1.icache.ReadReq_miss_latency::total 7383473218 # number of ReadReq miss cycles system.cpu1.icache.demand_miss_latency::cpu1.inst 7383473218 # number of demand (read+write) miss cycles system.cpu1.icache.demand_miss_latency::total 7383473218 # number of demand (read+write) miss cycles system.cpu1.icache.overall_miss_latency::cpu1.inst 7383473218 # number of overall miss cycles system.cpu1.icache.overall_miss_latency::total 7383473218 # number of overall miss cycles system.cpu1.icache.ReadReq_accesses::cpu1.inst 38008433 # number of ReadReq accesses(hits+misses) system.cpu1.icache.ReadReq_accesses::total 38008433 # number of ReadReq accesses(hits+misses) system.cpu1.icache.demand_accesses::cpu1.inst 38008433 # number of demand (read+write) accesses system.cpu1.icache.demand_accesses::total 38008433 # number of demand (read+write) accesses system.cpu1.icache.overall_accesses::cpu1.inst 38008433 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::total 38008433 # number of overall (read+write) accesses system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014243 # miss rate for ReadReq accesses system.cpu1.icache.ReadReq_miss_rate::total 0.014243 # miss rate for ReadReq accesses system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014243 # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::total 0.014243 # miss rate for demand accesses system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014243 # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::total 0.014243 # miss rate for overall accesses system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13638.723916 # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::total 13638.723916 # average ReadReq miss latency system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13638.723916 # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::total 13638.723916 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13638.723916 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::total 13638.723916 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 541361 # number of ReadReq MSHR misses system.cpu1.icache.ReadReq_mshr_misses::total 541361 # number of ReadReq MSHR misses system.cpu1.icache.demand_mshr_misses::cpu1.inst 541361 # number of demand (read+write) MSHR misses system.cpu1.icache.demand_mshr_misses::total 541361 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 541361 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 541361 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6298814782 # number of ReadReq MSHR miss cycles system.cpu1.icache.ReadReq_mshr_miss_latency::total 6298814782 # number of ReadReq MSHR miss cycles system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6298814782 # number of demand (read+write) MSHR miss cycles system.cpu1.icache.demand_mshr_miss_latency::total 6298814782 # number of demand (read+write) MSHR miss cycles system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6298814782 # number of overall MSHR miss cycles system.cpu1.icache.overall_mshr_miss_latency::total 6298814782 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6977250 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6977250 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6977250 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 6977250 # number of overall MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014243 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014243 # mshr miss rate for ReadReq accesses system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014243 # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::total 0.014243 # mshr miss rate for demand accesses system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014243 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::total 0.014243 # mshr miss rate for overall accesses system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11635.146939 # average ReadReq mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11635.146939 # average ReadReq mshr miss latency system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11635.146939 # average overall mshr miss latency system.cpu1.icache.demand_avg_mshr_miss_latency::total 11635.146939 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11635.146939 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_miss_latency::total 11635.146939 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.tags.replacements 343803 # number of replacements system.cpu1.dcache.tags.tagsinuse 472.607785 # Cycle average of tags in use system.cpu1.dcache.tags.total_refs 13921652 # Total number of references to valid blocks. system.cpu1.dcache.tags.sampled_refs 344315 # Sample count of references to valid blocks. system.cpu1.dcache.tags.avg_refs 40.432894 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 85311468250 # Cycle when the warmup percentage was hit. system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.607785 # Average occupied blocks per requestor system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923062 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_percent::total 0.923062 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::1 377 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu1.dcache.tags.tag_accesses 57519242 # Number of tag accesses system.cpu1.dcache.tags.data_accesses 57519242 # Number of data accesses system.cpu1.dcache.ReadReq_hits::cpu1.data 8078143 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 8078143 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 5612875 # number of WriteReq hits system.cpu1.dcache.WriteReq_hits::total 5612875 # number of WriteReq hits system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 100617 # number of LoadLockedReq hits system.cpu1.dcache.LoadLockedReq_hits::total 100617 # number of LoadLockedReq hits system.cpu1.dcache.StoreCondReq_hits::cpu1.data 102310 # number of StoreCondReq hits system.cpu1.dcache.StoreCondReq_hits::total 102310 # number of StoreCondReq hits system.cpu1.dcache.demand_hits::cpu1.data 13691018 # number of demand (read+write) hits system.cpu1.dcache.demand_hits::total 13691018 # number of demand (read+write) hits system.cpu1.dcache.overall_hits::cpu1.data 13691018 # number of overall hits system.cpu1.dcache.overall_hits::total 13691018 # number of overall hits system.cpu1.dcache.ReadReq_misses::cpu1.data 207066 # number of ReadReq misses system.cpu1.dcache.ReadReq_misses::total 207066 # number of ReadReq misses system.cpu1.dcache.WriteReq_misses::cpu1.data 165297 # number of WriteReq misses system.cpu1.dcache.WriteReq_misses::total 165297 # number of WriteReq misses system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11987 # number of LoadLockedReq misses system.cpu1.dcache.LoadLockedReq_misses::total 11987 # number of LoadLockedReq misses system.cpu1.dcache.StoreCondReq_misses::cpu1.data 9884 # number of StoreCondReq misses system.cpu1.dcache.StoreCondReq_misses::total 9884 # number of StoreCondReq misses system.cpu1.dcache.demand_misses::cpu1.data 372363 # number of demand (read+write) misses system.cpu1.dcache.demand_misses::total 372363 # number of demand (read+write) misses system.cpu1.dcache.overall_misses::cpu1.data 372363 # number of overall misses system.cpu1.dcache.overall_misses::total 372363 # number of overall misses system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2696827750 # number of ReadReq miss cycles system.cpu1.dcache.ReadReq_miss_latency::total 2696827750 # number of ReadReq miss cycles system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 6860807042 # number of WriteReq miss cycles system.cpu1.dcache.WriteReq_miss_latency::total 6860807042 # number of WriteReq miss cycles system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 107474000 # number of LoadLockedReq miss cycles system.cpu1.dcache.LoadLockedReq_miss_latency::total 107474000 # number of LoadLockedReq miss cycles system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 50841959 # number of StoreCondReq miss cycles system.cpu1.dcache.StoreCondReq_miss_latency::total 50841959 # number of StoreCondReq miss cycles system.cpu1.dcache.demand_miss_latency::cpu1.data 9557634792 # number of demand (read+write) miss cycles system.cpu1.dcache.demand_miss_latency::total 9557634792 # number of demand (read+write) miss cycles system.cpu1.dcache.overall_miss_latency::cpu1.data 9557634792 # number of overall miss cycles system.cpu1.dcache.overall_miss_latency::total 9557634792 # number of overall miss cycles system.cpu1.dcache.ReadReq_accesses::cpu1.data 8285209 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_accesses::total 8285209 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::cpu1.data 5778172 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::total 5778172 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 112604 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::total 112604 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 112194 # number of StoreCondReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::total 112194 # number of StoreCondReq accesses(hits+misses) system.cpu1.dcache.demand_accesses::cpu1.data 14063381 # number of demand (read+write) accesses system.cpu1.dcache.demand_accesses::total 14063381 # number of demand (read+write) accesses system.cpu1.dcache.overall_accesses::cpu1.data 14063381 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 14063381 # number of overall (read+write) accesses system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.024992 # miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_miss_rate::total 0.024992 # miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.028607 # miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_miss_rate::total 0.028607 # miss rate for WriteReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.106453 # miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.106453 # miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.088097 # miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::total 0.088097 # miss rate for StoreCondReq accesses system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026477 # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::total 0.026477 # miss rate for demand accesses system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026477 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total 0.026477 # miss rate for overall accesses system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13024.000802 # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::total 13024.000802 # average ReadReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41505.938051 # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::total 41505.938051 # average WriteReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8965.879703 # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8965.879703 # average LoadLockedReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5143.864731 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5143.864731 # average StoreCondReq miss latency system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 25667.520113 # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::total 25667.520113 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 25667.520113 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::total 25667.520113 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed system.cpu1.dcache.writebacks::writebacks 315335 # number of writebacks system.cpu1.dcache.writebacks::total 315335 # number of writebacks system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 207066 # number of ReadReq MSHR misses system.cpu1.dcache.ReadReq_mshr_misses::total 207066 # number of ReadReq MSHR misses system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 165297 # number of WriteReq MSHR misses system.cpu1.dcache.WriteReq_mshr_misses::total 165297 # number of WriteReq MSHR misses system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11987 # number of LoadLockedReq MSHR misses system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11987 # number of LoadLockedReq MSHR misses system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9883 # number of StoreCondReq MSHR misses system.cpu1.dcache.StoreCondReq_mshr_misses::total 9883 # number of StoreCondReq MSHR misses system.cpu1.dcache.demand_mshr_misses::cpu1.data 372363 # number of demand (read+write) MSHR misses system.cpu1.dcache.demand_mshr_misses::total 372363 # number of demand (read+write) MSHR misses system.cpu1.dcache.overall_mshr_misses::cpu1.data 372363 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_misses::total 372363 # number of overall MSHR misses system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2282040250 # number of ReadReq MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2282040250 # number of ReadReq MSHR miss cycles system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 6506824958 # number of WriteReq MSHR miss cycles system.cpu1.dcache.WriteReq_mshr_miss_latency::total 6506824958 # number of WriteReq MSHR miss cycles system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 83489000 # number of LoadLockedReq MSHR miss cycles system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 83489000 # number of LoadLockedReq MSHR miss cycles system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31075041 # number of StoreCondReq MSHR miss cycles system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31075041 # number of StoreCondReq MSHR miss cycles system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8788865208 # number of demand (read+write) MSHR miss cycles system.cpu1.dcache.demand_mshr_miss_latency::total 8788865208 # number of demand (read+write) MSHR miss cycles system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8788865208 # number of overall MSHR miss cycles system.cpu1.dcache.overall_mshr_miss_latency::total 8788865208 # number of overall MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169960243250 # number of ReadReq MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169960243250 # number of ReadReq MSHR uncacheable cycles system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25194386277 # number of WriteReq MSHR uncacheable cycles system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25194386277 # number of WriteReq MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 195154629527 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_latency::total 195154629527 # number of overall MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024992 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.024992 # mshr miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028607 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028607 # mshr miss rate for WriteReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.106453 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.106453 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.088088 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.088088 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026477 # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::total 0.026477 # mshr miss rate for demand accesses system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026477 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::total 0.026477 # mshr miss rate for overall accesses system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11020.835144 # average ReadReq mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11020.835144 # average ReadReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 39364.446772 # average WriteReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 39364.446772 # average WriteReq mshr miss latency system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6964.962042 # average LoadLockedReq mshr miss latency system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6964.962042 # average LoadLockedReq mshr miss latency system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3144.292320 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3144.292320 # average StoreCondReq mshr miss latency system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23602.949831 # average overall mshr miss latency system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23602.949831 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23602.949831 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23602.949831 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. system.iocache.tags.avg_refs nan # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.tags.tag_accesses 0 # Number of tag accesses system.iocache.tags.data_accesses 0 # Number of data accesses system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 746722879500 # number of ReadReq MSHR uncacheable cycles system.iocache.ReadReq_mshr_uncacheable_latency::total 746722879500 # number of ReadReq MSHR uncacheable cycles system.iocache.overall_mshr_uncacheable_latency::realview.clcd 746722879500 # number of overall MSHR uncacheable cycles system.iocache.overall_mshr_uncacheable_latency::total 746722879500 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ----------