---------- Begin Simulation Statistics ---------- sim_seconds 0.370011 # Number of seconds simulated sim_ticks 370010840000 # Number of ticks simulated final_tick 370010840000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks host_inst_rate 1163147 # Simulator instruction rate (inst/s) host_tick_rate 1547047043 # Simulator tick rate (ticks/s) host_mem_usage 348152 # Number of bytes of host memory used host_seconds 239.17 # Real time elapsed on the host sim_insts 278192520 # Number of instructions simulated system.physmem.bytes_read 4900800 # Number of bytes read from this memory system.physmem.bytes_inst_read 51712 # Number of instructions bytes read from this memory system.physmem.bytes_written 1885440 # Number of bytes written to this memory system.physmem.num_reads 76575 # Number of read requests responded to by this memory system.physmem.num_writes 29460 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory system.physmem.bw_read 13245017 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read 139758 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write 5095634 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total 18340652 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 444 # Number of system calls system.cpu.numCycles 740021680 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.num_insts 278192520 # Number of instructions executed system.cpu.num_int_alu_accesses 278186228 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured system.cpu.num_conditional_control_insts 18628012 # number of instructions that are conditional controls system.cpu.num_int_insts 278186228 # number of integer instructions system.cpu.num_fp_insts 40 # number of float instructions system.cpu.num_int_register_reads 685043114 # number of times the integer registers were read system.cpu.num_int_register_writes 248344166 # number of times the integer registers were written system.cpu.num_fp_register_reads 40 # number of times the floating registers were read system.cpu.num_fp_register_writes 26 # number of times the floating registers were written system.cpu.num_mem_refs 122219139 # number of memory refs system.cpu.num_load_insts 90779388 # Number of load instructions system.cpu.num_store_insts 31439751 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_busy_cycles 740021680 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 24 # number of replacements system.cpu.icache.tagsinuse 666.191948 # Cycle average of tags in use system.cpu.icache.total_refs 217695401 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 808 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 269425.001238 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.occ_blocks::0 666.191948 # Average occupied blocks per context system.cpu.icache.occ_percent::0 0.325289 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits 217695401 # number of ReadReq hits system.cpu.icache.demand_hits 217695401 # number of demand (read+write) hits system.cpu.icache.overall_hits 217695401 # number of overall hits system.cpu.icache.ReadReq_misses 808 # number of ReadReq misses system.cpu.icache.demand_misses 808 # number of demand (read+write) misses system.cpu.icache.overall_misses 808 # number of overall misses system.cpu.icache.ReadReq_miss_latency 45248000 # number of ReadReq miss cycles system.cpu.icache.demand_miss_latency 45248000 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency 45248000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses 217696209 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses 217696209 # number of demand (read+write) accesses system.cpu.icache.overall_accesses 217696209 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses 808 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses 808 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses 808 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.ReadReq_mshr_miss_latency 42824000 # number of ReadReq MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency 42824000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency 42824000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 2062733 # number of replacements system.cpu.dcache.tagsinuse 4076.661903 # Cycle average of tags in use system.cpu.dcache.total_refs 120152372 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 2066829 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 58.133678 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 126200130000 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::0 4076.661903 # Average occupied blocks per context system.cpu.dcache.occ_percent::0 0.995279 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits 88818730 # number of ReadReq hits system.cpu.dcache.WriteReq_hits 31333642 # number of WriteReq hits system.cpu.dcache.demand_hits 120152372 # number of demand (read+write) hits system.cpu.dcache.overall_hits 120152372 # number of overall hits system.cpu.dcache.ReadReq_misses 1960720 # number of ReadReq misses system.cpu.dcache.WriteReq_misses 106109 # number of WriteReq misses system.cpu.dcache.demand_misses 2066829 # number of demand (read+write) misses system.cpu.dcache.overall_misses 2066829 # number of overall misses system.cpu.dcache.ReadReq_miss_latency 28849058000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency 3268793000 # number of WriteReq miss cycles system.cpu.dcache.demand_miss_latency 32117851000 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency 32117851000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses 90779450 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 31439751 # number of WriteReq accesses(hits+misses) system.cpu.dcache.demand_accesses 122219201 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses 122219201 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate 0.021599 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate 0.003375 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate 0.016911 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate 0.016911 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency 14713.502183 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency 30805.991952 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency 15539.675029 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency 15539.675029 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks 1437080 # number of writebacks system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses 1960720 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses 106109 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses 2066829 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses 2066829 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.ReadReq_mshr_miss_latency 22966898000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency 2950464500 # number of WriteReq MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency 25917362500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency 25917362500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.021599 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.003375 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate 0.016911 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate 0.016911 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11713.502183 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 27805.977815 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 12539.674303 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 12539.674303 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 49212 # number of replacements system.cpu.l2cache.tagsinuse 18614.603260 # Cycle average of tags in use system.cpu.l2cache.total_refs 3296079 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 77127 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 42.735735 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.occ_blocks::0 6551.798271 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 12062.804989 # Average occupied blocks per context system.cpu.l2cache.occ_percent::0 0.199945 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::1 0.368128 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits 1927411 # number of ReadReq hits system.cpu.l2cache.Writeback_hits 1437080 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits 63651 # number of ReadExReq hits system.cpu.l2cache.demand_hits 1991062 # number of demand (read+write) hits system.cpu.l2cache.overall_hits 1991062 # number of overall hits system.cpu.l2cache.ReadReq_misses 34117 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses 42458 # number of ReadExReq misses system.cpu.l2cache.demand_misses 76575 # number of demand (read+write) misses system.cpu.l2cache.overall_misses 76575 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency 1774084000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency 2207845500 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency 3981929500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency 3981929500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses 1961528 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses 1437080 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 106109 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses 2067637 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses 2067637 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate 0.017393 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate 0.400136 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate 0.037035 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate 0.037035 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.694804 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency 52000.385243 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency 52000.385243 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks 29460 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.l2cache.ReadReq_mshr_misses 34117 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses 42458 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses 76575 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses 76575 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.ReadReq_mshr_miss_latency 1364680000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency 1698320000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency 3063000000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency 3063000000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.017393 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.400136 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate 0.037035 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate 0.037035 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ----------