---------- Begin Simulation Statistics ---------- sim_seconds 47.395178 # Number of seconds simulated sim_ticks 47395178174000 # Number of ticks simulated final_tick 47395178174000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks host_inst_rate 85380 # Simulator instruction rate (inst/s) host_op_rate 100389 # Simulator op (including micro ops) rate (op/s) host_tick_rate 4378207332 # Simulator tick rate (ticks/s) host_mem_usage 733200 # Number of bytes of host memory used host_seconds 10825.25 # Real time elapsed on the host sim_insts 924259255 # Number of instructions simulated sim_ops 1086731985 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 173952 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 172224 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.inst 5051936 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 46751112 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.l2cache.prefetcher 21558016 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 154688 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 128576 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 2266144 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 13742800 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.l2cache.prefetcher 14572608 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 453056 # Number of bytes read from this memory system.physmem.bytes_read::total 105025112 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 5051936 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 2266144 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 7318080 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 87763520 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory system.physmem.bytes_written::total 87784104 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 2718 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2691 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.inst 94889 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 730499 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.l2cache.prefetcher 336844 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 2417 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 2009 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 35452 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 214744 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.l2cache.prefetcher 227697 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 7079 # Number of read requests responded to by this memory system.physmem.num_reads::total 1657039 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 1371305 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory system.physmem.num_writes::total 1373879 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 3670 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 3634 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.inst 106592 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.data 986411 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.l2cache.prefetcher 454857 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 3264 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 2713 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.inst 47814 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.data 289962 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.l2cache.prefetcher 307470 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 9559 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 2215945 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu0.inst 106592 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu1.inst 47814 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 154406 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 1851739 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 1852174 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 1851739 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 3670 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 3634 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.inst 106592 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.data 986845 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.l2cache.prefetcher 454857 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 3264 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 2713 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.inst 47814 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.data 289962 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.l2cache.prefetcher 307470 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 9559 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 4068119 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 1657039 # Number of read requests accepted system.physmem.writeReqs 1373879 # Number of write requests accepted system.physmem.readBursts 1657039 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 1373879 # Number of DRAM write bursts, including those merged in the write queue system.physmem.bytesReadDRAM 106020736 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 29760 # Total number of bytes read from write queue system.physmem.bytesWritten 87783296 # Total number of bytes written to DRAM system.physmem.bytesReadSys 105025112 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 87784104 # Total written bytes from the system interface side system.physmem.servicedByWrQ 465 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 224488 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 100246 # Per bank write bursts system.physmem.perBankRdBursts::1 102501 # Per bank write bursts system.physmem.perBankRdBursts::2 99063 # Per bank write bursts system.physmem.perBankRdBursts::3 111016 # Per bank write bursts system.physmem.perBankRdBursts::4 103342 # Per bank write bursts system.physmem.perBankRdBursts::5 111704 # Per bank write bursts system.physmem.perBankRdBursts::6 101938 # Per bank write bursts system.physmem.perBankRdBursts::7 100431 # Per bank write bursts system.physmem.perBankRdBursts::8 95106 # Per bank write bursts system.physmem.perBankRdBursts::9 125245 # Per bank write bursts system.physmem.perBankRdBursts::10 101573 # Per bank write bursts system.physmem.perBankRdBursts::11 106068 # Per bank write bursts system.physmem.perBankRdBursts::12 95582 # Per bank write bursts system.physmem.perBankRdBursts::13 100418 # Per bank write bursts system.physmem.perBankRdBursts::14 101028 # Per bank write bursts system.physmem.perBankRdBursts::15 101313 # Per bank write bursts system.physmem.perBankWrBursts::0 83566 # Per bank write bursts system.physmem.perBankWrBursts::1 87156 # Per bank write bursts system.physmem.perBankWrBursts::2 83944 # Per bank write bursts system.physmem.perBankWrBursts::3 90509 # Per bank write bursts system.physmem.perBankWrBursts::4 85224 # Per bank write bursts system.physmem.perBankWrBursts::5 91500 # Per bank write bursts system.physmem.perBankWrBursts::6 84276 # Per bank write bursts system.physmem.perBankWrBursts::7 85215 # Per bank write bursts system.physmem.perBankWrBursts::8 82233 # Per bank write bursts system.physmem.perBankWrBursts::9 88133 # Per bank write bursts system.physmem.perBankWrBursts::10 85317 # Per bank write bursts system.physmem.perBankWrBursts::11 88722 # Per bank write bursts system.physmem.perBankWrBursts::12 80882 # Per bank write bursts system.physmem.perBankWrBursts::13 85628 # Per bank write bursts system.physmem.perBankWrBursts::14 84824 # Per bank write bursts system.physmem.perBankWrBursts::15 84485 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 14 # Number of times write queue was full causing retry system.physmem.totGap 47395176675500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 21333 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) system.physmem.readPktSize::6 1635681 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 1371305 # Write request sizes (log2) system.physmem.rdQLenPdf::0 618737 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 421038 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 166212 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 166706 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 103650 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 63464 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 34359 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 32178 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 28455 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 8186 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 4495 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 2867 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 1852 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 1478 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 956 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 670 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 561 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 434 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 150 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 106 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 20142 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 22530 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 34959 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 43149 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 52927 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 61801 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 71450 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 78161 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 85169 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 89148 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 92391 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 98600 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 97124 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 100685 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 113079 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 104553 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 98049 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 87257 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 5674 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 3301 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 2066 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 1381 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 974 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 793 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 580 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 491 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 458 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 389 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 368 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 356 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 330 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 291 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 355 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 317 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 381 # What write queue length does an incoming req see system.physmem.wrQLenPdf::50 276 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 259 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 205 # What write queue length does an incoming req see system.physmem.wrQLenPdf::53 248 # What write queue length does an incoming req see system.physmem.wrQLenPdf::54 190 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 159 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 125 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 122 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 65 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 72 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 71 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 71 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 42 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 34 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 1046566 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 185.180531 # Bytes accessed per row activation system.physmem.bytesPerActivate::gmean 114.222366 # Bytes accessed per row activation system.physmem.bytesPerActivate::stdev 242.012748 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 630659 60.26% 60.26% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 204416 19.53% 79.79% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 66292 6.33% 86.13% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 36110 3.45% 89.58% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 25913 2.48% 92.05% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 14303 1.37% 93.42% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 14388 1.37% 94.79% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 7964 0.76% 95.55% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 46521 4.45% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 1046566 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 78027 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::mean 21.230689 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::stdev 247.022438 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-4095 78024 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8192-12287 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::65536-69631 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 78027 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 78027 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::mean 17.578710 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::gmean 17.107570 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::stdev 6.499017 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::16-19 72603 93.05% 93.05% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::20-23 2990 3.83% 96.88% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::24-27 480 0.62% 97.50% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::28-31 334 0.43% 97.92% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::32-35 81 0.10% 98.03% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::36-39 301 0.39% 98.41% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::40-43 173 0.22% 98.64% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::44-47 106 0.14% 98.77% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::48-51 88 0.11% 98.88% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::52-55 126 0.16% 99.05% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::56-59 37 0.05% 99.09% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::60-63 56 0.07% 99.16% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::64-67 406 0.52% 99.68% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::68-71 31 0.04% 99.72% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::72-75 24 0.03% 99.76% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::76-79 123 0.16% 99.91% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::80-83 13 0.02% 99.93% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::84-87 1 0.00% 99.93% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::92-95 4 0.01% 99.94% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::96-99 5 0.01% 99.94% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::100-103 1 0.00% 99.94% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::104-107 2 0.00% 99.95% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::112-115 2 0.00% 99.95% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::124-127 1 0.00% 99.95% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::128-131 17 0.02% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::136-139 1 0.00% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::140-143 5 0.01% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::144-147 2 0.00% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::152-155 6 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::156-159 2 0.00% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::164-167 3 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::168-171 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::236-239 2 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 78027 # Writes before turning the bus around for reads system.physmem.totQLat 82234419314 # Total ticks spent queuing system.physmem.totMemAccLat 113295181814 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 8282870000 # Total ticks spent in databus transfers system.physmem.avgQLat 49641.26 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst system.physmem.avgMemAccLat 68391.26 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.24 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.85 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.22 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 1.85 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.27 # Average read queue length when enqueuing system.physmem.avgWrQLen 24.73 # Average write queue length when enqueuing system.physmem.readRowHits 1332435 # Number of row buffer hits during reads system.physmem.writeRowHits 649185 # Number of row buffer hits during writes system.physmem.readRowHitRate 80.43 # Row buffer hit rate for reads system.physmem.writeRowHitRate 47.33 # Row buffer hit rate for writes system.physmem.avgGap 15637234.88 # Average gap between requests system.physmem.pageHitRate 65.44 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 4004169120 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 2184814500 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 6475833000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 4480207200 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 3095622519600 # Energy for refresh commands per rank (pJ) system.physmem_0.actBackEnergy 1180796903550 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 27401319159750 # Energy for precharge background per rank (pJ) system.physmem_0.totalEnergy 31694883606720 # Total energy per rank (pJ) system.physmem_0.averagePower 668.736482 # Core power per rank (mW) system.physmem_0.memoryStateTime::IDLE 45584100048214 # Time in different power states system.physmem_0.memoryStateTime::REF 1582629100000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_0.memoryStateTime::ACT 228448334286 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 3907869840 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 2132270250 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 6445397400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 4407851520 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 3095622519600 # Energy for refresh commands per rank (pJ) system.physmem_1.actBackEnergy 1181668397355 # Energy for active background per rank (pJ) system.physmem_1.preBackEnergy 27400554691500 # Energy for precharge background per rank (pJ) system.physmem_1.totalEnergy 31694738997465 # Total energy per rank (pJ) system.physmem_1.averagePower 668.733431 # Core power per rank (mW) system.physmem_1.memoryStateTime::IDLE 45582807436264 # Time in different power states system.physmem_1.memoryStateTime::REF 1582629100000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 229740006236 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 572 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 384 # Number of instructions bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu1.inst 144 # Number of instructions bytes read from this memory system.realview.nvmem.bytes_inst_read::total 528 # Number of instructions bytes read from this memory system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu1.inst 9 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 39 # Number of read requests responded to by this memory system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::cpu1.inst 3 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::total 12 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu1.inst 3 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::total 11 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 3 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 12 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1670 # Number of DMA write transactions. system.cpu0.branchPred.lookups 146971248 # Number of BP lookups system.cpu0.branchPred.condPredicted 97492286 # Number of conditional branches predicted system.cpu0.branchPred.condIncorrect 7372479 # Number of conditional branches incorrect system.cpu0.branchPred.BTBLookups 103605243 # Number of BTB lookups system.cpu0.branchPred.BTBHits 68020426 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu0.branchPred.BTBHitPct 65.653459 # BTB Hit Percentage system.cpu0.branchPred.usedRAS 20148210 # Number of times the RAS was used to get a target. system.cpu0.branchPred.RASInCorrect 220615 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.walker.walks 621589 # Table walker walks requested system.cpu0.dtb.walker.walksLong 621589 # Table walker walks initiated with long descriptors system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 13120 # Level at which table walker walks with long descriptors terminate system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 97816 # Level at which table walker walks with long descriptors terminate system.cpu0.dtb.walker.walksSquashedBefore 286624 # Table walks squashed before starting system.cpu0.dtb.walker.walkWaitTime::samples 334965 # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::mean 2330.974878 # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::stdev 14719.833023 # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::0-65535 332297 99.20% 99.20% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::65536-131071 1432 0.43% 99.63% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::131072-196607 943 0.28% 99.91% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::196608-262143 131 0.04% 99.95% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::262144-327679 57 0.02% 99.97% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::327680-393215 84 0.03% 99.99% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::393216-458751 13 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::458752-524287 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::524288-589823 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::720896-786431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::total 334965 # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkCompletionTime::samples 317874 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::mean 20050.667875 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::gmean 16636.288203 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::stdev 22186.320011 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::0-65535 314157 98.83% 98.83% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::65536-131071 825 0.26% 99.09% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::131072-196607 2043 0.64% 99.73% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::196608-262143 147 0.05% 99.78% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::262144-327679 407 0.13% 99.91% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::327680-393215 108 0.03% 99.94% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::393216-458751 100 0.03% 99.97% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::458752-524287 42 0.01% 99.99% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::524288-589823 23 0.01% 99.99% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::589824-655359 13 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::655360-720895 4 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::720896-786431 5 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::total 317874 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walksPending::samples 575732613804 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::mean 0.609948 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::stdev 0.538779 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0-1 574368413804 99.76% 99.76% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::2-3 774580000 0.13% 99.90% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::4-5 276702000 0.05% 99.95% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::6-7 125012500 0.02% 99.97% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::8-9 99386000 0.02% 99.98% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::10-11 49877000 0.01% 99.99% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::12-13 16787500 0.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::14-15 21052000 0.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::16-17 785500 0.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::18-19 17500 0.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 575732613804 # Table walker pending requests distribution system.cpu0.dtb.walker.walkPageSizes::4K 97816 88.17% 88.17% # Table walker page sizes translated system.cpu0.dtb.walker.walkPageSizes::2M 13120 11.83% 100.00% # Table walker page sizes translated system.cpu0.dtb.walker.walkPageSizes::total 110936 # Table walker page sizes translated system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 621589 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 621589 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 110936 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 110936 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin::total 732525 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses system.cpu0.dtb.read_hits 106854280 # DTB read hits system.cpu0.dtb.read_misses 451291 # DTB read misses system.cpu0.dtb.write_hits 87452638 # DTB write hits system.cpu0.dtb.write_misses 170298 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 44894 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 1069 # Number of times TLB was flushed by ASID system.cpu0.dtb.flush_entries 41576 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 658 # Number of TLB faults due to alignment restrictions system.cpu0.dtb.prefetch_faults 7382 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 40291 # Number of TLB faults due to permissions restrictions system.cpu0.dtb.read_accesses 107305571 # DTB read accesses system.cpu0.dtb.write_accesses 87622936 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses system.cpu0.dtb.hits 194306918 # DTB hits system.cpu0.dtb.misses 621589 # DTB misses system.cpu0.dtb.accesses 194928507 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.itb.walker.walks 88821 # Table walker walks requested system.cpu0.itb.walker.walksLong 88821 # Table walker walks initiated with long descriptors system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1050 # Level at which table walker walks with long descriptors terminate system.cpu0.itb.walker.walksLongTerminationLevel::Level3 63713 # Level at which table walker walks with long descriptors terminate system.cpu0.itb.walker.walksSquashedBefore 10161 # Table walks squashed before starting system.cpu0.itb.walker.walkWaitTime::samples 78660 # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::mean 1640.999237 # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::stdev 13001.605750 # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::0-32767 77771 98.87% 98.87% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::32768-65535 446 0.57% 99.44% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::65536-98303 46 0.06% 99.50% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::98304-131071 60 0.08% 99.57% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::131072-163839 236 0.30% 99.87% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::163840-196607 63 0.08% 99.95% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::196608-229375 4 0.01% 99.96% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::229376-262143 4 0.01% 99.96% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::262144-294911 12 0.02% 99.98% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::294912-327679 4 0.01% 99.98% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::327680-360447 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::360448-393215 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::393216-425983 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::458752-491519 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::total 78660 # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkCompletionTime::samples 74924 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::mean 26158.080188 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::gmean 21735.719179 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::stdev 28586.196281 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::0-65535 72785 97.15% 97.15% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::65536-131071 128 0.17% 97.32% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::131072-196607 1706 2.28% 99.59% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::196608-262143 120 0.16% 99.75% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::262144-327679 108 0.14% 99.90% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::327680-393215 38 0.05% 99.95% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::393216-458751 23 0.03% 99.98% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::458752-524287 11 0.01% 99.99% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::524288-589823 5 0.01% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::total 74924 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples 438261516832 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::mean 0.857100 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::stdev 0.350244 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 62664607652 14.30% 14.30% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::1 375564750680 85.69% 99.99% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::2 27774000 0.01% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::3 4139500 0.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::4 188000 0.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::5 57000 0.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 438261516832 # Table walker pending requests distribution system.cpu0.itb.walker.walkPageSizes::4K 63713 98.38% 98.38% # Table walker page sizes translated system.cpu0.itb.walker.walkPageSizes::2M 1050 1.62% 100.00% # Table walker page sizes translated system.cpu0.itb.walker.walkPageSizes::total 64763 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 88821 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Requested::total 88821 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 64763 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::total 64763 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin::total 153584 # Table walker requests started/completed, data/inst system.cpu0.itb.inst_hits 231690538 # ITB inst hits system.cpu0.itb.inst_misses 88821 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 44894 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 1069 # Number of times TLB was flushed by ASID system.cpu0.itb.flush_entries 30101 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 229340 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses system.cpu0.itb.inst_accesses 231779359 # ITB inst accesses system.cpu0.itb.hits 231690538 # DTB hits system.cpu0.itb.misses 88821 # DTB misses system.cpu0.itb.accesses 231779359 # DTB accesses system.cpu0.numCycles 863793222 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.fetch.icacheStallCycles 99193613 # Number of cycles fetch is stalled on an Icache miss system.cpu0.fetch.Insts 650316460 # Number of instructions fetch has processed system.cpu0.fetch.Branches 146971248 # Number of branches that fetch encountered system.cpu0.fetch.predictedBranches 88168636 # Number of branches that fetch has predicted taken system.cpu0.fetch.Cycles 710473999 # Number of cycles fetch has run and was not squashing or blocked system.cpu0.fetch.SquashCycles 15870286 # Number of cycles fetch has spent squashing system.cpu0.fetch.TlbCycles 2085677 # Number of cycles fetch has spent waiting for tlb system.cpu0.fetch.MiscStallCycles 375453 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu0.fetch.PendingTrapStallCycles 6582690 # Number of stall cycles due to pending traps system.cpu0.fetch.PendingQuiesceStallCycles 821108 # Number of stall cycles due to pending quiesce instructions system.cpu0.fetch.IcacheWaitRetryStallCycles 973136 # Number of stall cycles due to full MSHR system.cpu0.fetch.CacheLines 231460528 # Number of cache lines fetched system.cpu0.fetch.IcacheSquashes 1900058 # Number of outstanding Icache misses that were squashed system.cpu0.fetch.ItlbSquashes 29560 # Number of outstanding ITLB misses that were squashed system.cpu0.fetch.rateDist::samples 828440819 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::mean 0.919217 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::stdev 1.204961 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::0 463819781 55.99% 55.99% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::1 141489715 17.08% 73.07% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::2 49366419 5.96% 79.03% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::3 173764904 20.97% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::total 828440819 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.branchRate 0.170146 # Number of branch fetches per cycle system.cpu0.fetch.rate 0.752861 # Number of inst fetches per cycle system.cpu0.decode.IdleCycles 116939951 # Number of cycles decode is idle system.cpu0.decode.BlockedCycles 422028211 # Number of cycles decode is blocked system.cpu0.decode.RunCycles 244586455 # Number of cycles decode is running system.cpu0.decode.UnblockCycles 39268558 # Number of cycles decode is unblocking system.cpu0.decode.SquashCycles 5617644 # Number of cycles decode is squashing system.cpu0.decode.BranchResolved 21189817 # Number of times decode resolved a branch system.cpu0.decode.BranchMispred 2362286 # Number of times decode detected a branch misprediction system.cpu0.decode.DecodedInsts 672848975 # Number of instructions handled by decode system.cpu0.decode.SquashedInsts 25418616 # Number of squashed instructions handled by decode system.cpu0.rename.SquashCycles 5617644 # Number of cycles rename is squashing system.cpu0.rename.IdleCycles 154577177 # Number of cycles rename is idle system.cpu0.rename.BlockCycles 70595603 # Number of cycles rename is blocking system.cpu0.rename.serializeStallCycles 261705373 # count of cycles rename stalled for serializing inst system.cpu0.rename.RunCycles 245642920 # Number of cycles rename is running system.cpu0.rename.UnblockCycles 90302102 # Number of cycles rename is unblocking system.cpu0.rename.RenamedInsts 654266166 # Number of instructions processed by rename system.cpu0.rename.SquashedInsts 6467849 # Number of squashed instructions processed by rename system.cpu0.rename.ROBFullEvents 11101204 # Number of times rename has blocked due to ROB full system.cpu0.rename.IQFullEvents 403453 # Number of times rename has blocked due to IQ full system.cpu0.rename.LQFullEvents 928162 # Number of times rename has blocked due to LQ full system.cpu0.rename.SQFullEvents 53323892 # Number of times rename has blocked due to SQ full system.cpu0.rename.FullRegisterEvents 11721 # Number of times there has been no free registers system.cpu0.rename.RenamedOperands 625141147 # Number of destination operands rename has renamed system.cpu0.rename.RenameLookups 1009026275 # Number of register rename lookups that rename has made system.cpu0.rename.int_rename_lookups 772228505 # Number of integer rename lookups system.cpu0.rename.fp_rename_lookups 892399 # Number of floating rename lookups system.cpu0.rename.CommittedMaps 562735066 # Number of HB maps that are committed system.cpu0.rename.UndoneMaps 62406074 # Number of HB maps that are undone due to squashing system.cpu0.rename.serializingInsts 16247606 # count of serializing insts renamed system.cpu0.rename.tempSerializingInsts 14088158 # count of temporary serializing insts renamed system.cpu0.rename.skidInsts 79534921 # count of insts added to the skid buffer system.cpu0.memDep0.insertedLoads 107241964 # Number of loads inserted to the mem dependence unit. system.cpu0.memDep0.insertedStores 91079408 # Number of stores inserted to the mem dependence unit. system.cpu0.memDep0.conflictingLoads 9519471 # Number of conflicting loads. system.cpu0.memDep0.conflictingStores 8265411 # Number of conflicting stores. system.cpu0.iq.iqInstsAdded 630985849 # Number of instructions added to the IQ (excludes non-spec) system.cpu0.iq.iqNonSpecInstsAdded 16282634 # Number of non-speculative instructions added to the IQ system.cpu0.iq.iqInstsIssued 634912655 # Number of instructions issued system.cpu0.iq.iqSquashedInstsIssued 2916139 # Number of squashed instructions issued system.cpu0.iq.iqSquashedInstsExamined 58420750 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu0.iq.iqSquashedOperandsExamined 38187791 # Number of squashed operands that are examined and possibly removed from graph system.cpu0.iq.iqSquashedNonSpecRemoved 288602 # Number of squashed non-spec instructions that were removed system.cpu0.iq.issued_per_cycle::samples 828440819 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::mean 0.766395 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::stdev 1.051588 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::0 482464203 58.24% 58.24% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::1 143786503 17.36% 75.59% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::2 123657330 14.93% 90.52% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::3 70325398 8.49% 99.01% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::4 8201627 0.99% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::5 5758 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::total 828440819 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IntAlu 65751499 45.58% 45.58% # attempts to use FU when none available system.cpu0.iq.fu_full::IntMult 72629 0.05% 45.63% # attempts to use FU when none available system.cpu0.iq.fu_full::IntDiv 24296 0.02% 45.64% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.64% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.64% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.64% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.64% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.64% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.64% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.64% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.64% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.64% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.64% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.64% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.64% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.64% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.64% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.64% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.64% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.64% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.64% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.64% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.64% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.64% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.64% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatMisc 30 0.00% 45.64% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.64% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.64% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.64% # attempts to use FU when none available system.cpu0.iq.fu_full::MemRead 37784970 26.19% 71.84% # attempts to use FU when none available system.cpu0.iq.fu_full::MemWrite 40630472 28.16% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued system.cpu0.iq.FU_type_0::IntAlu 434162938 68.38% 68.38% # Type of FU issued system.cpu0.iq.FU_type_0::IntMult 1557110 0.25% 68.63% # Type of FU issued system.cpu0.iq.FU_type_0::IntDiv 85116 0.01% 68.64% # Type of FU issued system.cpu0.iq.FU_type_0::FloatAdd 3 0.00% 68.64% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.64% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.64% # Type of FU issued system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.64% # Type of FU issued system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.64% # Type of FU issued system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.64% # Type of FU issued system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.64% # Type of FU issued system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.64% # Type of FU issued system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.64% # Type of FU issued system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.64% # Type of FU issued system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.64% # Type of FU issued system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.64% # Type of FU issued system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.64% # Type of FU issued system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.64% # Type of FU issued system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.64% # Type of FU issued system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.64% # Type of FU issued system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.64% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.64% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.64% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.64% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.64% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.64% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMisc 85507 0.01% 68.65% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.65% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.65% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.65% # Type of FU issued system.cpu0.iq.FU_type_0::MemRead 110176891 17.35% 86.01% # Type of FU issued system.cpu0.iq.FU_type_0::MemWrite 88845090 13.99% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::total 634912655 # Type of FU issued system.cpu0.iq.rate 0.735029 # Inst issue rate system.cpu0.iq.fu_busy_cnt 144263896 # FU busy when requested system.cpu0.iq.fu_busy_rate 0.227218 # FU busy rate (busy events/executed inst) system.cpu0.iq.int_inst_queue_reads 2243978291 # Number of integer instruction queue reads system.cpu0.iq.int_inst_queue_writes 705234549 # Number of integer instruction queue writes system.cpu0.iq.int_inst_queue_wakeup_accesses 616677073 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 1467869 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_writes 599303 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 545442 # Number of floating instruction queue wakeup accesses system.cpu0.iq.int_alu_accesses 778270494 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 906057 # Number of floating point alu accesses system.cpu0.iew.lsq.thread0.forwLoads 2895519 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu0.iew.lsq.thread0.squashedLoads 13298175 # Number of loads squashed system.cpu0.iew.lsq.thread0.ignoredResponses 18246 # Number of memory responses ignored because the instruction is squashed system.cpu0.iew.lsq.thread0.memOrderViolation 145606 # Number of memory ordering violations system.cpu0.iew.lsq.thread0.squashedStores 6202009 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread0.rescheduledLoads 2767326 # Number of loads that were rescheduled system.cpu0.iew.lsq.thread0.cacheBlocked 4824800 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu0.iew.iewSquashCycles 5617644 # Number of cycles IEW is squashing system.cpu0.iew.iewBlockCycles 8735359 # Number of cycles IEW is blocking system.cpu0.iew.iewUnblockCycles 7907130 # Number of cycles IEW is unblocking system.cpu0.iew.iewDispatchedInsts 647396791 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch system.cpu0.iew.iewDispLoadInsts 107241964 # Number of dispatched load instructions system.cpu0.iew.iewDispStoreInsts 91079408 # Number of dispatched store instructions system.cpu0.iew.iewDispNonSpecInsts 13794371 # Number of dispatched non-speculative instructions system.cpu0.iew.iewIQFullEvents 59022 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 7772545 # Number of times the LSQ has become full, causing a stall system.cpu0.iew.memOrderViolationEvents 145606 # Number of memory order violations system.cpu0.iew.predictedTakenIncorrect 2195305 # Number of branches that were predicted taken incorrectly system.cpu0.iew.predictedNotTakenIncorrect 3186569 # Number of branches that were predicted not taken incorrectly system.cpu0.iew.branchMispredicts 5381874 # Number of branch mispredicts detected at execute system.cpu0.iew.iewExecutedInsts 626447733 # Number of executed instructions system.cpu0.iew.iewExecLoadInsts 106847652 # Number of load instructions executed system.cpu0.iew.iewExecSquashedInsts 7850968 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed system.cpu0.iew.exec_nop 128308 # number of nop insts executed system.cpu0.iew.exec_refs 194298385 # number of memory reference insts executed system.cpu0.iew.exec_branches 118240799 # Number of branches executed system.cpu0.iew.exec_stores 87450733 # Number of stores executed system.cpu0.iew.exec_rate 0.725229 # Inst execution rate system.cpu0.iew.wb_sent 618051464 # cumulative count of insts sent to commit system.cpu0.iew.wb_count 617222515 # cumulative count of insts written-back system.cpu0.iew.wb_producers 300479191 # num instructions producing a value system.cpu0.iew.wb_consumers 493067457 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu0.iew.wb_rate 0.714549 # insts written-back per cycle system.cpu0.iew.wb_fanout 0.609408 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu0.commit.commitSquashedInsts 50926327 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 15994032 # The number of times commit has been forced to stall to communicate backwards system.cpu0.commit.branchMispredicts 5054980 # The number of times a branch was mispredicted system.cpu0.commit.committed_per_cycle::samples 818740070 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::mean 0.719212 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::stdev 1.525829 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::0 561213375 68.55% 68.55% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::1 132109065 16.14% 84.68% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::2 58113446 7.10% 91.78% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::3 19548895 2.39% 94.17% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::4 13854430 1.69% 95.86% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::5 9447713 1.15% 97.01% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::6 6268110 0.77% 97.78% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::7 3880157 0.47% 98.25% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::8 14304879 1.75% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::total 818740070 # Number of insts commited each cycle system.cpu0.commit.committedInsts 501771314 # Number of instructions committed system.cpu0.commit.committedOps 588847718 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed system.cpu0.commit.refs 178821180 # Number of memory references committed system.cpu0.commit.loads 93943789 # Number of loads committed system.cpu0.commit.membars 3938709 # Number of memory barriers committed system.cpu0.commit.branches 112215548 # Number of branches committed system.cpu0.commit.fp_insts 531565 # Number of committed floating point instructions. system.cpu0.commit.int_insts 540152053 # Number of committed integer instructions. system.cpu0.commit.function_calls 14962116 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu0.commit.op_class_0::IntAlu 408576800 69.39% 69.39% # Class of committed instruction system.cpu0.commit.op_class_0::IntMult 1307130 0.22% 69.61% # Class of committed instruction system.cpu0.commit.op_class_0::IntDiv 67517 0.01% 69.62% # Class of committed instruction system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.62% # Class of committed instruction system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.62% # Class of committed instruction system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.62% # Class of committed instruction system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.62% # Class of committed instruction system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.62% # Class of committed instruction system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.62% # Class of committed instruction system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.62% # Class of committed instruction system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.62% # Class of committed instruction system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.62% # Class of committed instruction system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.62% # Class of committed instruction system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.62% # Class of committed instruction system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.62% # Class of committed instruction system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.62% # Class of committed instruction system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.62% # Class of committed instruction system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.62% # Class of committed instruction system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.62% # Class of committed instruction system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.62% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.62% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.62% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.62% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.62% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.62% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatMisc 75091 0.01% 69.63% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.63% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.63% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.63% # Class of committed instruction system.cpu0.commit.op_class_0::MemRead 93943789 15.95% 85.59% # Class of committed instruction system.cpu0.commit.op_class_0::MemWrite 84877391 14.41% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::total 588847718 # Class of committed instruction system.cpu0.commit.bw_lim_events 14304879 # number cycles where commit BW limit reached system.cpu0.rob.rob_reads 1439565573 # The number of ROB reads system.cpu0.rob.rob_writes 1289210941 # The number of ROB writes system.cpu0.timesIdled 1140163 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu0.idleCycles 35352403 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu0.quiesceCycles 93926563172 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu0.committedInsts 501771314 # Number of Instructions Simulated system.cpu0.committedOps 588847718 # Number of Ops (including micro ops) Simulated system.cpu0.cpi 1.721488 # CPI: Cycles Per Instruction system.cpu0.cpi_total 1.721488 # CPI: Total CPI of All Threads system.cpu0.ipc 0.580893 # IPC: Instructions Per Cycle system.cpu0.ipc_total 0.580893 # IPC: Total IPC of All Threads system.cpu0.int_regfile_reads 739095549 # number of integer regfile reads system.cpu0.int_regfile_writes 439787902 # number of integer regfile writes system.cpu0.fp_regfile_reads 872002 # number of floating regfile reads system.cpu0.fp_regfile_writes 484356 # number of floating regfile writes system.cpu0.cc_regfile_reads 137161341 # number of cc regfile reads system.cpu0.cc_regfile_writes 137881500 # number of cc regfile writes system.cpu0.misc_regfile_reads 1443535644 # number of misc regfile reads system.cpu0.misc_regfile_writes 16079939 # number of misc regfile writes system.cpu0.dcache.tags.replacements 6407370 # number of replacements system.cpu0.dcache.tags.tagsinuse 508.018138 # Cycle average of tags in use system.cpu0.dcache.tags.total_refs 166146345 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 6407881 # Sample count of references to valid blocks. system.cpu0.dcache.tags.avg_refs 25.928438 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 2962355000 # Cycle when the warmup percentage was hit. system.cpu0.dcache.tags.occ_blocks::cpu0.data 508.018138 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.992223 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.992223 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 248 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 223 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 40 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id system.cpu0.dcache.tags.tag_accesses 371124901 # Number of tag accesses system.cpu0.dcache.tags.data_accesses 371124901 # Number of data accesses system.cpu0.dcache.ReadReq_hits::cpu0.data 87218466 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 87218466 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 73809320 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::total 73809320 # number of WriteReq hits system.cpu0.dcache.SoftPFReq_hits::cpu0.data 228978 # number of SoftPFReq hits system.cpu0.dcache.SoftPFReq_hits::total 228978 # number of SoftPFReq hits system.cpu0.dcache.WriteLineReq_hits::cpu0.data 263867 # number of WriteLineReq hits system.cpu0.dcache.WriteLineReq_hits::total 263867 # number of WriteLineReq hits system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1900288 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 1900288 # number of LoadLockedReq hits system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1938762 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 1938762 # number of StoreCondReq hits system.cpu0.dcache.demand_hits::cpu0.data 161027786 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::total 161027786 # number of demand (read+write) hits system.cpu0.dcache.overall_hits::cpu0.data 161256764 # number of overall hits system.cpu0.dcache.overall_hits::total 161256764 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.data 7088028 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 7088028 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::cpu0.data 7798635 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::total 7798635 # number of WriteReq misses system.cpu0.dcache.SoftPFReq_misses::cpu0.data 740346 # number of SoftPFReq misses system.cpu0.dcache.SoftPFReq_misses::total 740346 # number of SoftPFReq misses system.cpu0.dcache.WriteLineReq_misses::cpu0.data 850980 # number of WriteLineReq misses system.cpu0.dcache.WriteLineReq_misses::total 850980 # number of WriteLineReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 273336 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 273336 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu0.data 194663 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 194663 # number of StoreCondReq misses system.cpu0.dcache.demand_misses::cpu0.data 14886663 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::total 14886663 # number of demand (read+write) misses system.cpu0.dcache.overall_misses::cpu0.data 15627009 # number of overall misses system.cpu0.dcache.overall_misses::total 15627009 # number of overall misses system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 124519522000 # number of ReadReq miss cycles system.cpu0.dcache.ReadReq_miss_latency::total 124519522000 # number of ReadReq miss cycles system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 171455239141 # number of WriteReq miss cycles system.cpu0.dcache.WriteReq_miss_latency::total 171455239141 # number of WriteReq miss cycles system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 101116390498 # number of WriteLineReq miss cycles system.cpu0.dcache.WriteLineReq_miss_latency::total 101116390498 # number of WriteLineReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4428125500 # number of LoadLockedReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::total 4428125500 # number of LoadLockedReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4749567500 # number of StoreCondReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::total 4749567500 # number of StoreCondReq miss cycles system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 4799500 # number of StoreCondFailReq miss cycles system.cpu0.dcache.StoreCondFailReq_miss_latency::total 4799500 # number of StoreCondFailReq miss cycles system.cpu0.dcache.demand_miss_latency::cpu0.data 295974761141 # number of demand (read+write) miss cycles system.cpu0.dcache.demand_miss_latency::total 295974761141 # number of demand (read+write) miss cycles system.cpu0.dcache.overall_miss_latency::cpu0.data 295974761141 # number of overall miss cycles system.cpu0.dcache.overall_miss_latency::total 295974761141 # number of overall miss cycles system.cpu0.dcache.ReadReq_accesses::cpu0.data 94306494 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 94306494 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 81607955 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::total 81607955 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 969324 # number of SoftPFReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::total 969324 # number of SoftPFReq accesses(hits+misses) system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1114847 # number of WriteLineReq accesses(hits+misses) system.cpu0.dcache.WriteLineReq_accesses::total 1114847 # number of WriteLineReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2173624 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 2173624 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2133425 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 2133425 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.demand_accesses::cpu0.data 175914449 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::total 175914449 # number of demand (read+write) accesses system.cpu0.dcache.overall_accesses::cpu0.data 176883773 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 176883773 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.075159 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.075159 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.095562 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::total 0.095562 # miss rate for WriteReq accesses system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.763776 # miss rate for SoftPFReq accesses system.cpu0.dcache.SoftPFReq_miss_rate::total 0.763776 # miss rate for SoftPFReq accesses system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.763316 # miss rate for WriteLineReq accesses system.cpu0.dcache.WriteLineReq_miss_rate::total 0.763316 # miss rate for WriteLineReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.125751 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.125751 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.091244 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.091244 # miss rate for StoreCondReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.084624 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total 0.084624 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.088346 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total 0.088346 # miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17567.583254 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::total 17567.583254 # average ReadReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 21985.288341 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::total 21985.288341 # average WriteReq miss latency system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 118823.462946 # average WriteLineReq miss latency system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 118823.462946 # average WriteLineReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16200.301095 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16200.301095 # average LoadLockedReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24398.922754 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24398.922754 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19881.874208 # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::total 19881.874208 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18939.949490 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::total 18939.949490 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 31639371 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 26128725 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 779388 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 763893 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs 40.595148 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets 34.204692 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 4315919 # number of writebacks system.cpu0.dcache.writebacks::total 4315919 # number of writebacks system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3584647 # number of ReadReq MSHR hits system.cpu0.dcache.ReadReq_mshr_hits::total 3584647 # number of ReadReq MSHR hits system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6264689 # number of WriteReq MSHR hits system.cpu0.dcache.WriteReq_mshr_hits::total 6264689 # number of WriteReq MSHR hits system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4628 # number of WriteLineReq MSHR hits system.cpu0.dcache.WriteLineReq_mshr_hits::total 4628 # number of WriteLineReq MSHR hits system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 139100 # number of LoadLockedReq MSHR hits system.cpu0.dcache.LoadLockedReq_mshr_hits::total 139100 # number of LoadLockedReq MSHR hits system.cpu0.dcache.demand_mshr_hits::cpu0.data 9849336 # number of demand (read+write) MSHR hits system.cpu0.dcache.demand_mshr_hits::total 9849336 # number of demand (read+write) MSHR hits system.cpu0.dcache.overall_mshr_hits::cpu0.data 9849336 # number of overall MSHR hits system.cpu0.dcache.overall_mshr_hits::total 9849336 # number of overall MSHR hits system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3503381 # number of ReadReq MSHR misses system.cpu0.dcache.ReadReq_mshr_misses::total 3503381 # number of ReadReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1533946 # number of WriteReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::total 1533946 # number of WriteReq MSHR misses system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 733362 # number of SoftPFReq MSHR misses system.cpu0.dcache.SoftPFReq_mshr_misses::total 733362 # number of SoftPFReq MSHR misses system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 846352 # number of WriteLineReq MSHR misses system.cpu0.dcache.WriteLineReq_mshr_misses::total 846352 # number of WriteLineReq MSHR misses system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 134236 # number of LoadLockedReq MSHR misses system.cpu0.dcache.LoadLockedReq_mshr_misses::total 134236 # number of LoadLockedReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 194661 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::total 194661 # number of StoreCondReq MSHR misses system.cpu0.dcache.demand_mshr_misses::cpu0.data 5037327 # number of demand (read+write) MSHR misses system.cpu0.dcache.demand_mshr_misses::total 5037327 # number of demand (read+write) MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu0.data 5770689 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 5770689 # number of overall MSHR misses system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 33238 # number of ReadReq MSHR uncacheable system.cpu0.dcache.ReadReq_mshr_uncacheable::total 33238 # number of ReadReq MSHR uncacheable system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 33405 # number of WriteReq MSHR uncacheable system.cpu0.dcache.WriteReq_mshr_uncacheable::total 33405 # number of WriteReq MSHR uncacheable system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 66643 # number of overall MSHR uncacheable misses system.cpu0.dcache.overall_mshr_uncacheable_misses::total 66643 # number of overall MSHR uncacheable misses system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 56780867000 # number of ReadReq MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_latency::total 56780867000 # number of ReadReq MSHR miss cycles system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 38418617555 # number of WriteReq MSHR miss cycles system.cpu0.dcache.WriteReq_mshr_miss_latency::total 38418617555 # number of WriteReq MSHR miss cycles system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 19943250500 # number of SoftPFReq MSHR miss cycles system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 19943250500 # number of SoftPFReq MSHR miss cycles system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 100022529998 # number of WriteLineReq MSHR miss cycles system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 100022529998 # number of WriteLineReq MSHR miss cycles system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1962249500 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1962249500 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4554969500 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4554969500 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 4736500 # number of StoreCondFailReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 4736500 # number of StoreCondFailReq MSHR miss cycles system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 95199484555 # number of demand (read+write) MSHR miss cycles system.cpu0.dcache.demand_mshr_miss_latency::total 95199484555 # number of demand (read+write) MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 115142735055 # number of overall MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_latency::total 115142735055 # number of overall MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5997592500 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5997592500 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5944742000 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5944742000 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11942334500 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11942334500 # number of overall MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.037149 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037149 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018797 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018797 # mshr miss rate for WriteReq accesses system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.756571 # mshr miss rate for SoftPFReq accesses system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.756571 # mshr miss rate for SoftPFReq accesses system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.759164 # mshr miss rate for WriteLineReq accesses system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.759164 # mshr miss rate for WriteLineReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.061757 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.061757 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.091243 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.091243 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028635 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total 0.028635 # mshr miss rate for demand accesses system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032624 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.032624 # mshr miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 16207.448462 # average ReadReq mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 16207.448462 # average ReadReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 25045.612789 # average WriteReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25045.612789 # average WriteReq mshr miss latency system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 27194.278542 # average SoftPFReq mshr miss latency system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 27194.278542 # average SoftPFReq mshr miss latency system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 118180.768756 # average WriteLineReq mshr miss latency system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 118180.768756 # average WriteLineReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14617.908013 # average LoadLockedReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14617.908013 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23399.497074 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23399.497074 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18898.809737 # average overall mshr miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18898.809737 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19953.030748 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19953.030748 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 180443.844395 # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 180443.844395 # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 177959.646759 # average WriteReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 177959.646759 # average WriteReq mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 179198.633015 # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 179198.633015 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 6757482 # number of replacements system.cpu0.icache.tags.tagsinuse 511.935144 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 224272608 # Total number of references to valid blocks. system.cpu0.icache.tags.sampled_refs 6757994 # Sample count of references to valid blocks. system.cpu0.icache.tags.avg_refs 33.186269 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 22852216000 # Cycle when the warmup percentage was hit. system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.935144 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999873 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999873 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 82 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu0.icache.tags.tag_accesses 469620349 # Number of tag accesses system.cpu0.icache.tags.data_accesses 469620349 # Number of data accesses system.cpu0.icache.ReadReq_hits::cpu0.inst 224272608 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 224272608 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 224272608 # number of demand (read+write) hits system.cpu0.icache.demand_hits::total 224272608 # number of demand (read+write) hits system.cpu0.icache.overall_hits::cpu0.inst 224272608 # number of overall hits system.cpu0.icache.overall_hits::total 224272608 # number of overall hits system.cpu0.icache.ReadReq_misses::cpu0.inst 7158551 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 7158551 # number of ReadReq misses system.cpu0.icache.demand_misses::cpu0.inst 7158551 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 7158551 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 7158551 # number of overall misses system.cpu0.icache.overall_misses::total 7158551 # number of overall misses system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 82703845756 # number of ReadReq miss cycles system.cpu0.icache.ReadReq_miss_latency::total 82703845756 # number of ReadReq miss cycles system.cpu0.icache.demand_miss_latency::cpu0.inst 82703845756 # number of demand (read+write) miss cycles system.cpu0.icache.demand_miss_latency::total 82703845756 # number of demand (read+write) miss cycles system.cpu0.icache.overall_miss_latency::cpu0.inst 82703845756 # number of overall miss cycles system.cpu0.icache.overall_miss_latency::total 82703845756 # number of overall miss cycles system.cpu0.icache.ReadReq_accesses::cpu0.inst 231431159 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::total 231431159 # number of ReadReq accesses(hits+misses) system.cpu0.icache.demand_accesses::cpu0.inst 231431159 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::total 231431159 # number of demand (read+write) accesses system.cpu0.icache.overall_accesses::cpu0.inst 231431159 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::total 231431159 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.030932 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::total 0.030932 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.030932 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total 0.030932 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.030932 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.030932 # miss rate for overall accesses system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11553.154508 # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::total 11553.154508 # average ReadReq miss latency system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11553.154508 # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::total 11553.154508 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11553.154508 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::total 11553.154508 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 13180342 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 1608 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 863819 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 14 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.258222 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets 114.857143 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 400520 # number of ReadReq MSHR hits system.cpu0.icache.ReadReq_mshr_hits::total 400520 # number of ReadReq MSHR hits system.cpu0.icache.demand_mshr_hits::cpu0.inst 400520 # number of demand (read+write) MSHR hits system.cpu0.icache.demand_mshr_hits::total 400520 # number of demand (read+write) MSHR hits system.cpu0.icache.overall_mshr_hits::cpu0.inst 400520 # number of overall MSHR hits system.cpu0.icache.overall_mshr_hits::total 400520 # number of overall MSHR hits system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6758031 # number of ReadReq MSHR misses system.cpu0.icache.ReadReq_mshr_misses::total 6758031 # number of ReadReq MSHR misses system.cpu0.icache.demand_mshr_misses::cpu0.inst 6758031 # number of demand (read+write) MSHR misses system.cpu0.icache.demand_mshr_misses::total 6758031 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 6758031 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 6758031 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 21294 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 21294 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 21294 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 21294 # number of overall MSHR uncacheable misses system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 74295068991 # number of ReadReq MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_latency::total 74295068991 # number of ReadReq MSHR miss cycles system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 74295068991 # number of demand (read+write) MSHR miss cycles system.cpu0.icache.demand_mshr_miss_latency::total 74295068991 # number of demand (read+write) MSHR miss cycles system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 74295068991 # number of overall MSHR miss cycles system.cpu0.icache.overall_mshr_miss_latency::total 74295068991 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 2939725498 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 2939725498 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 2939725498 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 2939725498 # number of overall MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.029201 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.029201 # mshr miss rate for ReadReq accesses system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.029201 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total 0.029201 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.029201 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.029201 # mshr miss rate for overall accesses system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10993.596950 # average ReadReq mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10993.596950 # average ReadReq mshr miss latency system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10993.596950 # average overall mshr miss latency system.cpu0.icache.demand_avg_mshr_miss_latency::total 10993.596950 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10993.596950 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::total 10993.596950 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138054.170095 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138054.170095 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138054.170095 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138054.170095 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.l2cache.prefetcher.num_hwpf_issued 8609545 # number of hwpf issued system.cpu0.l2cache.prefetcher.pfIdentified 8618519 # number of prefetch candidates identified system.cpu0.l2cache.prefetcher.pfBufferHit 8045 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu0.l2cache.prefetcher.pfSpanPage 1094401 # number of prefetches not generated due to page crossing system.cpu0.l2cache.tags.replacements 2903307 # number of replacements system.cpu0.l2cache.tags.tagsinuse 16246.409963 # Cycle average of tags in use system.cpu0.l2cache.tags.total_refs 22353900 # Total number of references to valid blocks. system.cpu0.l2cache.tags.sampled_refs 2918996 # Sample count of references to valid blocks. system.cpu0.l2cache.tags.avg_refs 7.658078 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 21271828500 # Cycle when the warmup percentage was hit. system.cpu0.l2cache.tags.occ_blocks::writebacks 7113.964436 # Average occupied blocks per requestor system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 80.712375 # Average occupied blocks per requestor system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 97.665127 # Average occupied blocks per requestor system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4225.088231 # Average occupied blocks per requestor system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3888.580421 # Average occupied blocks per requestor system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 840.399372 # Average occupied blocks per requestor system.cpu0.l2cache.tags.occ_percent::writebacks 0.434202 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.004926 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.005961 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.257879 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.237340 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.051294 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::total 0.991602 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1391 # Occupied blocks per task id system.cpu0.l2cache.tags.occ_task_id_blocks::1023 88 # Occupied blocks per task id system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14210 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 4 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 134 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 197 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 595 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 461 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 5 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 66 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 7 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 745 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4851 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4773 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3664 # Occupied blocks per task id system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.084900 # Percentage of cache occupancy per task id system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005371 # Percentage of cache occupancy per task id system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.867310 # Percentage of cache occupancy per task id system.cpu0.l2cache.tags.tag_accesses 448966117 # Number of tag accesses system.cpu0.l2cache.tags.data_accesses 448966117 # Number of data accesses system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 605202 # number of ReadReq hits system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 189837 # number of ReadReq hits system.cpu0.l2cache.ReadReq_hits::total 795039 # number of ReadReq hits system.cpu0.l2cache.Writeback_hits::writebacks 4315912 # number of Writeback hits system.cpu0.l2cache.Writeback_hits::total 4315912 # number of Writeback hits system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 110882 # number of UpgradeReq hits system.cpu0.l2cache.UpgradeReq_hits::total 110882 # number of UpgradeReq hits system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 36120 # number of SCUpgradeReq hits system.cpu0.l2cache.SCUpgradeReq_hits::total 36120 # number of SCUpgradeReq hits system.cpu0.l2cache.ReadExReq_hits::cpu0.data 962986 # number of ReadExReq hits system.cpu0.l2cache.ReadExReq_hits::total 962986 # number of ReadExReq hits system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 6062865 # number of ReadCleanReq hits system.cpu0.l2cache.ReadCleanReq_hits::total 6062865 # number of ReadCleanReq hits system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 3276140 # number of ReadSharedReq hits system.cpu0.l2cache.ReadSharedReq_hits::total 3276140 # number of ReadSharedReq hits system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 213470 # number of InvalidateReq hits system.cpu0.l2cache.InvalidateReq_hits::total 213470 # number of InvalidateReq hits system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 605202 # number of demand (read+write) hits system.cpu0.l2cache.demand_hits::cpu0.itb.walker 189837 # number of demand (read+write) hits system.cpu0.l2cache.demand_hits::cpu0.inst 6062865 # number of demand (read+write) hits system.cpu0.l2cache.demand_hits::cpu0.data 4239126 # number of demand (read+write) hits system.cpu0.l2cache.demand_hits::total 11097030 # number of demand (read+write) hits system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 605202 # number of overall hits system.cpu0.l2cache.overall_hits::cpu0.itb.walker 189837 # number of overall hits system.cpu0.l2cache.overall_hits::cpu0.inst 6062865 # number of overall hits system.cpu0.l2cache.overall_hits::cpu0.data 4239126 # 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number of SCUpgradeReq miss cycles system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3851336998 # number of SCUpgradeReq miss cycles system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 4641499 # number of SCUpgradeFailReq miss cycles system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 4641499 # number of SCUpgradeFailReq miss cycles system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 22977113499 # number of ReadExReq miss cycles system.cpu0.l2cache.ReadExReq_miss_latency::total 22977113499 # number of ReadExReq miss cycles system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 27999451498 # number of ReadCleanReq miss cycles system.cpu0.l2cache.ReadCleanReq_miss_latency::total 27999451498 # number of ReadCleanReq miss cycles system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 50408930969 # number of ReadSharedReq miss cycles system.cpu0.l2cache.ReadSharedReq_miss_latency::total 50408930969 # number of ReadSharedReq miss cycles system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 96428495994 # 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number of overall miss cycles system.cpu0.l2cache.overall_miss_latency::total 102652233466 # number of overall miss cycles system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 618985 # number of ReadReq accesses(hits+misses) system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 200087 # number of ReadReq accesses(hits+misses) system.cpu0.l2cache.ReadReq_accesses::total 819072 # number of ReadReq accesses(hits+misses) system.cpu0.l2cache.Writeback_accesses::writebacks 4315913 # number of Writeback accesses(hits+misses) system.cpu0.l2cache.Writeback_accesses::total 4315913 # number of Writeback accesses(hits+misses) system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 244508 # number of UpgradeReq accesses(hits+misses) system.cpu0.l2cache.UpgradeReq_accesses::total 244508 # number of UpgradeReq accesses(hits+misses) system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 194651 # number of SCUpgradeReq accesses(hits+misses) system.cpu0.l2cache.SCUpgradeReq_accesses::total 194651 # number of SCUpgradeReq accesses(hits+misses) system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 10 # number of SCUpgradeFailReq accesses(hits+misses) system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 10 # number of SCUpgradeFailReq accesses(hits+misses) system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1299948 # number of ReadExReq accesses(hits+misses) system.cpu0.l2cache.ReadExReq_accesses::total 1299948 # number of ReadExReq accesses(hits+misses) system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 6758000 # number of ReadCleanReq accesses(hits+misses) system.cpu0.l2cache.ReadCleanReq_accesses::total 6758000 # number of ReadCleanReq accesses(hits+misses) system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4368659 # number of ReadSharedReq accesses(hits+misses) system.cpu0.l2cache.ReadSharedReq_accesses::total 4368659 # number of ReadSharedReq accesses(hits+misses) system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 844897 # number of InvalidateReq accesses(hits+misses) system.cpu0.l2cache.InvalidateReq_accesses::total 844897 # number of InvalidateReq accesses(hits+misses) system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 618985 # 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miss rate for ReadExReq accesses system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.102861 # miss rate for ReadCleanReq accesses system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.102861 # miss rate for ReadCleanReq accesses system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.250081 # miss rate for ReadSharedReq accesses system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.250081 # miss rate for ReadSharedReq accesses system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.747342 # miss rate for InvalidateReq accesses system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.747342 # miss rate for InvalidateReq accesses system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.022267 # miss rate for demand accesses system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.051228 # miss rate for demand accesses system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.102861 # miss rate for demand accesses system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.252175 # miss rate for demand accesses system.cpu0.l2cache.demand_miss_rate::total 0.162215 # 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number of demand (read+write) MSHR misses system.cpu0.l2cache.demand_mshr_misses::total 2073081 # number of demand (read+write) MSHR misses system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 13777 # number of overall MSHR misses system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 10085 # number of overall MSHR misses system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 695131 # number of overall MSHR misses system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1354088 # number of overall MSHR misses system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 832278 # number of overall MSHR misses system.cpu0.l2cache.overall_mshr_misses::total 2905359 # number of overall MSHR misses system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 21294 # number of ReadReq MSHR uncacheable system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 33238 # number of ReadReq MSHR uncacheable system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 54532 # number of ReadReq MSHR uncacheable system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 33405 # number of WriteReq MSHR uncacheable system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 33405 # number of WriteReq MSHR uncacheable system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 21294 # number of overall MSHR uncacheable misses system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 66643 # number of overall MSHR uncacheable misses system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 87937 # number of overall MSHR uncacheable misses system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 597098000 # number of ReadReq MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 519597500 # number of ReadReq MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 1116695500 # number of ReadReq MSHR miss cycles system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 67202265861 # number of HardPFReq MSHR miss cycles system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 67202265861 # number of HardPFReq MSHR miss cycles system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 4741207495 # number of UpgradeReq MSHR miss cycles system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 4741207495 # number of UpgradeReq MSHR miss cycles system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3076689494 # number of SCUpgradeReq MSHR miss cycles system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3076689494 # number of SCUpgradeReq MSHR miss cycles system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 4263499 # number of SCUpgradeFailReq MSHR miss cycles system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 4263499 # number of SCUpgradeFailReq MSHR miss cycles system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 17260521499 # number of ReadExReq MSHR miss cycles system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 17260521499 # number of ReadExReq MSHR miss cycles system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 23828492498 # number of ReadCleanReq MSHR miss cycles system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 23828492498 # number of ReadCleanReq MSHR miss cycles system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 43284601971 # number of ReadSharedReq MSHR miss cycles system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 43284601971 # number of ReadSharedReq MSHR miss cycles system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 92639933994 # number of InvalidateReq MSHR miss cycles system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 92639933994 # number of InvalidateReq MSHR miss cycles system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 597098000 # number of demand (read+write) MSHR miss cycles system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 519597500 # number of demand (read+write) MSHR miss cycles system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 23828492498 # number of demand (read+write) MSHR miss cycles system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 60545123470 # number of demand (read+write) MSHR miss cycles system.cpu0.l2cache.demand_mshr_miss_latency::total 85490311468 # number of demand (read+write) MSHR miss cycles system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 597098000 # number of overall MSHR miss cycles system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 519597500 # number of overall MSHR miss cycles system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 23828492498 # number of overall MSHR miss cycles system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 60545123470 # number of overall MSHR miss cycles system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 67202265861 # number of overall MSHR miss cycles system.cpu0.l2cache.overall_mshr_miss_latency::total 152692577329 # number of overall MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 2780019500 # number of ReadReq MSHR uncacheable cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5731623000 # number of ReadReq MSHR uncacheable cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 8511642500 # number of ReadReq MSHR uncacheable cycles system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5688753467 # number of WriteReq MSHR uncacheable cycles system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5688753467 # number of WriteReq MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 2780019500 # number of overall MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11420376467 # number of overall MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 14200395967 # number of overall MSHR uncacheable cycles system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.022257 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.050403 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.029133 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for Writeback accesses system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000000 # mshr miss rate for Writeback accesses system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.546510 # mshr miss rate for UpgradeReq accesses system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.546510 # mshr miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.814437 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.814437 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.207605 # mshr miss rate for ReadExReq accesses system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.207605 # mshr miss rate for ReadExReq accesses system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.102860 # mshr miss rate for ReadCleanReq accesses system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.102860 # mshr miss rate for ReadCleanReq accesses system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.248180 # mshr miss rate for ReadSharedReq accesses system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248180 # mshr miss rate for ReadSharedReq accesses system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.747342 # mshr miss rate for InvalidateReq accesses system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.747342 # mshr miss rate for InvalidateReq accesses system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.022257 # mshr miss rate for demand accesses system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.050403 # mshr miss rate for demand accesses system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.102860 # mshr miss rate for demand accesses system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.238875 # mshr miss rate for demand accesses system.cpu0.l2cache.demand_mshr_miss_rate::total 0.156510 # mshr miss rate for demand accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.022257 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.050403 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.102860 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.238875 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::total 0.219344 # mshr miss rate for overall accesses system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 43340.204689 # average ReadReq mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 51521.814576 # average ReadReq mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 46798.068058 # average ReadReq mshr miss latency system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 80744.974469 # average HardPFReq mshr miss latency system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 80744.974469 # average HardPFReq mshr miss latency system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 35481.175033 # average UpgradeReq mshr miss latency system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 35481.175033 # average UpgradeReq mshr miss latency system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19407.494395 # average SCUpgradeReq mshr miss latency system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19407.494395 # average SCUpgradeReq mshr miss latency system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 426349.900000 # average SCUpgradeFailReq mshr miss latency system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 426349.900000 # average SCUpgradeFailReq mshr miss latency system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 63957.230354 # average ReadExReq mshr miss latency system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 63957.230354 # average ReadExReq mshr miss latency system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 34279.139469 # average ReadCleanReq mshr miss latency system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 34279.139469 # average ReadCleanReq mshr miss latency system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 39922.636875 # average ReadSharedReq mshr miss latency system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 39922.636875 # average ReadSharedReq mshr miss latency system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 146715.192721 # average InvalidateReq mshr miss latency system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 146715.192721 # average InvalidateReq mshr miss latency system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 43340.204689 # average overall mshr miss latency system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 51521.814576 # average overall mshr miss latency system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 34279.139469 # average overall mshr miss latency system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 44712.842496 # average overall mshr miss latency system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 41238.288069 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 43340.204689 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 51521.814576 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 34279.139469 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 44712.842496 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 80744.974469 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 52555.493944 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130554.123227 # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 172441.873759 # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 156085.280202 # average ReadReq mshr uncacheable latency system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 170296.466607 # average WriteReq mshr uncacheable latency system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 170296.466607 # average WriteReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130554.123227 # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 171366.482106 # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 161483.743669 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.toL2Bus.snoop_filter.tot_requests 27252548 # Total number of requests made to the snoop filter. system.cpu0.toL2Bus.snoop_filter.hit_single_requests 13981170 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2244 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu0.toL2Bus.snoop_filter.tot_snoops 570842 # Total number of snoops made to the snoop filter. system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 570828 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 14 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu0.toL2Bus.trans_dist::ReadReq 1016473 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadResp 12252394 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteReq 33406 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteResp 33405 # Transaction distribution system.cpu0.toL2Bus.trans_dist::Writeback 5923375 # Transaction distribution system.cpu0.toL2Bus.trans_dist::CleanEvict 10861944 # Transaction distribution system.cpu0.toL2Bus.trans_dist::HardPFReq 1063583 # Transaction distribution system.cpu0.toL2Bus.trans_dist::HardPFResp 5 # Transaction distribution system.cpu0.toL2Bus.trans_dist::UpgradeReq 463812 # Transaction distribution system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 352945 # Transaction distribution system.cpu0.toL2Bus.trans_dist::UpgradeResp 515465 # Transaction distribution system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 72 # Transaction distribution system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 125 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadExReq 1384026 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadExResp 1310731 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadCleanReq 6758031 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5399513 # Transaction distribution system.cpu0.toL2Bus.trans_dist::InvalidateReq 852147 # Transaction distribution system.cpu0.toL2Bus.trans_dist::InvalidateResp 844897 # Transaction distribution system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 20314687 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 20641650 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 432749 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1348262 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count::total 42737348 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 432852704 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 646893668 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1600696 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4951880 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size::total 1086298948 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.snoops 6525445 # Total snoops (count) system.cpu0.toL2Bus.snoop_fanout::samples 34111599 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::mean 0.027918 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::stdev 0.164740 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 33159285 97.21% 97.21% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 952300 2.79% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 14 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::total 34111599 # Request fanout histogram system.cpu0.toL2Bus.reqLayer0.occupancy 18295414402 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.cpu0.toL2Bus.snoopLayer0.occupancy 218599021 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) system.cpu0.toL2Bus.respLayer0.occupancy 10163463729 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu0.toL2Bus.respLayer1.occupancy 9200637125 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.toL2Bus.respLayer2.occupancy 233049222 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu0.toL2Bus.respLayer3.occupancy 729789968 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu1.branchPred.lookups 123149965 # Number of BP lookups system.cpu1.branchPred.condPredicted 82495484 # Number of conditional branches predicted system.cpu1.branchPred.condIncorrect 5956200 # Number of conditional branches incorrect system.cpu1.branchPred.BTBLookups 86779618 # Number of BTB lookups system.cpu1.branchPred.BTBHits 56690061 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu1.branchPred.BTBHitPct 65.326470 # BTB Hit Percentage system.cpu1.branchPred.usedRAS 16440472 # Number of times the RAS was used to get a target. system.cpu1.branchPred.RASInCorrect 156518 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.walker.walks 527411 # Table walker walks requested system.cpu1.dtb.walker.walksLong 527411 # Table walker walks initiated with long descriptors system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10595 # Level at which table walker walks with long descriptors terminate system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 86487 # Level at which table walker walks with long descriptors terminate system.cpu1.dtb.walker.walksSquashedBefore 240409 # Table walks squashed before starting system.cpu1.dtb.walker.walkWaitTime::samples 287002 # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::mean 2359.187392 # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::stdev 14719.861354 # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::0-65535 284807 99.24% 99.24% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::65536-131071 1123 0.39% 99.63% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::131072-196607 785 0.27% 99.90% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::196608-262143 158 0.06% 99.96% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::262144-327679 41 0.01% 99.97% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::327680-393215 63 0.02% 99.99% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::393216-458751 20 0.01% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::458752-524287 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::total 287002 # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkCompletionTime::samples 269681 # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::mean 19234.134032 # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::gmean 15959.440473 # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::stdev 20416.372217 # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::0-65535 266977 99.00% 99.00% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::65536-131071 731 0.27% 99.27% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::131072-196607 1349 0.50% 99.77% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::196608-262143 143 0.05% 99.82% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::262144-327679 295 0.11% 99.93% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::327680-393215 58 0.02% 99.95% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::393216-458751 94 0.03% 99.99% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::458752-524287 19 0.01% 99.99% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::589824-655359 6 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::786432-851967 2 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::851968-917503 2 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::total 269681 # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walksPending::samples 429707115240 # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::mean 0.574612 # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::stdev 0.551988 # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::0-1 428613446240 99.75% 99.75% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::2-3 584261000 0.14% 99.88% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::4-5 233148000 0.05% 99.94% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::6-7 115723000 0.03% 99.96% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::8-9 78401000 0.02% 99.98% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::10-11 45162000 0.01% 99.99% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::12-13 15712000 0.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::14-15 20912500 0.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::16-17 347500 0.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::18-19 2000 0.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::total 429707115240 # Table walker pending requests distribution system.cpu1.dtb.walker.walkPageSizes::4K 86487 89.09% 89.09% # Table walker page sizes translated system.cpu1.dtb.walker.walkPageSizes::2M 10595 10.91% 100.00% # Table walker page sizes translated system.cpu1.dtb.walker.walkPageSizes::total 97082 # Table walker page sizes translated system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 527411 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 527411 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 97082 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 97082 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin::total 624493 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses system.cpu1.dtb.read_hits 91393564 # DTB read hits system.cpu1.dtb.read_misses 362569 # DTB read misses system.cpu1.dtb.write_hits 75279430 # DTB write hits system.cpu1.dtb.write_misses 164842 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 44894 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 1069 # Number of times TLB was flushed by ASID system.cpu1.dtb.flush_entries 36642 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 200 # Number of TLB faults due to alignment restrictions system.cpu1.dtb.prefetch_faults 5827 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 40054 # Number of TLB faults due to permissions restrictions system.cpu1.dtb.read_accesses 91756133 # DTB read accesses system.cpu1.dtb.write_accesses 75444272 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses system.cpu1.dtb.hits 166672994 # DTB hits system.cpu1.dtb.misses 527411 # DTB misses system.cpu1.dtb.accesses 167200405 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.itb.walker.walks 82282 # Table walker walks requested system.cpu1.itb.walker.walksLong 82282 # Table walker walks initiated with long descriptors system.cpu1.itb.walker.walksLongTerminationLevel::Level2 773 # Level at which table walker walks with long descriptors terminate system.cpu1.itb.walker.walksLongTerminationLevel::Level3 59282 # Level at which table walker walks with long descriptors terminate system.cpu1.itb.walker.walksSquashedBefore 9946 # Table walks squashed before starting system.cpu1.itb.walker.walkWaitTime::samples 72336 # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::mean 1446.824541 # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::stdev 11538.500060 # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::0-65535 71995 99.53% 99.53% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::65536-131071 83 0.11% 99.64% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::131072-196607 237 0.33% 99.97% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::196608-262143 12 0.02% 99.99% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::262144-327679 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::327680-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::393216-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::458752-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::total 72336 # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkCompletionTime::samples 70001 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::mean 24228.861016 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::gmean 20738.037138 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::stdev 24674.307569 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::0-65535 68717 98.17% 98.17% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::65536-131071 87 0.12% 98.29% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::131072-196607 984 1.41% 99.70% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::196608-262143 73 0.10% 99.80% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::262144-327679 83 0.12% 99.92% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::327680-393215 23 0.03% 99.95% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::393216-458751 22 0.03% 99.98% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::458752-524287 4 0.01% 99.99% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::524288-589823 2 0.00% 99.99% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::589824-655359 4 0.01% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::917504-983039 1 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::total 70001 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walksPending::samples 391052327076 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::mean 0.846616 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::stdev 0.360520 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 60001678208 15.34% 15.34% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::1 331032470368 84.65% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::2 15971500 0.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::3 2073000 0.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::4 134000 0.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total 391052327076 # Table walker pending requests distribution system.cpu1.itb.walker.walkPageSizes::4K 59282 98.71% 98.71% # Table walker page sizes translated system.cpu1.itb.walker.walkPageSizes::2M 773 1.29% 100.00% # Table walker page sizes translated system.cpu1.itb.walker.walkPageSizes::total 60055 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 82282 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Requested::total 82282 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 60055 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::total 60055 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin::total 142337 # Table walker requests started/completed, data/inst system.cpu1.itb.inst_hits 193960223 # ITB inst hits system.cpu1.itb.inst_misses 82282 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 44894 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 1069 # Number of times TLB was flushed by ASID system.cpu1.itb.flush_entries 26113 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 206259 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses system.cpu1.itb.inst_accesses 194042505 # ITB inst accesses system.cpu1.itb.hits 193960223 # DTB hits system.cpu1.itb.misses 82282 # DTB misses system.cpu1.itb.accesses 194042505 # DTB accesses system.cpu1.numCycles 680051209 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.fetch.icacheStallCycles 76309039 # Number of cycles fetch is stalled on an Icache miss system.cpu1.fetch.Insts 545586843 # Number of instructions fetch has processed system.cpu1.fetch.Branches 123149965 # Number of branches that fetch encountered system.cpu1.fetch.predictedBranches 73130533 # Number of branches that fetch has predicted taken system.cpu1.fetch.Cycles 567094976 # Number of cycles fetch has run and was not squashing or blocked system.cpu1.fetch.SquashCycles 12846360 # Number of cycles fetch has spent squashing system.cpu1.fetch.TlbCycles 1862646 # Number of cycles fetch has spent waiting for tlb system.cpu1.fetch.MiscStallCycles 285569 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu1.fetch.PendingTrapStallCycles 6032568 # Number of stall cycles due to pending traps system.cpu1.fetch.PendingQuiesceStallCycles 729307 # Number of stall cycles due to pending quiesce instructions system.cpu1.fetch.IcacheWaitRetryStallCycles 772817 # Number of stall cycles due to full MSHR system.cpu1.fetch.CacheLines 193732934 # Number of cache lines fetched system.cpu1.fetch.IcacheSquashes 1488213 # Number of outstanding Icache misses that were squashed system.cpu1.fetch.ItlbSquashes 27982 # Number of outstanding ITLB misses that were squashed system.cpu1.fetch.rateDist::samples 659510102 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::mean 0.972600 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::stdev 1.218843 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::0 352323655 53.42% 53.42% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::1 119769188 18.16% 71.58% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::2 40581175 6.15% 77.74% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::3 146836084 22.26% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::total 659510102 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.branchRate 0.181089 # Number of branch fetches per cycle system.cpu1.fetch.rate 0.802273 # Number of inst fetches per cycle system.cpu1.decode.IdleCycles 93216709 # Number of cycles decode is idle system.cpu1.decode.BlockedCycles 325116567 # Number of cycles decode is blocked system.cpu1.decode.RunCycles 201438015 # Number of cycles decode is running system.cpu1.decode.UnblockCycles 35171632 # Number of cycles decode is unblocking system.cpu1.decode.SquashCycles 4567179 # Number of cycles decode is squashing system.cpu1.decode.BranchResolved 17405067 # Number of times decode resolved a branch system.cpu1.decode.BranchMispred 1892222 # Number of times decode detected a branch misprediction system.cpu1.decode.DecodedInsts 567399835 # Number of instructions handled by decode system.cpu1.decode.SquashedInsts 20537774 # Number of squashed instructions handled by decode system.cpu1.rename.SquashCycles 4567179 # Number of cycles rename is squashing system.cpu1.rename.IdleCycles 125466899 # Number of cycles rename is idle system.cpu1.rename.BlockCycles 47033211 # Number of cycles rename is blocking system.cpu1.rename.serializeStallCycles 215743407 # count of cycles rename stalled for serializing inst system.cpu1.rename.RunCycles 203915656 # Number of cycles rename is running system.cpu1.rename.UnblockCycles 62783750 # Number of cycles rename is unblocking system.cpu1.rename.RenamedInsts 552356795 # Number of instructions processed by rename system.cpu1.rename.SquashedInsts 5241539 # Number of squashed instructions processed by rename system.cpu1.rename.ROBFullEvents 9909237 # Number of times rename has blocked due to ROB full system.cpu1.rename.IQFullEvents 240791 # Number of times rename has blocked due to IQ full system.cpu1.rename.LQFullEvents 292344 # Number of times rename has blocked due to LQ full system.cpu1.rename.SQFullEvents 29944703 # Number of times rename has blocked due to SQ full system.cpu1.rename.FullRegisterEvents 11393 # Number of times there has been no free registers system.cpu1.rename.RenamedOperands 524936389 # Number of destination operands rename has renamed system.cpu1.rename.RenameLookups 854810992 # Number of register rename lookups that rename has made system.cpu1.rename.int_rename_lookups 653637843 # Number of integer rename lookups system.cpu1.rename.fp_rename_lookups 615050 # Number of floating rename lookups system.cpu1.rename.CommittedMaps 473696954 # Number of HB maps that are committed system.cpu1.rename.UndoneMaps 51239429 # Number of HB maps that are undone due to squashing system.cpu1.rename.serializingInsts 15119385 # count of serializing insts renamed system.cpu1.rename.tempSerializingInsts 13351935 # count of temporary serializing insts renamed system.cpu1.rename.skidInsts 70628253 # count of insts added to the skid buffer system.cpu1.memDep0.insertedLoads 91219643 # Number of loads inserted to the mem dependence unit. system.cpu1.memDep0.insertedStores 78311402 # Number of stores inserted to the mem dependence unit. system.cpu1.memDep0.conflictingLoads 8799360 # Number of conflicting loads. system.cpu1.memDep0.conflictingStores 7480777 # Number of conflicting stores. system.cpu1.iq.iqInstsAdded 531265202 # Number of instructions added to the IQ (excludes non-spec) system.cpu1.iq.iqNonSpecInstsAdded 15384643 # Number of non-speculative instructions added to the IQ system.cpu1.iq.iqInstsIssued 536975559 # Number of instructions issued system.cpu1.iq.iqSquashedInstsIssued 2409415 # Number of squashed instructions issued system.cpu1.iq.iqSquashedInstsExamined 48765571 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu1.iq.iqSquashedOperandsExamined 31310459 # Number of squashed operands that are examined and possibly removed from graph system.cpu1.iq.iqSquashedNonSpecRemoved 261406 # Number of squashed non-spec instructions that were removed system.cpu1.iq.issued_per_cycle::samples 659510102 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::mean 0.814204 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::stdev 1.064087 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::0 364889522 55.33% 55.33% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::1 126119203 19.12% 74.45% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::2 101926801 15.45% 89.91% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::3 59299384 8.99% 98.90% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::4 7271358 1.10% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::5 3834 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::total 659510102 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IntAlu 53688772 43.65% 43.65% # attempts to use FU when none available system.cpu1.iq.fu_full::IntMult 42849 0.03% 43.69% # attempts to use FU when none available system.cpu1.iq.fu_full::IntDiv 9758 0.01% 43.69% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatAdd 0 0.00% 43.69% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatCmp 0 0.00% 43.69% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatCvt 0 0.00% 43.69% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatMult 0 0.00% 43.69% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatDiv 0 0.00% 43.69% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 43.69% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdAdd 0 0.00% 43.69% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 43.69% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdAlu 0 0.00% 43.69% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdCmp 0 0.00% 43.69% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdCvt 0 0.00% 43.69% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdMisc 0 0.00% 43.69% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdMult 0 0.00% 43.69% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 43.69% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdShift 0 0.00% 43.69% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 43.69% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 43.69% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 43.69% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 43.69% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 43.69% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 43.69% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 43.69% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMisc 12 0.00% 43.69% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 43.69% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.69% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 43.69% # attempts to use FU when none available system.cpu1.iq.fu_full::MemRead 33350405 27.12% 70.81% # attempts to use FU when none available system.cpu1.iq.fu_full::MemWrite 35903096 29.19% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 84 0.00% 0.00% # Type of FU issued system.cpu1.iq.FU_type_0::IntAlu 365127801 68.00% 68.00% # Type of FU issued system.cpu1.iq.FU_type_0::IntMult 1207443 0.22% 68.22% # Type of FU issued system.cpu1.iq.FU_type_0::IntDiv 64356 0.01% 68.23% # Type of FU issued system.cpu1.iq.FU_type_0::FloatAdd 5 0.00% 68.23% # Type of FU issued system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.23% # Type of FU issued system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.23% # Type of FU issued system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.23% # Type of FU issued system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.23% # Type of FU issued system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.23% # Type of FU issued system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.23% # Type of FU issued system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.23% # Type of FU issued system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.23% # Type of FU issued system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.23% # Type of FU issued system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.23% # Type of FU issued system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.23% # Type of FU issued system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.23% # Type of FU issued system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.23% # Type of FU issued system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.23% # Type of FU issued system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.23% # Type of FU issued system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.23% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.23% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.23% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.23% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatCvt 24 0.00% 68.23% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.23% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMisc 40592 0.01% 68.24% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.24% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.24% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.24% # Type of FU issued system.cpu1.iq.FU_type_0::MemRead 94109837 17.53% 85.77% # Type of FU issued system.cpu1.iq.FU_type_0::MemWrite 76425394 14.23% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::total 536975559 # Type of FU issued system.cpu1.iq.rate 0.789610 # Inst issue rate system.cpu1.iq.fu_busy_cnt 122994892 # FU busy when requested system.cpu1.iq.fu_busy_rate 0.229051 # FU busy rate (busy events/executed inst) system.cpu1.iq.int_inst_queue_reads 1857852304 # Number of integer instruction queue reads system.cpu1.iq.int_inst_queue_writes 595160433 # Number of integer instruction queue writes system.cpu1.iq.int_inst_queue_wakeup_accesses 521544916 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 1013221 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_writes 400944 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 372548 # Number of floating instruction queue wakeup accesses system.cpu1.iq.int_alu_accesses 659338375 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 631992 # Number of floating point alu accesses system.cpu1.iew.lsq.thread0.forwLoads 2462766 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu1.iew.lsq.thread0.squashedLoads 11273364 # Number of loads squashed system.cpu1.iew.lsq.thread0.ignoredResponses 14330 # Number of memory responses ignored because the instruction is squashed system.cpu1.iew.lsq.thread0.memOrderViolation 146929 # Number of memory ordering violations system.cpu1.iew.lsq.thread0.squashedStores 5363484 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread0.rescheduledLoads 2532880 # Number of loads that were rescheduled system.cpu1.iew.lsq.thread0.cacheBlocked 4046276 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu1.iew.iewSquashCycles 4567179 # Number of cycles IEW is squashing system.cpu1.iew.iewBlockCycles 5912411 # Number of cycles IEW is blocking system.cpu1.iew.iewUnblockCycles 2185508 # Number of cycles IEW is unblocking system.cpu1.iew.iewDispatchedInsts 546765447 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch system.cpu1.iew.iewDispLoadInsts 91219643 # Number of dispatched load instructions system.cpu1.iew.iewDispStoreInsts 78311402 # Number of dispatched store instructions system.cpu1.iew.iewDispNonSpecInsts 13149679 # Number of dispatched non-speculative instructions system.cpu1.iew.iewIQFullEvents 62909 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewLSQFullEvents 2062449 # Number of times the LSQ has become full, causing a stall system.cpu1.iew.memOrderViolationEvents 146929 # Number of memory order violations system.cpu1.iew.predictedTakenIncorrect 1850208 # Number of branches that were predicted taken incorrectly system.cpu1.iew.predictedNotTakenIncorrect 2506307 # Number of branches that were predicted not taken incorrectly system.cpu1.iew.branchMispredicts 4356515 # Number of branch mispredicts detected at execute system.cpu1.iew.iewExecutedInsts 530131647 # Number of executed instructions system.cpu1.iew.iewExecLoadInsts 91388835 # Number of load instructions executed system.cpu1.iew.iewExecSquashedInsts 6328626 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed system.cpu1.iew.exec_nop 115602 # number of nop insts executed system.cpu1.iew.exec_refs 166669354 # number of memory reference insts executed system.cpu1.iew.exec_branches 99325061 # Number of branches executed system.cpu1.iew.exec_stores 75280519 # Number of stores executed system.cpu1.iew.exec_rate 0.779547 # Inst execution rate system.cpu1.iew.wb_sent 522591798 # cumulative count of insts sent to commit system.cpu1.iew.wb_count 521917464 # cumulative count of insts written-back system.cpu1.iew.wb_producers 252132377 # num instructions producing a value system.cpu1.iew.wb_consumers 413034686 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu1.iew.wb_rate 0.767468 # insts written-back per cycle system.cpu1.iew.wb_fanout 0.610439 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu1.commit.commitSquashedInsts 42738935 # The number of squashed insts skipped by commit system.cpu1.commit.commitNonSpecStalls 15123237 # The number of times commit has been forced to stall to communicate backwards system.cpu1.commit.branchMispredicts 4100199 # The number of times a branch was mispredicted system.cpu1.commit.committed_per_cycle::samples 651431241 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::mean 0.764293 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::stdev 1.565341 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::0 432003686 66.32% 66.32% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::1 115523895 17.73% 84.05% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::2 47761812 7.33% 91.38% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::3 15857432 2.43% 93.82% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::4 11422302 1.75% 95.57% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::5 7738049 1.19% 96.76% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::6 5451213 0.84% 97.59% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::7 3205095 0.49% 98.09% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::8 12467757 1.91% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::total 651431241 # Number of insts commited each cycle system.cpu1.commit.committedInsts 422487941 # Number of instructions committed system.cpu1.commit.committedOps 497884267 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed system.cpu1.commit.refs 152894196 # Number of memory references committed system.cpu1.commit.loads 79946278 # Number of loads committed system.cpu1.commit.membars 3616952 # Number of memory barriers committed system.cpu1.commit.branches 94285217 # Number of branches committed system.cpu1.commit.fp_insts 364520 # Number of committed floating point instructions. system.cpu1.commit.int_insts 457066504 # Number of committed integer instructions. system.cpu1.commit.function_calls 12254498 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu1.commit.op_class_0::IntAlu 343931170 69.08% 69.08% # Class of committed instruction system.cpu1.commit.op_class_0::IntMult 972359 0.20% 69.27% # Class of committed instruction system.cpu1.commit.op_class_0::IntDiv 50623 0.01% 69.28% # Class of committed instruction system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.28% # Class of committed instruction system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.28% # Class of committed instruction system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.28% # Class of committed instruction system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.28% # Class of committed instruction system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.28% # Class of committed instruction system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.28% # Class of committed instruction system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.28% # Class of committed instruction system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.28% # Class of committed instruction system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.28% # Class of committed instruction system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.28% # Class of committed instruction system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.28% # Class of committed instruction system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.28% # Class of committed instruction system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.28% # Class of committed instruction system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.28% # Class of committed instruction system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.28% # Class of committed instruction system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.28% # Class of committed instruction system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.28% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.28% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.28% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.28% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.28% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.28% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatMisc 35877 0.01% 69.29% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.29% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.29% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.29% # Class of committed instruction system.cpu1.commit.op_class_0::MemRead 79946278 16.06% 85.35% # Class of committed instruction system.cpu1.commit.op_class_0::MemWrite 72947918 14.65% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::total 497884267 # Class of committed instruction system.cpu1.commit.bw_lim_events 12467757 # number cycles where commit BW limit reached system.cpu1.rob.rob_reads 1176002301 # The number of ROB reads system.cpu1.rob.rob_writes 1089287670 # The number of ROB writes system.cpu1.timesIdled 891748 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu1.idleCycles 20541107 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu1.quiesceCycles 94110305176 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu1.committedInsts 422487941 # Number of Instructions Simulated system.cpu1.committedOps 497884267 # Number of Ops (including micro ops) Simulated system.cpu1.cpi 1.609635 # CPI: Cycles Per Instruction system.cpu1.cpi_total 1.609635 # CPI: Total CPI of All Threads system.cpu1.ipc 0.621259 # IPC: Instructions Per Cycle system.cpu1.ipc_total 0.621259 # IPC: Total IPC of All Threads system.cpu1.int_regfile_reads 627139214 # number of integer regfile reads system.cpu1.int_regfile_writes 370414988 # number of integer regfile writes system.cpu1.fp_regfile_reads 604419 # number of floating regfile reads system.cpu1.fp_regfile_writes 299356 # number of floating regfile writes system.cpu1.cc_regfile_reads 113711382 # number of cc regfile reads system.cpu1.cc_regfile_writes 114470989 # number of cc regfile writes system.cpu1.misc_regfile_reads 1170516156 # number of misc regfile reads system.cpu1.misc_regfile_writes 15242864 # number of misc regfile writes system.cpu1.dcache.tags.replacements 5157965 # number of replacements system.cpu1.dcache.tags.tagsinuse 429.133488 # Cycle average of tags in use system.cpu1.dcache.tags.total_refs 142089244 # Total number of references to valid blocks. system.cpu1.dcache.tags.sampled_refs 5158477 # Sample count of references to valid blocks. system.cpu1.dcache.tags.avg_refs 27.544805 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 8487531137500 # Cycle when the warmup percentage was hit. system.cpu1.dcache.tags.occ_blocks::cpu1.data 429.133488 # Average occupied blocks per requestor system.cpu1.dcache.tags.occ_percent::cpu1.data 0.838151 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_percent::total 0.838151 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::1 378 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu1.dcache.tags.tag_accesses 317144363 # Number of tag accesses system.cpu1.dcache.tags.data_accesses 317144363 # Number of data accesses system.cpu1.dcache.ReadReq_hits::cpu1.data 74103111 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 74103111 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 63551574 # number of WriteReq hits system.cpu1.dcache.WriteReq_hits::total 63551574 # number of WriteReq hits system.cpu1.dcache.SoftPFReq_hits::cpu1.data 164336 # number of SoftPFReq hits system.cpu1.dcache.SoftPFReq_hits::total 164336 # number of SoftPFReq hits system.cpu1.dcache.WriteLineReq_hits::cpu1.data 50299 # number of WriteLineReq hits system.cpu1.dcache.WriteLineReq_hits::total 50299 # number of WriteLineReq hits system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1740316 # number of LoadLockedReq hits system.cpu1.dcache.LoadLockedReq_hits::total 1740316 # number of LoadLockedReq hits system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1762571 # number of StoreCondReq hits system.cpu1.dcache.StoreCondReq_hits::total 1762571 # number of StoreCondReq hits system.cpu1.dcache.demand_hits::cpu1.data 137654685 # number of demand (read+write) hits system.cpu1.dcache.demand_hits::total 137654685 # number of demand (read+write) hits system.cpu1.dcache.overall_hits::cpu1.data 137819021 # number of overall hits system.cpu1.dcache.overall_hits::total 137819021 # number of overall hits system.cpu1.dcache.ReadReq_misses::cpu1.data 6065944 # number of ReadReq misses system.cpu1.dcache.ReadReq_misses::total 6065944 # number of ReadReq misses system.cpu1.dcache.WriteReq_misses::cpu1.data 6987777 # number of WriteReq misses system.cpu1.dcache.WriteReq_misses::total 6987777 # number of WriteReq misses system.cpu1.dcache.SoftPFReq_misses::cpu1.data 664365 # number of SoftPFReq misses system.cpu1.dcache.SoftPFReq_misses::total 664365 # number of SoftPFReq misses system.cpu1.dcache.WriteLineReq_misses::cpu1.data 405961 # number of WriteLineReq misses system.cpu1.dcache.WriteLineReq_misses::total 405961 # number of WriteLineReq misses system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 258244 # number of LoadLockedReq misses system.cpu1.dcache.LoadLockedReq_misses::total 258244 # number of LoadLockedReq misses system.cpu1.dcache.StoreCondReq_misses::cpu1.data 193910 # number of StoreCondReq misses system.cpu1.dcache.StoreCondReq_misses::total 193910 # number of StoreCondReq misses system.cpu1.dcache.demand_misses::cpu1.data 13053721 # number of demand (read+write) misses system.cpu1.dcache.demand_misses::total 13053721 # number of demand (read+write) misses system.cpu1.dcache.overall_misses::cpu1.data 13718086 # number of overall misses system.cpu1.dcache.overall_misses::total 13718086 # number of overall misses system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 97739183000 # number of ReadReq miss cycles system.cpu1.dcache.ReadReq_miss_latency::total 97739183000 # number of ReadReq miss cycles system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 145756860728 # number of WriteReq miss cycles system.cpu1.dcache.WriteReq_miss_latency::total 145756860728 # number of WriteReq miss cycles system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 16103531712 # number of WriteLineReq miss cycles system.cpu1.dcache.WriteLineReq_miss_latency::total 16103531712 # number of WriteLineReq miss cycles system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 4003848500 # number of LoadLockedReq miss cycles system.cpu1.dcache.LoadLockedReq_miss_latency::total 4003848500 # number of LoadLockedReq miss cycles system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4624613000 # number of StoreCondReq miss cycles system.cpu1.dcache.StoreCondReq_miss_latency::total 4624613000 # number of StoreCondReq miss cycles system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 5341000 # number of StoreCondFailReq miss cycles system.cpu1.dcache.StoreCondFailReq_miss_latency::total 5341000 # number of StoreCondFailReq miss cycles system.cpu1.dcache.demand_miss_latency::cpu1.data 243496043728 # number of demand (read+write) miss cycles system.cpu1.dcache.demand_miss_latency::total 243496043728 # number of demand (read+write) miss cycles system.cpu1.dcache.overall_miss_latency::cpu1.data 243496043728 # number of overall miss cycles system.cpu1.dcache.overall_miss_latency::total 243496043728 # number of overall miss cycles system.cpu1.dcache.ReadReq_accesses::cpu1.data 80169055 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_accesses::total 80169055 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::cpu1.data 70539351 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::total 70539351 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 828701 # number of SoftPFReq accesses(hits+misses) system.cpu1.dcache.SoftPFReq_accesses::total 828701 # number of SoftPFReq accesses(hits+misses) system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 456260 # number of WriteLineReq accesses(hits+misses) system.cpu1.dcache.WriteLineReq_accesses::total 456260 # number of WriteLineReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1998560 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::total 1998560 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1956481 # number of StoreCondReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::total 1956481 # number of StoreCondReq accesses(hits+misses) system.cpu1.dcache.demand_accesses::cpu1.data 150708406 # number of demand (read+write) accesses system.cpu1.dcache.demand_accesses::total 150708406 # number of demand (read+write) accesses system.cpu1.dcache.overall_accesses::cpu1.data 151537107 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 151537107 # number of overall (read+write) accesses system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.075664 # miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_miss_rate::total 0.075664 # miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.099062 # miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_miss_rate::total 0.099062 # miss rate for WriteReq accesses system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.801694 # miss rate for SoftPFReq accesses system.cpu1.dcache.SoftPFReq_miss_rate::total 0.801694 # miss rate for SoftPFReq accesses system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.889758 # miss rate for WriteLineReq accesses system.cpu1.dcache.WriteLineReq_miss_rate::total 0.889758 # miss rate for WriteLineReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.129215 # miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.129215 # miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.099112 # miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::total 0.099112 # miss rate for StoreCondReq accesses system.cpu1.dcache.demand_miss_rate::cpu1.data 0.086616 # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::total 0.086616 # miss rate for demand accesses system.cpu1.dcache.overall_miss_rate::cpu1.data 0.090526 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total 0.090526 # miss rate for overall accesses system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16112.773708 # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::total 16112.773708 # average ReadReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20858.831174 # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::total 20858.831174 # average WriteReq miss latency system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 39667.681654 # average WriteLineReq miss latency system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 39667.681654 # average WriteLineReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15504.129815 # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15504.129815 # average LoadLockedReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23849.275437 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23849.275437 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18653.381954 # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::total 18653.381954 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17750.001256 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::total 17750.001256 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 4190229 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 23645788 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 332306 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 708476 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs 12.609550 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets 33.375567 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed system.cpu1.dcache.writebacks::writebacks 3362559 # number of writebacks system.cpu1.dcache.writebacks::total 3362559 # number of writebacks system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3121386 # number of ReadReq MSHR hits system.cpu1.dcache.ReadReq_mshr_hits::total 3121386 # number of ReadReq MSHR hits system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5664444 # number of WriteReq MSHR hits system.cpu1.dcache.WriteReq_mshr_hits::total 5664444 # number of WriteReq MSHR hits system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3068 # number of WriteLineReq MSHR hits system.cpu1.dcache.WriteLineReq_mshr_hits::total 3068 # number of WriteLineReq MSHR hits system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 133009 # number of LoadLockedReq MSHR hits system.cpu1.dcache.LoadLockedReq_mshr_hits::total 133009 # number of LoadLockedReq MSHR hits system.cpu1.dcache.demand_mshr_hits::cpu1.data 8785830 # number of demand (read+write) MSHR hits system.cpu1.dcache.demand_mshr_hits::total 8785830 # number of demand (read+write) MSHR hits system.cpu1.dcache.overall_mshr_hits::cpu1.data 8785830 # number of overall MSHR hits system.cpu1.dcache.overall_mshr_hits::total 8785830 # number of overall MSHR hits system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2944558 # number of ReadReq MSHR misses system.cpu1.dcache.ReadReq_mshr_misses::total 2944558 # number of ReadReq MSHR misses system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1323333 # number of WriteReq MSHR misses system.cpu1.dcache.WriteReq_mshr_misses::total 1323333 # number of WriteReq MSHR misses system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 664291 # number of SoftPFReq MSHR misses system.cpu1.dcache.SoftPFReq_mshr_misses::total 664291 # number of SoftPFReq MSHR misses system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 402893 # number of WriteLineReq MSHR misses system.cpu1.dcache.WriteLineReq_mshr_misses::total 402893 # number of WriteLineReq MSHR misses system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 125235 # number of LoadLockedReq MSHR misses system.cpu1.dcache.LoadLockedReq_mshr_misses::total 125235 # number of LoadLockedReq MSHR misses system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 193904 # number of StoreCondReq MSHR misses system.cpu1.dcache.StoreCondReq_mshr_misses::total 193904 # number of StoreCondReq MSHR misses system.cpu1.dcache.demand_mshr_misses::cpu1.data 4267891 # number of demand (read+write) MSHR misses system.cpu1.dcache.demand_mshr_misses::total 4267891 # number of demand (read+write) MSHR misses system.cpu1.dcache.overall_mshr_misses::cpu1.data 4932182 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_misses::total 4932182 # number of overall MSHR misses system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 5159 # number of ReadReq MSHR uncacheable system.cpu1.dcache.ReadReq_mshr_uncacheable::total 5159 # number of ReadReq MSHR uncacheable system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 4882 # number of WriteReq MSHR uncacheable system.cpu1.dcache.WriteReq_mshr_uncacheable::total 4882 # number of WriteReq MSHR uncacheable system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 10041 # number of overall MSHR uncacheable misses system.cpu1.dcache.overall_mshr_uncacheable_misses::total 10041 # number of overall MSHR uncacheable misses system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 44629208000 # number of ReadReq MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_miss_latency::total 44629208000 # number of ReadReq MSHR miss cycles system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 29351732295 # number of WriteReq MSHR miss cycles system.cpu1.dcache.WriteReq_mshr_miss_latency::total 29351732295 # number of WriteReq MSHR miss cycles system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 15227596000 # number of SoftPFReq MSHR miss cycles system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 15227596000 # number of SoftPFReq MSHR miss cycles system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 15536076712 # number of WriteLineReq MSHR miss cycles system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 15536076712 # number of WriteLineReq MSHR miss cycles system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1817525500 # number of LoadLockedReq MSHR miss cycles system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1817525500 # number of LoadLockedReq MSHR miss cycles system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4430771000 # number of StoreCondReq MSHR miss cycles system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4430771000 # number of StoreCondReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 5279000 # number of StoreCondFailReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 5279000 # number of StoreCondFailReq MSHR miss cycles system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 73980940295 # number of demand (read+write) MSHR miss cycles system.cpu1.dcache.demand_mshr_miss_latency::total 73980940295 # number of demand (read+write) MSHR miss cycles system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 89208536295 # number of overall MSHR miss cycles system.cpu1.dcache.overall_mshr_miss_latency::total 89208536295 # number of overall MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 520581000 # number of ReadReq MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 520581000 # number of ReadReq MSHR uncacheable cycles system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 549653500 # number of WriteReq MSHR uncacheable cycles system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 549653500 # number of WriteReq MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1070234500 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1070234500 # number of overall MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036729 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036729 # mshr miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018760 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018760 # mshr miss rate for WriteReq accesses system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.801605 # mshr miss rate for SoftPFReq accesses system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.801605 # mshr miss rate for SoftPFReq accesses system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.883034 # mshr miss rate for WriteLineReq accesses system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.883034 # mshr miss rate for WriteLineReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.062663 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.062663 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.099109 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.099109 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028319 # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::total 0.028319 # mshr miss rate for demand accesses system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032548 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::total 0.032548 # mshr miss rate for overall accesses system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15156.504983 # average ReadReq mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15156.504983 # average ReadReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22180.155936 # average WriteReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 22180.155936 # average WriteReq mshr miss latency system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22923.080397 # average SoftPFReq mshr miss latency system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22923.080397 # average SoftPFReq mshr miss latency system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 38561.297198 # average WriteLineReq mshr miss latency system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 38561.297198 # average WriteLineReq mshr miss latency system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14512.919711 # average LoadLockedReq mshr miss latency system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14512.919711 # average LoadLockedReq mshr miss latency system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22850.333155 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22850.333155 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17334.308748 # average overall mshr miss latency system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17334.308748 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18087.032533 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18087.032533 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 100907.346385 # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 100907.346385 # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 112587.771405 # average WriteReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 112587.771405 # average WriteReq mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 106586.445573 # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 106586.445573 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.tags.replacements 5202817 # number of replacements system.cpu1.icache.tags.tagsinuse 501.771617 # Cycle average of tags in use system.cpu1.icache.tags.total_refs 188211208 # Total number of references to valid blocks. system.cpu1.icache.tags.sampled_refs 5203329 # Sample count of references to valid blocks. system.cpu1.icache.tags.avg_refs 36.171306 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 8527218243000 # Cycle when the warmup percentage was hit. system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.771617 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.980023 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.980023 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::1 319 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 70 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu1.icache.tags.tag_accesses 392655056 # Number of tag accesses system.cpu1.icache.tags.data_accesses 392655056 # Number of data accesses system.cpu1.icache.ReadReq_hits::cpu1.inst 188211208 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 188211208 # number of ReadReq hits system.cpu1.icache.demand_hits::cpu1.inst 188211208 # number of demand (read+write) hits system.cpu1.icache.demand_hits::total 188211208 # number of demand (read+write) hits system.cpu1.icache.overall_hits::cpu1.inst 188211208 # number of overall hits system.cpu1.icache.overall_hits::total 188211208 # number of overall hits system.cpu1.icache.ReadReq_misses::cpu1.inst 5514651 # number of ReadReq misses system.cpu1.icache.ReadReq_misses::total 5514651 # number of ReadReq misses system.cpu1.icache.demand_misses::cpu1.inst 5514651 # number of demand (read+write) misses system.cpu1.icache.demand_misses::total 5514651 # number of demand (read+write) misses system.cpu1.icache.overall_misses::cpu1.inst 5514651 # number of overall misses system.cpu1.icache.overall_misses::total 5514651 # number of overall misses system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 61642094935 # number of ReadReq miss cycles system.cpu1.icache.ReadReq_miss_latency::total 61642094935 # number of ReadReq miss cycles system.cpu1.icache.demand_miss_latency::cpu1.inst 61642094935 # number of demand (read+write) miss cycles system.cpu1.icache.demand_miss_latency::total 61642094935 # number of demand (read+write) miss cycles system.cpu1.icache.overall_miss_latency::cpu1.inst 61642094935 # number of overall miss cycles system.cpu1.icache.overall_miss_latency::total 61642094935 # number of overall miss cycles system.cpu1.icache.ReadReq_accesses::cpu1.inst 193725859 # number of ReadReq accesses(hits+misses) system.cpu1.icache.ReadReq_accesses::total 193725859 # number of ReadReq accesses(hits+misses) system.cpu1.icache.demand_accesses::cpu1.inst 193725859 # number of demand (read+write) accesses system.cpu1.icache.demand_accesses::total 193725859 # number of demand (read+write) accesses system.cpu1.icache.overall_accesses::cpu1.inst 193725859 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::total 193725859 # number of overall (read+write) accesses system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.028466 # miss rate for ReadReq accesses system.cpu1.icache.ReadReq_miss_rate::total 0.028466 # miss rate for ReadReq accesses system.cpu1.icache.demand_miss_rate::cpu1.inst 0.028466 # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::total 0.028466 # miss rate for demand accesses system.cpu1.icache.overall_miss_rate::cpu1.inst 0.028466 # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::total 0.028466 # miss rate for overall accesses system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 11177.877790 # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::total 11177.877790 # average ReadReq miss latency system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 11177.877790 # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::total 11177.877790 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 11177.877790 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::total 11177.877790 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 9398442 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 360 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 665033 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 6 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.132294 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets 60 # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 311313 # number of ReadReq MSHR hits system.cpu1.icache.ReadReq_mshr_hits::total 311313 # number of ReadReq MSHR hits system.cpu1.icache.demand_mshr_hits::cpu1.inst 311313 # number of demand (read+write) MSHR hits system.cpu1.icache.demand_mshr_hits::total 311313 # number of demand (read+write) MSHR hits system.cpu1.icache.overall_mshr_hits::cpu1.inst 311313 # number of overall MSHR hits system.cpu1.icache.overall_mshr_hits::total 311313 # number of overall MSHR hits system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5203338 # number of ReadReq MSHR misses system.cpu1.icache.ReadReq_mshr_misses::total 5203338 # number of ReadReq MSHR misses system.cpu1.icache.demand_mshr_misses::cpu1.inst 5203338 # number of demand (read+write) MSHR misses system.cpu1.icache.demand_mshr_misses::total 5203338 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 5203338 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 5203338 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 67 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 67 # number of overall MSHR uncacheable misses system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 55550609345 # number of ReadReq MSHR miss cycles system.cpu1.icache.ReadReq_mshr_miss_latency::total 55550609345 # number of ReadReq MSHR miss cycles system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 55550609345 # number of demand (read+write) MSHR miss cycles system.cpu1.icache.demand_mshr_miss_latency::total 55550609345 # number of demand (read+write) MSHR miss cycles system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 55550609345 # number of overall MSHR miss cycles system.cpu1.icache.overall_mshr_miss_latency::total 55550609345 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8907998 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8907998 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8907998 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 8907998 # number of overall MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.026859 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.026859 # mshr miss rate for ReadReq accesses system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.026859 # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::total 0.026859 # mshr miss rate for demand accesses system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.026859 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::total 0.026859 # mshr miss rate for overall accesses system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10675.956347 # average ReadReq mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10675.956347 # average ReadReq mshr miss latency system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10675.956347 # average overall mshr miss latency system.cpu1.icache.demand_avg_mshr_miss_latency::total 10675.956347 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10675.956347 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_miss_latency::total 10675.956347 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 132955.194030 # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 132955.194030 # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 132955.194030 # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 132955.194030 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.l2cache.prefetcher.num_hwpf_issued 7284852 # number of hwpf issued system.cpu1.l2cache.prefetcher.pfIdentified 7288644 # number of prefetch candidates identified system.cpu1.l2cache.prefetcher.pfBufferHit 3499 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu1.l2cache.prefetcher.pfSpanPage 858524 # number of prefetches not generated due to page crossing system.cpu1.l2cache.tags.replacements 2147738 # number of replacements system.cpu1.l2cache.tags.tagsinuse 13168.263726 # Cycle average of tags in use system.cpu1.l2cache.tags.total_refs 17929780 # Total number of references to valid blocks. system.cpu1.l2cache.tags.sampled_refs 2163721 # Sample count of references to valid blocks. system.cpu1.l2cache.tags.avg_refs 8.286549 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 10234175062500 # Cycle when the warmup percentage was hit. system.cpu1.l2cache.tags.occ_blocks::writebacks 5935.884902 # Average occupied blocks per requestor system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 83.839548 # Average occupied blocks per requestor system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 89.493119 # Average occupied blocks per requestor system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2981.742674 # Average occupied blocks per requestor system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3164.985598 # Average occupied blocks per requestor system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 912.317885 # Average occupied blocks per requestor system.cpu1.l2cache.tags.occ_percent::writebacks 0.362298 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.005117 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005462 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.181991 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.193175 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.055683 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::total 0.803727 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1279 # Occupied blocks per task id system.cpu1.l2cache.tags.occ_task_id_blocks::1023 76 # Occupied blocks per task id system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14628 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 14 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 228 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 605 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 432 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 36 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 24 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 16 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 129 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1303 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5317 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4591 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3288 # Occupied blocks per task id system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.078064 # Percentage of cache occupancy per task id system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004639 # Percentage of cache occupancy per task id system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.892822 # Percentage of cache occupancy per task id system.cpu1.l2cache.tags.tag_accesses 355115319 # Number of tag accesses system.cpu1.l2cache.tags.data_accesses 355115319 # Number of data accesses system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 503903 # number of ReadReq hits system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 170407 # number of ReadReq hits system.cpu1.l2cache.ReadReq_hits::total 674310 # number of ReadReq hits system.cpu1.l2cache.Writeback_hits::writebacks 3362546 # number of Writeback hits system.cpu1.l2cache.Writeback_hits::total 3362546 # number of Writeback hits system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 76168 # number of UpgradeReq hits system.cpu1.l2cache.UpgradeReq_hits::total 76168 # number of UpgradeReq hits system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 33807 # number of SCUpgradeReq hits system.cpu1.l2cache.SCUpgradeReq_hits::total 33807 # number of SCUpgradeReq hits system.cpu1.l2cache.ReadExReq_hits::cpu1.data 827137 # number of ReadExReq hits system.cpu1.l2cache.ReadExReq_hits::total 827137 # number of ReadExReq hits system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4627973 # number of ReadCleanReq hits system.cpu1.l2cache.ReadCleanReq_hits::total 4627973 # number of ReadCleanReq hits system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2745456 # number of ReadSharedReq hits system.cpu1.l2cache.ReadSharedReq_hits::total 2745456 # number of ReadSharedReq hits system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 178495 # number of InvalidateReq hits system.cpu1.l2cache.InvalidateReq_hits::total 178495 # number of InvalidateReq hits system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 503903 # number of demand (read+write) hits system.cpu1.l2cache.demand_hits::cpu1.itb.walker 170407 # number of demand (read+write) hits system.cpu1.l2cache.demand_hits::cpu1.inst 4627973 # number of demand (read+write) hits system.cpu1.l2cache.demand_hits::cpu1.data 3572593 # number of demand (read+write) hits system.cpu1.l2cache.demand_hits::total 8874876 # number of demand (read+write) hits system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 503903 # number of overall hits system.cpu1.l2cache.overall_hits::cpu1.itb.walker 170407 # number of overall hits system.cpu1.l2cache.overall_hits::cpu1.inst 4627973 # number of overall hits system.cpu1.l2cache.overall_hits::cpu1.data 3572593 # number of overall hits system.cpu1.l2cache.overall_hits::total 8874876 # number of overall hits system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 11662 # number of ReadReq misses system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8601 # number of ReadReq misses system.cpu1.l2cache.ReadReq_misses::total 20263 # number of ReadReq misses system.cpu1.l2cache.Writeback_misses::writebacks 12 # number of Writeback misses system.cpu1.l2cache.Writeback_misses::total 12 # number of Writeback misses system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 140170 # number of UpgradeReq misses system.cpu1.l2cache.UpgradeReq_misses::total 140170 # number of UpgradeReq misses system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 160091 # number of SCUpgradeReq misses system.cpu1.l2cache.SCUpgradeReq_misses::total 160091 # number of SCUpgradeReq misses system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 6 # number of SCUpgradeFailReq misses system.cpu1.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses system.cpu1.l2cache.ReadExReq_misses::cpu1.data 288732 # number of ReadExReq misses system.cpu1.l2cache.ReadExReq_misses::total 288732 # number of ReadExReq misses system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 575353 # number of ReadCleanReq misses system.cpu1.l2cache.ReadCleanReq_misses::total 575353 # number of ReadCleanReq misses system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 984374 # number of ReadSharedReq misses system.cpu1.l2cache.ReadSharedReq_misses::total 984374 # number of ReadSharedReq misses system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 223283 # number of InvalidateReq misses system.cpu1.l2cache.InvalidateReq_misses::total 223283 # number of InvalidateReq misses system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 11662 # number of demand (read+write) misses system.cpu1.l2cache.demand_misses::cpu1.itb.walker 8601 # number of demand (read+write) misses system.cpu1.l2cache.demand_misses::cpu1.inst 575353 # number of demand (read+write) misses system.cpu1.l2cache.demand_misses::cpu1.data 1273106 # number of demand (read+write) misses system.cpu1.l2cache.demand_misses::total 1868722 # number of demand (read+write) misses system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 11662 # number of overall misses system.cpu1.l2cache.overall_misses::cpu1.itb.walker 8601 # number of overall misses system.cpu1.l2cache.overall_misses::cpu1.inst 575353 # number of overall misses system.cpu1.l2cache.overall_misses::cpu1.data 1273106 # number of overall misses system.cpu1.l2cache.overall_misses::total 1868722 # number of overall misses system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 594160000 # number of ReadReq miss cycles system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 468390500 # number of ReadReq miss cycles system.cpu1.l2cache.ReadReq_miss_latency::total 1062550500 # number of ReadReq miss cycles system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 4210266499 # number of UpgradeReq miss cycles system.cpu1.l2cache.UpgradeReq_miss_latency::total 4210266499 # number of UpgradeReq miss cycles system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3771249000 # number of SCUpgradeReq miss cycles system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3771249000 # number of SCUpgradeReq miss cycles system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 5184498 # number of SCUpgradeFailReq miss cycles system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 5184498 # number of SCUpgradeFailReq miss cycles system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 15534540997 # number of ReadExReq miss cycles system.cpu1.l2cache.ReadExReq_miss_latency::total 15534540997 # number of ReadExReq miss cycles system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 20167259000 # number of ReadCleanReq miss cycles system.cpu1.l2cache.ReadCleanReq_miss_latency::total 20167259000 # number of ReadCleanReq miss cycles system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 37839552480 # number of ReadSharedReq miss cycles system.cpu1.l2cache.ReadSharedReq_miss_latency::total 37839552480 # number of ReadSharedReq miss cycles system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 13425130499 # number of InvalidateReq miss cycles system.cpu1.l2cache.InvalidateReq_miss_latency::total 13425130499 # number of InvalidateReq miss cycles system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 594160000 # number of demand (read+write) miss cycles system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 468390500 # number of demand (read+write) miss cycles system.cpu1.l2cache.demand_miss_latency::cpu1.inst 20167259000 # number of demand (read+write) miss cycles system.cpu1.l2cache.demand_miss_latency::cpu1.data 53374093477 # number of demand (read+write) miss cycles system.cpu1.l2cache.demand_miss_latency::total 74603902977 # number of demand (read+write) miss cycles system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 594160000 # number of overall miss cycles system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 468390500 # number of overall miss cycles system.cpu1.l2cache.overall_miss_latency::cpu1.inst 20167259000 # number of overall miss cycles system.cpu1.l2cache.overall_miss_latency::cpu1.data 53374093477 # number of overall miss cycles system.cpu1.l2cache.overall_miss_latency::total 74603902977 # number of overall miss cycles system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 515565 # number of ReadReq accesses(hits+misses) system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 179008 # number of ReadReq accesses(hits+misses) system.cpu1.l2cache.ReadReq_accesses::total 694573 # number of ReadReq accesses(hits+misses) system.cpu1.l2cache.Writeback_accesses::writebacks 3362558 # number of Writeback accesses(hits+misses) system.cpu1.l2cache.Writeback_accesses::total 3362558 # number of Writeback accesses(hits+misses) system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 216338 # number of UpgradeReq accesses(hits+misses) system.cpu1.l2cache.UpgradeReq_accesses::total 216338 # number of UpgradeReq accesses(hits+misses) system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 193898 # number of SCUpgradeReq accesses(hits+misses) system.cpu1.l2cache.SCUpgradeReq_accesses::total 193898 # number of SCUpgradeReq accesses(hits+misses) system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 6 # number of SCUpgradeFailReq accesses(hits+misses) system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses) system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1115869 # number of ReadExReq accesses(hits+misses) system.cpu1.l2cache.ReadExReq_accesses::total 1115869 # number of ReadExReq accesses(hits+misses) system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 5203326 # number of ReadCleanReq accesses(hits+misses) system.cpu1.l2cache.ReadCleanReq_accesses::total 5203326 # number of ReadCleanReq accesses(hits+misses) system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3729830 # number of ReadSharedReq accesses(hits+misses) system.cpu1.l2cache.ReadSharedReq_accesses::total 3729830 # number of ReadSharedReq accesses(hits+misses) system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 401778 # number of InvalidateReq accesses(hits+misses) system.cpu1.l2cache.InvalidateReq_accesses::total 401778 # number of InvalidateReq accesses(hits+misses) system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 515565 # number of demand (read+write) accesses system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 179008 # number of demand (read+write) accesses system.cpu1.l2cache.demand_accesses::cpu1.inst 5203326 # number of demand (read+write) accesses system.cpu1.l2cache.demand_accesses::cpu1.data 4845699 # number of demand (read+write) accesses system.cpu1.l2cache.demand_accesses::total 10743598 # number of demand (read+write) accesses system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 515565 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 179008 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::cpu1.inst 5203326 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::cpu1.data 4845699 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::total 10743598 # number of overall (read+write) accesses system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.022620 # miss rate for ReadReq accesses system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.048048 # miss rate for ReadReq accesses system.cpu1.l2cache.ReadReq_miss_rate::total 0.029173 # miss rate for ReadReq accesses system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000004 # miss rate for Writeback accesses system.cpu1.l2cache.Writeback_miss_rate::total 0.000004 # miss rate for Writeback accesses system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.647921 # miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.647921 # miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.825645 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.825645 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.258751 # miss rate for ReadExReq accesses system.cpu1.l2cache.ReadExReq_miss_rate::total 0.258751 # miss rate for ReadExReq accesses system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.110574 # miss rate for ReadCleanReq accesses system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.110574 # miss rate for ReadCleanReq accesses system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.263919 # miss rate for ReadSharedReq accesses system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.263919 # miss rate for ReadSharedReq accesses system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.555737 # miss rate for InvalidateReq accesses system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.555737 # miss rate for InvalidateReq accesses system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.022620 # miss rate for demand accesses system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.048048 # miss rate for demand accesses system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.110574 # miss rate for demand accesses system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.262729 # miss rate for demand accesses system.cpu1.l2cache.demand_miss_rate::total 0.173938 # miss rate for demand accesses system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.022620 # miss rate for overall accesses system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.048048 # miss rate for overall accesses system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.110574 # miss rate for overall accesses system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.262729 # miss rate for overall accesses system.cpu1.l2cache.overall_miss_rate::total 0.173938 # miss rate for overall accesses system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 50948.379352 # average ReadReq miss latency system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 54457.679340 # average ReadReq miss latency system.cpu1.l2cache.ReadReq_avg_miss_latency::total 52437.965750 # average ReadReq miss latency system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 30036.858807 # average UpgradeReq miss latency system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 30036.858807 # average UpgradeReq miss latency system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 23556.908258 # average SCUpgradeReq miss latency system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 23556.908258 # average SCUpgradeReq miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 864083 # average SCUpgradeFailReq miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 864083 # average SCUpgradeFailReq miss latency system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 53802.630110 # average ReadExReq miss latency system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 53802.630110 # average ReadExReq miss latency system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 35051.975048 # average ReadCleanReq miss latency system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 35051.975048 # average ReadCleanReq miss latency system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 38440.219348 # average ReadSharedReq miss latency system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 38440.219348 # average ReadSharedReq miss latency system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 60126.075424 # average InvalidateReq miss latency system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 60126.075424 # average InvalidateReq miss latency system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 50948.379352 # average overall miss latency system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 54457.679340 # average overall miss latency system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 35051.975048 # average overall miss latency system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 41924.312254 # average overall miss latency system.cpu1.l2cache.demand_avg_miss_latency::total 39922.419160 # average overall miss latency system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 50948.379352 # average overall miss latency system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 54457.679340 # average overall miss latency system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 35051.975048 # average overall miss latency system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 41924.312254 # average overall miss latency system.cpu1.l2cache.overall_avg_miss_latency::total 39922.419160 # average overall miss latency system.cpu1.l2cache.blocked_cycles::no_mshrs 689 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 137.800000 # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed system.cpu1.l2cache.writebacks::writebacks 1011189 # number of writebacks system.cpu1.l2cache.writebacks::total 1011189 # number of writebacks system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 3 # number of ReadReq MSHR hits system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 149 # number of ReadReq MSHR hits system.cpu1.l2cache.ReadReq_mshr_hits::total 152 # number of ReadReq MSHR hits system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 48488 # number of ReadExReq MSHR hits system.cpu1.l2cache.ReadExReq_mshr_hits::total 48488 # number of ReadExReq MSHR hits system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 3759 # number of ReadSharedReq MSHR hits system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 3759 # number of ReadSharedReq MSHR hits system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 12 # number of InvalidateReq MSHR hits system.cpu1.l2cache.InvalidateReq_mshr_hits::total 12 # number of InvalidateReq MSHR hits system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 3 # number of demand (read+write) MSHR hits system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 149 # number of demand (read+write) MSHR hits system.cpu1.l2cache.demand_mshr_hits::cpu1.data 52247 # number of demand (read+write) MSHR hits system.cpu1.l2cache.demand_mshr_hits::total 52399 # number of demand (read+write) MSHR hits system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 3 # number of overall MSHR hits system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 149 # number of overall MSHR hits system.cpu1.l2cache.overall_mshr_hits::cpu1.data 52247 # number of overall MSHR hits system.cpu1.l2cache.overall_mshr_hits::total 52399 # number of overall MSHR hits system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 11659 # number of ReadReq MSHR misses system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 8452 # number of ReadReq MSHR misses system.cpu1.l2cache.ReadReq_mshr_misses::total 20111 # number of ReadReq MSHR misses system.cpu1.l2cache.Writeback_mshr_misses::writebacks 12 # number of Writeback MSHR misses system.cpu1.l2cache.Writeback_mshr_misses::total 12 # number of Writeback MSHR misses system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks 102199 # number of CleanEvict MSHR misses system.cpu1.l2cache.CleanEvict_mshr_misses::total 102199 # number of CleanEvict MSHR misses system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 721665 # number of HardPFReq MSHR misses system.cpu1.l2cache.HardPFReq_mshr_misses::total 721665 # number of HardPFReq MSHR misses system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 140170 # number of UpgradeReq MSHR misses system.cpu1.l2cache.UpgradeReq_mshr_misses::total 140170 # number of UpgradeReq MSHR misses system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 160091 # number of SCUpgradeReq MSHR misses system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 160091 # number of SCUpgradeReq MSHR misses system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 6 # number of SCUpgradeFailReq MSHR misses system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 6 # number of SCUpgradeFailReq MSHR misses system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 240244 # number of ReadExReq MSHR misses system.cpu1.l2cache.ReadExReq_mshr_misses::total 240244 # number of ReadExReq MSHR misses system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 575353 # number of ReadCleanReq MSHR misses system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 575353 # number of ReadCleanReq MSHR misses system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 980615 # number of ReadSharedReq MSHR misses system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 980615 # number of ReadSharedReq MSHR misses system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 223271 # number of InvalidateReq MSHR misses system.cpu1.l2cache.InvalidateReq_mshr_misses::total 223271 # number of InvalidateReq MSHR misses system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 11659 # number of demand (read+write) MSHR misses system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 8452 # number of demand (read+write) MSHR misses system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 575353 # number of demand (read+write) MSHR misses system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1220859 # number of demand (read+write) MSHR misses system.cpu1.l2cache.demand_mshr_misses::total 1816323 # number of demand (read+write) MSHR misses system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 11659 # number of overall MSHR misses system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 8452 # number of overall MSHR misses system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 575353 # number of overall MSHR misses system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1220859 # number of overall MSHR misses system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 721665 # number of overall MSHR misses system.cpu1.l2cache.overall_mshr_misses::total 2537988 # number of overall MSHR misses system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 5159 # number of ReadReq MSHR uncacheable system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 5226 # number of ReadReq MSHR uncacheable system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 4882 # number of WriteReq MSHR uncacheable system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 4882 # number of WriteReq MSHR uncacheable system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 10041 # number of overall MSHR uncacheable misses system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 10108 # number of overall MSHR uncacheable misses system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 524142000 # number of ReadReq MSHR miss cycles system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 406910000 # number of ReadReq MSHR miss cycles system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 931052000 # number of ReadReq MSHR miss cycles system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 46701535932 # number of HardPFReq MSHR miss cycles system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 46701535932 # number of HardPFReq MSHR miss cycles system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 4601332497 # number of UpgradeReq MSHR miss cycles system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 4601332497 # number of UpgradeReq MSHR miss cycles system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2959393998 # number of SCUpgradeReq MSHR miss cycles system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2959393998 # number of SCUpgradeReq MSHR miss cycles system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 4812498 # number of SCUpgradeFailReq MSHR miss cycles system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 4812498 # number of SCUpgradeFailReq MSHR miss cycles system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 11648353997 # number of ReadExReq MSHR miss cycles system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 11648353997 # number of ReadExReq MSHR miss cycles system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 16715141000 # number of ReadCleanReq MSHR miss cycles system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 16715141000 # number of ReadCleanReq MSHR miss cycles system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 31784270480 # number of ReadSharedReq MSHR miss cycles system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 31784270480 # number of ReadSharedReq MSHR miss cycles system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 12084897499 # number of InvalidateReq MSHR miss cycles system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 12084897499 # number of InvalidateReq MSHR miss cycles system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 524142000 # number of demand (read+write) MSHR miss cycles system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 406910000 # number of demand (read+write) MSHR miss cycles system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 16715141000 # number of demand (read+write) MSHR miss cycles system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 43432624477 # number of demand (read+write) MSHR miss cycles system.cpu1.l2cache.demand_mshr_miss_latency::total 61078817477 # number of demand (read+write) MSHR miss cycles system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 524142000 # number of overall MSHR miss cycles system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 406910000 # number of overall MSHR miss cycles system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 16715141000 # number of overall MSHR miss cycles system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 43432624477 # number of overall MSHR miss cycles system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 46701535932 # number of overall MSHR miss cycles system.cpu1.l2cache.overall_mshr_miss_latency::total 107780353409 # number of overall MSHR miss cycles system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8404500 # number of ReadReq MSHR uncacheable cycles system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 479244000 # number of ReadReq MSHR uncacheable cycles system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 487648500 # number of ReadReq MSHR uncacheable cycles system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 512985500 # number of WriteReq MSHR uncacheable cycles system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 512985500 # number of WriteReq MSHR uncacheable cycles system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8404500 # number of overall MSHR uncacheable cycles system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 992229500 # number of overall MSHR uncacheable cycles system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1000634000 # number of overall MSHR uncacheable cycles system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.022614 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.047216 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.028954 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000004 # mshr miss rate for Writeback accesses system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000004 # mshr miss rate for Writeback accesses system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.647921 # mshr miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.647921 # mshr miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.825645 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.825645 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.215298 # mshr miss rate for ReadExReq accesses system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.215298 # mshr miss rate for ReadExReq accesses system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.110574 # mshr miss rate for ReadCleanReq accesses system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.110574 # mshr miss rate for ReadCleanReq accesses system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.262911 # mshr miss rate for ReadSharedReq accesses system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.262911 # mshr miss rate for ReadSharedReq accesses system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.555707 # mshr miss rate for InvalidateReq accesses system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.555707 # mshr miss rate for InvalidateReq accesses system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.022614 # mshr miss rate for demand accesses system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.047216 # mshr miss rate for demand accesses system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.110574 # mshr miss rate for demand accesses system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.251947 # mshr miss rate for demand accesses system.cpu1.l2cache.demand_mshr_miss_rate::total 0.169061 # mshr miss rate for demand accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.022614 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.047216 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.110574 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.251947 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::total 0.236233 # mshr miss rate for overall accesses system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 44955.999657 # average ReadReq mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 48143.634643 # average ReadReq mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 46295.659092 # average ReadReq mshr miss latency system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 64713.594163 # average HardPFReq mshr miss latency system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 64713.594163 # average HardPFReq mshr miss latency system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 32826.799579 # average UpgradeReq mshr miss latency system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 32826.799579 # average UpgradeReq mshr miss latency system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18485.698746 # average SCUpgradeReq mshr miss latency system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18485.698746 # average SCUpgradeReq mshr miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 802083 # average SCUpgradeFailReq mshr miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 802083 # average SCUpgradeFailReq mshr miss latency system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 48485.514714 # average ReadExReq mshr miss latency system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 48485.514714 # average ReadExReq mshr miss latency system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29051.975048 # average ReadCleanReq mshr miss latency system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29051.975048 # average ReadCleanReq mshr miss latency system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 32412.588508 # average ReadSharedReq mshr miss latency system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 32412.588508 # average ReadSharedReq mshr miss latency system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 54126.588312 # average InvalidateReq mshr miss latency system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 54126.588312 # average InvalidateReq mshr miss latency system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 44955.999657 # average overall mshr miss latency system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 48143.634643 # average overall mshr miss latency system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29051.975048 # average overall mshr miss latency system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 35575.463241 # average overall mshr miss latency system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 33627.728921 # average overall mshr miss latency system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 44955.999657 # average overall mshr miss latency system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 48143.634643 # average overall mshr miss latency system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29051.975048 # average overall mshr miss latency system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 35575.463241 # average overall mshr miss latency system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 64713.594163 # average overall mshr miss latency system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 42466.849098 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 125440.298507 # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 92894.747044 # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 93311.997704 # average ReadReq mshr uncacheable latency system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 105076.915199 # average WriteReq mshr uncacheable latency system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 105076.915199 # average WriteReq mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 125440.298507 # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 98817.797032 # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 98994.261971 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.toL2Bus.snoop_filter.tot_requests 21572446 # Total number of requests made to the snoop filter. system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11121796 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1158 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu1.toL2Bus.snoop_filter.tot_snoops 524506 # Total number of snoops made to the snoop filter. system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 524489 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 17 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu1.toL2Bus.trans_dist::ReadReq 847854 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadResp 9869269 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteReq 4882 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteResp 4882 # Transaction distribution system.cpu1.toL2Bus.trans_dist::Writeback 4416651 # Transaction distribution system.cpu1.toL2Bus.trans_dist::CleanEvict 8880510 # Transaction distribution system.cpu1.toL2Bus.trans_dist::HardPFReq 907695 # Transaction distribution system.cpu1.toL2Bus.trans_dist::HardPFResp 13 # Transaction distribution system.cpu1.toL2Bus.trans_dist::UpgradeReq 421769 # Transaction distribution system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 350236 # Transaction distribution system.cpu1.toL2Bus.trans_dist::UpgradeResp 471619 # Transaction distribution system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 69 # Transaction distribution system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 125 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadExReq 1189775 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadExResp 1122660 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5203338 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4763767 # Transaction distribution system.cpu1.toL2Bus.trans_dist::InvalidateReq 409409 # Transaction distribution system.cpu1.toL2Bus.trans_dist::InvalidateResp 401778 # Transaction distribution system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 15609171 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16649345 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 393406 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1143795 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count::total 33795717 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 333013936 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 531452177 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1432064 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4124520 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size::total 870022697 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.snoops 5627139 # Total snoops (count) system.cpu1.toL2Bus.snoop_fanout::samples 27397107 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::mean 0.032027 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::stdev 0.176075 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 26519684 96.80% 96.80% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 877406 3.20% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 17 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::total 27397107 # Request fanout histogram system.cpu1.toL2Bus.reqLayer0.occupancy 14402314458 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.cpu1.toL2Bus.snoopLayer0.occupancy 173479331 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) system.cpu1.toL2Bus.respLayer0.occupancy 7809268085 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu1.toL2Bus.respLayer1.occupancy 7687735490 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu1.toL2Bus.respLayer2.occupancy 214700392 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu1.toL2Bus.respLayer3.occupancy 628828296 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 40404 # Transaction distribution system.iobus.trans_dist::ReadResp 40404 # Transaction distribution system.iobus.trans_dist::WriteReq 136681 # Transaction distribution system.iobus.trans_dist::WriteResp 136681 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47892 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122826 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231264 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 231264 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::total 354170 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47912 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155933 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339072 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 7339072 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 7497091 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 36369000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 21986000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer27.occupancy 566086533 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92876000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 147960000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 115614 # number of replacements system.iocache.tags.tagsinuse 11.301705 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 115630 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 9126915715000 # Cycle when the warmup percentage was hit. system.iocache.tags.occ_blocks::realview.ethernet 3.837722 # Average occupied blocks per requestor system.iocache.tags.occ_blocks::realview.ide 7.463983 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ethernet 0.239858 # Average percentage of cache occupancy system.iocache.tags.occ_percent::realview.ide 0.466499 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.706357 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 1041045 # Number of tag accesses system.iocache.tags.data_accesses 1041045 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses system.iocache.ReadReq_misses::realview.ide 8904 # number of ReadReq misses system.iocache.ReadReq_misses::total 8941 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses system.iocache.demand_misses::realview.ide 8904 # number of demand (read+write) misses system.iocache.demand_misses::total 8944 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses system.iocache.overall_misses::realview.ide 8904 # number of overall misses system.iocache.overall_misses::total 8944 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5199000 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::realview.ide 1751682968 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 1756881968 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles system.iocache.WriteLineReq_miss_latency::realview.ide 13928366565 # number of WriteLineReq miss cycles system.iocache.WriteLineReq_miss_latency::total 13928366565 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 5568000 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::realview.ide 1751682968 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::total 1757250968 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 5568000 # number of overall miss cycles system.iocache.overall_miss_latency::realview.ide 1751682968 # number of overall miss cycles system.iocache.overall_miss_latency::total 1757250968 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::realview.ide 8904 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 8941 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses system.iocache.demand_accesses::realview.ide 8904 # number of demand (read+write) accesses system.iocache.demand_accesses::total 8944 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses system.iocache.overall_accesses::realview.ide 8904 # number of overall (read+write) accesses system.iocache.overall_accesses::total 8944 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140513.513514 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::realview.ide 196729.893082 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 196497.256235 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130503.397094 # average WriteLineReq miss latency system.iocache.WriteLineReq_avg_miss_latency::total 130503.397094 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 139200 # average overall miss latency system.iocache.demand_avg_miss_latency::realview.ide 196729.893082 # average overall miss latency system.iocache.demand_avg_miss_latency::total 196472.603757 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 139200 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ide 196729.893082 # average overall miss latency system.iocache.overall_avg_miss_latency::total 196472.603757 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 36915 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 3596 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs 10.265573 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 106695 # number of writebacks system.iocache.writebacks::total 106695 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::realview.ide 8904 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 8941 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::realview.ide 8904 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 8944 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses system.iocache.overall_mshr_misses::realview.ide 8904 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 8944 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3349000 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::realview.ide 1306482968 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 1309831968 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8591966565 # number of WriteLineReq MSHR miss cycles system.iocache.WriteLineReq_mshr_miss_latency::total 8591966565 # number of WriteLineReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ethernet 3568000 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ide 1306482968 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::total 1310050968 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ethernet 3568000 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ide 1306482968 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_latency::total 1310050968 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90513.513514 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 146729.893082 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 146497.256235 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80503.397094 # average WriteLineReq mshr miss latency system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80503.397094 # average WriteLineReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89200 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ide 146729.893082 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 146472.603757 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89200 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ide 146729.893082 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 146472.603757 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.tags.replacements 1633941 # number of replacements system.l2c.tags.tagsinuse 63813.673701 # Cycle average of tags in use system.l2c.tags.total_refs 5902225 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 1694519 # Sample count of references to valid blocks. system.l2c.tags.avg_refs 3.483127 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.l2c.tags.occ_blocks::writebacks 18421.604397 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 145.885026 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 177.213344 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.inst 5018.050694 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.data 11022.844294 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 9747.408023 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.dtb.walker 214.913940 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.itb.walker 271.296665 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.inst 2354.078258 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.data 5504.302098 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 10936.076961 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.281091 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002226 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.002704 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.inst 0.076569 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.data 0.168195 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.148734 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.003279 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.itb.walker 0.004140 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.inst 0.035920 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.data 0.083989 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.166871 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.973719 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1022 11165 # Occupied blocks per task id system.l2c.tags.occ_task_id_blocks::1023 256 # Occupied blocks per task id system.l2c.tags.occ_task_id_blocks::1024 49157 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1022::2 1008 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1022::3 549 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1022::4 9608 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::4 249 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::1 266 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::2 2663 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::3 4864 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::4 41332 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1022 0.170364 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1023 0.003906 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1024 0.750076 # Percentage of cache occupancy per task id system.l2c.tags.tag_accesses 73803894 # Number of tag accesses system.l2c.tags.data_accesses 73803894 # Number of data accesses system.l2c.Writeback_hits::writebacks 2578909 # number of Writeback hits system.l2c.Writeback_hits::total 2578909 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 27661 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 31933 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 59594 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu0.data 6629 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu1.data 5839 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 12468 # number of SCUpgradeReq hits system.l2c.ReadExReq_hits::cpu0.data 166000 # number of ReadExReq hits system.l2c.ReadExReq_hits::cpu1.data 160567 # number of ReadExReq hits system.l2c.ReadExReq_hits::total 326567 # number of ReadExReq hits system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 7163 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4665 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu0.inst 621325 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu0.data 619304 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 290117 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6244 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4367 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu1.inst 539807 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu1.data 573735 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 292658 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::total 2959385 # number of ReadSharedReq hits system.l2c.demand_hits::cpu0.dtb.walker 7163 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.itb.walker 4665 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.inst 621325 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.data 785304 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.l2cache.prefetcher 290117 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.dtb.walker 6244 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.itb.walker 4367 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.inst 539807 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.data 734302 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.l2cache.prefetcher 292658 # number of demand (read+write) hits system.l2c.demand_hits::total 3285952 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.dtb.walker 7163 # number of overall hits system.l2c.overall_hits::cpu0.itb.walker 4665 # number of overall hits system.l2c.overall_hits::cpu0.inst 621325 # number of overall hits system.l2c.overall_hits::cpu0.data 785304 # number of overall hits system.l2c.overall_hits::cpu0.l2cache.prefetcher 290117 # number of overall hits system.l2c.overall_hits::cpu1.dtb.walker 6244 # number of overall hits system.l2c.overall_hits::cpu1.itb.walker 4367 # number of overall hits system.l2c.overall_hits::cpu1.inst 539807 # number of overall hits system.l2c.overall_hits::cpu1.data 734302 # number of overall hits system.l2c.overall_hits::cpu1.l2cache.prefetcher 292658 # number of overall hits system.l2c.overall_hits::total 3285952 # number of overall hits system.l2c.UpgradeReq_misses::cpu0.data 47272 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu1.data 44187 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 91459 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu0.data 10524 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 8835 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 19359 # number of SCUpgradeReq misses system.l2c.ReadExReq_misses::cpu0.data 557751 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 109635 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 667386 # number of ReadExReq misses system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2718 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2691 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu0.inst 73804 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu0.data 176754 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 337074 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 2418 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu1.itb.walker 2009 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu1.inst 35546 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu1.data 108545 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 227714 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::total 969273 # number of ReadSharedReq misses system.l2c.demand_misses::cpu0.dtb.walker 2718 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2691 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.inst 73804 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.data 734505 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.l2cache.prefetcher 337074 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 2418 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.itb.walker 2009 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.inst 35546 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.data 218180 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.l2cache.prefetcher 227714 # number of demand (read+write) misses system.l2c.demand_misses::total 1636659 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 2718 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2691 # number of overall misses system.l2c.overall_misses::cpu0.inst 73804 # number of overall misses system.l2c.overall_misses::cpu0.data 734505 # number of overall misses system.l2c.overall_misses::cpu0.l2cache.prefetcher 337074 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 2418 # number of overall misses system.l2c.overall_misses::cpu1.itb.walker 2009 # number of overall misses system.l2c.overall_misses::cpu1.inst 35546 # number of overall misses system.l2c.overall_misses::cpu1.data 218180 # number of overall misses system.l2c.overall_misses::cpu1.l2cache.prefetcher 227714 # number of overall misses system.l2c.overall_misses::total 1636659 # number of overall misses system.l2c.UpgradeReq_miss_latency::cpu0.data 726731000 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu1.data 727663000 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::total 1454394000 # number of UpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::cpu0.data 175002000 # number of SCUpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::cpu1.data 129347000 # number of SCUpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::total 304349000 # number of SCUpgradeReq miss cycles system.l2c.ReadExReq_miss_latency::cpu0.data 99619806501 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::cpu1.data 16419004998 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::total 116038811499 # number of ReadExReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 387278500 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 381455000 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu0.inst 10138420502 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu0.data 26142956500 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 61823794743 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 346383500 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 287503000 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu1.inst 4887103000 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu1.data 15686030000 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 41333236319 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::total 161414161064 # number of ReadSharedReq miss cycles system.l2c.demand_miss_latency::cpu0.dtb.walker 387278500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.itb.walker 381455000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.inst 10138420502 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.data 125762763001 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 61823794743 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.dtb.walker 346383500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.itb.walker 287503000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.inst 4887103000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.data 32105034998 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 41333236319 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::total 277452972563 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu0.dtb.walker 387278500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.itb.walker 381455000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.inst 10138420502 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.data 125762763001 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 61823794743 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.dtb.walker 346383500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.itb.walker 287503000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.inst 4887103000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.data 32105034998 # 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number of ReadSharedReq accesses(hits+misses) system.l2c.ReadSharedReq_accesses::cpu1.data 682280 # number of ReadSharedReq accesses(hits+misses) system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 520372 # number of ReadSharedReq accesses(hits+misses) system.l2c.ReadSharedReq_accesses::total 3928658 # number of ReadSharedReq accesses(hits+misses) system.l2c.demand_accesses::cpu0.dtb.walker 9881 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.itb.walker 7356 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.inst 695129 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.data 1519809 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.l2cache.prefetcher 627191 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.dtb.walker 8662 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.itb.walker 6376 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.inst 575353 # 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number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.data 952482 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.l2cache.prefetcher 520372 # number of overall (read+write) accesses system.l2c.overall_accesses::total 4922611 # number of overall (read+write) accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.630857 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 0.580491 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 0.605476 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.613537 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.602085 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::total 0.608257 # miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 0.770639 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 0.405752 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::total 0.671446 # miss rate for ReadExReq accesses system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.275073 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.365824 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.106173 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.222037 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.537434 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.279150 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.315088 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.061781 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.159092 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.437598 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::total 0.246719 # miss rate for ReadSharedReq accesses system.l2c.demand_miss_rate::cpu0.dtb.walker 0.275073 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.itb.walker 0.365824 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.inst 0.106173 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.483288 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.537434 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.dtb.walker 0.279150 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.itb.walker 0.315088 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.061781 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.data 0.229065 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.437598 # miss rate for demand accesses system.l2c.demand_miss_rate::total 0.332478 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.dtb.walker 0.275073 # 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average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.data 171221.112179 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 183413.122172 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 143252.067825 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.itb.walker 143107.516177 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.inst 137486.721431 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.data 147149.303318 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 181513.812585 # average overall miss latency system.l2c.overall_avg_miss_latency::total 169523.995263 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 5328 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 43 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # 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number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.inst 4514510000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.data 29921158498 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 39056095819 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::total 261046166563 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 360098500 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 354545000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.inst 9382267002 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.data 118415109501 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 58453054743 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 321914500 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 267413000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.inst 4514510000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.data 29921158498 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 39056095819 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::total 261046166563 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 2396727000 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5133320000 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 7197500 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 386376500 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::total 7923621000 # number of ReadReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 5120804533 # number of WriteReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 429980000 # number of WriteReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency::total 5550784533 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 2396727000 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10254124533 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 7197500 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.data 816356500 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::total 13474405533 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.630857 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.580491 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total 0.605476 # mshr miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.613537 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.602085 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.608257 # mshr miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.770639 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.405752 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total 0.671446 # mshr miss rate for ReadExReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.275073 # mshr miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.365824 # mshr miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.105927 # mshr miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.222008 # mshr miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.537434 # mshr miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.279035 # mshr miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.315088 # mshr miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.061517 # mshr miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.159068 # mshr miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.437597 # mshr miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::total 0.246626 # mshr miss rate for ReadSharedReq accesses system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.275073 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.365824 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.inst 0.105927 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.data 0.483273 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.537434 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.279035 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.315088 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.inst 0.061517 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.data 0.229048 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.437597 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total 0.332404 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.275073 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.365824 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.inst 0.105927 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.data 0.483273 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.537434 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.279035 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.315088 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.inst 0.061517 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.data 0.229048 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.437597 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total 0.332404 # mshr miss rate for overall accesses system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 73616.390294 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 73553.635707 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::total 73586.071387 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 76461.516819 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76478.098585 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76469.084354 # average SCUpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 168609.821410 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 139760.614749 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::total 163870.610859 # average ReadExReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 132486.571008 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 131752.136752 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 127419.322885 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 137909.099139 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 173413.122172 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 133187.629293 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 133107.516177 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 127550.149743 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 134512.466714 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 171514.563591 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 156548.463338 # average ReadSharedReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 132486.571008 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 131752.136752 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 127419.322885 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.data 161222.616076 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 173413.122172 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 133187.629293 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 133107.516177 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 127550.149743 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.data 137149.843686 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 171514.563591 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::total 159534.904503 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 132486.571008 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 131752.136752 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 127419.322885 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.data 161222.616076 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 173413.122172 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 133187.629293 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 133107.516177 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 127550.149743 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.data 137149.843686 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 171514.563591 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::total 159534.904503 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112554.099746 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 154441.302124 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 107425.373134 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 74922.726391 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 132599.588326 # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 153294.552702 # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 88074.559607 # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 144978.309426 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112554.099746 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 153866.490599 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 107425.373134 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 81318.507820 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total 137433.631498 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 59756 # Transaction distribution system.membus.trans_dist::ReadResp 1037606 # Transaction distribution system.membus.trans_dist::WriteReq 38287 # Transaction distribution system.membus.trans_dist::WriteResp 38287 # Transaction distribution system.membus.trans_dist::Writeback 1371305 # Transaction distribution system.membus.trans_dist::CleanEvict 262648 # Transaction distribution system.membus.trans_dist::UpgradeReq 440849 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 306045 # Transaction distribution system.membus.trans_dist::UpgradeResp 117782 # Transaction distribution system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution system.membus.trans_dist::ReadExReq 681386 # Transaction distribution system.membus.trans_dist::ReadExResp 660425 # Transaction distribution system.membus.trans_dist::ReadSharedReq 977850 # Transaction distribution system.membus.trans_dist::InvalidateReq 106728 # Transaction distribution system.membus.trans_dist::InvalidateResp 106728 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122826 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 78 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25318 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5711814 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::total 5860036 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 343033 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 343033 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 6203069 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155933 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 572 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50636 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 185527680 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::total 185734821 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7281536 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 7281536 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 193016357 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 652692 # Total snoops (count) system.membus.snoop_fanout::samples 4246933 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::1 4246933 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram system.membus.snoop_fanout::total 4246933 # Request fanout histogram system.membus.reqLayer0.occupancy 98658999 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 54500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) system.membus.reqLayer2.occupancy 21380469 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer5.occupancy 9518454911 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) system.membus.respLayer2.occupancy 8904498116 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.membus.respLayer3.occupancy 230513312 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) system.realview.ethernet.totPackets 3 # Total Packets system.realview.ethernet.totBytes 966 # Total Bytes system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks system.toL2Bus.snoop_filter.tot_requests 11772030 # Total number of requests made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_requests 5986527 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_requests 2060183 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 193514 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 180675 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 12839 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.trans_dist::ReadReq 59758 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 4863251 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 38287 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 38287 # Transaction distribution system.toL2Bus.trans_dist::Writeback 3950228 # Transaction distribution system.toL2Bus.trans_dist::CleanEvict 1568757 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 493482 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 318513 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 811995 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeFailReq 125 # Transaction distribution system.toL2Bus.trans_dist::UpgradeFailResp 125 # Transaction distribution system.toL2Bus.trans_dist::ReadExReq 1145198 # Transaction distribution system.toL2Bus.trans_dist::ReadExResp 1145198 # Transaction distribution system.toL2Bus.trans_dist::ReadSharedReq 4810734 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 106728 # Transaction distribution system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9122705 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6709100 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count::total 15831805 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 283955252 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 196820081 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size::total 480775333 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.snoops 3520564 # Total snoops (count) system.toL2Bus.snoop_fanout::samples 13735314 # Request fanout histogram system.toL2Bus.snoop_fanout::mean 0.326662 # Request fanout histogram system.toL2Bus.snoop_fanout::stdev 0.470981 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 9261350 67.43% 67.43% # Request fanout histogram system.toL2Bus.snoop_fanout::1 4461125 32.48% 99.91% # Request fanout histogram system.toL2Bus.snoop_fanout::2 12839 0.09% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram system.toL2Bus.snoop_fanout::total 13735314 # Request fanout histogram system.toL2Bus.reqLayer0.occupancy 9000721880 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 2650288 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) system.toL2Bus.respLayer0.occupancy 5320683808 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.toL2Bus.respLayer1.occupancy 4098533956 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 13032 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 5368 # number of quiesce instructions executed ---------- End Simulation Statistics ----------