---------- Begin Simulation Statistics ---------- sim_seconds 2.542157 # Number of seconds simulated sim_ticks 2542156879500 # Number of ticks simulated final_tick 2542156879500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks host_inst_rate 53622 # Simulator instruction rate (inst/s) host_op_rate 64601 # Simulator op (including micro ops) rate (op/s) host_tick_rate 2260157205 # Simulator tick rate (ticks/s) host_mem_usage 463148 # Number of bytes of host memory used host_seconds 1124.77 # Real time elapsed on the host sim_insts 60311972 # Number of instructions simulated sim_ops 72661518 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 640 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 798448 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 9072920 # Number of bytes read from this memory system.physmem.bytes_read::total 130982728 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 798448 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 798448 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 3743232 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory system.physmem.bytes_written::total 6759304 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 10 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 14989 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 141790 # Number of read requests responded to by this memory system.physmem.num_reads::total 15295608 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 58488 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory system.physmem.num_writes::total 812506 # Number of write requests responded to by this memory system.physmem.bw_read::realview.clcd 47640855 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 252 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 76 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 314083 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 3568985 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 51524251 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 314083 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 314083 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 1472463 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 1186422 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 2658885 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 1472463 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.clcd 47640855 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 252 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 76 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 314083 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 4755408 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 54183136 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 15295608 # Number of read requests accepted system.physmem.writeReqs 812506 # Number of write requests accepted system.physmem.readBursts 15295608 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 812506 # Number of DRAM write bursts, including those merged in the write queue system.physmem.bytesReadDRAM 977064192 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 1854720 # Total number of bytes read from write queue system.physmem.bytesWritten 6781120 # Total number of bytes written to DRAM system.physmem.bytesReadSys 130982728 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 6759304 # Total written bytes from the system interface side system.physmem.servicedByWrQ 28980 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 706520 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 4612 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 955787 # Per bank write bursts system.physmem.perBankRdBursts::1 955478 # Per bank write bursts system.physmem.perBankRdBursts::2 953511 # Per bank write bursts system.physmem.perBankRdBursts::3 951566 # Per bank write bursts system.physmem.perBankRdBursts::4 958612 # Per bank write bursts system.physmem.perBankRdBursts::5 955530 # Per bank write bursts system.physmem.perBankRdBursts::6 953056 # Per bank write bursts system.physmem.perBankRdBursts::7 951020 # Per bank write bursts system.physmem.perBankRdBursts::8 956158 # Per bank write bursts system.physmem.perBankRdBursts::9 955874 # Per bank write bursts system.physmem.perBankRdBursts::10 952686 # Per bank write bursts system.physmem.perBankRdBursts::11 950200 # Per bank write bursts system.physmem.perBankRdBursts::12 956166 # Per bank write bursts system.physmem.perBankRdBursts::13 955918 # Per bank write bursts system.physmem.perBankRdBursts::14 953812 # Per bank write bursts system.physmem.perBankRdBursts::15 951254 # Per bank write bursts system.physmem.perBankWrBursts::0 6556 # Per bank write bursts system.physmem.perBankWrBursts::1 6344 # Per bank write bursts system.physmem.perBankWrBursts::2 6481 # Per bank write bursts system.physmem.perBankWrBursts::3 6512 # Per bank write bursts system.physmem.perBankWrBursts::4 6422 # Per bank write bursts system.physmem.perBankWrBursts::5 6709 # Per bank write bursts system.physmem.perBankWrBursts::6 6691 # Per bank write bursts system.physmem.perBankWrBursts::7 6631 # Per bank write bursts system.physmem.perBankWrBursts::8 6968 # Per bank write bursts system.physmem.perBankWrBursts::9 6764 # Per bank write bursts system.physmem.perBankWrBursts::10 6424 # Per bank write bursts system.physmem.perBankWrBursts::11 6068 # Per bank write bursts system.physmem.perBankWrBursts::12 7033 # Per bank write bursts system.physmem.perBankWrBursts::13 6638 # Per bank write bursts system.physmem.perBankWrBursts::14 6915 # Per bank write bursts system.physmem.perBankWrBursts::15 6799 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry system.physmem.totGap 2542155562500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 18 # Read request sizes (log2) system.physmem.readPktSize::3 15138826 # Read request sizes (log2) system.physmem.readPktSize::4 3351 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) system.physmem.readPktSize::6 153413 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754018 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 58488 # Write request sizes (log2) system.physmem.rdQLenPdf::0 1110331 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 964948 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 965784 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1077100 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 974799 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1038209 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 2680927 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 2586042 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 3366057 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 129275 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 112161 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 103418 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 99187 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 20031 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 19249 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 19008 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 90 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 2611 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 2919 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 5332 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 6280 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 6367 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 6319 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 6325 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 6633 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 6459 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 6367 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 6344 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 6269 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 6292 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 6282 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 6253 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 6254 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 6225 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 6210 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 108 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 70 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 43 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 1010646 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 973.481627 # Bytes accessed per row activation system.physmem.bytesPerActivate::gmean 909.246732 # Bytes accessed per row activation system.physmem.bytesPerActivate::stdev 200.676766 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 22575 2.23% 2.23% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 19975 1.98% 4.21% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 8601 0.85% 5.06% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 2200 0.22% 5.28% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 2445 0.24% 5.52% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 1700 0.17% 5.69% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 8928 0.88% 6.57% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 928 0.09% 6.66% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 943294 93.34% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 1010646 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 6195 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::mean 2464.343987 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::stdev 113708.986245 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-524287 6190 99.92% 99.92% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.03% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1.04858e+06-1.57286e+06 2 0.03% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.02% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 6195 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 6195 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::mean 17.103309 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::gmean 17.049475 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::stdev 1.400786 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::16 3455 55.77% 55.77% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::17 44 0.71% 56.48% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::18 1683 27.17% 83.65% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::19 856 13.82% 97.47% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::20 62 1.00% 98.47% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::21 32 0.52% 98.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::22 30 0.48% 99.47% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::23 14 0.23% 99.69% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::24 13 0.21% 99.90% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::25 3 0.05% 99.95% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::26 1 0.02% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::27 1 0.02% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::35 1 0.02% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 6195 # Writes before turning the bus around for reads system.physmem.totQLat 395458190750 # Total ticks spent queuing system.physmem.totMemAccLat 681707465750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 76333140000 # Total ticks spent in databus transfers system.physmem.avgQLat 25903.44 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst system.physmem.avgMemAccLat 44653.44 # Average memory access latency per DRAM burst system.physmem.avgRdBW 384.34 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.67 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 51.52 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.66 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 3.02 # Data bus utilization in percentage system.physmem.busUtilRead 3.00 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 7.09 # Average read queue length when enqueuing system.physmem.avgWrQLen 24.73 # Average write queue length when enqueuing system.physmem.readRowHits 14271218 # Number of row buffer hits during reads system.physmem.writeRowHits 90719 # Number of row buffer hits during writes system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads system.physmem.writeRowHitRate 85.60 # Row buffer hit rate for writes system.physmem.avgGap 157818.32 # Average gap between requests system.physmem.pageHitRate 93.43 # Row buffer hit rate, read and write combined system.physmem.memoryStateTime::IDLE 2194559119750 # Time in different power states system.physmem.memoryStateTime::REF 84888180000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 262709081500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 48 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 48 # Number of instructions bytes read from this memory system.realview.nvmem.bytes_inst_read::total 48 # Number of instructions bytes read from this memory system.realview.nvmem.num_reads::cpu.inst 3 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 3 # Number of read requests responded to by this memory system.realview.nvmem.bw_read::cpu.inst 19 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::total 19 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu.inst 19 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::total 19 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 19 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 19 # Total bandwidth to/from this memory (bytes/s) system.membus.trans_dist::ReadReq 16348037 # Transaction distribution system.membus.trans_dist::ReadResp 16348037 # Transaction distribution system.membus.trans_dist::WriteReq 763357 # Transaction distribution system.membus.trans_dist::WriteResp 763357 # Transaction distribution system.membus.trans_dist::Writeback 58488 # Transaction distribution system.membus.trans_dist::UpgradeReq 4612 # Transaction distribution system.membus.trans_dist::UpgradeResp 4612 # Transaction distribution system.membus.trans_dist::ReadExReq 131654 # Transaction distribution system.membus.trans_dist::ReadExResp 131654 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383056 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 6 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3780 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1889332 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4276176 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 34553808 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390478 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 48 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7560 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16631504 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::total 19029594 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 140140122 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 216513 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::1 216513 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram system.membus.snoop_fanout::total 216513 # Request fanout histogram system.membus.reqLayer0.occupancy 1556318500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 3500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) system.membus.reqLayer2.occupancy 3760500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) system.membus.reqLayer6.occupancy 17512345000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) system.membus.respLayer1.occupancy 4726136292 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.membus.respLayer2.occupancy 37419189712 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.5 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.iobus.trans_dist::ReadReq 16322168 # Transaction distribution system.iobus.trans_dist::ReadResp 16322168 # Transaction distribution system.iobus.trans_dist::WriteReq 8176 # Transaction distribution system.iobus.trans_dist::WriteResp 8176 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7940 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 520 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1028 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 2383056 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::total 32660688 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 15880 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 1040 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2056 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 2390478 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 123501006 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 3975000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 520000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 520000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 15138816000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%) system.iobus.respLayer0.occupancy 2374880000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) system.iobus.respLayer1.occupancy 38173439288 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 13200672 # Number of BP lookups system.cpu.branchPred.condPredicted 9675464 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 704019 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 8378152 # Number of BTB lookups system.cpu.branchPred.BTBHits 6024616 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 71.908650 # BTB Hit Percentage system.cpu.branchPred.usedRAS 1435808 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 30777 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 31644036 # DTB read hits system.cpu.dtb.read_misses 39518 # DTB read misses system.cpu.dtb.write_hits 11381434 # DTB write hits system.cpu.dtb.write_misses 10146 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_entries 3436 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 314 # Number of TLB faults due to alignment restrictions system.cpu.dtb.prefetch_faults 314 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 1342 # Number of TLB faults due to permissions restrictions system.cpu.dtb.read_accesses 31683554 # DTB read accesses system.cpu.dtb.write_accesses 11391580 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses system.cpu.dtb.hits 43025470 # DTB hits system.cpu.dtb.misses 49664 # DTB misses system.cpu.dtb.accesses 43075134 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 24158829 # ITB inst hits system.cpu.itb.inst_misses 10513 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID system.cpu.itb.flush_entries 2463 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.perms_faults 4177 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses system.cpu.itb.inst_accesses 24169342 # ITB inst accesses system.cpu.itb.hits 24158829 # DTB hits system.cpu.itb.misses 10513 # DTB misses system.cpu.itb.accesses 24169342 # DTB accesses system.cpu.numCycles 499362415 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.fetch.icacheStallCycles 43030394 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 74128653 # Number of instructions fetch has processed system.cpu.fetch.Branches 13200672 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 7460424 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 448275105 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1858360 # Number of cycles fetch has spent squashing system.cpu.fetch.TlbCycles 133126 # Number of cycles fetch has spent waiting for tlb system.cpu.fetch.MiscStallCycles 12568 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 145919 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 3031035 # Number of stall cycles due to pending quiesce instructions system.cpu.fetch.IcacheWaitRetryStallCycles 43 # Number of stall cycles due to full MSHR system.cpu.fetch.CacheLines 24157528 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 404783 # Number of outstanding Icache misses that were squashed system.cpu.fetch.ItlbSquashes 4525 # Number of outstanding ITLB misses that were squashed system.cpu.fetch.rateDist::samples 495557370 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 0.179785 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 0.652906 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::0 454652495 91.75% 91.75% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 13614115 2.75% 94.49% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 6392828 1.29% 95.78% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 20897932 4.22% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 495557370 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.026435 # Number of branch fetches per cycle system.cpu.fetch.rate 0.148447 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 35569711 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 424983346 # Number of cycles decode is blocked system.cpu.decode.RunCycles 30281377 # Number of cycles decode is running system.cpu.decode.UnblockCycles 4038894 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 684042 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 1691471 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 250415 # Number of times decode detected a branch misprediction system.cpu.decode.DecodedInsts 80255110 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 2078434 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 684042 # Number of cycles rename is squashing system.cpu.rename.IdleCycles 38792488 # Number of cycles rename is idle system.cpu.rename.BlockCycles 217877928 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 28703436 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 30648610 # Number of cycles rename is running system.cpu.rename.UnblockCycles 178850866 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 78212678 # Number of instructions processed by rename system.cpu.rename.SquashedInsts 597297 # Number of squashed instructions processed by rename system.cpu.rename.ROBFullEvents 61152111 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 42400388 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 160465834 # Number of times rename has blocked due to LQ full system.cpu.rename.SQFullEvents 14716938 # Number of times rename has blocked due to SQ full system.cpu.rename.RenamedOperands 82091302 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 364181024 # Number of register rename lookups that rename has made system.cpu.rename.int_rename_lookups 97016550 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 9816 # Number of floating rename lookups system.cpu.rename.CommittedMaps 75931219 # Number of HB maps that are committed system.cpu.rename.UndoneMaps 6160077 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 1133996 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 964709 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 9001428 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 14558433 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 12101238 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 791096 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 1255692 # Number of conflicting stores. system.cpu.iq.iqInstsAdded 75818942 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 1655707 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqInstsIssued 93904368 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 178701 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsExamined 4397117 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 8687724 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 172240 # Number of squashed non-spec instructions that were removed system.cpu.iq.issued_per_cycle::samples 495557370 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 0.189492 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 0.548385 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::0 430560734 86.88% 86.88% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 43002673 8.68% 95.56% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 15716973 3.17% 98.73% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 5640247 1.14% 99.87% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 636707 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 36 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::total 495557370 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 4845097 15.77% 15.77% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 148 0.00% 15.77% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 15.77% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 15.77% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.77% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.77% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMult 0 0.00% 15.77% # attempts to use FU when none available system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.77% # attempts to use FU when none available system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.77% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.77% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.77% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.77% # attempts to use FU when none available system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.77% # attempts to use FU when none available system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.77% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.77% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMult 0 0.00% 15.77% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.77% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShift 0 0.00% 15.77% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.77% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.77% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.77% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.77% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.77% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.77% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.77% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.77% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.77% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.77% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.77% # attempts to use FU when none available system.cpu.iq.fu_full::MemRead 20357888 66.27% 82.04% # attempts to use FU when none available system.cpu.iq.fu_full::MemWrite 5517607 17.96% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 28518 0.03% 0.03% # Type of FU issued system.cpu.iq.FU_type_0::IntAlu 49538039 52.75% 52.78% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 91860 0.10% 52.88% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.88% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 52.88% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.88% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.88% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.88% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.88% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 52.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.88% # Type of FU issued system.cpu.iq.FU_type_0::MemRead 32268758 34.36% 87.25% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 11975082 12.75% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 93904368 # Type of FU issued system.cpu.iq.rate 0.188049 # Inst issue rate system.cpu.iq.fu_busy_cnt 30720740 # FU busy when requested system.cpu.iq.fu_busy_rate 0.327149 # FU busy rate (busy events/executed inst) system.cpu.iq.int_inst_queue_reads 714233003 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 81866264 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 74968812 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 32544 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 12124 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 10212 # Number of floating instruction queue wakeup accesses system.cpu.iq.int_alu_accesses 124575127 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 21463 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 210020 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 1045495 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 540 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 6662 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 369586 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 17074158 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 1006174 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 684042 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 94158200 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 98278744 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 77650660 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 14558433 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 12101238 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 1114427 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 20284 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 98194153 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 6662 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 210239 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 275440 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 485679 # Number of branch mispredicts detected at execute system.cpu.iew.iewExecutedInsts 93249449 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 32002025 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 605470 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 176011 # number of nop insts executed system.cpu.iew.exec_refs 43890987 # number of memory reference insts executed system.cpu.iew.exec_branches 10791373 # Number of branches executed system.cpu.iew.exec_stores 11888962 # Number of stores executed system.cpu.iew.exec_rate 0.186737 # Inst execution rate system.cpu.iew.wb_sent 92183769 # cumulative count of insts sent to commit system.cpu.iew.wb_count 74979024 # cumulative count of insts written-back system.cpu.iew.wb_producers 35461894 # num instructions producing a value system.cpu.iew.wb_consumers 52697256 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 0.150150 # insts written-back per cycle system.cpu.iew.wb_fanout 0.672936 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 3942249 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1483467 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 458881 # The number of times a branch was mispredicted system.cpu.commit.committed_per_cycle::samples 494573774 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 0.147222 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 0.699394 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::0 457850390 92.57% 92.57% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 22155471 4.48% 97.05% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 6977487 1.41% 98.47% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 2402189 0.49% 98.95% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 1803487 0.36% 99.32% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 1041949 0.21% 99.53% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 590384 0.12% 99.65% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 490446 0.10% 99.74% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 1261971 0.26% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 494573774 # Number of insts commited each cycle system.cpu.commit.committedInsts 60462353 # Number of instructions committed system.cpu.commit.committedOps 72811899 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 25244590 # Number of memory references committed system.cpu.commit.loads 13512938 # Number of loads committed system.cpu.commit.membars 403660 # Number of memory barriers committed system.cpu.commit.branches 10308077 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. system.cpu.commit.int_insts 64250158 # Number of committed integer instructions. system.cpu.commit.function_calls 991634 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.commit.op_class_0::IntAlu 47477309 65.21% 65.21% # Class of committed instruction system.cpu.commit.op_class_0::IntMult 87889 0.12% 65.33% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 65.33% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 65.33% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.33% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.33% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.33% # Class of committed instruction system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.33% # Class of committed instruction system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.33% # Class of committed instruction system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.33% # Class of committed instruction system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.33% # Class of committed instruction system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.33% # Class of committed instruction system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.33% # Class of committed instruction system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.33% # Class of committed instruction system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.33% # Class of committed instruction system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.33% # Class of committed instruction system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.33% # Class of committed instruction system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.33% # Class of committed instruction system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.33% # Class of committed instruction system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.33% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.33% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.33% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.33% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.33% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.33% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMisc 2111 0.00% 65.33% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.33% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.33% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.33% # Class of committed instruction system.cpu.commit.op_class_0::MemRead 13512938 18.56% 83.89% # Class of committed instruction system.cpu.commit.op_class_0::MemWrite 11731652 16.11% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 72811899 # Class of committed instruction system.cpu.commit.bw_lim_events 1261971 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.rob.rob_reads 568215140 # The number of ROB reads system.cpu.rob.rob_writes 154414029 # The number of ROB writes system.cpu.timesIdled 543953 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 3805045 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.quiesceCycles 4584951345 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu.committedInsts 60311972 # Number of Instructions Simulated system.cpu.committedOps 72661518 # Number of Ops (including micro ops) Simulated system.cpu.cpi 8.279657 # CPI: Cycles Per Instruction system.cpu.cpi_total 8.279657 # CPI: Total CPI of All Threads system.cpu.ipc 0.120778 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.120778 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 109116744 # number of integer regfile reads system.cpu.int_regfile_writes 47012206 # number of integer regfile writes system.cpu.fp_regfile_reads 8305 # number of floating regfile reads system.cpu.fp_regfile_writes 2780 # number of floating regfile writes system.cpu.cc_regfile_reads 320409300 # number of cc regfile reads system.cpu.cc_regfile_writes 30332935 # number of cc regfile writes system.cpu.misc_regfile_reads 605119297 # number of misc regfile reads system.cpu.misc_regfile_writes 1173998 # number of misc regfile writes system.cpu.toL2Bus.trans_dist::ReadReq 2604204 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 2604204 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 763357 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 763357 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 599947 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2950 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2952 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 246567 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 246567 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1926460 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5768361 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 27152 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 85364 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 7807337 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61454112 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 84373434 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 37904 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 135564 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 146001014 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 26770 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 2266210 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::5 2266210 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 2266210 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 3090363565 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1446991237 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 2544137605 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer2.occupancy 17681240 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer3.occupancy 51517661 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu.icache.tags.replacements 959838 # number of replacements system.cpu.icache.tags.tagsinuse 511.383389 # Cycle average of tags in use system.cpu.icache.tags.total_refs 23148830 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 960350 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 24.104576 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 11339333250 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 511.383389 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.998796 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.998796 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 171 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 221 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 25114544 # Number of tag accesses system.cpu.icache.tags.data_accesses 25114544 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 23148830 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 23148830 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 23148830 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 23148830 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 23148830 # number of overall hits system.cpu.icache.overall_hits::total 23148830 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 1005344 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 1005344 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 1005344 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 1005344 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 1005344 # number of overall misses system.cpu.icache.overall_misses::total 1005344 # number of overall misses system.cpu.icache.ReadReq_miss_latency::cpu.inst 13667748229 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 13667748229 # number of ReadReq miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 13667748229 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 13667748229 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 13667748229 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 13667748229 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 24154174 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 24154174 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 24154174 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 24154174 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 24154174 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 24154174 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.041622 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.041622 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.041622 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.041622 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.041622 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.041622 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13595.096036 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 13595.096036 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 13595.096036 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 13595.096036 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 13595.096036 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 13595.096036 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 1628 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 118 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs 13.796610 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_hits::cpu.inst 44974 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::total 44974 # number of ReadReq MSHR hits system.cpu.icache.demand_mshr_hits::cpu.inst 44974 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits::total 44974 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 44974 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 44974 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 960370 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 960370 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 960370 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 960370 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 960370 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 960370 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11288731510 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 11288731510 # number of ReadReq MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11288731510 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 11288731510 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11288731510 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 11288731510 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 223034500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 223034500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 223034500 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 223034500 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.039760 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.039760 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.039760 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.039760 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.039760 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.039760 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11754.564918 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11754.564918 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11754.564918 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 11754.564918 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11754.564918 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 11754.564918 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 63303 # number of replacements system.cpu.l2cache.tags.tagsinuse 51126.923594 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1828959 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 128691 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 14.212019 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 2530750696500 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 37301.769799 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 6.815946 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000703 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.inst 7722.177507 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 6096.159639 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.569180 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000104 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.117831 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.093020 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.780135 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1023 7 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_blocks::1024 65381 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 269 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3025 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6220 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55834 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000107 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997635 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 18315394 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 18315394 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 33880 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 9473 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.inst 947730 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 377075 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1368158 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 599947 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 599947 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 41 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 41 # number of UpgradeReq hits system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 2 # number of SCUpgradeReq hits system.cpu.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits system.cpu.l2cache.ReadExReq_hits::cpu.data 113210 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 113210 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.dtb.walker 33880 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.itb.walker 9473 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.inst 947730 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 490285 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 1481368 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.dtb.walker 33880 # number of overall hits system.cpu.l2cache.overall_hits::cpu.itb.walker 9473 # number of overall hits system.cpu.l2cache.overall_hits::cpu.inst 947730 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 490285 # number of overall hits system.cpu.l2cache.overall_hits::total 1481368 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 11 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.inst 11652 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 10148 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 21814 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 2909 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 2909 # number of UpgradeReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 133357 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 133357 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.dtb.walker 11 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.inst 11652 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 143505 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 155171 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 11 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses system.cpu.l2cache.overall_misses::cpu.inst 11652 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 143505 # number of overall misses system.cpu.l2cache.overall_misses::total 155171 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 790750 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 238250 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 835556749 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 759914000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 1596499749 # number of ReadReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 349485 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 349485 # number of UpgradeReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9345897297 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 9345897297 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 790750 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 238250 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 835556749 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 10105811297 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 10942397046 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 790750 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 238250 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 835556749 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 10105811297 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 10942397046 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 33891 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 9476 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.inst 959382 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 387223 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 1389972 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 599947 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 599947 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2950 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 2950 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 246567 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 246567 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.dtb.walker 33891 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.itb.walker 9476 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.inst 959382 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 633790 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 1636539 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.dtb.walker 33891 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.itb.walker 9476 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 959382 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 633790 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 1636539 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000325 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000317 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012145 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026207 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.015694 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986102 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986102 # miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.540855 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.540855 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000325 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000317 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012145 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.226424 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.094817 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000325 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000317 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012145 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.226424 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.094817 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 71886.363636 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 79416.666667 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71709.298747 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74883.129681 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 73186.932658 # average ReadReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 120.139223 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 120.139223 # average UpgradeReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70081.790210 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70081.790210 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 71886.363636 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 79416.666667 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71709.298747 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70421.318400 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 70518.312352 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 71886.363636 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 79416.666667 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71709.298747 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70421.318400 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 70518.312352 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 58488 # number of writebacks system.cpu.l2cache.writebacks::total 58488 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.dtb.walker 1 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 14 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 55 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.dtb.walker 1 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 14 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 40 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 55 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.dtb.walker 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 14 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 40 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 55 # number of overall MSHR hits system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 10 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 11638 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10108 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 21759 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2909 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 2909 # number of UpgradeReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133357 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 133357 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 10 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 11638 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 143465 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 155116 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 10 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 11638 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 143465 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 155116 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 596250 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 201250 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 688774749 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 631278500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1320850749 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29121909 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29121909 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7684221703 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7684221703 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 596250 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 201250 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 688774749 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8315500203 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 9005072452 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 596250 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 201250 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 688774749 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8315500203 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 9005072452 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 174356000 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 167012344750 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167186700750 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 17146783596 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 17146783596 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 174356000 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184159128346 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184333484346 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000295 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000317 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012131 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026104 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015654 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986102 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986102 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.540855 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.540855 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000295 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000317 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012131 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.226360 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.094783 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000295 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000317 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012131 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.226360 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.094783 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 59625 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 67083.333333 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59183.257347 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62453.353779 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60703.651317 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10010.969062 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10010.969062 # average UpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57621.434968 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57621.434968 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 59625 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 67083.333333 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59183.257347 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57961.873649 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58053.794915 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 59625 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 67083.333333 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59183.257347 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57961.873649 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58053.794915 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 633278 # number of replacements system.cpu.dcache.tags.tagsinuse 511.949941 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 19068568 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 633790 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 30.086571 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 267154250 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.949941 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999902 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999902 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 319 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 91796938 # Number of tag accesses system.cpu.dcache.tags.data_accesses 91796938 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 11311263 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 11311263 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 7209463 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 7209463 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 60828 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 60828 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 236419 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 236419 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 247594 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 247594 # number of StoreCondReq hits system.cpu.dcache.demand_hits::cpu.data 18520726 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 18520726 # number of demand (read+write) hits system.cpu.dcache.overall_hits::cpu.data 18581554 # number of overall hits system.cpu.dcache.overall_hits::total 18581554 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 573243 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 573243 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 3012489 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 3012489 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 126499 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 126499 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 12987 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 12987 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses system.cpu.dcache.demand_misses::cpu.data 3585732 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 3585732 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 3712231 # number of overall misses system.cpu.dcache.overall_misses::total 3712231 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 7223298916 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 7223298916 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 126143348315 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 126143348315 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 177246500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 177246500 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 26000 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 26000 # number of StoreCondReq miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 133366647231 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 133366647231 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 133366647231 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 133366647231 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 11884506 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 11884506 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 10221952 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 10221952 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 187327 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::total 187327 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 249406 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 249406 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 247596 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 247596 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.demand_accesses::cpu.data 22106458 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 22106458 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 22293785 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 22293785 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.048234 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.048234 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.294708 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.294708 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.675284 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.675284 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052072 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052072 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000008 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000008 # miss rate for StoreCondReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.162203 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.162203 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.166514 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.166514 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12600.762532 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 12600.762532 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41873.463543 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 41873.463543 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13647.994148 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13647.994148 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 37193.701936 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 37193.701936 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 35926.279165 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 35926.279165 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 17394 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 459 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 1226 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.187602 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 459 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 599947 # number of writebacks system.cpu.dcache.writebacks::total 599947 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 271762 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 271762 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2763128 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 2763128 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1233 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 1233 # number of LoadLockedReq MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 3034890 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 3034890 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 3034890 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 3034890 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 301481 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 301481 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249361 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 249361 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 74144 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 74144 # number of SoftPFReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11754 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 11754 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses system.cpu.dcache.demand_mshr_misses::cpu.data 550842 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 550842 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 624986 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 624986 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3569589078 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 3569589078 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10791306319 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 10791306319 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1230913250 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1230913250 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 139261250 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 139261250 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 22000 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14360895397 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 14360895397 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15591808647 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 15591808647 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182406065750 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182406065750 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26598901323 # number of WriteReq MSHR uncacheable cycles system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26598901323 # number of WriteReq MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209004967073 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::total 209004967073 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025368 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.025368 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024395 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024395 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.395800 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.395800 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047128 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047128 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000008 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000008 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024918 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.024918 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028034 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.028034 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11840.179242 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11840.179242 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43275.838319 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43275.838319 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16601.656911 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16601.656911 # average SoftPFReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11847.987919 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11847.987919 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26070.806868 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 26070.806868 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24947.452658 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 24947.452658 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. system.iocache.tags.avg_refs nan # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.tags.tag_accesses 0 # Number of tag accesses system.iocache.tags.data_accesses 0 # Number of data accesses system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1736978742288 # number of ReadReq MSHR uncacheable cycles system.iocache.ReadReq_mshr_uncacheable_latency::total 1736978742288 # number of ReadReq MSHR uncacheable cycles system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1736978742288 # number of overall MSHR uncacheable cycles system.iocache.overall_mshr_uncacheable_latency::total 1736978742288 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 83186 # number of quiesce instructions executed ---------- End Simulation Statistics ----------